Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device and a method for manufacturing the semiconductor device which facilitate control of the shape of a regrowth layer.SOLUTION: A semiconductor device 100 has a first opening 31 and a second opening 32 formed in an electron supply layer 22 and an electron transit layer 21, and a third opening 33 connected to the first opening and a fourth opening 34 connected to the second opening formed in an insulating layer 51. The first opening has a first edge 31A. The second opening has a second edge 32A. The third opening has a third edge 33A. The fourth opening has a fourth edge 34A. The bottom 31B of the first opening and the bottom 32B of the second opening are positioned deeper toward the substrate 10 side than a first upper surface 21A, a source region 24 is provided in the first opening, and a drain region 2 is provided in the second opening. In plan view from a direction perpendicular to the first main surface 10A, the first edge of the first opening is located closer to the second opening than the third edge of the third opening, and the second edge of the second opening is located closer to the first opening than the fourth edge of the fourth opening.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] A method has been proposed for reducing the contact resistance, which indicates the total resistance component between the source electrode and the drain electrode and the two-dimensional electron gas (2DEG), in a high electron mobility transistor (HEMT). In this method, openings are formed in the electron supply layer and the electron transport layer, and a GaN (n + GaN) layer is regrown and n + The source and drain electrodes are formed on the GaN layer (regrowth layer). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-125600 A [Patent Document 2] U.S. Patent No. 9,515,161 Summary of the Invention [Problem to be solved by the invention]

[0004] When forming the opening and regrowth layer using conventional methods, it can be difficult to control the shape of the regrowth layer.

[0005] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device in which the shape of a regrowth layer can be easily controlled. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a substrate having a first main surface, a semiconductor layer provided on the first main surface of the substrate, an insulating layer provided on the semiconductor layer, a source electrode and a drain electrode provided on the semiconductor layer, and a gate electrode provided on the insulating layer, the semiconductor layer being provided above the substrate and including an electron transit layer having a first upper surface and an electron supply layer provided above the electron transit layer, a first opening and a second opening are formed in the electron supply layer and the electron transit layer, a third opening connected to the first opening and a fourth opening connected to the second opening are formed in the insulating layer, the first opening has a first edge on the second opening side, the second opening has a second edge on the first opening side, and the third opening has a front edge. a third edge on the fourth opening side, the fourth opening having a fourth edge on the third opening side, a bottom of the first opening and a bottom of the second opening being located deeper toward the substrate than the first upper surface, the semiconductor layer further having a source region containing impurities of a first conductivity type and located in the first opening, and a drain region containing impurities of the first conductivity type and located in the second opening, the source electrode being located on the source region, and the drain electrode being located on the drain region, in a plan view from a direction perpendicular to the first main surface, the first edge of the first opening being located closer to the second opening than the third edge of the third opening, and the second edge of the second opening being located closer to the first opening than the fourth edge of the fourth opening, the first edge is between the gate electrode and the third edge, and the second edge is between the gate electrode and the fourth edge; A portion of the source region overlaps the insulating layer, and a portion of the drain region overlaps the insulating layer. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to easily control the shapes of the source and drain regions as regrown layers. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2]FIG. 2 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a ninth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 1) showing a method for manufacturing a semiconductor device according to a reference example. [Figure 13] FIG. 13 is a cross-sectional view (part 2) showing a method for manufacturing a semiconductor device according to a reference example. [Figure 14] FIG. 14 is a cross-sectional view (part 3) showing a method for manufacturing a semiconductor device according to a reference example. [Figure 15] FIG. 15 is a cross-sectional view (part 4) showing a method for manufacturing a semiconductor device according to a reference example. [Figure 16] FIG. 16 is a cross-sectional view (part 1) illustrating a method for manufacturing a semiconductor device according to a first modification of the first embodiment. [Figure 17]FIG. 17 is a cross-sectional view (part 2) illustrating a method for manufacturing a semiconductor device according to a first modification of the first embodiment. [Figure 18] FIG. 18 is a cross-sectional view (part 1) illustrating a method for manufacturing a semiconductor device according to a second modification of the first embodiment. [Figure 19] FIG. 19 is a cross-sectional view (part 2) illustrating a method for manufacturing a semiconductor device according to a second modification of the first embodiment. [Figure 20] FIG. 20 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 21] FIG. 21 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 22] FIG. 22 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 23] FIG. 23 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A semiconductor device according to one aspect of the present disclosure includes a substrate having a first main surface, a semiconductor layer provided on the first main surface of the substrate, an insulating layer provided on the semiconductor layer, a source electrode and a drain electrode provided on the semiconductor layer, and a gate electrode provided on the insulating layer, the semiconductor layer being provided above the substrate and including an electron transit layer having a first upper surface and an electron supply layer provided above the electron transit layer, a first opening and a second opening are formed in the electron supply layer and the electron transit layer, a third opening connected to the first opening and a fourth opening connected to the second opening are formed in the insulating layer, the first opening has a first edge on the second opening side, the second opening has a second edge on the first opening side, the third opening has a third edge on the fourth opening side, and the fourth opening has a second edge on the fourth opening side. the opening has a fourth edge on the third opening side, a bottom of the first opening and a bottom of the second opening are located deeper toward the substrate than the first upper surface, the semiconductor layer further has a source region containing impurities of a first conductivity type and located in the first opening, and a drain region containing impurities of the first conductivity type and located in the second opening, the source electrode is located on the source region, the drain electrode is located on the drain region, in a planar view from a direction perpendicular to the first main surface, the first edge of the first opening is located closer to the second opening than the third edge of the third opening, the second edge of the second opening is located closer to the first opening than the fourth edge of the fourth opening, a portion of the source region overlaps the insulating layer, and a portion of the drain region overlaps the insulating layer.

[0011] In a plan view, the first edge of the first opening is located closer to the second opening than the third edge of the third opening, the second edge of the second opening is located closer to the first opening than the fourth edge of the fourth opening, a portion of the source region overlaps with the insulating layer, and a portion of the drain region overlaps with the insulating layer. Therefore, when the source region and the drain region are formed as regrown layers, the generation of abnormal growth portions described below is suppressed, and the shapes of the source region and the drain region can be easily controlled.

[0012] [2] In [1], in a plan view from a direction perpendicular to the first main surface, a distance between the first edge and the third edge may be 0.2 μm or more and 1.5 μm or less, and a distance between the second edge and the fourth edge may be 0.2 μm or more and 1.5 μm or less. When these distances are 0.2 μm or more and 1.5 μm or less, it is easier to control the shapes of the source region and the drain region.

[0013] [3] In [1] or [2], a part of the upper surface of the source region may be in contact with a part of the lower surface of the insulating layer, and a part of the upper surface of the drain region may be in contact with another part of the lower surface of the insulating layer, making it easier to control the shapes of the source and drain regions by regrowth.

[0014] [4] In any of [1] to [3], the gate electrode may be in Schottky contact with the semiconductor layer, which enables higher speed operation than an MIS gate structure.

[0015] [5] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes forming an electron transit layer having a first upper surface above a first main surface of a substrate having the first main surface, forming an electron supply layer above the electron transit layer, forming an insulating layer above the electron supply layer, forming a third opening and a fourth opening in the insulating layer, forming a first opening connected to the third opening and a second opening connected to the fourth opening in the electron supply layer and the electron transit layer, forming a source region containing impurities of a first conductivity type in the first opening, forming a drain region containing impurities of the first conductivity type in the second opening, forming a source electrode on the source region, and forming a drain electrode on the drain region. and a step of forming a gate electrode on the insulating layer, wherein the first opening has a first edge on the second opening side, the second opening has a second edge on the first opening side, the third opening has a third edge on the fourth opening side, and the fourth opening has a fourth edge on the third opening side, a bottom of the first opening and a bottom of the second opening are located deeper toward the substrate than the first top surface, and in a plan view from a direction perpendicular to the first main surface, the first edge of the first opening is located closer to the second opening than the third edge of the third opening, and the second edge of the second opening is located closer to the first opening than the fourth edge of the fourth opening, and a portion of the source region overlaps the insulating layer, and a portion of the drain region overlaps the insulating layer.

[0016] In a plan view, the first edge of the first opening is located closer to the second opening than the third edge of the third opening, and the second edge of the second opening is located closer to the first opening than the fourth edge of the fourth opening. Therefore, when forming the source and drain regions by regrowth, the generation of abnormally grown portions, which will be described later, is suppressed, and the shapes of the source and drain regions can be easily controlled.

[0017] [6] In the method of [5], a step of forming a mask on the insulating layer may be included between the step of forming the insulating layer and the step of forming the third and fourth openings, the step of forming the third and fourth openings may include a step of reactive ion etching the insulating layer using the mask, and the step of forming the first and second openings may include a step of photoelectrochemical etching the electron supply layer and the electron transit layer using the mask. Photoelectrochemical etching makes it easy to form the first and second openings in desired shapes.

[0018] [7] In the method of [5], the method may further include forming a mask on the insulating layer between the step of forming the insulating layer and the step of forming the third and fourth openings, wherein the step of forming the third and fourth openings includes performing reactive ion etching on the insulating layer using the mask, and the step of forming the first and second openings includes performing reactive ion etching on the electron supply layer and the electron transit layer using the mask, wherein the reactive ion etching of the electron supply layer and the electron transit layer continues after the first main surface of the substrate is exposed. By continuing the supply of reactive gas after the first main surface of the substrate is exposed, it is easy to form the first and second openings in desired shapes.

[0019] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In the present specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description. In the crystallographic descriptions in this specification, individual orientations are indicated by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. Furthermore, while a negative index in crystallographic terms is usually represented by placing a "-" (bar) before the number, in this specification, a negative sign is placed before the number.

[0020] (First embodiment) A first embodiment will be described. The first embodiment relates to a semiconductor device including a GaN-HEMT whose main constituent material is a nitride semiconductor. Fig. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0021] As shown in FIG. 1, the semiconductor device 100 according to the first embodiment includes a substrate 10 having a first principal surface 10A and a stacked structure 20 of multiple semiconductor layers disposed on the first principal surface 10A. The substrate 10 is, for example, a SiC substrate having a (0001) principal surface as the first principal surface 10A, and the stacking direction of the stacked structure 20 is, for example, the

[0001] direction. The stacked structure 20 includes, in order from the substrate 10 side, an electron transit layer 21, an electron supply layer 22, and a cap layer 23. The electron transit layer 21 is, for example, an undoped GaN layer having a thickness of approximately 1000 nm. The electron supply layer 22 is, for example, an n-type AlGaN layer having a thickness of approximately 20 nm. The cap layer 23 is, for example, an n-type GaN layer having a thickness of approximately 5 nm. The n-type impurity used in this embodiment is, for example, Si or Ge. The stacked structure 20 may include a buffer layer (not shown) between the electron transit layer 21 and the substrate 10. The buffer layer is, for example, an AlN layer. The stacked structure 20 is an example of a semiconductor layer.

[0022] A first opening 31 for a source and a second opening 32 for a drain are formed in the stacked structure 20. A bottom 31B of the first opening 31 and a bottom 32B of the second opening 32 are located deeper toward the substrate 10 than the top surface 21A of the electron transit layer 21. That is, the first opening 31 and the second opening 32 are formed deeper than the top surface 21A of the electron transit layer 21. The first opening 31 and the second opening 32 do not reach the substrate 10, and the bottom 31B of the first opening 31 and the bottom 32B of the second opening 32 are farther away from the substrate 10. The bottom 31B of the first opening 31 and the bottom 32B of the second opening 32 are closer to the first main surface 10A than the top surface 21A of the electron transit layer 21. The top surface 21A is an example of a first top surface.

[0023] The semiconductor device 100 has an insulating layer 51 provided on the stacked structure 20. The insulating layer 51 is, for example, a Si nitride layer or an Al oxide layer. A third opening 33 for a source and a fourth opening 34 for a drain are formed in the insulating layer 51. The third opening 33 is connected to the first opening 31, and the fourth opening 34 is connected to the second opening 32.

[0024] The first opening 31 has a first edge 31A on the second opening 32 side, and the second opening 32 has a second edge 32A on the first opening 31 side. The third opening 33 has a third edge 33A on the fourth opening 34 side, and the fourth opening 34 has a fourth edge 34A on the third opening 33 side. In a plan view from a direction perpendicular to the first main surface 10A, the first edge 31A of the first opening 31 is located closer to the second opening 32 than the third edge 33A of the third opening 33, and the second edge 32A of the second opening 32 is located closer to the first opening 31 than the fourth edge 34A of the fourth opening 34. In other words, the insulating layer 51 has portions that serve as overhangs for the first opening 31 and the second opening 32. The insulating layer 51 extends beyond the first edge 31A of the first opening 31 in a direction away from the second opening 32 and extends beyond the second edge 32A of the second opening 32 in a direction away from the first opening 31.

[0025] The stacked structure 20 has a source region 24 provided in the first opening 31. The source region 24 is provided on the bottom 31B of the first opening 31. In a plan view perpendicular to the first main surface 10A, a portion of the source region 24 overlaps with the insulating layer 51. A portion of the upper surface 24A of the source region 24 contacts a lower surface 51A of a portion of the insulating layer 51 that protrudes toward the first opening 31. For example, the lower surface 51A of the portion of the insulating layer 51 that protrudes toward the first opening 31 is covered by the source region 24. Another portion of the upper surface 24A of the source region 24 may be located closer to the first main surface 10A of the substrate 10 than the lower surface 51A of the portion of the insulating layer 51 that protrudes toward the first opening 31. The source region 24 is, for example, an n-type GaN layer. The source region 24 contains, for example, n-type impurities at a higher concentration than the electron supply layer 22. In other words, the electron supply layer 22 contains n-type impurities at a lower concentration than the source region 24. Therefore, the electrical resistance of the source region 24 is lower than the electrical resistance of the electron supply layer 22. The concentration of n-type impurities in the source region 24 is, for example, 5×10 18cm -3 Over 2×10 19 cm -3 It is about the following.

[0026] The stacked structure 20 has a drain region 25 provided in the second opening 32. The drain region 25 is provided on the bottom 32B of the second opening 32. In a plan view perpendicular to the first main surface 10A, a portion of the drain region 25 overlaps with the insulating layer 51. A portion of the upper surface 25A of the drain region 25 contacts a lower surface 51B of the portion of the insulating layer 51 that protrudes toward the second opening 32. For example, the lower surface 51B of the portion of the insulating layer 51 that protrudes toward the second opening 32 is covered by the drain region 25. Another portion of the upper surface 25A of the drain region 25 may be located closer to the first main surface 10A of the substrate 10 than the lower surface 51B of the portion of the insulating layer 51 that protrudes toward the second opening 32. The drain region 25 is, for example, an n-type GaN layer. The drain region 25 contains, for example, n-type impurities at a higher concentration than the electron supply layer 22. In other words, the electron supply layer 22 contains n-type impurities at a lower concentration than the drain region 25. Therefore, the electrical resistance of the drain region 25 is lower than the electrical resistance of the electron supply layer 22. The concentration of n-type impurities in the drain region 25 is, for example, 5×10 18 cm -3 Over 2×10 19 cm -3 It is about the following.

[0027] The semiconductor device 100 has a source electrode 41 provided on the source region 24 and a drain electrode 42 provided on the drain region 25. The source electrode 41 and the drain electrode 42 include, for example, a Ta film and an Al film.

[0028] A seventh opening 52 for a gate is formed in the insulating layer 51 between the source electrode 41 and the drain electrode 42. A portion of the surface of the stacked structure 20 is exposed through the seventh opening 52. The semiconductor device 100 has a gate electrode 43 that contacts the stacked structure 20 through the seventh opening 52. The gate electrode 43 includes, for example, a Ni film and an Au film. The gate electrode 43 has, for example, a T-shape in cross section. The gate electrode 43 is in Schottky contact with the stacked structure 20. The gate electrode 43 making Schottky contact with the stacked structure 20 enables high-speed operation.

[0029] The semiconductor device 100 further includes an insulating layer 53 that covers the gate electrode 43, the source electrode 41, and the drain electrode 42. The insulating layer 53 is, for example, a Si nitride layer or an Al oxide layer. A fifth opening 35 that exposes a portion of the source electrode 41 and a sixth opening 36 that exposes a portion of the drain electrode 42 are formed in the insulating layer 53.

[0030] In the semiconductor device 100, the 2DEG 29 is present near the top surface 21A of the electron transit layer 21. The source electrode 41 is in ohmic contact with the 2DEG 29 via the source region 24, and the drain electrode 42 is in ohmic contact with the 2DEG 29 via the drain region 25. Therefore, the presence of the source region 24 and the drain region 25 reduces the contact resistance, which is the resistance component from each of the source electrode 41 and the drain electrode 42 to the 2DEG 29.

[0031] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 2 to 11 are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.

[0032] 2, an electron transit layer 21, an electron supply layer 22, and a cap layer 23 are formed on a substrate 10. The electron transit layer 21, the electron supply layer 22, and the cap layer 23 are formed by, for example, metal organic chemical vapor deposition (MOCVD). Next, an insulating layer 51 is formed on the cap layer 23. The insulating layer 51 is formed by, for example, chemical vapor deposition (CVD).

[0033] Next, as shown in FIG. 3 , a resist mask 71 is formed on the insulating layer 51. An opening 73 exposing a region where the third opening 33 will be formed and an opening 74 exposing a region where the fourth opening 34 will be formed are formed in the resist mask 71. Next, the third opening 33 is formed in the insulating layer 51 through the opening 73, and the fourth opening 34 is formed through the opening 74 by reactive ion etching (RIE). A reactive gas containing fluorine (F) may be used to etch the insulating layer 51. Next, the first opening 31 is formed in the electron transit layer 21, the electron supply layer 22, and the cap layer 23 through the opening 73 and the third opening 33, and the second opening 32 is formed through the opening 74 and the fourth opening 34 by photoelectrochemical etching. In the photoelectrochemical etching, the electron transit layer 21, the electron supply layer 22, and the cap layer 23 are isotropically etched. As a result, the insulating layer 51 protrudes further away from the second opening 32 than the first edge 31A of the first opening 31, and protrudes further away from the first opening 31 than the second edge 32A of the second opening 32. That is, the insulating layer 51 has a portion that acts as an overhang over the first opening 31 and the second opening 32. In a plan view from a direction perpendicular to the first main surface 10A, the first edge 31A of the first opening 31 is located closer to the second opening 32 than the third edge 33A of the third opening 33, and the second edge 32A of the second opening 32 is located closer to the first opening 31 than the fourth edge 34A of the fourth opening 34.

[0034] Next, as shown in FIGS. 4 to 7, the resist mask 71 is removed, and the source region 24 is formed in the first opening 31, and the drain region 25 is formed in the second opening 32. The source region 24 and the drain region 25 are formed by, for example, MOCVD. FIGS. 4 to 7 sequentially show the epitaxial growth of the source region 24 and the drain region 25. When the source region 24 and the drain region 25 are formed, the temperature of the substrate 10 is set to, for example, about 700° C.

[0035] As shown in FIGS. 4 to 7, polycrystalline GaN deposits 61 are formed on insulating layer 51 in parallel with the epitaxial growth of source region 24 and drain region 25. Although the Ga source material (e.g., trimethylgallium (TMG)) and the N source material (e.g., ammonia (NH)) are consumed in the formation of deposits 61, deposits 61 are formed more slowly than source region 24 and drain region 25. Therefore, the source gas supplied to the upper surface of insulating layer 51 is not easily consumed, and flows toward third opening 33 or fourth opening 34, and is supplied into first opening 31 or second opening 32.

[0036] Furthermore, crystallographically, GaN constituting source region 24 and drain region 25 tends to preferentially grow epitaxially in a direction tilted from first main surface 10A. For example, when first main surface 10A is the C-plane ((0001) plane), the growth rate is highest in the <11-22> direction tilted at approximately 60 degrees from first main surface 10A. On the other hand, source gases have difficulty reaching the portions of first opening 31 and second opening 32 that overlap with the overhanging portions of insulating layer 51.

[0037] Therefore, when the growth rate is compared among the direction perpendicular to first main surface 10A, the direction parallel to first main surface 10A, and the direction tilted from first main surface 10A, the growth rate is lowest in the direction parallel to first main surface 10A and highest in the direction tilted from first main surface 10A. For example, the growth rate in the direction perpendicular to first main surface 10A is about twice the growth rate in the direction parallel to first main surface 10A, and the growth rate in the direction tilted from first main surface 10A is about three times the growth rate in the direction parallel to first main surface 10A.

[0038] The formation of the source region 24 and the drain region 25 is stopped, for example, when the entire lower surfaces 51A and 51B of the insulating layer 51 are covered with the source region 24 and the drain region 25. At this time, a portion of the upper surface 24A of the source region 24 may be located closer to the first main surface 10A of the substrate 10 than the lower surface 51A of the insulating layer 51. The distance between the lower surface 51A of the insulating layer 51 and the upper surface 24A of the source region 24 in the thickness direction of the substrate 10 may be approximately 100 nm at its greatest. Similarly, a portion of the upper surface 25A of the drain region 25 may be located closer to the first main surface 10A of the substrate 10 than the lower surface 51B of the insulating layer 51. The distance between the lower surface 51B of the insulating layer 51 and the upper surface 25A of the drain region 25 in the thickness direction of the substrate 10 may be approximately 100 nm at its greatest.

[0039] After the source region 24 and the drain region 25 are formed, the deposit 61 on the insulating layer 51 is removed as shown in Fig. 8. The deposit 61 can be removed using, for example, tetramethyl ammonium hydroxide (TMAH) at a temperature of about 70°C. The source region 24 and the drain region 25 may be slightly etched by TMAH.

[0040] 9, a source electrode 41 is formed on the source region 24, and a drain electrode 42 is formed on the drain region 25. The source electrode 41 and the drain electrode 42 can be formed by, for example, evaporation, lift-off, and alloying heat treatment. The source electrode 41 and the drain electrode 42 include, for example, a Ta film and an Al film. The source electrode 41 and the drain electrode 42 make ohmic contact with the 2DEG 29 via the source region 24 and the drain region 25, respectively.

[0041] 10, a seventh opening 52 is formed in the insulating layer 51. The seventh opening 52 is formed by, for example, RIE using a resist mask (not shown). A reactive gas containing F is used to etch the insulating layer 51. Next, a gate electrode 43 is formed on the insulating layer 51. The gate electrode 43 can be formed by, for example, vapor deposition and lift-off. The gate electrode 43 includes, for example, a Ni film and an Au film.

[0042] 11, an insulating layer 53 is formed to cover the gate electrode 43, the source electrode 41, and the drain electrode 42. The insulating layer 53 can be formed by, for example, a VD method. Next, a fifth opening 35 exposing a portion of the source electrode 41 and a sixth opening 36 exposing a portion of the drain electrode 42 are formed in the insulating layer 53. The fifth opening 35 and the sixth opening 36 are formed by, for example, RIE using a resist mask (not shown).

[0043] Thereafter, wiring and the like are formed as necessary. In this manner, the semiconductor device 100 including the GaN-HEMT can be manufactured.

[0044] According to this manufacturing method, in a plan view perpendicular to first main surface 10A, first edge 31A of first opening 31 is located closer to second opening 32 than third edge 33A of third opening 33, and second edge 32A of second opening 32 is located closer to first opening 31 than fourth edge 34A of fourth opening 34. Therefore, when source region 24 and drain region 25 are formed as regrown layers, the generation of abnormally grown portions in the reference example described below is suppressed, and the shapes of source region 24 and drain region 25 can be easily controlled.

[0045] In plan view perpendicular to the first main surface 10A, the distance L1 between the first edge 31A and the third edge 33A is preferably 0.2 μm or more and 1.5 μm or less, and the distance L2 between the second edge 32A and the fourth edge 34A is preferably 0.2 μm or more and 1.5 μm or less. If the distances L1 and L2 are less than 0.2 μm, it may be difficult to suppress abnormal growth, as described below. If the distances L1 and L2 are greater than 1.5 μm, it may be difficult to adjust the etching amount in photoelectrochemical etching. Each of the distances L1 and L2 is more preferably 0.5 μm or more and 1.0 μm or less, and even more preferably 0.5 μm or more and 0.6 μm or less.

[0046] Here, a reference example will be described for comparison with the first embodiment. Figures 12 to 15 are cross-sectional views showing a method for manufacturing a semiconductor device according to the reference example.

[0047] 12 , the processes up to the formation of the resist mask 71 are performed in the same manner as in the first embodiment. Next, a third opening 33 and a fourth opening 34 are formed in the insulating layer 51 by RIE. Furthermore, an opening 131 is formed in the electron transit layer 21, the electron supply layer 22, and the cap layer 23 through the opening 73 and the third opening 33, and an opening 132 is formed through the opening 74 and the fourth opening 34 by RIE. The formation of the openings 131 and 132 is stopped midway through the electron transit layer 21, and the openings 131 and 132 are formed so as not to reach the substrate 10. A reactive gas containing chlorine (Cl) is used to etch the electron transit layer 21, the electron supply layer 22, and the cap layer 23.

[0048] Because RIE is anisotropic etching, in a plan view from a direction perpendicular to first main surface 10A, edge 131A of opening 131 is aligned with third edge 33A of third opening 33, and edge 132A of opening 132 is aligned with fourth edge 34A of fourth opening 34. In other words, unlike the first embodiment, no portion that serves as an overhang for first opening 31 and second opening 32 is formed in insulating layer 51. Therefore, substantially, bottom 131B and side surface of opening 131 are perpendicular to each other, and bottom 132B and side surface of opening 132 are perpendicular to each other.

[0049] 13, the resist mask 71 is removed, and the source region 24 is formed in the opening 131, and the drain region 25 is formed in the opening 132. The source region 24 and the drain region 25 are formed by, for example, MOCVD. As in the first embodiment, polycrystalline GaN deposits 61 are deposited on the insulating layer 51 in parallel with the epitaxial growth of the source region 24 and the drain region 25.

[0050] In the reference example, the source gas supplied to the upper surface of the insulating layer 51 is also less likely to be consumed, and is supplied into the opening 131 or 132. However, in the reference example, unlike the first embodiment, the insulating layer 51 does not have any portions that act as overhangs over the openings 131 and 132. Therefore, the source region 24 and the drain region 25 grow preferentially near the side surfaces of the openings 131 and 132, and the source region 24 grows to include the abnormal growth portion 124 near the insulating layer 51, while the drain region 25 grows to include the abnormal growth portion 125 near the insulating layer 51. The heights of the abnormal growth portions 124 and 125 can be approximately 100 μm.

[0051] After the source region 24 and the drain region 25 are formed, the deposit 61 on the insulating layer 51 is removed as shown in FIG. 14. The deposit 61 can be removed using, for example, TMAH at a temperature of about 70° C. Although the abnormal growth portions 124 and 125 can also be etched by TMAH, the abnormal growth portions 124 and 125 do not disappear.

[0052] 15, a source electrode 41 is formed on the source region 24, and a drain electrode 42 is formed on the drain region 25. The source electrode 41 and the drain electrode 42 can be formed by, for example, evaporation, lift-off, and alloying heat treatment. The source electrode 41 and the drain electrode 42 make ohmic contact with the 2DEG 29 via the source region 24 and the drain region 25, respectively.

[0053] Thereafter, similarly to the first embodiment, the processes from the formation of the seventh opening 52 in the insulating layer 51 onwards are carried out, thereby completing the manufacture of the semiconductor device.

[0054] However, in the reference example, as shown in FIG. 15 , the source region 24 includes an abnormal growth portion 124, and the drain region 25 includes an abnormal growth portion 125, making it difficult to control the shapes of the regrown layers, the source region 24 and the drain region 25. When the source region 24 includes the abnormal growth portion 124, the contact resistance between the source electrode 41 and the source region 24 is likely to vary. Similarly, when the drain region 25 includes the abnormal growth portion 125, the contact resistance between the drain electrode 42 and the drain region 25 is likely to vary. This may result in failure to obtain desired characteristics. In particular, when the abnormal growth portion 124 penetrates the source electrode 41 or the abnormal growth portion 125 penetrates the drain electrode 42, the characteristics are likely to vary.

[0055] In contrast, in the first embodiment, the insulating layer 51 has portions that act as overhangs over the first opening 31 and the second opening 32, thereby suppressing the generation of abnormal growth portions 124 and 125 and making it easier to control the shapes of the source region 24 and the drain region 25, which are regrown layers.

[0056] (First Modification of the First Embodiment) Next, a description will be given of a first modified example of the first embodiment. Figures 16 and 17 are cross-sectional views showing a method for manufacturing a semiconductor device according to the first modified example of the first embodiment.

[0057] In the first modification of the first embodiment, similarly to the first embodiment, processing up to the formation of the source region 24 and the drain region 25 is performed (see FIG. 7 ). Next, as shown in FIG. 16 , deposit 61 on insulating layer 51 is removed. Deposit 61 can be removed using TMAH at a temperature of about 70° C. In this case, in the first modification, a portion of the portion of insulating layer 51 covering lower surface 51A of source region 24 is removed, and a portion of the portion of insulating layer 51 covering lower surface 51B of drain region 25 is removed. Therefore, a portion of lower surface 51A of insulating layer 51 is exposed in first opening 31, and a portion of lower surface 51B of insulating layer 51 is exposed in second opening 32. Furthermore, the distance between lower surface 51A of insulating layer 51 and upper surface 24A of source region 24 in the thickness direction of substrate 10 increases, and may be approximately 200 nm at its greatest. Similarly, the distance between the lower surface 51B of the insulating layer 51 and the upper surface 25A of the drain region 25 in the thickness direction of the substrate 10 may increase to about 100 nm at its largest.

[0058] 17, a source electrode 41 is formed on the source region 24, and a drain electrode 42 is formed on the drain region 25. The source electrode 41 and the drain electrode 42 can be formed by, for example, burying a metal under the eaves of the insulating layer 51 by vapor deposition, sputtering, and plating, followed by lift-off and alloying heat treatment. The source electrode 41 and the drain electrode 42 make ohmic contact with the 2DEG 29 via the source region 24 and the drain region 25, respectively.

[0059] Thereafter, similarly to the first embodiment, the processes from the formation of the seventh opening 52 in the insulating layer 51 onwards are carried out, whereby the semiconductor device 101 according to the first modification of the first embodiment can be manufactured.

[0060] In the semiconductor device 101 according to the first modification of the first embodiment, part of the source electrode 41 contacts part of the lower surface 51A of the insulating layer 51, and part of the drain electrode 42 contacts part of the lower surface 51B of the insulating layer 51.

[0061] The first modification of the first embodiment also provides the same effects as the first embodiment.

[0062] (Second Modification of the First Embodiment) Next, a description will be given of a second modified example of the first embodiment. Figures 18 and 19 are cross-sectional views showing a method for manufacturing a semiconductor device according to the second modified example of the first embodiment.

[0063] In the second modified example of the first embodiment, a first opening 31 and a second opening 32 are formed by photoelectrochemical etching in the same manner as in the first embodiment (see FIG. 3). Next, the resist mask 71 is removed, and a source region 24 is formed in the first opening 31, and a drain region 25 is formed in the second opening 32. At this time, in the second modified example, as shown in FIG. 18, the formation of the source region 24 and the drain region 25 is stopped after the upper surface 24A of the source region 24 has moved above the lower surface 51A of the insulating layer 51 and the upper surface 25A of the drain region 25 has moved above the lower surface 51B of the insulating layer 51.

[0064] 19, the deposit 61 on the insulating layer 51 is removed. The deposit 61 can be removed using, for example, TMAH at a temperature of about 70° C. The source region 24 and the drain region 25 may be slightly etched by the TMAH.

[0065] Thereafter, similarly to the first embodiment, the processes subsequent to the formation of the source electrode 41 and the drain electrode 42 are carried out, whereby the semiconductor device 102 according to the second modification of the first embodiment can be manufactured.

[0066] In the semiconductor device 102 according to the second modification of the first embodiment, the upper surface 24A of the source region 24 is located above the lower surface 51A of the insulating layer 51, and the upper surface 25A of the drain region 25 is located above the lower surface 51B of the insulating layer 51.

[0067] The second modification of the first embodiment also provides the same effects as the first embodiment.

[0068] (Second embodiment) Next, a second embodiment will be described below with reference to Fig. 20, which is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0069] 20 , in the semiconductor device 200 according to the second embodiment, a first opening 231 for a source is formed in the stacked structure 20 instead of the first opening 31, and a second opening 232 for a drain is formed in place of the second opening 32. The first opening 231 and the second opening 232 reach the substrate 10. Therefore, the first main surface 10A of the substrate 10 forms the bottom 231B of the first opening 231 and the bottom 232B of the second opening 232. The bottom 231B of the first opening 231 and the bottom 232B of the second opening 232 are located deeper toward the substrate 10 than the top surface 21A of the electron transit layer 21.

[0070] The first opening 231 has a first edge 231A on the second opening 232 side, and the second opening 232 has a second edge 232A on the first opening 231 side. In a plan view from a direction perpendicular to the first main surface 10A, the first edge 231A of the first opening 231 is located closer to the second opening 232 than the third edge 33A of the third opening 33, and the second edge 232A of the second opening 232 is located closer to the first opening 231 than the fourth edge 34A of the fourth opening 34. In other words, the insulating layer 51 has a portion that forms an overhang over the first opening 231 and the second opening 232. The insulating layer 51 protrudes further from the first edge 231A of the first opening 231 in a direction away from the second opening 232, and protrudes further from the second edge 232A of the second opening 232 in a direction away from the first opening 231.

[0071] The first opening 231 has a first side wall surface 231C on the second opening 232 side, and the second opening 232 has a second side wall surface 232C on the first opening 231 side. The first side wall surface 231C and the second side wall surface 232C are inclined from a plane perpendicular to the first main surface 10A of the substrate 10. The first side wall surface 231C is inclined from a plane perpendicular to the first main surface 10A of the substrate 10 so that the first opening 231 widens as it approaches the substrate 10. The second side wall surface 232C is inclined from a plane perpendicular to the first main surface 10A of the substrate 10 so that the second opening 232 widens as it approaches the substrate 10. Therefore, the portions of the electron transit layer 21, the electron supply layer 22, and the cap layer 23 between the first opening 231 and the second opening 232 have a cross-sectional shape that is reverse tapered toward the substrate 10.

[0072] The other configurations are the same as those in the first embodiment.

[0073] In the semiconductor device 200, the 2DEG 29 is present near the top surface 21A of the electron transit layer 21. The source electrode 41 is in ohmic contact with the 2DEG 29 via the source region 24, and the drain electrode 42 is in ohmic contact with the 2DEG 29 via the drain region 25. Therefore, the presence of the source region 24 and the drain region 25 reduces the contact resistance, which is the resistance component from each of the source electrode 41 and the drain electrode 42 to the 2DEG 29.

[0074] Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. Figures 21 to 23 are cross-sectional views showing the method for manufacturing the semiconductor device according to the second embodiment.

[0075] First, as in the first embodiment, processes up to the formation of a resist mask 71 are performed as shown in FIG. 21 . Next, a third opening 33 and a fourth opening 34 are formed in the insulating layer 51 by RIE. Next, a first opening 231 is formed in the electron transit layer 21, the electron supply layer 22, and the cap layer 23 through the opening 73 and the third opening 33, and a second opening 232 is formed through the opening 74 and the fourth opening 34 by RIE. A reactive gas containing chlorine (Cl) is used to etch the electron transit layer 21, the electron supply layer 22, and the cap layer 23. In this embodiment, unlike the reference example, the first opening 231 and the second opening 232 are formed so as to reach the substrate 10. Furthermore, even after the first main surface 10A of the substrate 10 is exposed, the supply of the reactive gas is not stopped immediately, but is continued. The substrate 10 is not etched even when the supply of the reactive gas is continued, and the concentration of the reactive gas increases near the first main surface 10A. As a result, etching of the electron transit layer 21, the electron supply layer 22, and the cap layer 23 progresses in a direction parallel to the first main surface 10A (lateral direction). Therefore, the insulating layer 51 protrudes further away from the second opening 232 than the first edge 231A of the first opening 231, and protrudes further away from the first opening 231 than the second edge 232A of the second opening 232. In other words, the insulating layer 51 has portions that act as overhangs over the first opening 231 and the second opening 232.

[0076] 22, similarly to the first embodiment, the resist mask 71 is removed, and the source region 24 is formed in the first opening 231, and the drain region 25 is formed in the second opening 232. Then, similarly to the first embodiment, the deposit 61 generated during the formation of the source region 24 and the drain region 25 is removed.

[0077] 23, a source electrode 41 is formed on the source region 24, and a drain electrode 42 is formed on the drain region 25. The source electrode 41 and the drain electrode 42 can be formed by, for example, evaporation, lift-off, and alloying heat treatment. The source electrode 41 and the drain electrode 42 make ohmic contact with the 2DEG 29 via the source region 24 and the drain region 25, respectively.

[0078] Thereafter, similarly to the first embodiment, the processes from the formation of the seventh opening 52 in the insulating layer 51 onwards are carried out, whereby the semiconductor device 200 according to the second embodiment can be manufactured.

[0079] The second embodiment also provides the same effects as the first embodiment.

[0080] In the second embodiment, a material that is resistant to reactive gases containing chlorine is used as the material of the substrate 10. Therefore, the substrate 10 may be a sapphire substrate.

[0081] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0082] 10: Circuit board 10A: First main surface 20: Laminated structure 21: Electron transit layer 21A:Top surface 22: Electron supply layer 23: Cap layer 24: Source area 24A:Top surface 25: Drain region 25A:Top surface 31: First opening 31A: First Edge 31B: Bottom 32: Second opening 32A: Second Edge 32B: Bottom 33: Third opening 33A: Third Edge 34: 4th opening 34A: 4th Edge 35: 5th opening 36: 6th opening 41: Source electrode 42: Drain electrode 43: Gate electrode 51: Insulating layer 51A, 51B: Bottom surface 52: 7th opening 53: Insulating layer 61: Sediment 71: Resist mask 73, 74: Opening 100, 101, 102, 200: semiconductor device 124, 125: Abnormal growth area 131, 132: Opening 131A, 132A: Edge 131B, 132B: Bottom 231: First opening 231A: First Edge 231B: Bottom 231C: 1st side wall surface 232: Second opening 232A: Second Edge 232B: Bottom 232C: Second side wall

Claims

1. a substrate having a first major surface; a semiconductor layer provided on the first major surface of the substrate; an insulating layer provided on the semiconductor layer; a source electrode and a drain electrode provided on the semiconductor layer; a gate electrode provided on the insulating layer; and The semiconductor layer is an electron transit layer provided above the substrate and having a first upper surface; an electron supply layer provided above the electron transit layer; and a first opening and a second opening are formed in the electron supply layer and the electron transit layer; a third opening connected to the first opening and a fourth opening connected to the second opening are formed in the insulating layer; the first opening has a first edge on the second opening side; the second opening has a second edge on the first opening side; the third opening has a third edge on the fourth opening side, the fourth opening has a fourth edge on the third opening side, a bottom of the first opening and a bottom of the second opening are located deeper than the first upper surface toward the substrate; The semiconductor layer further comprises: a source region containing impurities of a first conductivity type and provided in the first opening; a drain region containing impurities of the first conductivity type and provided in the second opening; and the source electrode is provided on the source region; the drain electrode is provided on the drain region; In a plan view from a direction perpendicular to the first main surface, the first edge of the first opening is located closer to the second opening than the third edge of the third opening; the second edge of the second opening is located closer to the first opening than the fourth edge of the fourth opening; the first edge is between the gate electrode and the third edge; the second edge is between the gate electrode and the fourth edge; a portion of the source region overlaps with the insulating layer; The semiconductor device has a portion of the drain region overlapping with the insulating layer.

2. In a plan view from a direction perpendicular to the first main surface, a distance between the first edge and the third edge is 0.2 μm or more and 1.5 μm or less; The semiconductor device according to claim 1 , wherein the distance between the second edge and the fourth edge is not less than 0.2 μm and not more than 1.5 μm.

3. a portion of the upper surface of the source region contacts a portion of the lower surface of the insulating layer; 3. The semiconductor device according to claim 1, wherein a part of the upper surface of the drain region is in contact with another part of the lower surface of the insulating layer.

4. 4. The semiconductor device according to claim 1, wherein the gate electrode forms a Schottky contact with the semiconductor layer.

5. forming an electron transit layer having a first upper surface above a first main surface of a substrate having the first main surface; forming an electron supply layer above the electron transit layer; forming an insulating layer above the electron supply layer; forming a third opening and a fourth opening in the insulating layer; forming a first opening connected to the third opening and a second opening connected to the fourth opening in the electron supply layer and the electron transit layer; forming a source region containing impurities of a first conductivity type in the first opening and a drain region containing impurities of the first conductivity type in the second opening; forming a source electrode on the source region and a drain electrode on the drain region; forming a gate electrode on the insulating layer; and the first opening has a first edge on the second opening side; the second opening has a second edge on the first opening side; the third opening has a third edge on the fourth opening side, the fourth opening has a fourth edge on the third opening side, a bottom of the first opening and a bottom of the second opening are located deeper than the first upper surface toward the substrate; In a plan view from a direction perpendicular to the first main surface, the first edge of the first opening is located closer to the second opening than the third edge of the third opening; the second edge of the second opening is located closer to the first opening than the fourth edge of the fourth opening; the first edge is between the gate electrode and the third edge; the second edge is between the gate electrode and the fourth edge; a portion of the source region overlaps with the insulating layer; A method for manufacturing a semiconductor device, wherein a portion of the drain region overlaps with the insulating layer.

6. forming a mask on the insulating layer between the step of forming the insulating layer and the step of forming the third opening and the fourth opening; the step of forming the third opening and the fourth opening includes a step of reactive ion etching the insulating layer using the mask; 6. The method for manufacturing a semiconductor device according to claim 5, wherein the step of forming the first opening and the second opening comprises a step of photoelectrochemically etching the electron supply layer and the electron transit layer using the mask.

7. forming a mask on the insulating layer between the step of forming the insulating layer and the step of forming the third opening and the fourth opening; the step of forming the third opening and the fourth opening includes a step of reactive ion etching the insulating layer using the mask; the step of forming the first opening and the second opening includes a step of performing reactive ion etching on the electron supply layer and the electron transit layer using the mask; 6. The method for manufacturing a semiconductor device according to claim 5, wherein the reactive ion etching of the electron supply layer and the electron transit layer continues supplying reactive gas after the first main surface of the substrate is exposed.

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