Semiconductor Devices

Abstract

To obtain a semiconductor device with reduced recovery loss in the diode region of RC-IGBTs.SOLUTION: A semiconductor device according to the present disclosure is a RC-IGBT in which an IGBT region 10 and a diode region 20 are provided adjacent to each other. A diode region 20 has a p-type anode layer 25 provided on the first major surface side than the n- type drift layer 1, a p-type contact layer 24 provided on the first major surface side of the p-type anode layer 25 and on the surface layer on the first major surface side of the semiconductor substrate and connected to the emitter electrode 6, and a n+-type cathode layer 26 provided on the surface layer on the second main surface side of the semiconductor substrate. The p-type contact layer 24 contains aluminum as a p-type impurity, and the thickness of the p-type contact layer 24 is smaller than the thickness of the n+ type source layer 13 provided in the IGBT region 10.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, a semiconductor device called an RC-IGBT (Reverse Conducting IGBT) has been proposed, which is a semiconductor device in which an insulated gate bipolar transistor (IGBT) and a freewheeling diode are formed on a single semiconductor substrate. In such a semiconductor device, in order to reduce the contact resistance between the surface electrode and the anode in the anode region of the diode, a p-type semiconductor with a high impurity concentration is formed on the surface layer of the anode. + A mold contact layer is provided (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-192597 Summary of the Invention [Problem to be solved by the invention]

[0004] However, p + When the contact layer is provided in the anode portion of the diode region, the amount of holes injected from the anode portion increases during diode operation, resulting in an increase in recovery loss.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device in which the recovery loss in the diode region of an RC-IGBT is reduced. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure is a semiconductor device in which an insulated gate bipolar transistor region and a diode region are provided adjacent to each other in a semiconductor substrate having an n-type drift layer between a first main surface and a second main surface opposite the first main surface, and an emitter electrode is provided on the first main surface of the semiconductor substrate, and the insulated gate bipolar transistor region includes a p-type base layer provided closer to the first main surface than the drift layer, an n-type source layer selectively provided on the first main surface side of the base layer and in a surface layer of the semiconductor substrate on the first main surface side, and an n-type source layer connected to the emitter electrode and provided on the first main surface side of the base layer in a region of the surface layer of the semiconductor substrate on the first main surface side where the source layer is not provided. a p-type first contact layer, a gate trench insulating film provided on the inner surface of a trench that penetrates the base layer and reaches the drift layer, a gate trench electrode provided in the trench via the gate trench insulating film, and a p-type collector layer provided in a surface layer on the second main surface side of the semiconductor substrate; and the diode region is provided with a p-type anode layer provided closer to the first main surface than the drift layer, a p-type second contact layer that is provided on the first main surface side of the anode layer and in a surface layer on the first main surface side of the semiconductor substrate and connected to the emitter electrode, and an n-type cathode layer provided in a surface layer on the second main surface side of the semiconductor substrate, and the second contact layer contains aluminum as a p-type impurity. The first contact layer contains aluminum as a p-type impurity, and the thickness of the first contact layer is 1 / 2 or less of the thickness of the source layer. It is characterized by: [Effects of the Invention]

[0007] The semiconductor device according to the present disclosure has an advantage that a semiconductor device with reduced recovery loss in the diode region can be obtained because the second contact layer provided in the diode region of the RC-IGBT contains aluminum as a p-type impurity. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 4 is a plan view showing another configuration of the semiconductor device according to the first embodiment. [Figure 3]2 is a partially enlarged plan view showing the configuration of an IGBT region of the semiconductor device of the first embodiment. FIG. [Figure 4] 2 is a cross-sectional view taken along line AA showing the configuration of an IGBT region of the semiconductor device of the first embodiment. FIG. [Figure 5] 1 is a BB cross-sectional view showing the configuration of an IGBT region of the semiconductor device of the first embodiment. [Figure 6] 2 is a partially enlarged plan view showing the configuration of a diode region of the semiconductor device of the first embodiment. FIG. [Figure 7] 2 is a cross-sectional view taken along line CC showing the configuration of a diode region of the semiconductor device of the first embodiment. FIG. [Figure 8] 2 is a cross-sectional view taken along the line DD showing the configuration of a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 9] GG cross-sectional view showing the configuration of the boundary between the IGBT region and the diode region of the semiconductor device of the first embodiment. FIG. [Figure 10] 2 is a cross-sectional view showing the configuration of a termination region of the semiconductor device of the first embodiment. FIG. [Figure 11] 1A to 1C are first diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] FIG. 10 is a second diagram showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] FIG. 10 is a third diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] FIG. 4 is a fourth diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] FIG. 5 is a fifth diagram showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] FIG. 6 is a sixth diagram showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] GG cross-sectional view showing the configuration of the boundary between the IGBT region and the diode region of the semiconductor device of the second embodiment. [Figure 18] FIG. 10 is a cross-sectional view taken along line GG showing the configuration of the boundary between the IGBT region and the diode region in a modified example of the semiconductor device according to the second embodiment. [Figure 19]FIG. 11 is a cross-sectional view taken along line GG showing the configuration of the boundary between the IGBT region and the diode region in a modified example of the semiconductor device according to the third embodiment. [Figure 20] FIG. 10 is a cross-sectional view taken along line GG showing the configuration of the boundary between the IGBT region and the diode region in a modified example of the semiconductor device according to the fourth embodiment. [Figure 21] FIG. 13 is a cross-sectional view taken along line GG showing the configuration of the boundary between the IGBT region and the diode region in a modified example of the semiconductor device according to the fifth embodiment. [Figure 22] FIG. 20 is a cross-sectional view taken along line GG showing the configuration of the boundary between the IGBT region and the diode region in a modified example of the semiconductor device according to the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. In the following drawings, identical or corresponding parts are designated by the same reference numerals, and their description will not be repeated. In the following description, terms indicating specific directions such as "upper" or "lower" may be used, but these terms are used for convenience and do not relate to the directions in actual practice.

[0010] In the following description, n and p indicate the conductivity type of the semiconductor. - indicates that the impurity concentration is lower than n, and n + indicates that the impurity concentration is higher than n. Similarly, p - indicates that the impurity concentration is lower than p, and p + indicates that the impurity concentration is higher than p.

[0011] Embodiment 1 The semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.

[0012] First, the overall configuration of the semiconductor device of the first embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a plan view showing a semiconductor device 100 which is an RC-IGBT. Fig. 2 is a plan view showing a semiconductor device 101 which is an RC-IGBT with another configuration.

[0013] The semiconductor device 100 shown in Fig. 1 has IGBT regions 10 and diode regions 20 arranged side by side in a stripe pattern, and may be simply called a "stripe type." The semiconductor device 101 shown in Fig. 2 has a plurality of diode regions 20 arranged vertically and horizontally, and the IGBT regions 10 are arranged around the diode regions 20, and may be simply called an "island type."

[0014] In FIG. 1 , a semiconductor device 100 includes an IGBT region 10 and a diode region 20 within the semiconductor device. The IGBT region 10 and the diode region 20 extend from one end to the other end of the semiconductor device 100 and are arranged in alternating stripes in a direction perpendicular to the extension direction of the IGBT region 10 and the diode region 20. In FIG. 1 , three IGBT regions 10 and two diode regions are shown, and all of the diode regions 20 are sandwiched between the IGBT regions 10. However, the number of IGBT regions 10 and the diode region 20 is not limited to this. The number of IGBT regions 10 may be three or more or less, and the number of diode regions 20 may be two or more or less. Furthermore, the positions of the IGBT regions 10 and the diode regions 20 in FIG. 1 may be interchanged, or all of the IGBT regions 10 may be sandwiched between the diode regions 20. Furthermore, one IGBT region 10 and one diode region 20 may be provided adjacent to each other.

[0015] As shown in FIG. 1 , a pad region 40 is provided adjacent to the IGBT region 10 on the lower side of the page. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 100 is provided. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. A termination region 30 is provided around the combined cell region and pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A known breakdown voltage maintaining structure can be appropriately selected and provided in the termination region 30. The breakdown voltage maintaining structure may be configured, for example, by providing a field limiting ring (FLR) on the first main surface side, which is the front surface side of the semiconductor device 100, in which the cell region is surrounded by a p-type termination well layer of a p-type semiconductor, or a variation of lateral doping (VLD) on which the cell region is surrounded by a p-type well layer with a concentration gradient. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 100. In addition, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and an IGBT cell or a diode cell may be provided in the pad region 40.

[0016] The control pad 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, or temperature sense diode pads 41d and 41e. The current sense pad 41a is a control pad for detecting a current flowing in a cell region of the semiconductor device 100, and is electrically connected to a portion of the IGBT cells or diode cells in the cell region so that when a current flows in the cell region of the semiconductor device 100, a current that is one-several to one-tens-of-thousandth of the current flowing in the entire cell region flows.

[0017] The Kelvin emitter pad 41b and gate pad 41c are control pads to which a gate drive voltage is applied to turn the semiconductor device 100 on and off. The Kelvin emitter pad 41b is electrically connected to the p-type base layer of the IGBT cell, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer may be electrically connected via a p-type contact layer. The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 100. The temperature of the semiconductor device 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0018] 2, the semiconductor device 101 includes an IGBT region 10 and a diode region 20 within a single semiconductor device. A plurality of diode regions 20 are arranged side by side in both the vertical and horizontal directions within the semiconductor device, and the diode regions 20 are surrounded by the IGBT region 10. In other words, a plurality of diode regions 20 are arranged in an island shape within the IGBT region 10. In FIG. 2, the diode regions 20 are shown arranged in a matrix shape with four columns in the left-right direction of the page and two rows in the upper-right direction of the page, but the number and arrangement of the diode regions 20 are not limited to this. It is sufficient that one or a plurality of diode regions 20 are arranged in a scattered manner within the IGBT region 10, and each diode region 20 is surrounded by the IGBT region 10.

[0019] 2, a pad region 40 is provided adjacent to the lower side of the IGBT region 10, and a termination region 30 is provided around the combined region of the pad region 40, the IGBT region 10, and the cell region including the diode region 20 to maintain the breakdown voltage of the semiconductor device 101. The structures of the pad region 40 and the termination region 30 may be similar to those of the semiconductor device 100 shown in FIG.

[0020] Next, the configuration of the IGBT region of the semiconductor device of the first embodiment will be described in detail with reference to FIGS. 3 to 5. FIG. 3 is a partially enlarged plan view showing the configuration of the IGBT region of the semiconductor device, which is an RC-IGBT. Also, FIGS. 4 and 5 are cross-sectional views showing the configuration of the IGBT region of the semiconductor device, which is an RC-IGBT. FIG. 3 is an enlarged view of the region surrounded by dashed line 82 in semiconductor device 100 shown in FIG. 1 or semiconductor device 101 shown in FIG. 2. FIG. 4 is a cross-sectional view taken along dashed line AA of semiconductor device 100 or semiconductor device 101 shown in FIG. 3, and FIG. 5 is a cross-sectional view taken along dashed line BB of semiconductor device 100 or semiconductor device 101 shown in FIG. 3.

[0021] 3, active trench gates 11 and dummy trench gates 12 are provided in a striped pattern in the IGBT region 10. In the semiconductor device 100, the active trench gates 11 and dummy trench gates 12 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 is the longitudinal direction of the active trench gates 11 and dummy trench gates 12. On the other hand, in the semiconductor device 101, there is no particular distinction between the longitudinal direction and the lateral direction of the IGBT region 10, but the longitudinal direction of the active trench gates 11 and dummy trench gates 12 may be the left-right direction on the paper, or the vertical direction on the paper may be the longitudinal direction of the active trench gates 11 and dummy trench gates 12.

[0022] The active trench gate 11 is configured by providing a gate trench electrode 11a in a trench formed in the semiconductor substrate with a gate trench insulating film 11b interposed therebetween. The dummy trench gate 12 is configured by providing a dummy trench electrode 12a in a trench formed in the semiconductor substrate with a dummy trench insulating film 12b interposed therebetween. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100 or the semiconductor device 101.

[0023] n + The source layer 13 is provided on both sides of the active trench gate 11 in the width direction so as to contact the gate trench insulating film 11b. + The source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+17 / cm 3 ~1.0E+20 / cm 3 n + The type source layers 13 are provided alternately with p-type contact layers 14 along the extension direction of the active trench gates 11. The p-type contact layers 14 are also provided between two adjacent dummy trench gates 12. The p-type contact layers 14 are semiconductor layers containing aluminum as a p-type impurity, and the concentration of aluminum as a p-type impurity is 1.0E+12 / cm 3 ~1.0E+18 / cm 3 It is desirable that:

[0024] As shown in FIG. 3 , the IGBT region 10 of the semiconductor device 100 or 101 has a configuration in which three active trench gates 11 are lined up next to three dummy trench gates 12, and three active trench gates 11 are lined up next to three dummy trench gates 12. In this manner, the IGBT region 10 has a configuration in which sets of active trench gates 11 and sets of dummy trench gates 12 are alternately arranged. In FIG. 3 , the number of active trench gates 11 included in one set of active trench gates 11 is three, but it may be one or more. Furthermore, the number of dummy trench gates 12 included in one set of dummy trench gates 12 may be one or more, and the number of dummy trench gates 12 may be zero. In other words, all trenches provided in the IGBT region 10 may be active trench gates 11.

[0025] 4 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 taken along the dashed line AA in FIG. 3, and is a cross-sectional view of the IGBT region 10. The semiconductor device 100 or the semiconductor device 101 is an n-type semiconductor device made of a semiconductor substrate. - The n-type drift layer 1 is -The drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+12 / cm 3 ~1.0E+15 / cm 3 and n - The concentration of n-type impurities in the n-type drift layer 1 is lower than the concentration of p-type impurities in the p-type contact layer 14. In FIG. + The n-type source layer 13 and the p-type contact layer 14 extend to the p-type collector layer 16. + The upper ends of the p-type source layer 13 and the p-type contact layer 14 on the paper are called the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper are called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. In the IGBT region 10, which is the cell region, the semiconductor device 100 has an n-type interlayer insulating film between the first main surface and the second main surface opposite to the first main surface. - The semiconductor device has a type drift layer 1.

[0026] As shown in FIG. 4, in the IGBT region 10, n - On the first main surface side of the n-type drift layer 1, - The n-type carrier accumulation layer 2 has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+13 / cm 3 ~1.0E+17 / cm 3 In the semiconductor device 100 or 101, the n-type carrier accumulation layer 2 is not provided, and the n-type carrier accumulation layer 2 region shown in FIG. - The n-type drift layer 1 may be provided. By providing the n-type carrier accumulation layer 2, it is possible to reduce the current loss when a current flows through the IGBT region 10. - The combined layer and the type drift layer 1 may be called a drift layer.

[0027] The n-type carrier accumulation layer 2 is -n-type impurities are ion-implanted into the semiconductor substrate that constitutes the n-type drift layer 1, and then annealed to convert the implanted n-type impurities into n-type impurities. - The dopant is formed by diffusing it into the semiconductor substrate, which is the type drift layer 1.

[0028] A p-type base layer 15 is provided on the first main surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0E+12 / cm 3 ~1.0E+18 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. On the first main surface side of the p-type base layer 15, there is provided an n-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11. + A p-type source layer 13 is provided in the n-type region, and a p-type contact layer 14 is provided in the remaining region. + The p-type source layer 13 and the p-type contact layer 14 form a first main surface of the semiconductor substrate. The p-type contact layer 14 is a region having a higher concentration of p-type impurities than the p-type base layer 15. When it is necessary to distinguish between the p-type contact layer 14 and the p-type base layer 15, they may be referred to individually, or the p-type contact layer 14 and the p-type base layer 15 may be collectively referred to as the p-type base layer.

[0029] 3 and 4, the p-type contact layer 14 is a semiconductor layer formed on the surface layer between the trenches and containing aluminum as a p-type impurity. By containing aluminum as a p-type impurity, the p-type contact layer 14 + The thickness can be made smaller than that of the n-type source layer 13. + It is desirable that the thickness of the p-type contact layer 14 is half or less than the thickness of the p-type source layer 13. The aluminum impurity concentration of the p-type contact layer 14 is 1.0E+12 / cm 3 ~1.0E+18 / cm 3As a method for doping aluminum, aluminum ions may be implanted from the first main surface side, or an electrolyte containing aluminum may be used. Note that it is sufficient that the p-type contact layer 14 is formed on at least a part of the surface layer between the trenches.

[0030] In addition, the semiconductor device 100 or the semiconductor device 101 has n - On the second main surface side of the n-type drift layer 1, - The n-type buffer layer 3 has a higher concentration of n-type impurities than the p-type drift layer 1. The n-type buffer layer 3 is provided to prevent a depletion layer extending from the p-type base layer 15 toward the second main surface from punching through when the semiconductor device 100 is in an off state. The n-type buffer layer 3 is doped with, for example, phosphorus (P) or protons (H + ) may be injected to form phosphorus (P) and protons (H + The n-type buffer layer 3 may be formed by implanting both n-type impurities. 3 ~1.0E+18 / cm 3 is.

[0031] The semiconductor device 100 or 101 does not have the n-type buffer layer 3, and the n-type buffer layer 3 shown in FIG. - The n-type buffer layer 3 and the n-type drift layer 1 may be provided. - The combined layer and the type drift layer 1 may be called a drift layer.

[0032] In the semiconductor device 100 or 101, a p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3. - A p-type collector layer 16 is provided between the drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0E+16 / cm 3 ~1.0E+20 / cm 3The p-type collector layer 16 forms the second main surface of the semiconductor substrate. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the termination region 30, and the portion of the p-type collector layer 16 provided in the termination region 30 forms a p-type termination collector layer 16a. Furthermore, the p-type collector layer 16 may be provided so that a portion thereof protrudes from the IGBT region 10 into the diode region 20.

[0033] As shown in FIG. 4, the semiconductor device 100 or the semiconductor device 101 has an n-type semiconductor layer extending from the first main surface of the semiconductor substrate through the p-type base layer 15. - A trench is formed in the n-type drift layer 1. A gate trench electrode 11a is provided in the trench via a gate trench insulating film 11b, thereby forming an active trench gate 11. The gate trench electrode 11a is connected to the n-type drift layer 1 via the gate trench insulating film 11b. - The n-type drift layer 1 is opposed to the n-type drift layer 1. A dummy trench electrode 12a is provided in the trench via a dummy trench insulating film 12b, thereby forming a dummy trench gate 12. The dummy trench electrode 12a is connected to the n-type drift layer 1 via the dummy trench insulating film 12b. - The gate trench insulating film 11b of the active trench gate 11 faces the p-type base layer 15 and the n-type drift layer 1. + The active trench gate 11 is in contact with the p-type source layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0034] As shown in FIG. 4, an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4. The barrier metal 5 is preferably formed of titanium (Ti) or a titanium alloy, and may be, for example, a conductor containing titanium, such as titanium nitride, or TiSi, which is an alloy of titanium and silicon (Si). As shown in FIG. 4, the barrier metal 5 is formed of n +ohmic contact with the p-type source layer 13, the p-type contact layer 14, and the dummy trench electrode 12a, + The n-type source layer 13, the p-type contact layer 14 and the dummy trench electrode 12a are electrically connected to the n-type source layer 13, the p-type contact layer 14 and the dummy trench electrode 12a.

[0035] An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 may be formed of an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or may be an electrode consisting of multiple metal films formed by electroless or electrolytic plating on an aluminum alloy electrode. The plating film formed by electroless or electrolytic plating may be, for example, a nickel (Ni) plating film or a copper (Cu) plating film. Forming the emitter electrode 6 from copper or a copper alloy with high mechanical strength, such as a copper plating film, improves the power cycle resistance. The emitter electrode 6 may further have a gold (Au) plating film on the nickel or copper plating film.

[0036] Furthermore, when there is a fine region between adjacent interlayer insulating films 4 where the emitter electrode 6 cannot be filled well, tungsten, which has better filling properties than the emitter electrode 6, may be disposed in the fine region, and the emitter electrode 6 may be provided on the tungsten. + The barrier metal 5 may be provided only on an n-type semiconductor layer such as the n-type source layer 13. The barrier metal 5 and the emitter electrode 6 may be collectively referred to as an emitter electrode. Although FIG. 4 shows a diagram in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, the interlayer insulating film 4 may be formed on the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a may be electrically connected in another cross section.

[0037] Although the semiconductor device of this embodiment has a structure including the barrier metal 5, the semiconductor device may have a structure without the barrier metal 5 and an n +An emitter electrode 6 can also be provided on the p-type source layer 13, the p-type contact layer 14, and the dummy trench electrode 12a. Titanium, which constitutes the barrier metal, has a high energy barrier height against p-type silicon, so in the past, ohmic contact between the barrier metal and the p-type contact layer, which is p-type silicon, was made possible by increasing the impurity concentration of the p-type contact layer. On the other hand, aluminum, which constitutes the emitter electrode, has a lower barrier height against p-type silicon than titanium, so ohmic contact between the emitter electrode and the p-type contact layer, which is p-type silicon, is made possible even with a low p-type impurity concentration.

[0038] A collector electrode 7 is provided on the second main surface side of the p-type collector layer 16. The collector electrode 7 may be made of an aluminum alloy or an aluminum alloy and a plating film, similar to the emitter electrode 6. The collector electrode 7 may also have a different structure from the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0039] 5 is a cross-sectional view of the semiconductor device 100 or 101 taken along dashed line BB in FIG. 3, and is a cross-sectional view of the IGBT region 10. The cross-sectional view taken along dashed line AA in FIG. 4 is a cross-sectional view of the n-type IGBT region 10 provided on the first main surface side of the semiconductor substrate in contact with the active trench gate 11. + The difference is that the n-type source layer 13 is not visible in the cross section taken along the dashed line BB in FIG. + The p-type source layer 13 is selectively provided on the first main surface side of the p-type base layer. Note that the p-type base layer referred to here refers to the p-type base layer 15 and the p-type contact layer 14 collectively.

[0040] Next, the configuration of the diode region of the semiconductor device of the first embodiment will be described in detail with reference to FIGS. 6 to 8. FIG. 6 is a partially enlarged plan view showing the configuration of the diode region of the semiconductor device which is an RC-IGBT. Also, FIGS. 7 and 8 are cross-sectional views showing the configuration of the diode region of the semiconductor device which is an RC-IGBT. FIG. 6 is an enlarged view of the region surrounded by dashed line 83 in semiconductor device 100 or semiconductor device 101 shown in FIG. 1. FIG. 7 is a cross-sectional view taken along dashed line CC of semiconductor device 100 shown in FIG. 6. FIG. 8 is a cross-sectional view taken along dashed line DD of semiconductor device 100 shown in FIG. 6.

[0041] The diode trench gate 21 extends from one end of the diode region 20, which is a cell region, to the other opposing end along the first main surface of the semiconductor device 100 or 101. The diode trench gate 21 is configured by providing a diode trench electrode 21a via a diode trench insulating film 21b in a trench formed in the semiconductor substrate of the diode region 20. The diode trench electrode 21a is connected to the n-type MOS transistor 100 via the diode trench insulating film 21b. - The p-type contact layer 24 faces the p-type drift layer 1. A p-type contact layer 24 and a p-type anode layer 25 are provided between two adjacent diode trench gates 21. The p-type contact layer 24 is a semiconductor layer containing aluminum as a p-type impurity, and the concentration of aluminum as a p-type impurity is 1.0E+12 / cm 3 ~1.0E+18 / cm 3 The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is preferably 1.0E+12 / cm 3 ~1.0E+18 / cm 3 The p-type contact layers 24 and the p-type anode layers 25 are alternately provided in the longitudinal direction of the diode trench gate 21.

[0042] 7 is a cross-sectional view of the semiconductor device 100 or 101 taken along the dashed line CC in FIG. 6, and is a cross-sectional view of the diode region 20. The semiconductor device 100 or 101 has an n-type semiconductor substrate in the diode region 20 as in the IGBT region 10. - The n-type drift layer 1 is formed in the diode region 20. - n-type drift layer 1 and IGBT region 10 - The n-type drift layer 1 is formed integrally with the p-type contact layer 24 and is made of the same semiconductor substrate. + 7, the upper end of the p-type contact layer 24 is the first main surface of the semiconductor substrate, and the n-type cathode layer 26 is the second main surface of the semiconductor substrate. + The lower end of the cathode layer 26 in the drawing is called the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are flush with each other, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are flush with each other.

[0043] As shown in FIG. 7, in the diode region 20, similarly to the IGBT region 10, n - An n-type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, - An n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the diode region 20 have the same configuration as the n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the IGBT region 10. Note that it is not always necessary to provide the n-type carrier accumulation layer 2 in the IGBT region 10 and the diode region 20, and even if the n-type carrier accumulation layer 2 is provided in the IGBT region 10, the diode region 20 may not have the n-type carrier accumulation layer 2. Also, like the IGBT region 10, - The n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as a drift layer.

[0044] A p-type anode layer 25 is provided on the first major surface side of the n-type carrier accumulation layer 2. The p-type anode layer 25 is -The p-type anode layer 25 is provided between the first main surface and the first drift layer 1. The p-type anode layer 25 may have the same p-type impurity concentration as the p-type base layer 15 of the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously. Alternatively, the p-type impurity concentration of the p-type anode layer 25 may be set lower than the p-type impurity concentration of the p-type base layer 15 of the IGBT region 10, thereby reducing the number of holes injected into the diode region 20 during diode operation. Reducing the number of holes injected during diode operation can reduce recovery loss during diode operation.

[0045] A p-type contact layer 24 is provided on the first main surface side of the p-type anode layer 25. The concentration of aluminum as a p-type impurity in the p-type contact layer 24 may be the same as or different from the concentration of aluminum as a p-type impurity in the p-type contact layer 14 of the IGBT region 10. The p-type contact layer 24 constitutes the first main surface of the semiconductor substrate. Note that the p-type contact layer 24 is a region having a higher concentration of p-type impurity than the p-type anode layer 25. When it is necessary to distinguish between the p-type contact layer 24 and the p-type anode layer 25, they may be referred to individually, or the p-type contact layer 24 and the p-type anode layer 25 may be collectively referred to as the p-type anode layer.

[0046] In the diode region 20, an n-type buffer layer 3 is provided on the second main surface side thereof. + A cathode layer 26 is provided. + The cathode layer 26 is an n-type - The n-type drift layer 1 is provided between the n-type drift layer 1 and the second main surface. + The cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+16 / cm 3 ~1.0E+21 / cm 3 As shown in Figure 2, n + The cathode layer 26 is provided on part or all of the diode region 20. + The cathode layer 26 forms the second main surface of the semiconductor substrate. +The p-type impurity is further selectively implanted into the region where the p-type cathode layer 26 is formed, + A part of the region where the p-type cathode layer 26 is formed may be made into a p-type semiconductor to provide a p-type cathode layer.

[0047] As shown in FIG. 7, the diode region 20 of the semiconductor device 100 or the semiconductor device 101 includes an n-type anode layer 25 extending from the first main surface of the semiconductor substrate. - A trench is formed in the diode region 20, reaching the n-type drift layer 1. A diode trench electrode 21a is provided in the trench of the diode region 20 via a diode trench insulating film 21b, thereby forming a diode trench gate 21. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. - The semiconductor layer 1 faces the drift layer 1 .

[0048] As shown in FIG. 7 , a barrier metal 5 is provided on the diode trench electrode 21a and the p-type contact layer 24. The barrier metal 5 is in ohmic contact with the diode trench electrode 21a and the p-type contact layer 24 and is electrically connected to the diode trench electrode and the p-type contact layer 24. The barrier metal 5 may have the same configuration as the barrier metal 5 in the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 in the diode region 20 is formed continuously with the emitter electrode 6 in the IGBT region 10. Note that, as in the case of the IGBT region 10, the diode trench electrode 21a and the p-type contact layer 24 may be in ohmic contact with the emitter electrode 6 without providing the barrier metal 5. Note that, although FIG. 7 illustrates a diagram in which the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected at another cross section.

[0049] n + A collector electrode 7 is provided on the second main surface side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is an n-type + ohmic contact with the n-type cathode layer 26, + The cathode layer 26 is electrically connected to the cathode layer 26 .

[0050] 8 is a cross-sectional view of the semiconductor device 100 or 101 taken along dashed line DD in FIG. 6, and is a cross-sectional view of the diode region 20. It differs from the cross-sectional view taken along dashed line CC shown in FIG. 7 in that the p-type contact layer 24 is not provided between the p-type anode layer 25 and the barrier metal 5, and the p-type anode layer 25 forms the first main surface of the semiconductor substrate. In other words, the p-type contact layer 24 shown in FIG. 7 is selectively provided on the first main surface side of the p-type anode layer 25.

[0051] Here, the boundary region between the IGBT region and the diode region of the semiconductor device of the first embodiment will be described with reference to FIG. 9. FIG. 9 is a cross-sectional view showing the configuration of the boundary between the IGBT region and the diode region of a semiconductor device that is an RC-IGBT. FIG. 9 is a cross-sectional view taken along dashed line GG in the semiconductor device 100 or the semiconductor device 101 shown in FIG. 1. Also, FIG. 9 shows n in the cross section as shown by dashed line AA in FIG. + 1 is a cross-sectional view of a portion having a mold source layer 13. FIG.

[0052] 9, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is provided so as to protrude into the diode region 20 by a distance U1 from the boundary between the IGBT region 10 and the diode region 20. By providing the p-type terminal collector layer 16a so as to protrude into the diode region 20, the n-type terminal collector layer 16a of the diode region 20 can be +The distance between the cathode layer 26 and the active trench gate 11 can be increased, and even when a gate drive voltage is applied to the gate trench electrode 11a during freewheeling diode operation, n + This can prevent current from flowing through the cathode layer 26. The distance U1 may be, for example, 100 μm. Depending on the application of the semiconductor device 100 or 101, which is an RC-IGBT, the distance U1 may be zero or less than 100 μm.

[0053] 9, the p-type contact layer 24 is a semiconductor layer formed on the surface layer between the trenches and containing aluminum as a p-type impurity. By containing aluminum as a p-type impurity, the p-type contact layer 24 + The thickness can be made smaller than that of the n-type source layer 13. + The p-type contact layer 24 preferably has a thickness half that of the p-type source layer 13. As a method for doping aluminum, aluminum ions may be implanted from the first main surface side, or an electrolyte containing aluminum may be used. The p-type contact layer 24 may be formed on at least a portion of the surface layer between the trenches.

[0054] The configuration of the termination region of the semiconductor device of the first embodiment will be described with reference to Fig. 10. Fig. 10 is a cross-sectional view showing the configuration of the termination region of a semiconductor device that is an RC-IGBT. Fig. 10(a) is a cross-sectional view taken along dashed line EE in Fig. 1 or 2, and is a cross-sectional view from the IGBT region 10 to the termination region 30. Fig. 10(b) is a cross-sectional view taken along dashed line FF in Fig. 1, and is a cross-sectional view from the diode region 20 to the termination region 30.

[0055] As shown in FIGS. 10(a) and 10(b), the termination region 30 of the semiconductor device 100 has n-type junctions between the first and second main surfaces of the semiconductor substrate. -The termination region 30 has a first main surface and a second main surface which are flush with the first main surface and the second main surface of the IGBT region 10 and the diode region 20, respectively. - The n-type drift layer 1 is formed in the IGBT region 10 and the diode region 20. - It has the same configuration as the drift layer 1 and is formed continuously and integrally.

[0056] n - The first main surface side of the n-type drift layer 1, i.e., the first main surface of the semiconductor substrate, - A p-type termination well layer 31 is provided between the n-type drift layer 1 and the n-type drift layer 1. The p-type termination well layer 31 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+14 / cm 3 ~1.0E+19 / cm 3 The p-type termination well layer 31 is provided to surround the cell region including the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is provided in a ring shape, and the number of p-type termination well layers 31 provided is appropriately selected depending on the breakdown voltage design of the semiconductor device 100 or the semiconductor device 101. In addition, on the outer edge side of the p-type termination well layer 31, there is an n + A type channel stopper layer 32 is provided, and an n + The p-type channel stopper layer 32 surrounds the p-type termination well layer 31 .

[0057] n -A p-type termination collector layer 16a is provided between the drift layer 1 and the second main surface of the semiconductor substrate. The p-type termination collector layer 16a is formed integrally and continuously with the p-type collector layer 16 provided in the cell region. Therefore, the p-type collector layer 16 may be collectively referred to as the p-type collector layer 16. In addition, in a configuration such as the semiconductor device 100 shown in FIG. 1, which can accommodate the diode region 20 adjacent to the termination region 30, the end of the p-type termination collector layer 16a on the diode region 20 side is provided to extend into the diode region 20 by a distance U2, as shown in FIG. 10(b). In this way, by providing the p-type termination collector layer 16a to extend into the diode region 20, the n-type collector layer 16a of the diode region 20 can be reduced. + This increases the distance between the p-type cathode layer 26 and the p-type termination well layer 31, thereby preventing the p-type termination well layer 31 from functioning as the anode of a diode. The distance U2 may be, for example, 100 μm.

[0058] A collector electrode 7 is provided on the second main surface of the semiconductor substrate. The collector electrode 7 is formed continuously and integrally from the cell region including the IGBT region 10 and the diode region 20 to the termination region 30. On the other hand, an emitter electrode 6 continuing from the cell region and a termination electrode 6a separated from the emitter electrode 6 are provided on the first main surface of the semiconductor substrate in the termination region 30.

[0059] The emitter electrode 6 and the termination electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, a semi-insulating silicon nitride (sinSiN) film. The termination electrode 6a, the p-type termination well layer 31, and the n-type termination well layer 32 are electrically connected via a semi-insulating film 33. + The emitter electrode 6 is electrically connected to the channel stopper layer 32 via a contact hole formed in the interlayer insulating film 4 provided on the first main surface of the termination region 30. In addition, a termination protective film 34 is provided in the termination region 30 to cover the emitter electrode 6, the termination electrode 6a, and the semi-insulating film 33. The termination protective film 34 may be made of, for example, polyimide.

[0060] Next, a method for manufacturing the semiconductor device of the first embodiment will be described with reference to Fig. 11 to Fig. 16. Fig. 11 to Fig. 16 are diagrams showing a method for manufacturing a semiconductor device that is an RC-IGBT. Fig. 11 to Fig. 14 are diagrams showing steps for forming the front surface side of semiconductor device 100 or semiconductor device 101, and Fig. 15 and Fig. 16 are diagrams showing steps for forming the back surface side of semiconductor device 100 or semiconductor device 101.

[0061] First, as shown in Figure 11(a), - A semiconductor substrate that constitutes the n-type drift layer 1 is prepared. The semiconductor substrate may be, for example, a so-called FZ wafer produced by the FZ (Floating Zone) method or a so-called MCZ wafer produced by the MCZ (Magnetic Applied CZochralki) method, and may be an n-type wafer containing n-type impurities. The concentration of the n-type impurities contained in the semiconductor substrate is appropriately selected depending on the withstand voltage of the semiconductor device to be fabricated. For example, in a semiconductor device with a withstand voltage of 1200 V, the n-type impurities constituting the semiconductor substrate - The concentration of n-type impurities is adjusted so that the resistivity of the n-type drift layer 1 is about 40 to 120 Ω·cm. As shown in FIG. 11(a), in the step of preparing the semiconductor substrate, the entire semiconductor substrate is - Semiconductor device 100 or semiconductor device 101 is manufactured by injecting p-type or n-type impurity ions from the first main surface side or the second main surface side of such a semiconductor substrate and then diffusing them into the semiconductor substrate by heat treatment or the like to form a p-type or n-type semiconductor layer.

[0062] As shown in Figure 11(a), n -The semiconductor substrate constituting the drift layer 1 includes regions that will become the IGBT region 10 and the diode region 20. Furthermore, although not shown, a region that will become the termination region 30 is also provided around the regions that will become the IGBT region 10 and the diode region 20. The following mainly describes a manufacturing method for the IGBT region 10 and the diode region 20 of the semiconductor device 100 or the semiconductor device 101, but the termination region 30 of the semiconductor device 100 or the semiconductor device 101 may be fabricated by a well-known manufacturing method. For example, when an FLR having a p-type termination well layer 51 as a breakdown voltage retention structure is formed in the termination region 30, the FLR may be formed by implanting p-type impurity ions before processing the IGBT region 10 and the diode region 20 of the semiconductor device 100 or the semiconductor device 101, or by implanting p-type impurity ions simultaneously when implanting p-type impurity ions into the IGBT region 10 or the diode region 20 of the semiconductor device 100.

[0063] Next, as shown in FIG. 11(b), n-type impurities such as phosphorus (P) are implanted from the first main surface side of the semiconductor substrate to form an n-type carrier accumulation layer 2. Furthermore, p-type impurities such as boron (B) are implanted from the first main surface side of the semiconductor substrate to form a p-type base layer 15 and a p-type anode layer 25. The n-type carrier accumulation layer 2, p-type base layer 15, and p-type anode layer 25 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions by heat treatment. The n-type impurities and p-type impurities are implanted after masking the first main surface of the semiconductor substrate, so they are selectively formed on the first main surface side of the semiconductor substrate. The n-type carrier accumulation layer 2, p-type base layer 15, and p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20 and are connected to the p-type termination well layer 51 in the termination region 30. The mask process refers to a process of forming a mask on a semiconductor substrate by applying a resist onto the semiconductor substrate, forming openings in predetermined areas of the resist using photolithography, and then performing ion implantation or etching on the predetermined areas of the semiconductor substrate through the openings.

[0064] The p-type base layer 15 and the p-type anode layer 25 may be formed simultaneously by ion implantation of p-type impurities. In this case, the p-type base layer 15 and the p-type anode layer 25 have the same depth and p-type impurity concentration, resulting in the same configuration. Alternatively, the p-type base layer 15 and the p-type anode layer 25 may have different depths and p-type impurity concentrations by ion implanting p-type impurities into them separately using mask processing.

[0065] The p-type termination well layer 51 formed in another cross section may be formed by ion implantation of p-type impurities simultaneously with the p-type anode layer 25. In this case, the p-type termination well layer 51 and the p-type anode layer 25 have the same depth and p-type impurity concentration, allowing for the same configuration. Alternatively, the p-type termination well layer 51 and the p-type anode layer 25 may be formed by ion implantation of p-type impurities simultaneously, allowing the p-type termination well layer 51 and the p-type anode layer 25 to have different p-type impurity concentrations. In this case, one or both of the masks may be a mesh mask to change the aperture ratio. Alternatively, the p-type termination well layer 51 and the p-type anode layer 25 may be ion implanted with p-type impurities separately using mask processing, allowing the p-type termination well layer 51 and the p-type anode layer 25 to have different depths and p-type impurity concentrations. The p-type termination well layer 51, the p-type base layer 15, and the p-type anode layer 25 may be formed by ion implantation of p-type impurities simultaneously.

[0066] Next, as shown in FIG. 12(a), n-type impurities are selectively implanted into the first main surface side of the p-type base layer 15 of the IGBT region 10 by mask processing. + The n-type source layer 13 is formed. The n-type impurity to be implanted may be, for example, arsenic (As) or phosphorus (P). Furthermore, a mask process is used to selectively implant aluminum, which is a p-type impurity, into the first main surface side of the p-type base layer 15 in the IGBT region, to form the p-type contact layer 14. Furthermore, a mask process is used to selectively implant aluminum, which is a p-type impurity, into the first main surface side of the p-type anode layer 25 in the diode region 20, to form the p-type contact layer 24. At this time, the p-type contact layers 14, 24 are n + The thickness is smaller than that of the n-type source layer 13, for example.+ The p-type contact layer 14 is formed to have a thickness equal to or less than half the thickness of the p-type source layer 13. The p-type contact layer 14 and the p-type contact layer 24 may be formed simultaneously or separately.

[0067] Next, as shown in FIG. 12(b), a semiconductor substrate is formed from the first main surface side thereof through the p-type base layer 15 and the p-type anode layer 25, and n - A trench 8 is formed in the IGBT region 10, reaching the n-type drift layer 1. + The trench 8 that penetrates the p-type source layer 13 and the p-type contact layer 14 has a part of its side wall that is n-type. + The trench 8 is composed of a p-type source layer 13 and a p-type contact layer 14. The trench 8 may be formed by depositing an oxide film such as SiO2 on the semiconductor substrate, then forming openings in the oxide film by masking where the trench 8 will be formed, and etching the semiconductor substrate using the oxide film with the openings as a mask. In FIG. 12(b), the trenches 8 are formed with the same pitch in the IGBT region 10 and the diode region 20, but the pitch of the trenches 8 may be different in the IGBT region 10 and the diode region 20. The pitch of the trenches 8 in a plan view can be changed as appropriate by changing the mask pattern used in the masking process.

[0068] 13(a), the semiconductor substrate is heated in an atmosphere containing oxygen to form oxide films 9 on the inner walls of the trenches 8 and on the first main surface of the semiconductor substrate. Of the oxide films 9 formed on the inner walls of the trenches 8, the oxide films 9 formed in the trenches 8 in the IGBT region 10 are the gate trench insulating film 11b of the active trench gates 11 and the dummy trench insulating film 12b of the dummy trench gates 12. Furthermore, the oxide films 9 formed in the trenches 8 in the diode region 20 are the diode trench insulating films 21b. The oxide films 9 formed on the first main surface of the semiconductor substrate are removed in a later process.

[0069] Next, as shown in FIG. 13(b), polysilicon doped with n-type or p-type impurities is deposited by CVD (chemical vapor deposition) or the like in the trench 8 with an oxide film 9 formed on its inner wall to form a gate trench electrode 11a, a dummy trench electrode 12a, and a diode trench electrode 21a.

[0070] Next, as shown in FIG. 14(a), the interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11 in the IGBT region 10, and then the oxide film 9 formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 4 may be, for example, SiO2. Then, a contact hole is formed in the deposited interlayer insulating film 4 by a mask process. The contact hole has an n + The gate insulating film 12 is formed on the p-type source layer 13, the p-type contact layer 14, the p-type contact layer 24, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0071] 14(b), a barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 4, and an emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 is formed by depositing titanium nitride by PVD (physical vapor deposition) or CVD.

[0072] The emitter electrode 6 may be formed by depositing an aluminum silicon alloy (Al-Si alloy) on the barrier metal 5 by PVD such as sputtering or vapor deposition. Alternatively, a nickel alloy (Ni alloy) may be further formed on the formed aluminum silicon alloy by electroless plating or electrolytic plating to form the emitter electrode 6. When the emitter electrode 6 is formed by plating, a thick metal film can be easily formed as the emitter electrode 6, thereby increasing the heat capacity of the emitter electrode 6 and improving its heat resistance. Note that when a nickel alloy is further formed by plating after forming the emitter electrode 6 made of an aluminum silicon alloy by PVD, the plating process to form the nickel alloy may be performed after processing the second main surface of the semiconductor substrate.

[0073] 15(a), the second main surface side of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined designed thickness. The thickness of the semiconductor substrate after grinding may be, for example, 80 μm to 200 μm.

[0074] 15(b), n-type impurities are implanted from the second main surface side of the semiconductor substrate to form an n-type buffer layer 3. Furthermore, p-type impurities are implanted from the second main surface side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, and the termination region 30, or may be formed only in the IGBT region 10 or the diode region 20.

[0075] The n-type buffer layer 3 may be formed by implanting, for example, phosphorus (P) ions. + ) may be implanted. Furthermore, it may be formed by implanting both protons and phosphorus. Protons can be implanted deep into the second main surface of the semiconductor substrate with a relatively low acceleration energy. Furthermore, the depth to which protons are implanted can be changed relatively easily by changing the acceleration energy. Therefore, when forming the n-type buffer layer 3 with protons, if the protons are implanted multiple times while changing the acceleration energy, an n-type buffer layer 3 that is wider in the thickness direction of the semiconductor substrate than when formed with phosphorus can be formed.

[0076] Furthermore, phosphorus can have a higher activation rate as an n-type impurity than protons, so punch-through of the depletion layer can be more reliably suppressed even in a thinned semiconductor substrate by forming the n-type buffer layer 3 with phosphorus. To further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus, and in this case, the protons are implanted deeper from the second main surface than the phosphorus.

[0077] The p-type collector layer 16 may be formed by implanting, for example, boron (B). The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the second main surface of the semiconductor substrate, the implanted boron is activated by irradiating the second main surface with a laser for laser annealing, thereby forming the p-type collector layer 16. At this time, phosphorus for the n-type buffer layer 3, which is implanted relatively shallow from the second main surface of the semiconductor substrate, is also activated at the same time. Meanwhile, since protons are activated at a relatively low annealing temperature of 380°C to 420°C, care must be taken to prevent the entire semiconductor substrate from being heated to a temperature higher than 380°C to 420°C after the proton implantation, except during the proton activation process. Laser annealing can be used to activate n-type impurities and p-type impurities even after proton implantation, because it can heat only the area near the second main surface of the semiconductor substrate to a high temperature.

[0078] Next, as shown in FIG. 16(a), n + The cathode layer 26 is formed. + The p-type cathode layer 26 may be formed by implanting phosphorus (P), for example. As shown in FIG. 16(a), the p-type collector layer 16 and the n-type collector layer 17 are formed at a position a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20. + Phosphorus is selectively implanted from the second main surface side by mask processing so that the boundary with the cathode layer 26 is located. + The amount of n-type impurities implanted to form the n-type cathode layer 26 is greater than the amount of p-type impurities implanted to form the p-type collector layer 16. In FIG. 16(a), the p-type collector layer 16 and the n-type + The depth of the cathode layer 26 is shown as the same, but + The depth of the n-type cathode layer 26 is equal to or greater than the depth of the p-type collector layer 16. + The region where the cathode layer 26 is to be formed must be made into an n-type semiconductor by implanting n-type impurities into the region where p-type impurities have been implanted. + In the entire region where the cathode layer 26 is to be formed, the concentration of the implanted p-type impurities is made higher than the concentration of the n-type impurities.

[0079] Next, as shown in FIG. 16(b), a collector electrode 7 is formed on the second main surface of the semiconductor substrate. The collector electrode 7 is formed over the entire surfaces of the IGBT region 10, the diode region 20, and the termination region 30 on the second main surface. Alternatively, the collector electrode 7 may be formed over the entire surface of the second main surface of an n-type wafer, which is the semiconductor substrate. The collector electrode 7 may be formed by depositing an aluminum silicon alloy (Al-Si alloy), titanium (Ti), or the like by PVD such as sputtering or vapor deposition, or by laminating multiple metals such as an aluminum silicon alloy, titanium, nickel, or gold. Furthermore, the collector electrode 7 may be formed by forming an additional metal film on a metal film formed by PVD using electroless plating or electrolytic plating.

[0080] The above-described process is used to manufacture the semiconductor device 100 or the semiconductor device 101. A plurality of semiconductor devices 100 or 101 are manufactured in a matrix on a single n-type wafer, and the semiconductor device 100 or the semiconductor device 101 is completed by cutting the wafer into individual semiconductor devices 100 or 101 by laser dicing or blade dicing.

[0081] The effects of the semiconductor device and the method for manufacturing the semiconductor device according to this embodiment configured as above will be described below.

[0082] In the semiconductor devices 100 and 101 of the present embodiment, aluminum is used as a p-type impurity in the p-type contact layer 14 and the p-type contact layer 24, and therefore the thickness of the p-type contact layer 14 and the p-type contact layer 24 is set to n +The thickness of the p-type contact layer can be made smaller than the thickness of the p-type source layer 13. This is because aluminum has a larger atomic radius than boron, and therefore, when ions are implanted with the same acceleration energy, boron, which has a smaller atomic radius, is implanted deep, whereas aluminum, which has a larger atomic radius, is implanted only at a shallower position than boron. Furthermore, by using aluminum, which is a metal, as the p-type impurity, ohmic contact with the electrode portion can be maintained, so the impurity concentration of the p-type contact layer can be made lower than in conventional semiconductor devices, and the impurity concentration from the p-type contact layer 14 or p-type contact layer 24 can be made lower than in conventional semiconductor devices. - This can prevent a large amount of holes from being injected into the type drift layer 1. As a result, the semiconductor devices 100 and 101 of the present embodiment have the advantage of being able to reduce the recovery loss in the diode region 20 while suppressing the contact resistance.

[0083] In the semiconductor devices 100 and 101 of the present embodiment, the thickness of the p-type contact layers 14 and 24 is n + Although the description has been given assuming that the p-type contact layers 14 and 24 are smaller than the p-type source layer 13, the present invention is not limited to this and may be any p-type contact layers that use aluminum as the p-type impurity. With this configuration, it is possible to maintain ohmic contact with at least the electrode portion, and therefore the impurity concentration of the p-type contact layers can be reduced, thereby achieving the effect of reducing the recovery loss of the diode region 20 while suppressing the contact resistance.

[0084] Embodiment 2 A semiconductor device according to a second embodiment will be described with reference to FIG. 17. FIG. 17 is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of a semiconductor device that is an RC-IGBT. FIG. 17 corresponds to the cross-sectional view taken along dashed line GG in the semiconductor device 100 or 101 shown in FIG. 1. Also, FIG. 17 shows n in the cross section as shown by dashed line AA in FIG. + 1 is a cross-sectional view of a portion having a mold source layer 13. FIG.

[0085] In the semiconductor device of this embodiment, a p-type contact layer 24 in the IGBT region 10 has an impurity concentration higher than that of the p-type contact layer 24 in the diode region 20. + The semiconductor device of this embodiment differs from the semiconductor device 100 or 101 of the first embodiment in that it has a mold contact layer 44. Since the other configurations of the semiconductor device of this embodiment are similar to those of the semiconductor device 100 or 101 of the first embodiment, the following description will mainly focus on the differences from the semiconductor device 100 or 101.

[0086] The p-type contact layer 24 is the same as that in the first embodiment, and + The thickness is smaller than that of the n-type source layer 13, for example. + The p-type contact layer 24 has a thickness half that of the p-type source layer 13. The aluminum impurity concentration in the p-type contact layer 24 is 1.0E+12 / cm 3 ~1.0E+18 / cm 3 It is desirable that:

[0087] p + The contact layer 44 is a semiconductor layer formed on the surface layer between the trenches and containing boron as a p-type impurity. The concentration of the p-type impurity is 1.0E+15 / cm 3 ~1.0E+20 / cm 3 p + The p-type contact layer 44 has a higher impurity concentration than the p-type contact layer 24. + As shown in FIG. 17, the n-type contact layer 44 + The thickness is larger than that of the n-type source layer 13, for example. + The thickness is 1.5 times the thickness of the mold source layer 13 .

[0088] In addition, p + The p-type contact layer 44 preferably uses boron as the p-type impurity, but is not limited to this. Aluminum or other p-type impurities may also be used. + The thickness of the n-type contact layer 44 is + It is desirable that the thickness of the n-type source layer 13 is larger than that of the n-type source layer 14. + The thickness may be the same as that of the type source layer 13 .

[0089] In the semiconductor device of this embodiment configured as described above, the impurity concentration of the p-type contact layer 24 formed in the diode region 20 is higher than that of the p-type contact layer 24 formed in the IGBT region 10. + Since the impurity concentration is lower than that of the contact layer 44, it is possible to achieve both a reduction in recovery loss and an improvement in the current carrying performance of the IGBT region. + In order to promote the flow of the impurities into the contact layer 44 and improve the latch-up resistance, the p + The thickness of the n-type contact layer 44 is + It is desirable that the thickness is larger than that of the source layer 13, and boron or the like is used as an impurity or the impurity concentration is 1.0E+15 / cm 3 By doing so, a thick p + A contact layer can be formed.

[0090] A modified example of the semiconductor device of the second embodiment will be described with reference to Fig. 18. Fig. 18 corresponds to the cross-sectional view of the semiconductor device 100 or 101 shown in Fig. 1 taken along dashed line GG, but is a cross-sectional view at a position different from the cross-sectional view of Fig. 17. Figs. 17 and 18 show the configuration of the boundary between the IGBT region and the diode region of a semiconductor device that is an RC-IGBT, but Fig. 17 shows a cross-section with n-type junctions as shown by dashed line AA in Fig. 3. + 18 is a cross-sectional view of a portion having an n-type source layer 13, and FIG. 18 shows a cross section of the n-type source layer 13 as indicated by the dashed line BB in FIG. + 1 is a cross-sectional view of a portion not having a mold source layer 13. FIG.

[0091] 18, the semiconductor device according to the modification of this embodiment differs from the semiconductor device of this embodiment in that a p-type contact layer 14 is further formed in the boundary region on the IGBT region 10 side. Since the other configurations of the semiconductor device according to the modification are the same as those of the semiconductor device of this embodiment, the following description will mainly focus on the differences.

[0092] The configuration of the p-type contact layer 14 is the same as that of the p-type contact layer 14 provided in the semiconductor device of the first embodiment.+ The thickness is smaller than that of the n-type source layer 13. + It is desirable that the thickness of the p-type contact layer 14 is half or less than the thickness of the p-type source layer 13. The aluminum impurity concentration of the p-type contact layer 14 is 1.0E+12 / cm 3 ~1.0E+18 / cm 3 In the semiconductor device of this embodiment, the p-type contact layer 14 is provided only on the IGBT region 10 side of the boundary region between the IGBT region 10 and the diode region 20.

[0093] In the second embodiment, the boundary between the IGBT region 10 and the diode region 20 is the n-channel junction (n-channel junction) at the position of the IGBT region 10 closest to the diode region 20. + The position of the trench closest to the diode region 20 among the trenches in contact with the n-type source layer 13 is the position of the trench closest to the diode region 20 in the IGBT region 10. + Of the trenches in contact with the type source layer 13, the trench located closest to the diode region 20 may be called a boundary trench or a boundary trench, but here it is referred to as a boundary trench 50. The boundary trench 50 is configured by providing a boundary trench electrode 50a in a trench formed in a semiconductor substrate via a boundary trench insulating film 50b.

[0094] In this way, the p-type contact layer 14 is provided at a position close to the boundary trench 50, while the p + Since the p-type contact layer 44 is provided, the n-type contact layer of the IGBT region 10 - Since the amount of holes injected into the type drift layer 1 can be reduced in the vicinity of the boundary trench 50, the amount of holes flowing from the IGBT region 10 into the diode region 20 can be reduced, thereby achieving the effect of further reducing the recovery loss in the diode region 20.

[0095] Embodiment 3 A semiconductor device according to a third embodiment will be described with reference to FIG. 19. FIG. 19 is a cross-sectional view showing the configuration of the boundary between the IGBT region and the diode region of a semiconductor device that is an RC-IGBT. FIG. 19 corresponds to the cross-sectional view taken along dashed line GG in the semiconductor device 100 or 101 shown in FIG. 1. In addition, FIG. 19 shows n in the cross section as shown by dashed line AA in FIG. + 1 is a cross-sectional view of a portion having a mold source layer 13. FIG.

[0096] In the semiconductor device of this embodiment, a p-type contact layer 24 is formed in the diode region 20 under the p-type contact layer 24 using aluminum as a p-type impurity. - The semiconductor device of this embodiment differs from semiconductor device 100 or 101 of the first embodiment in that it has n-type anode layer 45 and does not have n-type carrier accumulation layer 2. Since the other configurations of the semiconductor device of this embodiment are similar to those of semiconductor device 100 or 101 of the first embodiment, the following description will mainly focus on the differences from semiconductor device 100 or 101.

[0097] p - The p-type anode layer 45 contains aluminum as a p-type impurity, and has a lower p-type impurity concentration than the p-type base layer 15 formed in the IGBT region 10. - The aluminum impurity concentration of the mold anode layer 45 is 1.0E+12 / cm 3 ~1.0E+17 / cm 3 Also, p - The n-type carrier accumulation layer 2 is not formed under the n-type anode layer 45 .

[0098] In addition, p - The anode layer 45 may have an impurity concentration equivalent to the p-type impurity concentration of the p-type base layer 15 formed in the IGBT region 10, but it is preferable to make the impurity concentration lower than that of the p-type base layer 15, since this can further reduce the recovery loss in the diode region 20.

[0099] In the semiconductor device of this embodiment configured as described above, the p-type contact layer 24 is formed on a part of the surface layer between the trenches, and the p -Since the p-type impurity of the p-type anode layer 45 is aluminum, the p-type contact layer 24 and the p - This makes it possible to suppress the injection of holes from the anode layer 45, thereby achieving the effect of further reducing the recovery loss in the diode region 20.

[0100] Embodiment 4 A semiconductor device according to a fourth embodiment will be described with reference to FIG. 20. FIG. 20 is a cross-sectional view showing the configuration of the boundary between the IGBT region and the diode region of a semiconductor device that is an RC-IGBT. FIG. 20 corresponds to the cross-sectional view taken along dashed line GG in the semiconductor device 100 or 101 shown in FIG. 1. Also, FIG. 20 shows n in the cross section as shown by dashed line AA in FIG. + 1 is a cross-sectional view of a portion having a mold source layer 13. FIG.

[0101] The semiconductor device of this embodiment has an n + The semiconductor device 100 or 101 differs from the semiconductor device 100 or 101 of the first embodiment in that the p-type collector layer 16 is interspersed in the p-type cathode layer 26. + The p-type collector layer 16 interspersed with the n-type cathode layer 26 may be formed simultaneously with the p-type collector layer 16 of the IGBT region 10, and the n-type collector layer 16 of the diode region 20 may be formed simultaneously with the p-type collector layer 16 of the IGBT region 10. + The p-type collector layers 16 scattered in the p-type cathode layer 26 are in contact with the collector electrode 7 on the second main surface side and in contact with the n-type buffer layer 3 on the first main surface side.

[0102] In the semiconductor device of this embodiment configured as described above, when the diode operates in the reverse direction, n - Since holes can be injected into the drift layer at an appropriate rate, the diode performance is further improved.

[0103] Embodiment 5 A semiconductor device according to a fifth embodiment will be described with reference to FIG. 21. FIG. 21 is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of a semiconductor device that is an RC-IGBT. FIG. 21 corresponds to the cross-sectional view taken along dashed line GG in the semiconductor device 100 or 101 shown in FIG. 1. Also, FIG. 21 shows n in the cross section, as shown by dashed line AA in FIG. + 1 is a cross-sectional view of a portion having a mold source layer 13. FIG.

[0104] The semiconductor device of this embodiment differs from the semiconductor device 100 or 101 of the first embodiment in that no trench is formed in the diode region 20. Note that "no trench is formed in the diode region 20" means a configuration that does not have the diode trench gate 21 described in the first embodiment, and includes a configuration that has a boundary trench 50 at the boundary between the IGBT region 10 and the diode region 20.

[0105] In the semiconductor device of this embodiment configured as described above, by not forming a trench in the diode region 20, the conduction area of ​​carriers is increased and current flows more easily, thereby achieving the effect of reducing the on-state voltage.

[0106] Embodiment 6 A semiconductor device according to a sixth embodiment will be described with reference to FIG. 22. FIG. 22 is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of a semiconductor device that is an RC-IGBT. FIG. 22 corresponds to the cross-sectional view taken along dashed line GG in the semiconductor device 100 or the semiconductor device 101 shown in FIG. 1. In addition, FIG. 22 shows n in the cross section as shown by dashed line AA in FIG. + 1 is a cross-sectional view of a portion having a mold source layer 13. FIG.

[0107] The semiconductor device of this embodiment differs from semiconductor device 100 or 101 of embodiment 1 in that it has a recessed trench contact 46 between adjacent trenches. Since the other configurations of the semiconductor device of this embodiment are similar to those of semiconductor device 100 or 101 of embodiment 1, the following description will mainly focus on the differences from semiconductor device 100 or 101.

[0108] The semiconductor device of this embodiment has trench contacts 46 recessed from the first main surface between adjacent trenches, and an emitter electrode 6 is buried in the trench contacts 46. A p-type contact layer 17 containing aluminum as a p-type impurity is formed on the surface layer of the trench contact 46 on the IGBT region 10 side, and a p-type contact layer 27 containing aluminum as a p-type impurity is formed on the surface layer of the trench contact 46 on the diode region 20 side. In addition, a barrier metal 5 is formed between the emitter electrode 6 and the p-type contact layer 17 or p-type contact layer 27 in the trench contact 46. The bottom of the trench contact 46 is an n-type contact layer. + The trench contacts 46 are located closer to the second main surface than the source layers 13. The trench contacts 46 do not necessarily have to be formed between all adjacent trenches.

[0109] In the semiconductor device of this embodiment configured as described above, the latch-up resistance is improved by the p-type contact layer 17 being located at the bottom of the trench contact in the IGBT region 10. In addition, the trench contact increases the surface area of ​​the contact, which further reduces the contact resistance.

[0110] It should be noted that the scope of the present disclosure also includes appropriate combinations, modifications, and omissions of the respective embodiments. [Explanation of symbols]

[0111] 1n -1. Type drift layer, 5. Barrier metal, 10. IGBT region, 11. Active trench gate, 11a. Gate trench electrode, 11b. Gate trench insulating film, 12. Dummy trench gate, 12a. Dummy trench electrode, 12b. Dummy trench insulating film, 13. n + p-type source layer, 14, 17 p-type contact layer, 15 p-type base layer, 16 p-type collector layer, 16a p-type termination collector layer, 20 diode region, 21 diode trench gate, 21a diode trench electrode, 21b diode trench insulating film, 24, 27 p-type contact layer, 25 p-type anode layer, 26 n + p-type cathode layer, 30 termination region, 31 p-type termination well layer, 44 p + Contact layer, 45p - Type anode layer, 46 trench contact

Claims

1. A semiconductor device comprising: a semiconductor substrate formed of silicon having an n-type drift layer between a first main surface and a second main surface opposite to the first main surface, an insulated gate bipolar transistor region and a diode region provided adjacent to each other in the semiconductor substrate; and an emitter electrode provided on the first main surface of the semiconductor substrate, The insulated gate bipolar transistor region includes: a p-type base layer provided closer to the first main surface than the drift layer; an n-type source layer selectively provided on the first main surface side of the base layer and on a surface layer on the first main surface side of the semiconductor substrate; a p-type first contact layer connected to the emitter electrode, the p-type first contact layer being provided on the first main surface side of the base layer in a region of the surface layer on the first main surface side of the semiconductor substrate where the source layer is not provided; a gate trench insulating film provided on an inner surface of a trench that penetrates the base layer and reaches the drift layer; a gate trench electrode provided in the trench via the gate trench insulating film; a p-type collector layer provided on a surface layer on the second main surface side of the semiconductor substrate, The diode region includes: a p-type anode layer provided closer to the first main surface than the drift layer; a p-type second contact layer provided on the first main surface side of the anode layer and on a surface layer on the first main surface side of the semiconductor substrate, the p-type second contact layer being connected to the emitter electrode; an n-type cathode layer provided on a surface layer on the second main surface side of the semiconductor substrate; the second contact layer contains aluminum as a p-type impurity; the first contact layer contains aluminum as a p-type impurity; The semiconductor device, wherein the thickness of the first contact layer is equal to or less than half the thickness of the source layer.

2. A semiconductor device comprising a semiconductor substrate formed of silicon having an n-type drift layer between a first main surface and a second main surface opposite the first main surface, an insulated gate bipolar transistor region and a diode region provided adjacent to each other, and an emitter electrode provided on the first main surface of the semiconductor substrate, The insulated gate bipolar transistor region includes: a p-type base layer provided closer to the first main surface than the drift layer; an n-type source layer selectively provided on the first main surface side of the base layer and on a surface layer on the first main surface side of the semiconductor substrate; a p-type first contact layer connected to the emitter electrode, the p-type first contact layer being provided on the first main surface side of the base layer in a region of the surface layer on the first main surface side of the semiconductor substrate where the source layer is not provided; a gate trench insulating film provided on an inner surface of a trench that penetrates the base layer and reaches the drift layer; a gate trench electrode provided in the trench via the gate trench insulating film; a p-type collector layer provided on a surface layer on the second main surface side of the semiconductor substrate, The diode region includes: a p-type anode layer provided closer to the first main surface than the drift layer; a p-type second contact layer provided on the first main surface side of the anode layer and on a surface layer on the first main surface side of the semiconductor substrate, the p-type second contact layer being connected to the emitter electrode; an n-type cathode layer provided on a surface layer on the second main surface side of the semiconductor substrate; the second contact layer contains aluminum as a p-type impurity; the first contact layer contains aluminum as a p-type impurity; The semiconductor device, wherein the first contact layer has an impurity concentration of less than 1.0E+18 / cm 3 .

3. A semiconductor device comprising a semiconductor substrate formed of silicon having an n-type drift layer between a first main surface and a second main surface opposite the first main surface, an insulated gate bipolar transistor region and a diode region provided adjacent to each other, and an emitter electrode provided on the first main surface of the semiconductor substrate, The insulated gate bipolar transistor region includes: a p-type base layer provided closer to the first main surface than the drift layer; an n-type source layer selectively provided on the first main surface side of the base layer and on a surface layer on the first main surface side of the semiconductor substrate; a p-type first contact layer connected to the emitter electrode, the p-type first contact layer being provided on the first main surface side of the base layer in a region of the surface layer on the first main surface side of the semiconductor substrate where the source layer is not provided; a gate trench insulating film provided on an inner surface of a trench that penetrates the base layer and reaches the drift layer; a gate trench electrode provided in the trench via the gate trench insulating film; a p-type collector layer provided on a surface layer on the second main surface side of the semiconductor substrate, The diode region includes: a p-type anode layer provided closer to the first main surface than the drift layer; a p-type second contact layer provided on the first main surface side of the anode layer and on a surface layer on the first main surface side of the semiconductor substrate, the p-type second contact layer being connected to the emitter electrode; an n-type cathode layer provided on a surface layer on the second main surface side of the semiconductor substrate; the second contact layer contains aluminum as a p-type impurity; a plurality of the first contact layers; the plurality of first contact layers include a third contact layer having an impurity concentration higher than that of the second contact layer, and a fourth contact layer having an impurity concentration lower than that of the third contact layer; The fourth contact layer is located closer to the diode region than the third contact layer.

4. A semiconductor device comprising a semiconductor substrate formed of silicon having an n-type drift layer between a first main surface and a second main surface opposite the first main surface, an insulated gate bipolar transistor region and a diode region provided adjacent to each other, and an emitter electrode provided on the first main surface of the semiconductor substrate, The insulated gate bipolar transistor region includes: a p-type base layer provided closer to the first main surface than the drift layer; an n-type source layer selectively provided on the first main surface side of the base layer and on a surface layer on the first main surface side of the semiconductor substrate; a p-type first contact layer connected to the emitter electrode, the p-type first contact layer being provided on the first main surface side of the base layer in a region of the surface layer on the first main surface side of the semiconductor substrate where the source layer is not provided; a gate trench insulating film provided on an inner surface of a trench that penetrates the base layer and reaches the drift layer; a gate trench electrode provided in the trench via the gate trench insulating film; a p-type collector layer provided on a surface layer on the second main surface side of the semiconductor substrate, The diode region includes: a p-type anode layer provided closer to the first main surface than the drift layer; a p-type second contact layer provided on the first main surface side of the anode layer and on a surface layer on the first main surface side of the semiconductor substrate, the p-type second contact layer being connected to the emitter electrode; an n-type cathode layer provided on a surface layer on the second main surface side of the semiconductor substrate; the second contact layer contains aluminum as a p-type impurity; a plurality of the first contact layers; at least some of the first contact layers among the plurality of first contact layers are third contact layers having an impurity concentration higher than the impurity concentration of the second contact layer; The semiconductor device, wherein the thickness of the third contact layer is greater than the thickness of the source layer.

5. 5. The semiconductor device according to claim 1, wherein said first contact layer contains aluminum as a p-type impurity.

6. 6. The semiconductor device according to claim 5, wherein the thickness of said first contact layer and said second contact layer is smaller than the thickness of said source layer.

7. The semiconductor device according to claim 5 , wherein both ends of said source layer contact two adjacent trenches.

8. The semiconductor device according to claim 7 , wherein both ends of said first contact layer contact two adjacent trenches.

9. The diode region includes: a diode trench insulating film provided on an inner surface of the trench reaching the anode layer; a diode trench electrode provided in the trench via the diode trench insulating film; The semiconductor device according to claim 8 , wherein both ends of said second contact layer contact two adjacent trenches.

10. 6. The semiconductor device according to claim 5, wherein the first contact layer and the second contact layer are in ohmic contact with the emitter electrode.

11. 5. The semiconductor device according to claim 1, wherein said collector layer is provided so as to extend beyond a boundary between said insulated gate bipolar transistor region and said diode region toward said diode region.

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