Semiconductor Devices

Abstract

To provide a semiconductor device that can reduce forward voltage degradation and turn-on loss.SOLUTION: A vertical MOSFET includes: a first conductive type semiconductor substrate 2; a first conductive type first semiconductor layer 1; a second conductive type second semiconductor layer 16; a first conductive type first semiconductor region 17; a first trench 31 and a second trench 32; a gate electrode 20 provided inside the first trench 31 via a gate insulating film 19; and a Schottky electrode 29 provided inside the second trench 32. The first trench 31 is provided in a striped pattern in a plan view, and the second trench 32 surrounds the first trench 31.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with a trench structure have been fabricated (manufactured) for power semiconductor elements to reduce the on-resistance of the elements. In vertical MOSFETs, a trench structure in which the channel is formed perpendicular to the substrate surface allows for a higher cell density per unit area than a planar structure in which the channel is formed parallel to the substrate surface, and therefore allows for an increased current density per unit area, which is advantageous in terms of cost.

[0003] Vertical MOSFETs incorporate a parasitic pn diode, formed between the source and drain as a body diode by a p-type base layer and an n-type drift layer. This allows the free wheeling diode (FWD) used in inverters to be omitted, contributing to lower costs and miniaturization. However, when a silicon carbide substrate is used as the semiconductor substrate, the parasitic pn diode has a higher built-in potential than when a silicon (Si) substrate is used, resulting in a higher on-resistance of the parasitic pn diode and increased losses. Furthermore, when the parasitic pn diode turns on and conducts current, its bipolar behavior causes its characteristics to change over time (aging degradation), resulting in forward degradation and increased turn-on losses.

[0004] To address this issue, a Schottky barrier diode (SBD) can be connected in parallel with the MOSFET so that current flows through the SBD during freewheeling and prevents current from flowing through the parasitic pn diode. However, this increases costs because the same number of SBD chips as MOSFETs are required.

[0005] For this reason, a technology has been proposed in which a contact trench is formed on the surface of the substrate that penetrates the p-type channel portion, an SBD is embedded in the inner wall of the trench, and the current during return flows through the built-in SBD instead of the PiN diode (see, for example, Patent Document 1 below).

[0006] Fig. 24 is a top view showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. Fig. 25 is a cross-sectional view taken along the line CC' of Fig. 24 showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. As shown in Fig. 24, silicon carbide semiconductor device 150 with an SBD built in comprises active region 140 in which an element structure is formed and through which current flows when the device is on, edge region 142 surrounding active region 140 and maintaining a breakdown voltage, and transition region 141 between active region 140 and edge region 142. Active region 140 is the region surrounded by a dashed line in Fig. 24.

[0007] 25, a MOS gate having a general trench gate structure is provided on the front surface (the surface on the side of the p-type base layer 116 described later) of a semiconductor substrate made of silicon carbide (hereinafter referred to as silicon carbide substrate). + Silicon carbide substrate (hereinafter referred to as n + On a silicon carbide substrate (102) - The silicon carbide layer is formed by epitaxially growing in order silicon carbide layers that become n-type drift layer 101, n-type region 115 that is a current diffusion region, and p-type base layer .

[0008] n + On a silicon carbide substrate 102 - n-type drift layer 101 - The n-type layer is epitaxially grown. + The front surface (n - On the side of the n-type drift layer 101, a p-type base layer 116 and an n-type + The MOS gate structure is formed of a type source region 117, a trench gate 131, a gate insulating film 119, and a gate electrode 120. Reference numerals 118, 121, and 122 denote p ++The source electrode is a mold contact region, an interlayer insulating film, and a source electrode.

[0009] The n-type region 115 is provided with a first p-type dopant layer 131 so as to cover the entire bottom surface of the trench gate 131. + The n-type region 115 is selectively provided with a first p-type region 103 so as to cover the entire bottom surface of the trench SBD 132. + A mold region 103 is selectively provided. + The type region 103 is n - The edge region 142 is formed at a depth not reaching the first p drift layer 101. + The second p + A mold area 104 is provided.

[0010] The trench SBD 132 is a trench whose inner wall is covered with a Schottky metal 129 that connects to the source electrode 122, and a Schottky contact is formed between the semiconductor region exposed on the inner wall and the Schottky metal 129. In this way, in Fig. 24, a parasitic Schottky diode (built-in SBD) is provided in parallel with the parasitic pn diode between the source and drain.

[0011] As shown in FIG. 24, in a conventional silicon carbide semiconductor device with an SBD built in, trench gate 131 is longer than trench SBD 132 to facilitate connection of trench gate 131 to a gate runner (not shown) provided in edge region 142.

[0012] A positive voltage is applied to the source electrode 122, and n + When a negative voltage is applied to a drain electrode (not shown) provided on the back surface of the silicon carbide substrate 102 (when the MOSFET is turned off), the p-type base layer 116 and the n-type - 24, by designing the parasitic Schottky diode to turn on before the parasitic pn diode turns on when the MOSFET is turned off, the bipolar operation of the parasitic pn diode can be suppressed, and deterioration over time due to the bipolar operation can be prevented.

[0013] Also known is a configuration that includes multiple rings made of p-type layers formed by arranging an epitaxial film within a linear frame-shaped trench surrounding the cell portion, and a Schottky electrode is arranged to cover part of the inner periphery of each ring (see, for example, Patent Document 2 below). [Prior art documents] [Patent documents]

[0014] [Patent Document 1] Japanese Patent Application Publication No. 8-204179 [Patent Document 2] Japanese Patent Application Publication No. 2018-006630 Summary of the Invention [Problem to be solved by the invention]

[0015] 26 is a cross-sectional view of the A-A' portion of FIG. 24 showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. FIG. 27 is a cross-sectional view of the B-B' portion of FIG. 24 showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. As shown in FIGS. 26 and 27, in the transition region 141, the first p + The second p + The p-type base layer 116 has a surface layer including a p-type region 104. ... region 104 is in contact with the trench SBD 132. ++ Therefore, in the transition region 141, the trench SBD 132 is surrounded by a p-type region (p-type base layer 116, p ++ contact region 118, first p + The mold region 103 and the second p + The structure is surrounded by a mold region 104).

[0016] As a result, the trench SBD 132 does not function as a parasitic Schottky diode and cannot suppress the bipolar operation of the parasitic pn diode in the transition region 141. When the parasitic pn diode is turned on and conducts current, the bipolar operation of the parasitic pn diode causes a hole current to flow along path D in Figures 26 and 27, and the energy generated by recombination of the hole current and electron current causes stacking faults to occur and expand.

[0017] Therefore, the transition region 141 has a problem that its characteristics change over time (deterioration over time) due to the bipolar operation of the parasitic pn diode, more so than the inside of the active region 140, resulting in forward deterioration and increased turn-on loss.

[0018] SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, an object of the present invention is to provide a semiconductor device capable of reducing the deterioration of the forward voltage and the loss at turn-on. [Means for solving the problem]

[0019] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. A first semiconductor layer of a first conductivity type, which has an impurity concentration lower than that of the semiconductor substrate, is provided on a front surface of a semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on the opposite side of the first semiconductor layer from the semiconductor substrate. A first semiconductor region of a first conductivity type, which has an impurity concentration higher than that of the semiconductor substrate, is selectively provided within the second semiconductor layer. A second semiconductor region of a second conductivity type is provided within the first semiconductor layer. A third semiconductor region of a second conductivity type, the bottom surface of which is in contact with the second semiconductor region, is provided in a surface layer of the first semiconductor layer. A first trench and a second trench are provided which penetrate the first semiconductor region and the second semiconductor layer and reach the first semiconductor layer. A gate electrode is provided within the first trench via a gate insulating film. A Schottky electrode is provided within the second trench. The first trench is provided in a striped pattern in a plan view, and the second trench surrounds the first trench. An edge region that surrounds the active region through which current flows in the on-state and maintains a breakdown voltage is provided with a junction termination structure for improving the breakdown voltage, and in the transition region between the active region and the edge region, the first trench is covered with the second semiconductor layer and a second semiconductor region of a second conductivity type, and the sidewalls of the second trench are in contact with the second semiconductor region, the first semiconductor layer, and the second semiconductor layer.

[0020] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the second trench has a stripe-shaped portion parallel to the first trench and an outer peripheral portion connecting the stripe-shaped portions, the distance between the end of the first trench and the outer peripheral portion of the second trench is equal to or greater than the spacing between the first trench and the second trench, and the end of the first trench is located closer to the active region than the junction termination structure.

[0021] In the semiconductor device according to the present invention, the second trench is a metal film formed along the inner wall of the second trench; It is characterized by being composed of a heterojunction with polysilicon.

[0022] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, a portion of the second trench is provided at a position opposite in the depth direction to a gate contact region that connects the gate electrode and the gate runner.

[0023] According to the above-described invention, the trench gate (first trench) is surrounded by the trench SBD (second trench). As a result, the portion of the trench gate that comes into contact with the source electrode is inside the region surrounded by the trench SBD. Therefore, outside the region surrounded by the trench SBD, when a negative bias is applied to the drain side of the silicon carbide semiconductor device with an SBD built in, the parasitic pn diode does not operate in a bipolar manner, thereby suppressing forward degradation and an increase in turn-on loss. [Effects of the Invention]

[0024] The semiconductor device according to the present invention has the effect of reducing the deterioration of the forward voltage and the loss at turn-on. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a top view showing a structure of a silicon carbide semiconductor device according to an embodiment; [Figure 2] 2 is a cross-sectional view taken along line AA' of FIG. 1, showing the structure of the silicon carbide semiconductor device according to the embodiment. [Figure 3] 2 is a cross-sectional view taken along the line BB' of FIG. 1, showing the structure of the silicon carbide semiconductor device according to the embodiment. [Figure 4] 2 is a cross-sectional view taken along the line CC' of FIG. 1, showing the structure of the silicon carbide semiconductor device according to the embodiment. [Figure 5] 2 is a cross-sectional view taken along the line DD' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the embodiment. [Figure 6] 1 is a top view showing an appearance of a silicon carbide semiconductor device according to an embodiment; [Figure 7]1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 1). [Figure 8] 10 is a cross-sectional view (part 2) showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 9] 10 is a cross-sectional view (part 3) showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 10] 10 is a cross-sectional view (part 4) showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. FIG. [Figure 11] 5 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 5). FIG. [Figure 12] 1 is a top view (part 1) showing a state during manufacture of a silicon carbide semiconductor device according to an embodiment. FIG. [Figure 13] 13 is a cross-sectional view (part 1) taken along line AA' of FIG. 12 showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 14] FIG. 2 is a second top view showing a state during manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 15] 13 is a cross-sectional view (part 2) taken along line AA' of FIG. 12 illustrating a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 16] FIG. 10 is a third top view showing a state during manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 17] 13 is a cross-sectional view (part 3) taken along line AA' of FIG. 12 illustrating a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 18] FIG. 4 is a top view showing a state during manufacture of the silicon carbide semiconductor device according to the embodiment (part 4). [Figure 19] 13 is a cross-sectional view (part 4) taken along line AA' of FIG. 12 illustrating a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 20] FIG. 5 is a fifth top view showing a state during manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 21]13 is a fifth cross-sectional view taken along the line AA' of FIG. 12 illustrating a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 22] FIG. 6 is a top view showing a state during manufacture of the silicon carbide semiconductor device according to the embodiment (part 6). [Figure 23] 13 is a cross-sectional view (part 6) taken along line AA' of FIG. 12 illustrating a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 24] FIG. 1 is a top view showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. [Figure 25] FIG. 25 is a cross-sectional view taken along the line CC' of FIG. 24, showing the structure of a conventional silicon carbide semiconductor device with an embedded SBD. [Figure 26] FIG. 25 is a cross-sectional view taken along the line AA' of FIG. 24, showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. [Figure 27] FIG. 25 is a cross-sectional view taken along the line BB' of FIG. 24, showing the structure of a conventional silicon carbide semiconductor device with an SBD built in. DETAILED DESCRIPTION OF THE INVENTION

[0026] Preferred embodiments of a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations will be omitted. In this specification, in the notation of Miller indices, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index.

[0027] (Embodiment) The semiconductor device according to the present invention is configured using a semiconductor having a wider bandgap than silicon (hereinafter referred to as a wide bandgap semiconductor). Here, the structure of a semiconductor device (silicon carbide semiconductor device) using, for example, silicon carbide (SiC) as the wide bandgap semiconductor will be described as an example. FIG. 1 is a top view showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view taken along line A-A' in FIG. 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view taken along line B-B' in FIG. 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view taken along line C-C' in FIG. 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. Here, FIG. 5 is a cross-sectional view taken along line D-D' in FIG. 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 4 ...

[0028] As shown in FIG. 1, a silicon carbide semiconductor device 50 with an SBD built in is composed of an active region 40 in which an element structure is formed and in which a main current flows in the thickness direction of the substrate when the device is in an on-state, an edge region 42 that surrounds the periphery of the active region 40 and maintains a breakdown voltage, and a transition region 41 between the active region 40 and the edge region 42. The active region 40 is the region surrounded by a dashed line in FIG. 1. As shown in FIG. 4, the transition region 41 is a region in which the side surface of a trench gate 31, which will be described later, is covered with a p-type region and does not function as a MOS. The silicon carbide semiconductor device 50 according to the embodiment shown in FIGS. 1 to 4 is a silicon carbide semiconductor device with an SBD built in, which includes a MOS gate on the front surface (the surface on the side of a p-type base layer 16, which will be described later) of a semiconductor substrate (silicon carbide substrate: semiconductor chip) made of silicon carbide.

[0029] The silicon carbide substrate is made of silicon carbide. + On a silicon carbide substrate (semiconductor substrate of a first conductivity type) 2, - The active region 40 is formed by epitaxially growing silicon carbide layers in order to form the p-type drift layer (first semiconductor layer of the first conductivity type) 1 and the p-type base layer (second semiconductor layer of the second conductivity type) 16. In the active region 40, the MOS gate is formed by epitaxially growing silicon carbide layers in order to form the p-type base layer 16 and the n-type+ The n-type source region (first semiconductor region of the first conductivity type) 17, the gate insulating film 19, and the gate electrode 20 are formed. - An n-type region 15 may be provided in the surface layer on the source side (the side of a source electrode 22 described later) of the drift layer 1 so as to be in contact with the p-type base layer 16. The n-type region 15 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type region 15 is provided uniformly in a direction parallel to the front surface of the substrate (the front surface of the silicon carbide substrate), for example.

[0030] n-type region 15 (or n-type region 15 if no n-type region is provided) - The first p + A first p-type region (second semiconductor region of a second conductivity type) 3 is selectively provided. + The n-type region 3 is provided so as to be in contact with the bottom surface of a trench gate (first trench) 31 (described later) and the bottom surface of a trench SBD (second trench) 32 (described later). + A second conductivity type region (third semiconductor region) 4 is selectively provided. + The mold region 4 has a bottom surface of the first p + It is provided so as to be in contact with the mold region 3 .

[0031] When the n-type region 15 is provided, the first p + The p-type region 3 is connected to the n-type region 15 from a position deeper on the drain side than the interface between the p-type base layer 16 and the n-type region 15. - The first p + By providing the mold region 3, the first p + A pn junction can be formed between the first p-type region 3 and the n-type region 15(1). + Type region 3 and 2p + The p-type region 4 has a higher impurity concentration than the p-type base layer 16 .

[0032] In addition, the p-type base layer 16 contains n + The n-type source region 17 is selectively provided. + type source region 17 and p ++ A p-type contact region (a fifth semiconductor region of the second conductivity type) (not shown) may be selectively provided. ++ The depth of the contact region is, for example, n + It may be the same depth as the n-type source region 17 or + It may be deeper than the source region 17 .

[0033] The trench gate 31 is formed on the n-type substrate surface. + The trench gate 31 has a gate insulating film 19 formed therein along the sidewalls of the trench gate 31, and a gate electrode 20 formed inside the gate insulating film 19. The source-side end of the gate electrode 20 may or may not protrude outward from the front surface of the substrate. The gate electrode 20 is electrically connected to a gate electrode pad (not shown). An interlayer insulating film 21 is formed on the front surface of the substrate so as to cover the gate electrode 20 embedded in the trench gate 31. The interlayer insulating film 21 has an opening at a junction region 41, and the gate electrode 20 is connected to a gate runner 27 at the opening via a gate contact region 26 of the polysilicon layer.

[0034] The trench SBD32 is formed from the front surface of the substrate to the n-type + The trench SBD32 penetrates the p-type source region 17 and the p-type base layer 16 to reach the n-type region 15(1). The inside of the trench SBD32 is covered along the sidewall of the trench SBD32 with a Schottky metal 29 that connects to the source electrode 22, forming a Schottky junction between the semiconductor region exposed on the inner wall and the Schottky metal 29. An oxide film, for example, silicon dioxide (SiO2), may be provided inside the Schottky metal 29.

[0035] As shown in FIG. 1 , in this embodiment, the trench gate 31 is surrounded by the trench SBD 32. As shown in FIG. 6 (described later), "surrounding" means that, in a plan view, it is necessary to cross the trench SBD 32 to reach the edge region 42 from any point on the trench gate 31. For example, the trench gate 31 is provided in a striped shape in a plan view, and the trench SBD 32 is provided parallel to the trench gate 31 and has a striped portion P1 that is longer than the trench gate 31 and an outer peripheral portion P2 that connects the striped portions. As a result, the portion of the trench gate 31 that contacts the source electrode 22 is inside the region surrounded by the trench SBD 32. Therefore, outside the region surrounded by the trench SBD 32, when a negative bias is applied to the drain side of a silicon carbide semiconductor device incorporating an SBD, a parasitic pn diode does not perform bipolar operation, thereby suppressing forward degradation and an increase in turn-on loss.

[0036] As shown in FIG. 4, in the transition region 41, the sidewall of the trench SBD 32 is + In other words, in a conventional silicon carbide semiconductor device with an SBD built in, the p-type region (first and second p + By opening a portion of n-type regions 103, 104, trench SBD 32 of this embodiment has its sidewalls in contact with n-type region 15(1). This allows trench SBD 32 to function as a parasitic Schottky diode even in transition region 41. Therefore, when a negative bias is applied to the drain side of a silicon carbide semiconductor device incorporating an SBD, the parasitic Schottky diode can be operated in transition region 41 as well, thereby suppressing the bipolar operation of the parasitic pn diode and suppressing forward degradation and increases in turn-on loss.

[0037] 6 is a top view showing the appearance of the silicon carbide semiconductor device according to the embodiment. As shown in FIG. 6, trench gate 31 has n +The active region 40 is surrounded by an edge region 42 that maintains a breakdown voltage and surrounds the active region 40. The edge region 42 is provided with a junction termination (JTE) extension (JTE) structure, which reduces or disperses the electric field to improve the breakdown voltage of the entire high-voltage semiconductor device. Outside the JTE region 43, an n-type silicon carbide substrate 40 is provided with an n-type silicon carbide substrate 40 that functions as a channel stopper. + A mold semiconductor region (not shown) is provided.

[0038] In this embodiment, the distance W1 between the end T of the trench gate 31 and the outer periphery P2 of the trench SBD 32 is preferably equal to or greater than the interval W2 between the trench gate 31 and the trench SBD 32. This is because if the distance W1 is short, the resistance of the current path of the trench SBD 32 may decrease, resulting in a decrease in the withstand voltage. Furthermore, the end T of the trench gate 31 is preferably located inside (closer to the active region 40) than the JTE region 43. Therefore, the outer periphery P2 of the trench SBD 32 is located opposite the gate contact region 26 in the depth direction.

[0039] The source electrode 22 is connected to the n-type + The p-type source region 17 is in contact with the p-type source region 17 and is electrically insulated from the gate electrode 20 by an interlayer insulating film 21. ++ When a contact region is provided, the source electrode 22 is ++ The source electrode 22 also contacts the gate electrode 20. A barrier metal may be provided between the source electrode 22 and the interlayer insulating film 21 to prevent diffusion of metal atoms from the source electrode 22 to the gate electrode 20. A source electrode pad (not shown) is provided on the source electrode 22. The back surface (n + n type drain region + A drain electrode (not shown) is provided on the back surface of the silicon carbide substrate 1.

[0040] (Method of manufacturing a semiconductor device according to an embodiment) Next, a method for manufacturing a semiconductor device according to an embodiment will be described. Figs. 7 to 11 are cross-sectional views showing states during the manufacturing of a silicon carbide semiconductor device according to an embodiment. Figs. 12, 14, 16, 18, 20, and 22 are top views showing states during the manufacturing of a silicon carbide semiconductor device according to an embodiment. Figs. 13, 15, 17, 19, 21, and 23 are cross-sectional views taken along the line A-A' in Fig. 12 showing states during the manufacturing of a silicon carbide semiconductor device according to an embodiment.

[0041] First, n + n type drain region + A silicon carbide substrate 2 is prepared. + The front surface of the silicon carbide substrate 2 is - The n-type drift layer 1 is epitaxially grown. - The epitaxial growth conditions for forming the n-type drift layer 1 are as follows: - The impurity concentration of the drift layer 1 is 3×10 15 / cm 3 The state up to this point is shown in Figure 7.

[0042] Next, n - A lower n-type region 15a (or a lower n-type region 15b if no n-type region 15 is formed) is formed on the n-type drift layer 1. - The n-type layer (hereinafter referred to as n-type layer) having the same impurity concentration as that of the n-type drift layer 1 is epitaxially grown. For example, the epitaxial growth conditions for forming the lower n-type region 15a are set as follows: the impurity concentration of the lower n-type region 15a is 1×10 17 / cm 3 The lower n-type region 15a is a part of the n-type region 15. Next, a first p-type impurity is formed in the surface layer of the lower n-type region 15a (n-type layer) by photolithography and ion implantation of p-type impurities. + The mold region 3 is selectively formed. For example, the first p + The dose of ions implanted to form the mold region 3 is set to 5×10 18 / cm 3 The state up to this point is shown in FIG.

[0043] Next, the lower n-type region 15a (n-type layer), the first p + An upper n-type region 15b (n-type layer) is epitaxially grown on the n-type region 3. For example, the conditions for epitaxial growth for forming the upper n-type region 15b may be set so that the impurity concentration is approximately the same as that of the lower n-type region 15a. This upper n-type region 15b is a part of the n-type region 15, and the lower n-type region 15a and the upper n-type region 15b together form the n-type region 15. Next, a second p-type impurity is implanted into the surface layer of the upper n-type region 15b (n-type layer) by photolithography and ion implantation of p-type impurities. + The mold region 4 is selectively formed. For example, the second p + The dose at the time of ion implantation for forming the type region 4 is set to a value where the impurity concentration is the first p + It may be set to be approximately the same as the mold region 3. + Type region 3 and 2p + The area including the mold area 4 is called the first and second p + These are called mold regions 3 and 4. + When the mold region 4 is formed, the sidewall of the trench SBD 32 is formed in the transition region 41. + It is formed so as not to come into contact with the mold region 4. The state up to this point is shown in FIG.

[0044] Next, the upper n-type region 15b and the second p + A p-type base layer 16 is epitaxially grown on the dopant region 4. For example, the epitaxial growth conditions for forming the p-type base layer 16 are set as follows: the impurity concentration of the p-type base layer 16 is 4×10 17 / cm 3 It may be set to about the same.

[0045] Next, photolithography and ion implantation of n-type impurities are performed to form n-type impurities in the surface layer of the p-type base layer 16. + The n-type source region 17 is selectively formed. + The dose at the time of ion implantation for forming the source region 17 is set to 3×10 20 / cm 3It may be set to about the same.

[0046] Next, by photolithography and ion implantation of p-type impurities, n + The p type source region 17 is in contact with the p type source region 17. ++ A type contact region may be selectively formed. For example, ++ The dose during ion implantation to form the contact region is set to an impurity concentration of 3×10 20 / cm 3 It may be set to about n + Type source region 17 and p ++ The order of forming the contact region and the JTE region may be reversed. Next, a JTE region 43 is formed in the edge region 42 by photolithography and ion implantation of p-type impurities. After all ion implantation is completed, activation annealing is performed. The state up to this point is shown in FIG. 10.

[0047] Next, by photolithography and etching, + A trench gate 31 is formed through the p-type source region 17 and the p-type base layer 16 to reach the n-type region 15(1). The bottom of the trench gate 31 is formed at the first p + The p-type base layer 16 and the first p-type region 3 may be connected. + The trench gate 31 may be located within the n-type region 15(1) sandwiched between the n-type regions 3. Next, the mask used to form the trench gate 31 is removed. An oxide film is used as a mask when forming the trench. After trench etching, isotropic etching may be performed to remove damage to the trench gate 31, or hydrogen annealing may be performed to round the corners of the bottom and opening of the trench gate 31. Only one of isotropic etching and hydrogen annealing may be performed. Alternatively, hydrogen annealing may be performed after isotropic etching.

[0048] Next, by photolithography and etching, +A trench SBD32 is formed through the p-type source region 17 and the p-type base layer 16 to reach the n-type region 15(1). The bottom of the trench SBD32 is formed at the first p + The p-type base layer 16 and the first p-type region 3 may be connected. + The trench SBD 32 may be located within the n-type region 15(1) sandwiched between the n-type regions 3. Next, the mask used to form the trench SBD 32 is removed. At this time, the distance W1 between the edge T of the trench gate 31 and the outer periphery P2 of the trench SBD 32 is equal to or greater than the interval W2 between the trench gate 31 and the trench SBD 32, and the edge of the trench gate 31 is formed closer to the active region 40 than the JTE region 42. The state up to this point is shown in FIG. 11.

[0049] Next, a gate insulating film 19 is formed on the front surface of the silicon carbide substrate and along the inner wall of the trench gate 31. Next, a metal film made of, for example, titanium (Ti) is formed along the inner wall of the trench SBD 32. Next, a heat treatment (annealing) is performed in a nitrogen (N2) atmosphere at a temperature of, for example, about 500°C or less, thereby forming a Schottky junction between the metal film and the semiconductor region on the inner wall of the trench SBD 32.

[0050] Next, polysilicon is deposited and etched so as to fill trench gate 31 and trench SBD 32, leaving polysilicon that will become gate electrode 20 inside trench gate 31 and polysilicon inside trench SBD 32. At this time, etching back may be performed so that the polysilicon remains inside the substrate surface. By filling trench SBD 32 with polysilicon in this way, trench SBD 32 is formed as a heterojunction between a metal film and polysilicon. A top view of the state up to this point is shown in FIG. 12, and a cross section A-A' of FIG. 12 is shown in FIG. 13.

[0051] Next, an interlayer insulating film 21 is formed on the entire front surface of the silicon carbide substrate so as to cover the gate electrode 20. The interlayer insulating film 21 is formed of, for example, NSG (Non-doped Silicate Glass), PSG (Phospho Silicate Glass), BPSG (Boro Phospho Silicate Glass), HTO (High Temperature Oxide), or a combination thereof. Next, the interlayer insulating film 21 and the gate insulating film 19 are patterned to form contact holes, and n + The source region 17 is exposed. ++ When a contact region is formed, n + type source region 17 and p ++ The mold contact region is exposed. The trench gate 31 opens the interlayer insulating film 21 only in the transition region 41. A top view of the state up to this point is shown in FIG. 14, and a cross section of this state taken along line A-A' in FIG. 12 is shown in FIG.

[0052] Next, a barrier metal is formed and patterned to cover the interlayer insulating film 21. + type source region 17 and p ++ The n-type contact area is then exposed again. + A source electrode 22 is formed so as to be in contact with the polysilicon buried in the type source region 17 and the trench SBD 32. The source electrode 22 may be formed so as to cover the barrier metal, or may be left only in the contact hole.

[0053] Next, polysilicon (Poly-Si) is deposited over the entire front surface of the silicon carbide substrate. A top view of the state up to this point is shown in FIG. 16, and a cross section A-A' of FIG. 12 at this point is shown in FIG. 17. Next, the polysilicon is patterned by etching, and gate contact region 26 is formed by leaving only the area along the gate runner. A top view of the state up to this point is shown in FIG. 18, and a cross section A-A' of FIG. 12 at this point is shown in FIG. 19. In this way, by dividing the deposition of polysilicon into two steps, one to fill trench SBD 32 and one to form gate contact region 26, it is possible to form a wide gate contact region 26 in the upper part of trench SBD 32.

[0054] Next, an interlayer insulating film 21 is formed over the entire front surface of the silicon carbide substrate. The interlayer insulating film 21 is formed of, for example, NSG, PSG, HTO, or a combination thereof. A top view of the state up to this point is shown in FIG. 20, and a cross section of this state taken along the line A-A' in FIG. 12 is shown in FIG. 21. Next, the interlayer insulating film 21 is patterned to form contact holes, exposing the gate contact region 26.

[0055] Next, a source electrode pad 28 and a gate runner 27 are formed so as to fill the contact hole. A part of the metal layer deposited to form the source electrode pad 28 may be used as a gate electrode pad. A top view of the state up to this point is shown in FIG. 22, and a cross section of the state taken along the line A-A' in FIG. 12 is shown in FIG. 23. + A metal film such as a nickel (Ni) film or a titanium (Ti) film is formed on the back surface of the silicon carbide substrate 2 at the contact portion of the drain electrode by sputter deposition or the like. This metal film may be a laminate of multiple Ni films and Ti films. Annealing such as rapid thermal annealing (RTA) is then performed so that the metal film is silicided to form an ohmic contact. A thick film, such as a laminate film in which a Ti film, a Ni film, and a gold (Au) film are sequentially laminated, is then formed by electron beam (EB) deposition or the like to form the drain electrode.

[0056] In the above-described epitaxial growth and ion implantation, n-type impurities (n-type dopants) may be, for example, nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb), which impart n-type conductivity to silicon carbide. P-type impurities (p-type dopants) may be, for example, boron (B), aluminum (Al), gallium (Ga), indium (In), or thallium (Tl), which impart p-type conductivity to silicon carbide. In this manner, the MOSFET shown in FIGS. 1 to 4 is completed.

[0057] As described above, according to the embodiment, the trench gate is surrounded by the trench SBD. As a result, the portion of the trench gate that contacts the source electrode is inside the region surrounded by the trench SBD. Therefore, outside the region surrounded by the trench SBD, when a negative bias is applied to the drain side of the silicon carbide semiconductor device with an SBD built in, the parasitic pn diode does not operate in a bipolar manner, thereby suppressing forward degradation and an increase in turn-on loss.

[0058] The present invention can be modified in various ways without departing from the spirit and scope of the present invention. In the above-described embodiments, for example, the dimensions and impurity concentrations of each component are variously set according to required specifications. Furthermore, while the above-described embodiments have been described using MOSFETs as examples, the present invention is not limited to these and can be widely applied to various silicon carbide semiconductor devices that conduct and block current by gate drive control based on a predetermined gate threshold voltage. Examples of silicon carbide semiconductor devices that are gate drive controlled include IGBTs (Insulated Gate Bipolar Transistors). Furthermore, while the above-described embodiments have been described using silicon carbide as a wide bandgap semiconductor, the present invention can also be applied to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). Furthermore, while the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0059] As described above, the semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable for silicon carbide semiconductor devices with a trench gate structure. [Explanation of symbols]

[0060] 1, 101 n - Mold drift layer 2, 102 n + Silicon carbide substrate 3, 103 1st p. + type area 4, 104 2nd p. + type area 5, 105 p. + type area 15, 115 n-type region 15a Lower n-type region 15b Upper n-type region 16, 116 p-type base layer 17, 117 n + Type Source Area 18, 118 p. ++ Mold contact area 19, 119 Gate insulating film 20, 120 gate electrode 21, 121 Interlayer insulating film 22, 122 Source electrode 25 Interlayer insulating film 26 Gate contact area 27 Gate Runner 28 Source electrode pad 29, 129 Schottky metal 31, 131 Trench gate 32, 132 Trench SBD 40, 140 active area 41, 141 Jumper area 42, 142 Edge area 43 JTE area 50, 150 Silicon carbide semiconductor device with built-in SBD

Claims

1. a semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided on the opposite side of the first semiconductor layer with respect to the semiconductor substrate; a first semiconductor region of a first conductivity type selectively provided inside the second semiconductor layer and having a higher impurity concentration than the semiconductor substrate; a first trench and a second trench that penetrate the first semiconductor region and the second semiconductor layer and reach the first semiconductor layer; a gate electrode provided inside the first trench via a gate insulating film; a Schottky electrode provided inside the second trench; Equipped with the first trenches are provided in a stripe shape in a plan view, the second trench surrounds the first trench, an edge region surrounding an active region through which current flows in an on-state and maintaining a breakdown voltage is provided with a junction termination structure for improving the breakdown voltage; In a transition region between the active region and the edge region, the first trench is covered with the second semiconductor layer and a second semiconductor region of a second conductivity type, and the sidewalls of the second trench are in contact with the second semiconductor region, the first semiconductor layer, and the second semiconductor layer.

2. the second trench has a stripe-shaped portion parallel to the first trench and a peripheral portion connecting the stripe-shaped portions, 2. The semiconductor device according to claim 1, wherein the distance between the end of the first trench and the outer periphery of the second trench is equal to or greater than the spacing between the first trench and the second trench, and the end of the first trench is located closer to the active region than the junction termination structure.

3. 3. The semiconductor device according to claim 1, wherein the second trench is formed by a heterojunction between a metal film formed along an inner wall of the second trench and polysilicon buried in the second trench.

4. 4. The semiconductor device according to claim 1, wherein a portion of the second trench is provided at a position opposite in the depth direction to a gate contact region that connects the gate electrode and the gate runner.

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