Memory circuit with variable resistance element and test device therefor

Abstract

To provide a storage circuit having a resistance change type element and a test device thereof, capable of accurately reading stored data of a memory cell composed of the resistance change type element.SOLUTION: A storage circuit 11 includes: an allay 21 of memory cells MC composed of a resistance change type element; conversion circuits BL, RTj, and RQj that convert a resistance value of each memory cell MCij to a signal level of an electric signal; reference signal generation circuits 23 and RTR that generate a reference signal V common to a plurality of columns; a correction circuit that corrects one of the signal level of the reference signal and the signal level of the electric signal per each column of the array 21 of the memory cells; and an RW circuit 24 that determines stored data of the memory cell belonging to the corresponding column by comparing one of the reference level corrected by the correction circuit and the signal level of the electric signal and the other of the reference level and the signal level of the electric signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a memory circuit including a resistance variable element as a memory cell and a test device for the memory circuit. [Background technology]

[0002] Patent Document 1 discloses a memory circuit including a plurality of bit lines connected to a plurality of resistance-change memory cells, and a plurality of sense amplifiers that amplify the difference between the bit line voltage and a reference voltage to determine data read from the memory cells. A common reference voltage is applied to the plurality of sense amplifiers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 112068 [Non-patent literature]

[0004] [Non-Patent Document 1] J. Solid-State Circuits, Jan 2019 P231"A 1-Mb 28nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination" Summary of the Invention [Problem to be solved by the invention]

[0005] The resistance value of a resistance change memory cell varies to some extent. As a result, even if the same data is stored in the memory cells, the voltage of the bit line varies depending on the memory cell. This point will be explained using a specific example.

[0006] In the memory circuit shown in FIG.i (i is a natural number) is connected to a bit line BL, which is connected to the positive input terminal of a sense amplifier SA. The bit line BL is supplied with a read voltage V R is pulled up to

[0007] Memory cell MC i , respectively, the select transistor ST i are connected in series. The select transistor ST i The other end is grounded via a source line SL and a ground transistor GT.

[0008] Each memory cell MC i is formed from a resistance variable element such as a magnetoresistive element, and is set to high or low resistance. Data is stored by assigning data "1" and "0" to the two resistance values. Here, "1" is assigned to high resistance, and "0" is assigned to low resistance.

[0009] In this configuration, the memory cell MC i When reading out stored data from the word line WL, first, the load transistor RT and the ground transistor GT are turned on. i The voltage of the select transistor ST i Then, as shown in FIG. 29, the voltage of the bit line BL (bit line voltage) V b gradually decreases, and the read voltage V R (memory cell MC i 29, the voltage drops to a value obtained by dividing the resistance of the memory cell MC i The bit line voltage V when the stored data is "1" and has high resistance b The dashed line indicates the change in memory cell MC i The bit line voltage V when the stored data is "0" and the resistance is low b Therefore, the memory cell MC i The bit line voltage V when b and the bit line voltage V at low resistance bDuring this time, the reference voltage V ref By setting i The stored data can be determined.

[0010] However, a large number of memory cells MC are connected to one bit line BL. The characteristics of the memory cells MC are not the same. Therefore, the bit line voltage V b As shown in FIG. 30(a), the bit line voltage V b1 and V b0 Therefore, in order to correctly determine the stored data, the reference voltage V ref is the bit line voltage V when the stored data is "1" b The distribution range of and the bit line voltage V when the stored data is "0" b The distribution range of the

[0011] Furthermore, in the memory circuit described in Patent Document 1, a common reference voltage V ref However, it is inevitable that the characteristics of the memory cells MC, the characteristics of the load transistors RT, the characteristics of the ground transistors GT, and the arrangement positions vary among the bit lines BL. b Therefore, a common reference voltage V ref For example, it is not easy to set the bit line voltage V b If the reference voltage V ref No matter how it is set, it is difficult to correctly determine the stored data of all memory cells MC.

[0012] In addition, the sense amplifier SA of each column has an offset voltage ΔV offset occurs. Offset voltage ΔV offsetAlthough 0V is desirable, in reality some significant voltage is generated. offset varies between the sense amplifiers SA. b and the reference voltage V ref Even if the voltage is supplied, the output of the sense amplifier SA varies.

[0013] In this regard, Non-Patent Document 1 discloses an offset cancellation technique that reduces variations in the offset voltage of a sense amplifier. This offset cancellation technique holds a voltage equivalent to the offset voltage in a capacitor inside the circuit, and cancels the offset voltage by adding that voltage to the gate voltage of the transistor that constitutes the sense amplifier.

[0014] However, this offset cancellation technique requires a capacitor, which is an analog element, and multiple transistors to control the charge, which makes the circuit large and makes it difficult to control the voltage due to the charge stored in the capacitor.Furthermore, it requires a voltage setting operation for each sense amplifier operation, which is cumbersome.

[0015] A similar problem occurs in a memory circuit in which a memory element is composed of a pair of memory cells that store complementary data and outputs a pair of complementary read data.

[0016] The present invention has been made in view of the above circumstances, and has an object to enable accurate reading of stored data in a memory cell formed of a resistance variable element. [Means for solving the problem]

[0017] In order to achieve the above object, a memory circuit according to a first aspect of the present invention comprises: a memory cell array including memory cells arranged in a matrix, each memory cell being made up of a resistance variable element; a selection circuit for selecting the memory cell in the memory cell array; a conversion circuit that converts the resistance value of the memory cell selected by the selection circuit into an electric signal; a reference signal generating circuit for generating a reference signal for determining data stored in the memory cell; The aforementioned Memory Cell Array Arranged in columns of Re, before a sense amplifier for determining the stored data of the memory cell selected by the selection circuit; a correction data storage means for storing correction data for correcting physical characteristics for determining the stored data of the memory cells for each of the sense amplifiers; a correction circuit for correcting the physical characteristics for each of the sense amplifiers in accordance with the correction data stored in the correction data storage means; Equipped with 、 the physical characteristic is a physical characteristic of one of the electrical signal converted by the conversion circuit and the reference signal; the correction circuit corrects the physical characteristics of the one signal in accordance with the correction data; The sense amplifier compares the one signal after the physical characteristics have been corrected by the correction circuit with the other signal, which is the electrical signal converted by the conversion circuit and the reference signal, to determine the stored data of the memory cell selected by the selection circuit. .

[0018] The physical characteristic is, for example, the physical characteristic of the reference signal. In this case, the correction circuit corrects the physical characteristic of the reference signal in accordance with the correction data. The sense amplifier compares the reference signal whose physical characteristic has been corrected by the correction circuit with the electrical signal converted by the conversion circuit to determine the storage data of the memory cell selected by the selection circuit. The physical characteristic is, for example, a physical characteristic of the electrical signal converted by the conversion circuit. In this case, the correction circuit corrects the physical characteristic of the electrical signal converted by the conversion circuit in accordance with the correction data, and the sense amplifier compares the electrical signal whose physical characteristic has been corrected by the correction circuit with the reference signal to determine the storage data of the memory cell selected by the selection circuit.

[0019] In order to achieve the above object, a memory circuit according to a second aspect of the present invention comprises: a memory cell array including memory cells arranged in a matrix, each memory cell being made up of a resistance variable element; a selection circuit for selecting the memory cell in the memory cell array; a conversion circuit that converts the resistance value of the memory cell selected by the selection circuit into an electric signal; a reference signal generating circuit for generating a reference signal for determining data stored in the memory cell; a sense amplifier arranged for each column of the memory cell array, for comparing the electrical signal converted by the conversion circuit with the reference signal generated by the reference signal generation circuit to determine the stored data of the memory cell selected by the selection circuit; a correction data storage means for storing correction data for correcting physical characteristics for determining the stored data of the memory cells for each of the sense amplifiers; a correction circuit for correcting the physical characteristics for each of the sense amplifiers in accordance with the correction data stored in the correction data storage means; Equipped with The correction circuit corrects the offset voltage of the sense amplifier as the physical characteristic in accordance with the correction data. The correction data storage means is configured to store or rewrite the correction data in accordance with a signal from an external device of the storage circuit, for example. For example, the correction data storage means is a multi-bit digital memory, and the correction circuit includes a D / A conversion circuit that converts the correction data stored in the correction data storage means into an analog correction signal, and corrects the physical characteristic in accordance with the analog correction signal output by the D / A conversion circuit. For example, the physical characteristic (physical quantity) is a voltage value or a current value. do.

[0020] The correction circuit includes, for example, a correction signal generation circuit for each sense amplifier that generates a correction signal in accordance with the correction data stored in the correction data storage means, and an addition circuit for each sense amplifier that adds the correction signal generated by the correction signal generation circuit to one of the electrical signal and the reference signal to correct it and supplies it to the sense amplifier.

[0021] The correction circuit includes, for example, an amplifier circuit that corrects one of the electrical signal and the reference signal by amplifying it with an amplification factor according to the correction data stored in the correction data storage means.

[0022] The amplifier circuit includes, for example, an operational amplifier and an amplification factor change circuit that changes at least one of the resistance value between the output terminal and negative input terminal of the operational amplifier and the resistance value between the negative input terminal of the operational amplifier and a reference voltage in accordance with the correction data.

[0023] The correction circuit may, for example, calculate a resistance between one end of each of the memory cells and a first reference voltage, and a resistance between each of the memory cells and a second reference voltage. At least one of and a voltage dividing resistor changing means for correcting the electrical signal output by the conversion circuit by changing the voltage dividing resistor in accordance with the correction data.

[0024] The correction circuit includes, for example, a plurality of transistors electrically connecting one end of each of the memory cells to the first reference voltage, and the plurality of transistors are turned on and off according to the correction data stored in the correction data storage means.

[0025] The correction circuit includes, for example, a resistance element connected in series to the current paths of the plurality of transistors.

[0027] If the physical characteristic is the offset voltage of the sense amplifier, for example, The sense amplifier is The correction circuit includes a plurality of transistors connected to each other, and corrects the voltage at a predetermined connection node of the plurality of transistors that make up the sense amplifier in accordance with the correction data.

[0028] The correction data storage means includes, for example, a resistance variable element having the same configuration as the memory cell.

[0029] The memory cells have resistance values ​​corresponding to variable data to be stored, for example, and the conversion circuit generates an electrical signal corresponding to the stored data of the memory cells selected by the selection circuit, and the reference signal generation circuit includes memory cells having resistance values ​​corresponding to fixed data to be stored, and generates the reference signal according to the resistance values.

[0030] The memory cells have resistance values ​​corresponding to variable data to be stored, for example. For example, the reference signal generation circuit includes a matrix of second memory cells, each paired with a corresponding one of the memory cells and configured with a resistance variable element that stores data complementary to the corresponding memory cell, and generates the reference signal having a signal level corresponding to the resistance value of the second memory cell selected by the selection circuit.

[0031] The test device of the present invention controls the correction circuit to set a plurality of correction amounts for each of the memory cells, and includes a read circuit that reads stored data for each correction amount, and a test circuit that can correctly read stored data for each of the memory cells when any correction amount is set. Or Discrimination means And, before Based on the result of the discrimination by the discrimination means for each column, the correction amount for each column is and storing correction data corresponding to the correction amounts for each column in the correction data storage means. and a setting means for setting the same.

[0032] The setting means, for example, sets in the correction circuit, for each column of the matrix of memory cells, a correction amount that is determined to enable all stored data in the memory cells of each column to be correctly read based on the results of the column-by-column determination by the determination means.

[0033] The memory circuit includes, for example, a column of redundant memory cells, and the setting unit performs the following operation based on the result of the determination by the determination unit: No matter what correction amount is used, the stored data cannot be read correctly.access to the memory cell is replaced with access to the redundant memory cell The selection circuit Set it up. [Effects of the Invention]

[0034] According to the memory circuit of the present invention, the physical characteristics for determining stored data can be customized for each sense amplifier, thereby enabling appropriate determination of stored data. [Brief explanation of the drawings]

[0035] [Figure 1] 1 is a block diagram of a memory circuit according to an embodiment of the present invention; [Figure 2] FIG. 1(a) is a diagram showing the configuration of a magnetic tunnel junction (MTJ) element, and FIG. 1(b) is a diagram explaining the change in resistivity of the magnetic tunnel junction (MTJ) element. [Figure 3] FIG. 2 is a diagram showing a configuration of a reference cell circuit shown in FIG. [Figure 4] FIG. 2 is a block diagram showing the configuration of an RW circuit shown in FIG. [Figure 5] 5 is a diagram illustrating a correction voltage Vame shown in FIG. 4. [Figure 6] 2(a) to 2(g) are timing charts for explaining the read operation of the memory circuit shown in FIG. [Figure 7] FIG. 2 is a diagram for explaining a test device for the memory circuit shown in FIG. [Figure 8] FIG. 8 is a block diagram showing the configuration of the test device shown in FIG. [Figure 9] 9 is a flowchart of an errata creation process executed by the test device shown in FIGS. 7 and 8. [Figure 10] 10 is a flowchart of a process for determining whether or not an errata sheet is to be created during the process shown in FIG. 9 . [Figure 11] 10(a) and 10(b) are diagrams showing an example of an errata created by the errata creation process shown in FIG. 9. [Figure 12] 10 is a flowchart of an evaluation process that is executed following the errata creation process shown in FIG. 9. [Figure 13] (a) is a diagram showing an example of a configuration in which an effective reference voltage is generated by subtracting a correction voltage from a reference voltage using a subtraction circuit; (b) is a diagram showing an example of a configuration in which an effective bit line voltage is generated by adding a correction voltage to a bit line voltage using an addition circuit; and (c) and (d) are diagrams showing examples of a configuration in which an addition circuit is placed within a sense amplifier to adjust the offset voltage. [Figure 14] (a) is a diagram showing an example of a configuration in which a reference voltage is amplified by an amplifier to generate an effective reference voltage; (b) is a diagram showing an example of a configuration in which a bit line voltage is amplified by an amplifier to generate an effective bit line voltage; and (c) and (d) are diagrams showing examples of a configuration in which an amplifier circuit is placed within a sense amplifier to adjust the offset voltage. [Figure 15] FIG. 1A is a circuit diagram showing an example of a configuration in which the bit line voltage is adjusted by adjusting the resistance value of a load resistor, and FIG. 1B is a circuit diagram showing an example of a configuration in which the bit line voltage is adjusted by adjusting the resistance value of a ground resistor circuit. [Figure 16] FIG. 1 is a block diagram showing an example of the configuration of a memory circuit using a current-driven sense amplifier. [Figure 17] FIG. 1A is a diagram showing an example of a configuration in which a reference current is amplified by a current amplifier to generate an effective reference current, and FIG. 1B is a diagram showing an example of a configuration in which a bit line current is amplified by a current amplifier to generate an effective bit line current. [Figure 18] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a sense amplifier. [Figure 19] FIG. 10 is a circuit diagram showing another example of the circuit configuration of the sense amplifier. [Figure 20] 5 is a circuit diagram showing an example of the configuration of one bit of the correction memory shown in FIG. 4. FIG. [Figure 21] 1A is a circuit diagram showing another example of a configuration for generating an effective reference voltage from a reference voltage, and FIG. 1B is a circuit diagram showing another example of a configuration for generating an effective bit line voltage from a bit line voltage. [Figure 22] FIG. 10 is a circuit diagram showing another example of a configuration for generating an effective reference voltage from a reference voltage. [Figure 23]10(a) and 10(b) are circuit diagrams showing other configuration examples for generating an effective reference voltage from a reference voltage. [Figure 24] 10(a) and 10(b) are circuit diagrams showing other configuration examples of the load resistance circuit that adjusts the bit line voltage. [Figure 25] 10(a) and 10(b) are circuit diagrams showing other configuration examples of the load resistance circuit that adjusts the bit line voltage. [Figure 26] FIG. 10 is a circuit diagram showing an example of the configuration of a sense amplifier having a configuration for adjusting an offset voltage. [Figure 27] 1 is a circuit diagram of an embodiment in which the present invention is applied to a memory circuit of a type that stores complementary data in a pair of memory cells. [Figure 28] FIG. 1 is a block diagram showing a basic configuration of a resistance variable memory circuit. [Figure 29] 24 is a timing chart illustrating a read operation of the resistance variable memory circuit shown in FIG. 23. [Figure 30] 10A and 10B are diagrams illustrating variations in bit line voltages. DETAILED DESCRIPTION OF THE INVENTION

[0036] A memory circuit 11 according to an embodiment of the present invention will be described below with reference to the drawings. The memory circuit 11 of this embodiment is a memory circuit that can correct and optimize the reference voltage used in the sense amplifiers arranged for each column of the memory cell array for each column.

[0037] As shown in FIG. 1, the memory circuit 11 according to this embodiment includes a memory cell array 21, a redundant memory cell array 22, a reference cell array 23, a read / write (RW) circuit array 24, a row decoder 31, a column decoder 32, and a read / write controller 33.

[0038] The memory cell array 21 is made up of memory cells MC arranged in a matrix of m rows and n columns. ij(i=1 to m, j=1 to n), where m and n are natural numbers.

[0039] The redundant memory cell array 22 is arranged adjacent to the memory cell array 21 in the column direction, and is made up of redundant memory cells RMC arranged in a matrix of m rows and N columns. ij (i=1 to m, j=1 to N). Note that FIG. 1 shows an example in which N=1, that is, the redundant memory cells RMC are arranged in a matrix of m rows and 1 column. In the following description, N=1, and redundant memory cells RMC1 to RMC m is assumed to be arranged.

[0040] The reference cell array 23 is arranged adjacent to the redundant memory cell array 22 in the column direction. The reference cell array 23 is made up of reference cells RC arranged in a matrix of m rows and 1 column. i (i=1 to m) and a common fixed resistor FR.

[0041] Memory cell MC ij and redundant memory cells RMC i and the reference cell RC i The elements are composed of MTJ (Magnetic Tunneling Junction) elements, which are an example of resistance variable elements, and have the same configuration and characteristics. Details will be described later with reference to Figures 2(a) and 2(b).

[0042] Memory cell MC in the i-th row ij and redundant memory cells RMC i and the reference cell RC i The positions of the pixels in the row direction on the semiconductor substrate are set to be equal to each other.

[0043] The RW circuit array 24 is made up of RW circuits 24 arranged in one row and n columns. j (j=1 to n) and N redundant RW circuits 24 R In this embodiment, N=1, so in FIG. 1, one redundant RW circuit 24 R are placed.

[0044] RW circuit 24 j and 24 R The memory cell MC arranged in the same column as itself during the read operation has a read function and a write function. ij or redundant memory cell RMC i ii) a sense amplifier function for reading out the stored data of the memory cell MC arranged in the same column as itself during a write operation; ij or redundant memory cell RMC i The RW circuit 24 also has the function of writing data to the j and redundant RW circuit 24 R In the following description, the RW circuit 24 j and redundant RW circuit 24 R These may be collectively referred to as the RW circuit 24.

[0045] Each memory cell MC constituting the memory cell array 21 ij At one end of the ij One end of the current path (source-drain path) of the select transistor ST ij The other end of the current path is connected to the source line SL arranged in the j-th column. j The select transistor ST ij are each composed of an NMOS transistor, and their drains are connected to the corresponding memory cells MC ij and its source is connected to a source line SL j is connected to.

[0046] Source line SL j One end of the transistor RQ j The source line SL is grounded through the current path. j The other end of the RW circuit 24 j The source line terminal TS is connected to the source line terminal TS.

[0047] Memory cell MC in the jth column ij The other ends of the bit lines BLj arranged in the j-th column are commonly connected to the bit lines BLj arranged in the j-th column. jOne end of the jth column is connected to the RW circuit 24 j The bit line terminal TB is connected to the bit line terminal TB.

[0048] jth column bit line BL j The load transistor RT j One end of the current path of the load transistor RT j The other end of the current path is connected to the read voltage V R is applied to the load transistor RT j is composed of a PMOS transistor and functions as a load resistor when reading data.

[0049] Redundant memory cells RMC constituting the redundant memory cell array 22 i One end of the redundant select transistor RST i One end of the current path of each redundant select transistor RST i The other ends of the current paths of the redundant select transistors RST are commonly connected to a redundant source line RSL. i is the select transistor ST ij It has the same configuration and characteristics as the

[0050] One end of the redundant source line RSL is grounded via the current path of the redundant ground transistor RRQ. The other end of the redundant source line RSL is connected to the redundant RW circuit 24. R The source line terminal TS is connected to the source line terminal TS.

[0051] Redundant memory cell RMC i The other ends of the redundant bit lines RBL are commonly connected to the redundant RW circuit 24. R The bit line terminal TB is connected to the bit line terminal TB.

[0052] One end of the current path of the redundant load transistor RRT is connected to the redundant bit line RBL. The other end of the current path of the redundant load transistor RRT is connected to a read voltage V R The redundant load transistor RRT is connected to the load transistor RT j It has the same configuration as

[0053] Reference cell RC that constitutes the reference cell array 23 i At one end of the i One end of the current path of each selection transistor AT i The other ends of the current paths of the select transistors AT are commonly connected to a reference source line SLR. i is the select transistor ST ij , RST i It has the same configuration and characteristics as the

[0054] Reference source line SL R One end of the transistor RQ R The current path is connected to ground through the grounded transistor RQ. R The gate of R is pulled up to

[0055] Reference cell RC i The other end of the reference bit line BL R are commonly connected to the reference bit line BL R One end of the RW circuit 241 to 24 n and redundant RW circuit 24 R are commonly connected to the reference bit line terminal TR of the first and second input terminals.

[0056] Reference bit line BL R A reference load transistor RT R One end of the current path of the reference load transistor RT R The other end of the current path is connected to the read voltage V R is applied to the reference load transistor RT R When reading data, the load transistors RT1 to RT n and has the same configuration and characteristics as RRT.

[0057] Also, the reference bit line BL R The reference cell RC in the m-th rowm and the connection node of the reference load transistor RT R A fixed resistor FR is inserted between the connection node and

[0058] In the following description, for the sake of distinction, the reference bit line BL R Among them, i) the reference load transistor RT R The reference memory cell RC i The side portion is connected to the first reference bit line BL R1 , ii) reference load transistor RT R The portion on the RW circuit array 24 side of the connection node with the second reference bit line BL R2 , is called.

[0059] First reference bit line BL R1 The material, thickness, and width of the bit line BL j On the other hand, the second reference bit line BL R2 The cross-sectional area (product of thickness and width) of the first reference bit line BL R1 The cross-sectional area of ​​the second reference bit line BL R2 The resistance value per unit length of the first reference bit line BL R1 is smaller than the resistance per unit length of

[0060] Grounded transistor RQ j A low active read enable signal / RE is applied to the gate of the redundant ground transistor RRQ via an inverter INV. Load transistor RT j and redundant load transistor RRT and reference load transistor RT R A low active read enable signal / RE is applied to the gate of .

[0061] Load transistor RT j and bit line BL j and the select transistor ST ij and grounded transistor RQ jand cooperate with each other to form a memory cell MC ij The resistance value of the bit line voltage V bj In this embodiment, the memory cell MC ij The resistance value of the bit line V is converted into a voltage signal, which is an example of an electrical signal. bj is an example of a signal level of an electrical signal.

[0062] In addition, the redundant load transistor RRT, the redundant bit line RBL, and the redundant selection transistor RST i and the redundant ground transistor RRQ cooperate to form a redundant memory cell RMC i The resistance of the redundant bit line voltage RV b This serves as an example of a conversion circuit that converts the redundant bit line voltage RV b is the redundant memory cell RMC i 10 is an example of a signal level corresponding to a resistance value of .

[0063] Reference load transistor RT R and the reference bit line BL R (BL R1 ,BL R2 ) and selection transistor AT i and grounded transistor RQ R and cooperate with each other to form a reference memory cell RC i and the resistance value Rfix of the fixed resistor FR, and the reference voltage V ref This serves as an example of a reference signal generating circuit that generates a reference voltage V ref is an example of a reference level of the reference signal.

[0064] The row decoder 31 decodes a row address from a higher-level device (not shown) and reads the row address from the memory cell MC to be accessed. ij The word line WL of the row to which i The voltage is set to high level.

[0065] The column decoder 32 decodes a column address from a host device. In addition, the column decoder 32 determines the address of the memory cell MC to be read according to the read / write control signal. ij RW circuit 24 of the column to which j A high-active read column selection signal CLR j ii) the memory cell MC to be written ij RW circuit 24 of the column to which j A high-active write column selection signal CLW j Output.

[0066] Also, a row decoder 31, a column decoder 32, and a word line WL i and the select transistor ST ij is the memory cell MC ij This is an example of a selection circuit that selects

[0067] In accordance with a read / write control signal from a higher-level device (not shown), the read / write controller 33: (i) supplies a low-active read enable signal / RE to the load transistor RT j and the redundant load transistor RRT, and ii) the read enable signal / RE is output to the gate of the ground transistor RQ via the inverter INV. j and to the gate of the redundant ground transistor RRQ, and further, iii) a low-active sense amplifier activation signal is output to all the RW circuits 24 j and redundant RW circuit 24 R In addition, the read / write controller 33 outputs a low active write enable signal / WE to all the RW circuits 24 during a write operation in accordance with the read / write control signal. j and redundant RW circuit 24 R Output to.

[0068] 24 RW circuits each j The bit line terminal TB is the bit line BL of the same column as itself. j The reference bit line terminal TR is connected to the second reference bit line BL R2The source line terminal TS is connected to the source line SL in the same column as itself. j is connected to.

[0069] In addition, each RW circuit 24 j The column decoder 32 outputs a read column selection signal CLR j and the write column selection signal CLW j However, a read enable signal / RE, a write enable signal / WE, and a sense amplifier enable signal / SAE are supplied from the read / write controller 33.

[0070] RW circuit 24 of the jth column j When reading data, the read column selection signal CLR j In response to the read enable signal / RE and the sense amplifier enable signal / SAE, the bit line BL j The bit line voltage V is supplied from bj and the second reference bit line BL R2 The reference voltage V is supplied from ref and the amplified result (read data DATA j ) is latched and output to bus 25.

[0071] In addition, the RW circuit 24 in the j-th column j When writing data, the write column selection signal CLW j and the write enable signal / WE, the write data DATA supplied from the bus 25 j In response to j and source line SL j A voltage is applied between the memory cell MC ij Write data to.

[0072] Redundant RW circuit 24 R Basically, the RW circuit 24 j The redundant RW circuit 24 has the same configuration as the R When reading data, the read column selection signal CLR R In response to the read enable signal / RE and the sense amplifier enable signal / SAE, a redundant bit line voltage RV is supplied from the redundant bit line RBL.b and the second reference bit line BL R2 The reference voltage V is supplied from ref The redundant RW circuit 24 differentially amplifies the read data DATA, latches the amplified result, and outputs it to the bus 25. R When writing data, the write column selection signal CLW R and a write enable signal / WE, the redundant bit line RBL and the reference source line SL are connected in accordance with the write data DATA supplied from the bus 25. R A voltage is applied between the redundant memory cell RMC i Write data to.

[0073] The bus 25 has a bus width of 1 bit.

[0074] Next, the memory cell MC ij , redundant memory cell RMC i , reference cell RC i 2(a) and 2(b) will be described. Since these have the same configuration and characteristics, in FIGS. 2(a) and 2(b), the memory cell MC ij Let us explain with an example.

[0075] Memory cell MC ij is composed of one two-terminal MTJ element M. As shown in Figure 2(a), the MTJ element is composed of three layers: a pinned (fixed) layer MP, an insulating layer MI, and a free (free) layer MF.

[0076] The pinned layer MP and the free layer MF are made of a material such as a ferromagnetic material (for example, CoFeB) or a ferromagnetic Heusler alloy (for example, Co2FeAl, Co2MnSi). The direction of magnetization in the pinned layer MP is fixed, and the direction of magnetization does not change even when a current flows through the layer. On the other hand, the direction of magnetization of the free layer MF is variable, and when a current flows through the layer, the direction of magnetization changes.

[0077] The insulating layer MI is a thin film provided between the pinned layer MP and the free layer MF. The insulating layer MI is made of a material such as magnesium oxide (MgO), alumina (Al2O3), or spinel single crystal (MgAl2O4).

[0078] When the direction of magnetization of the free layer MF changes relatively to the direction of magnetization of the pinned layer MP, the resistance value between one end T1 and the other end T2 of the MTJ element M changes. In the memory circuit 11 of FIG. 1, the memory cell MC ij The free layer MF of the same column is connected to the bit line BL j The pin layer MP is connected to the select transistor ST ij is connected to.

[0079] As shown in Figure 2(b), when the magnetization directions of the pinned layer MP and the free layer MF (indicated by the white arrows) are not aligned (anti-parallel: parallel but opposite), this state is called the anti-parallel state. On the other hand, when the magnetization directions of the pinned layer MP and the free layer MF are the same, this state is called the parallel state.

[0080] Resistance R when MTJ element M is in an antiparallel state ap is the resistance value R when in parallel p The resistance state of the MTJ element M in the antiparallel state is called a high resistance state, and the resistance state of the MTJ element M in the parallel state is called a low resistance state.

[0081] In this embodiment, the high resistance state of the MTJ element M corresponds to data "1", and the low resistance state corresponds to data "0".

[0082] In this embodiment, the MTJ element M is set to a high resistance state when a write current I equal to or greater than a threshold flows from the pinned layer MP to the free layer MF, and is set to a low resistance state when a write current I equal to or greater than a threshold flows from the free layer MF to the pinned layer MP. ij In order to write data "1" to the source line SL, j to the select transistor ST ijand memory cell MC ij via the bit line BL j On the other hand, a current needs to flow through the memory cell MC ij In order to write data "0" to the bit line BL, j From memory cell MC ij and the select transistor ST ij and via the source line SL j It is necessary to pass a current through it.

[0083] Next, the reference voltage V ref The details of the reference circuit for generating the reference signal will be described with reference to FIG. The reference circuit is a reference cell RC i and a common fixed resistor FR. Reference cell RC i is the memory cell MC ij It has the same structure (material, size, impurity concentration, etc.) as the MTJ element M that constitutes the pinned layer MP. However, the magnetization directions of the pinned layer MP and the free layer MF are set to a low resistance state (parallel state) in which they are aligned with each other, and fixed data is stored. Note that the term "same structure" does not mean complete identity. If both MTJ elements can achieve substantially the same function and action, slight structural differences are not a problem and should be interpreted as being within the scope of identity.

[0084] The fixed resistor FR is a high-precision linear resistor. The resistance value Rfix of the fixed resistor FR is greater than 0 and R ap -R p (=R p × MR ratio). fix is the bit line voltage V transmitted to the positive input terminal of the sense amplifier in the RW circuit 24 when reading stored data from the memory cell MC. b and the reference voltage V transmitted to the negative input terminal ref The difference between these values ​​is set to a value equal to or greater than the resolution of the sense amplifier.

[0085] Next, the configuration of the RW circuit 24 will be described with reference to FIG. As shown in the figure, the RW circuit 24 in the j-th column j is the read circuit 240 j and write circuit 246 j Equipped with. Readout circuit 240 j Sense amplifier 241 j and correction memory 242 j and D / A conversion circuit 243 j and the adder circuit 244 j and memory controller 245 j And, it is equipped with.

[0086] Sense Amplifier 241 j The positive input terminal of the bit line BL j and a negative input terminal of the adder circuit 244. j The output terminals of the

[0087] Sense Amplifier 241 j is the bit line BL connected to the positive input terminal j The bit line voltage V bj and adder circuit 244 j The effective reference voltage EV supplied to the negative input terminal from refj Difference with (V bj -EV refj ) is amplified, latched and output. j is (V bj -EV refj )>0, then data "1", (V bj -EV refj If )<0, generate data "0" and latch it. The latched 1-bit data DATA j is output to bus 25.

[0088] Correction memory 242 j is the correction voltage V amej 3-bit correction data D j Correction memory 242 jis composed of a rewritable nonvolatile memory element. The nonvolatile memory element may be, for example, an MTJ element manufactured in the same manufacturing process as the memory cells MC, etc. However, the nonvolatile memory element and circuit configuration are arbitrary.

[0089] Correction memory 242 j memory controller 245 j From the write control signal WC j and 3-bit correction data D j When this 3-bit correction data D j After that, the stored 3-bit correction data D j D / A conversion circuit 243 j Output to.

[0090] D / A (digital-analog) conversion circuit 243 j is the correction memory 242 j 3-bit correction data D output by j Analog correction voltage V amej and the summing circuit 244 j Correction data D j and the correction voltage V amej The correspondence between the 3-bit correction data and the analog correction voltage V amej is generated.

[0091] As shown in FIG. 4, the summing circuit 244 j is the reference voltage V applied to one of the input terminals ref and the compensation voltage V applied to the other input terminal amej By adding and, the reference voltage V ref is corrected to a value suitable for the jth column and output. j Output voltage = (reference voltage V ref + Correction voltage V amej ) is the effective reference voltage EV refj As mentioned above, the sense amplifier 241 j is the bit line voltage V bj and the effective reference voltage EV refj Difference (Vbj -EV refj ) is amplified, latched and output.

[0092] D / A conversion circuit 243 j and adder circuit 244 j and cooperate with each other to generate the correction memory 242. j 3-bit correction data D output by j Analog correction voltage V amej and the summing circuit 244 j Correction data D j and the correction voltage V amej The correspondence between the 3-bit correction data and the analog correction voltage V amej is generated.

[0093] Memory Controller 245 j The memory controller 245 receives a memory address, data, and a write instruction signal from a host device. j is the correction data D supplied when the memory address is specified and the write control signal is turned on. j and the write control signal WC j and the correction memory 242 j and supplying the correction data D j Correction memory 242 j Write to.

[0094] In addition, the correction memory 242 j is the correction data D for correcting the physical characteristics (physical quantity) for determining the stored data for each sense amplifier. j The physical characteristic to be corrected here is the sense amplifier 241. j The reference voltage V corresponds to the magnitude (physical quantity) of the signal input to ref In addition, the correction memory 242 j and D / A conversion circuit 243 j and the adder circuit 244 j and memory controller 245 jand are examples of correction circuits that correct the physical characteristics of the reference signal for each sense amplifier circuit. j and D / A conversion circuit 243 j is an example of a correction signal generating circuit that generates a correction signal.

[0095] On the other hand, the write circuit 246 j connects the bit line BL to the output terminal Tout1. j is connected to the output terminal Tout2, and the source line SL j Also, the write circuit 246 j The write enable signal / WE and the write column selection signal CLW are j The data terminal TD of the write circuit 246 receives write data DATA j is supplied.

[0096] Write circuit 246 j indicates that the write enable signal / WE is at a low level and the write column selection signal CLW j When a column to which it belongs is specified, the write data DATA supplied from the bus 25 is j In accordance with the above, the voltage applied between the output terminal Tout1 and the output terminal Tout2 is controlled to access the memory cell MC ij Specifically, the write circuit 246 writes data to j As shown in FIG. 2(b), the write data DATA j When VOUT = 0, a first voltage V1 is applied to the output terminal Tout2, and a second voltage V2 lower than the first voltage V1 is applied to the output terminal Tout1, and a current flows from the output terminal Tout2 to the bit line BL j →Selected memory cell MC ij →Select transistor ST that is on ij →Source line SL j → A current flows through the output terminal Tout1, and data "0" is stored in the memory cell MC ij On the other hand, the write circuit 246 writes the write data DATA jWhen the value of the second voltage V2 is 1, the second voltage V2 is applied to the output terminal Tout2, and the first voltage V1 higher than the second voltage V2 is applied to the output terminal Tout1, and the output terminal Tout1 → the source line SL j →Select transistor ST that is on ij →Selected memory cell MC ij →Bit line BL j → A current flows through the output terminal Tout2, and data "1" is stored in the memory cell MC ij Write to.

[0097] Redundant RW circuit 24 R RW circuit 24 j It has the same functions and configuration as the above.

[0098] Next, the operation of the memory circuit 11 having the above configuration will be described. First, the read operation will be described with reference to the timing charts of FIGS. 6(a) to 6(g).

[0099] For ease of understanding, the following description will be given taking as an example an operation in a page mode in which data stored in a plurality of memory cells MC in the same row is read out in sequence. The row to be read out is the first row, and the memory cell MC in the first row and first column is 11 →Memory cell MC in the first row and second column 12 →...→Memory cell MC in the first row and nth column 1n The stored data is read out in the order of

[0100] In addition, each read circuit 240 of each RW circuit 24 j Correction memory 242 that configures j The appropriate value of the correction data D j The method of storing will be described later.

[0101] First, to perform reading, the read / write controller 33 sets the read enable signal / RE to the active low level, as shown in FIG. 6(a).

[0102] In response to the read enable signal / RE going low, all the load transistors RT1 to RT n , redundant load transistor RRT, and reference load transistor RT R As a result, as shown in FIGS. 6(a) and 6(e), all the bit lines BL1 to BL n and the redundant bit line RBL and the reference bit line BL R is the read voltage V R will be charged.

[0103] Also, the inverted signal of the read enable signal / RE is input to the ground transistors RQ1 to RQ n and is supplied to the gate of the redundant ground transistor RRQ, and the ground transistors RQ1 to RQ n The redundant ground transistor RRQ is turned on. n , redundant source line RSL, reference source line SL R All are at ground level.

[0104] In addition, all RW circuits 241 to 24 n and redundant RW circuit 24 R goes into read mode, and the internal sense amplifier 241 goes into a standby state.

[0105] Next, the memory cell MC in the first row 1j 6(b), the row decoder 31 sets the voltage of the word line WL1 to a high level and maintains the voltages of the other word lines WL at a low level. When the voltage of the word line WL1 becomes high, the select transistor ST of the first row is 11 ~ST 1n ,RST1,AT1 turn on.

[0106] Then, in each column, the load transistor RT j →Bit line BL j → Memory cell MC in the first row 1j →Select transistor ST of the first row 1j →Source line SL j → Grounded transistor RQ j→Ground, and current flows. Therefore, as shown in Figure 6(d), j memory cell MC 1j The bit line voltage V bj The bit line voltage V bj However, RW circuit 24 j Similarly, a bit line voltage RV corresponding to the resistance value of the redundant memory cell RMC1 is applied to the redundant bit line RBL. b occurs, and the redundant RW circuit 24 R to reach.

[0107] Also, the reference load transistor RT R → Fixed resistor FR → First reference bit line BL R1 → Reference cell RC1 in the first row → Select transistor AT1 in the first row → Reference source line SL R → Grounded transistor RQ R → Ground, and a current flows, and as shown in FIG. 6(e), a reference voltage V corresponding to the sum (composite resistance) of the resistance value of the reference cell RC1 and the resistance value of the fixed resistor FR is applied to the first reference bit line BLR1. ref This reference voltage V ref is constant during a read operation unless there is a row change, and the RW circuit 24 j and redundant RW circuit 24 R is applied in parallel to

[0108] 24 RW circuits each j and redundant RW circuit 24 R Inside the adder circuit 244 j is the reference voltage V supplied via the reference bit line terminal TR ref D / A conversion circuit 243 j The correction voltage V is supplied from amej and the effective reference voltage EV refj That is, the adder circuit 244 j is the reference voltage V common to all sense amplifiers 241. ref is the correction voltage V corresponding to the correction amount appropriate for the jth column. amej By adding these, the effective reference voltage EV for the jth column is obtained.refj This effective reference voltage EV refj is the bit line BL of that column. j A plurality of memory cells MC connected to ij This corresponds to the optimum reference voltage for determining the stored data.

[0109] Here, the read / write controller 33 sets the sense amplifier enable signal / SAE to a low level (active) as shown in FIG. 6(c).

[0110] Full-column and redundant-column sense amplifiers 241 j In response to the falling edge of the sense amplifier enable signal / SAE, the bit line voltage V bj and the effective reference voltage EV refj The differential signal is amplified and the amplified data is latched.

[0111] The column decoder 32 decodes the column address and outputs the read column selection signals CLR1 to CLR2 in accordance with the read / write control signal, as shown in FIG. 6(f). n As a result, as shown in FIG. 6(g), the sense amplifier 241 j is the latched read data DATA j are output onto bus 25 in order.

[0112] Thereafter, the same operation is repeated according to the row address and column address of the memory cell MC to be read.

[0113] Note that the stored data can be read not only in page mode, but also by accessing the memory cells MC by sequentially switching the row address and column address, thereby reading the stored data.

[0114] Here, the memory cell MC in the first row and the k-th column (k is any one of 1 to n) of the memory cell array 21 1k is defective, and the memory cell MC in the first column and the k-th column is 1kIn this case, the row decoder 31 and the column decoder 32 are configured to receive the defective memory cell MC. 1k The row address and column address of the redundant memory cell RMC1 are registered in advance as the replacement address, and the row address and column address of the redundant memory cell RMC2 are registered in advance as the replacement address. The method of registration will be described later.

[0115] When the row address and column address specify the first row and the k-th column, the row decoder 31 sets the word line WL1 of the first row to a high level according to the setting, and the column decoder 32 sets the read column selection signal CLR k is kept at a low level, and the read column selection signal CLR R is set as the high level.

[0116] As previously mentioned, the sense amplifier 241 R In response to the falling edge of the sense amplifier enable signal / SAE, the redundant bit line voltage RV b and the effective reference voltage EV refR The differential signal is amplified and the amplified data is latched.

[0117] Subsequently, when the column address designates the k-th column, the column decoder 32 outputs the read column selection signal CLR k is kept at a low level, and the read column selection signal CLR R This sets the redundant column sense amplifier 241 R outputs the latched read data DATA onto the bus 25.

[0118] In this way, each memory cell MC ij The stored data is the effective reference voltage EV refj The defective memory cell MC ij is the redundant memory cell RMC j is replaced by the redundant memory cell RMC j The stored data is read out from

[0119] As described with reference to FIG. 30(b), the reference voltage V ref On the other hand, according to this embodiment, it is difficult to set the reference voltage V ref is common to all columns, but the correction voltage V ame By setting the appropriate effective reference voltage EV ref Therefore, as shown in FIG. 30(a), it is possible to set the effective reference voltage EV ref can be set, and the stored data can be accurately determined.

[0120] Reference voltage V for each column ref In order to optimize the effective reference voltage EV for each column of the memory cell array, it is conceivable to arrange a reference voltage generating circuit for each column of the memory cell array. However, this method would make the size of the reference voltage generating circuit too large. In this embodiment, the effective reference voltage EV for each column can be generated relatively easily with a relatively small circuit size. refj can be set.

[0121] As explained in the background art, the sense amplifier 241 of this embodiment also has an offset voltage ΔV offset , which varies between the sense amplifiers 241. If no countermeasures are taken, the offset voltage ΔV offset In contrast, in this embodiment, the correction voltage V ame Therefore, the offset voltage ΔV offset This can reduce misclassification due to variations in the

[0122] In this embodiment, the reference cell RC in the i-th row i and the memory cell MC in the i-th row ij Therefore, the memory cell MC to be accessed is located at the same position in the row direction. ij The reference cell RC to be accessed depends on the row position of iTherefore, the position of the memory cell MC to be accessed changes. ij The bit line voltage V bj The reference voltage V ref Therefore, the memory cell MC ij Data from the memory can be read accurately.

[0123] Next, a write operation of the memory circuit 11 will be described. Here, the memory cell MC ij Suppose you want to write data to First, the read / write controller 33 sets the write enable signal / WE to low level in accordance with the read / write control signal. The row decoder 31 decodes the row address and outputs the data to the memory cell MC ij The word line WL of the i-th row to which i The voltage is set to high level. Furthermore, the column decoder 32 decodes the column address and reads the data from the memory cell MC ij The RW circuit 24 of the j-th column to which j Write column selection signal CLW j supply.

[0124] The host device also transmits 1-bit write data DATA on the bus 25. j This data is transmitted to all the write circuits 246.

[0125] Write circuit 246 j is a low-level write enable signal / WE and a high-level write column select signal CLW. j In response to this, a write operation is performed and the write data DATA j When the value is "0", the voltage of the output terminal Tout2 is set to the first voltage V1 of high level, and the voltage of the output terminal Tout1 is set to the second voltage V2 of low level. As a result, the write current I flows from the output terminal Tout2 to the bit line BL j →Memory cell MC ij →Select transistor ST ij →Source line SLj → It flows through the output terminal Tout1 and the memory cell MC ij Data "0" is written to the write circuit 246. j When the write data is "1", the voltage of the output terminal Tout2 is set to the low-level second voltage V2, and the voltage of the output terminal Tout1 is set to the high-level first voltage V1. As a result, the write current I flows from the output terminal Tout1 to the source line SLj and the select transistor ST ij →Memory cell MC ij →Bit line BL j →Output terminal Tout2 and memory cell MC ij The data "1" is written to

[0126] Here, the memory cell MC in the i-th row and k-th column (k is any one of 1 to n) of the memory cell array 21 ik is defective, and the redundant memory cell RMC i In this case, the column decoder 32 detects the defective memory cell MC ik When the write column selection signal CLW is specified, k is maintained at a low level, and the write column selection signal CLW R is set to a high level.

[0127] When the column address specifies the defective column k, the column decoder 32 outputs the write column selection signal CLW according to the setting. k is maintained at a low level, and the write column selection signal CLW R is set to high level. R is a low-level write enable signal / WE and a high-level write column select signal CLW. R In response to this, a write operation is performed and the write data DATA j Redundant memory cell RMC i Write to.

[0128] Next, the appropriate effective reference voltage EV refj To generate j Readout circuit 240 jCorrection memory 242 j Correction data D j This setting process is performed, for example, after the memory circuit 11 is manufactured, during a test operation of a semiconductor chip including the memory circuit 11.

[0129] First, a test device that executes the test operation will be described. As shown in FIG. 7, the test device 100 includes the row decoder 31, the column decoder 32, the read / write controller 33 of the memory circuit 11, and the memory controllers 2451 to 2455 of all the RW circuits 24. n , 245 R , connected to bus 25.

[0130] When the test device 100 is connected, the row decoder 31 outputs the row address supplied from the test device 100 as is, the column decoder 32 outputs the column address supplied from the test device 100 as is, and the read / write controller 33 outputs the sense amplifier enable signal / SAE, the read enable signal / RE, and the write enable signal / WE supplied from the test device 100 as is. n ,245 R When its own address is specified, the correction data D supplied from the test device 100 j and the write control signal WC j Correction memory 242 j is output as is.

[0131] As shown in FIG. 8, the test device 100 includes a CPU 101, a memory 102, an interface (I / F) 103, an auxiliary storage device 104, and an input / output device (I / O device) 105.

[0132] A CPU (Central Processing Unit) 101 executes a test program stored in a memory 102, and performs evaluation processing and test processing, which will be described later.

[0133] The memory 102 includes a RAM (Random Access Memory), a ROM (Read Only Memory), etc., and stores the test program executed by the CPU 101 and also functions as a work memory for the CPU 101.

[0134] The interface (I / F) 103 connects the row decoder 31, column decoder 32, read / write controller 33, and each of the memory controllers 2451 to 2455 of the memory circuit 11 under test. n , 245 R , are connected to the bus 25 and transmit and receive signals.

[0135] The auxiliary storage device 104 is composed of a flash memory, a hard disk drive, etc., and stores intermediate test data, test results, and, for example, errata such as those shown in FIGS. 11(a) and 11(b).

[0136] The I / O device 105 includes an input device, a display device, and the like, and functions as a user interface.

[0137] Next, the operation of the test apparatus 100 for testing the memory circuit 11 will be described. The test operation mainly includes an errata creation process shown in FIG. 9 and an evaluation process shown in FIG. The errata creation process is performed on the memory cell MC ij and redundant memory cells RMC i The evaluation process is a process of determining whether the stored data can be read correctly for a plurality of correction voltages and creating an errata showing the results. In addition, the evaluation process is a process of determining the appropriate correction data D for each column based on the created errata. j Correction memory 242 j This is the process of setting the following.

[0138] First, the I / F 103 of the test device 100 is connected to the memory circuit 11 as shown in FIG.

[0139] The person in charge of testing issues an instruction to start the errata creation process by operating the I / O device 105. In response to this instruction, the CPU 101 starts executing the test program stored in the memory 102, and starts the errata creation process shown in the flowchart of FIG.

[0140] First, the CPU 101 controls the read / write controller 33, the column decoder 32, and the row decoder 31 to read all the memory cells MC ij and all redundant memory cells RMC i In step S11, bit data "1" is written to the reference cells RC in order. Note that the writing may be performed by magnetic writing. i It is assumed that the data "0" is stored in advance in

[0141] Next, the CPU 101 sets the read enable signal / RE to a low level, which is an active level, and sets the sense amplifier enable signal / SAE to a low level, which is an active level (step S12).

[0142] Next, CPU 101 sets column pointer j=1 (step S13) and row pointer i=1 (step S14).

[0143] Next, the CPU 101 reads the selected memory cell MC ij Whether the stored data "1" can be read correctly or not is checked by adjusting the seven-level correction voltage V amej That is, a determination is made for each of the plurality of correction amounts (step S15). By performing step S15, the CPU 101 functions as a determination unit.

[0144] This will be explained in detail with reference to Fig. 10. First, the CPU 101 outputs the read column selection signal CLR j is set to high level (step S21). j becomes ready to output data.

[0145] The CPU 101 selects the memory controller 245 in the jth column. j via the correction memory 242 j Correction data D j "000" is written (step S22). j is the correction voltage V of 0 mV amej The adder circuit 244 outputs j is (V ref +0mV) is the effective reference voltage EV refj Sense amplifier 241 j is the bit line BL of the jth column. j The bit line voltage V bj and the effective reference voltage EV refj The sense amplifier 241 compares the read data with the sense amplifier 241, determines the read data, and latches it. j is the latched data DATA j is output to bus 25.

[0146] The CPU 101 receives the correction data D j After setting, the CPU 101 waits for a certain time until the output data stabilizes, and then takes in the data output onto the bus 25 via the I / F 103 (step S23), and determines whether the read data is "1" or not (step S24). If the read data is "1" and correct (step S24: Yes), the CPU 101 registers "correct" in the errata (step S25), and if the read data is "0" and incorrect (step S24: No), the CPU 101 registers "incorrect" in the errata (step S26).

[0147] Next, the CPU 101 calculates the seven correction data D j If the process has not been completed (step S27: No), the unprocessed correction data D j Select one, for example, "001" to enter the correction memory 242 j Set the correction data D j (Step S28) After that, the control returns to Step S23 and the same processing is repeated.

[0148] 7 correction data D j When the process is completed for the selected memory cell MC ij The correction voltage V that can correctly read the stored data "1" is amej and the correction voltage V amej An errata sheet will be created showing the following:

[0149] Then, in step S27, all the correction data D j It is determined that the process has been completed (step S27: Yes), and the control proceeds to step S16 in FIG.

[0150] In step S16, the CPU 101 reads all the memory cells MC in the currently selected jth column. ij or redundant memory cell RMC i It is determined whether the process of creating an errata sheet has been completed. If not completed (step S16: No), the row pointer i is updated (+1) (step S17), and the control is returned to step S15, and the next memory cell MC ij The same processing as described above is performed for

[0151] In this way, in the auxiliary storage device 104, as shown in FIG. 11(a), each memory cell MC in the selected j-th column ij Errata will be created sequentially for the above. All memory cells MC in the selected jth column or redundant column ij or redundant memory cell RMC i When the errata for the j-th column is created, it is determined in step S16 that the errata for the j-th column is complete (step S16: Yes), and the process proceeds to step S18.

[0152] In step S18, the memory cell MC ij and redundant memory cells RMC i It is determined whether the processing is completed for all columns of the table. If there are any unprocessed columns remaining (step S18: No), the column pointer j is updated (step S19), the process returns to step S14, and the above-described operations are repeated. In step S19, the CPU 101 basically sets the column pointer j to j+1. However, when the updated column pointer is (m+1), j is set to the first column of the redundant memory cell array 22.

[0153] By repeating the above process, all memory cells MC ij and redundant memory cells RMC i Regarding the correction voltage V, whether the stored data "1" can be correctly read or not amej An errata sheet showing the following will be completed.

[0154] Then, in step S18, it is determined that the processing has been completed for all columns of the memory cell array 21 and the redundant memory cell array 22 (step S18: Yes), and control proceeds to step S20. In step S20, all memory cells MC ij and redundant memory cells RMC i Then, by repeating the same operations as in steps S12 to S19, an errata list for the read data "0" is created as shown in FIG. 11(b).

[0155] In this way, the errata shown in FIGS. 11(a) and 11(b) is completed. Next, the CPU 101 generates the correction data D shown in FIG. j Start the evaluation process to set First, the CPU 101 sets the column pointer j to 1 (step S31).

[0156] Next, referring to the errata shown in FIGS. 11(a) and 11(b), all memory cells MC 1j ~MC mj Correction data D that can read all data "1" and "0" correctly j It is determined whether or not there exists (step S32).

[0157] For example, considering the errata in Figs. 11(a) and 11(b), the memory cell MC 11 Regarding the data "1", the correct voltage V ame1 = +12mv to -8mv, and data "0" can be read correctly only when the correction voltage V ame1 = +4mV to -12mV. Therefore, the memory cell MC 11 Regarding the correction voltage V ame1 However, it is determined that the range of +4 mV to -8 mV is appropriate. 21 Regarding the correction voltage V ame1 However, it is determined that the range of 0 mV or -4 mV is appropriate, and the memory cell MC 31 Regarding the correction voltage V ame1 However, it is determined that the range of 0 mV to -8 mV is appropriate.

[0158] In the errata for Fig. 11(a) and (b), the memory cell MC 11 , M.C. 21 ,MC 31 Considering only this, the correction voltage that can correctly read out data "1" and "0" is 0 mV or -4 mV, and it is determined that "there is" (step S32: Yes).

[0159] All memory cells MC in column j ij The correction amount that can properly distinguish the stored data, that is, the correction voltage V amej If it is determined that the correction voltage V amej Correction data D corresponding to j Correction memory 242 j (Step S33) That is, the CPU 101 functions as a setting unit and sets an appropriate correction amount for each column in the correction memory.

[0160] In the errata for Fig. 11(a) and (b), the memory cell MC 11 , M.C. 21 ,MC 31 Considering only the correction data D corresponding to the correction voltages 0mV and -4mV that can correctly distinguish the data,j Either "000" or "101" is stored in the correction memory 242. j Set to.

[0161] All the memory cells MC in the j-th column ij The correction voltage V can be used to properly distinguish the stored data. amej If an odd number of correction voltages are specified, the correction data D j In addition, all memory cells MC in the j-th column are set ij The correction voltage V amej If an even number of values ​​are identified, one of the two medians is set based on the error rate or the like so as to maximize the operating margin.

[0162] In the errata for Fig. 11(a) and (b), the memory cell MC 11 , M.C. 21 ,MC 31 Considering only the correction voltage of 4 mV adjacent to the correction voltage of 0 mV, there are two misjudgments (memory cell MC when the read data is "0" 21 and MC 31 On the other hand, when the correction voltage -8 mV is considered to be adjacent to the correction voltage -4 mV, the number of misjudgments is one (the memory cell MC when the read data is "1"). 21 ) Therefore, it is considered that setting the correction voltage to -4mV provides a larger operating margin than setting the correction voltage to 0mV. Therefore, in this example, the correction data D corresponding to the correction voltage of -4mV is j Correct "101" to memory 242 j Set to.

[0163] Next, the CPU 101 determines whether or not the processing has been completed for all columns of the memory cell array 21 and the redundant memory cell array 22 (step S34).

[0164] If there are any unprocessed columns remaining (step S34: No), the column pointer j is updated (step S35), the process returns to step S32, and the above-described operations are repeated. In step S35, the CPU 101 basically sets the column pointer j to j+1. However, when the updated column pointer is (m+1), j is set to the first column of the redundant memory cell array 22. In this way, the CPU 101 stores the corrected j-th column in the correction memory 242 j The correction amount, i.e., the correction voltage V amej Correction data D indicating j Set.

[0165] On the other hand, in step S32, all the memory cells MC in the j-th column ij or redundant memory cell RMC i The correction voltage V can be used to properly distinguish the stored data. amej If it is determined that there is no defective column (step S32: No), the column number is recorded as a defective column (step S36), and the process proceeds to step S34.

[0166] In step S34, when it is determined that the process has been completed for all columns (step S34: Yes), the CPU 101 identifies the defective memory cell included in the defective column recorded in step S36 (step S37). amej However, a memory cell MC from which stored data cannot be read correctly is defined as a defective memory cell.

[0167] Next, it is determined whether the identified defective memory cell can be replaced with a redundant memory cell (step S38). For example, if there is an available redundant memory cell in the same row as the defective memory cell, it is determined that the defective memory cell can be replaced, and if there is no available redundant memory cell in the same row as the defective memory cell or the defective memory cell is defective, it is determined that the defective memory cell cannot be replaced.

[0168] Next, if it is determined that the identified defective memory cell can be replaced with a redundant memory cell (step S38: Yes), a correction voltage V that can correctly read data from memory cells MC other than the defective memory cell MC in the defective column is selected. amej and the determined correction voltage V amej Correction data D corresponding to j is set in the correction memory 242 for the defective column (step S39).

[0169] Next, the row decoder 31 and the column decoder 32 are set so that when a defective memory cell MC is addressed, a redundant memory cell RMC in the same row within the redundant memory cell is selected (step S40). That is, the CPU 101 functions as a setting means and sets the defective memory cell MC to be replaced with the redundant memory cell RMC.

[0170] For example, the memory cell in the first row and the kth column of the memory cell array 21 is amek Furthermore, it is assumed that the stored data cannot be read correctly even if the memory cell MC ik Among them, the memory cells MC 1k It is assumed that only the redundant memory cell RMC1 in the first row is defective, and that the redundant memory cell RMC1 in the first row is normal and available.

[0171] In this case, the memory cell MC in the first row and the kth column 1k As a defective cell (step S37), the CPU 101 determines that the redundant memory cell RMC1 in the first row of the redundant memory cell column is available and therefore replaceable (step S38: Yes). 2k ~MC mk In order to correctly read out the stored data, the correction data D k When an address specifying the first row and the k-th column is supplied to the row decoder 31 and the column decoder 32, the row decoder 31 sets the word line WL1 to a high level, and a read column selection signal CLR specifying the first row of the column of the redundant memory cell RCR is set. Ror write column selection signal CLW R is set to a high level.

[0172] On the other hand, if the defective memory cell MC cannot be replaced with the redundant memory cell RMC in step S38 (step S38: No), the memory circuit 11 is determined to be defective (step S41). In this case, for example, the I / O device 105 is notified of this.

[0173] If there are multiple defective memory cells, steps S35 to S41 are executed for each memory cell. This completes the test process.

[0174] As described above, according to the memory circuit 11 of this embodiment, each sense amplifier 241 j is the effective reference voltage EV refj Based on this, the bit line voltage V bj Therefore, the data can be judged more accurately. refj The common reference voltage V ref and each sense amplifier 241 j The correction voltage V amej Furthermore, it is possible to suppress defects in the memory circuit 11 that are caused by the inability to accurately determine data, and it is possible to increase the yield rate of the circuit.

[0175] The above-described embodiments are merely examples of the present invention, and the present invention is not limited to these. For example, in the illustration of Figure 4, the effective reference voltage EV refj To generate the reference voltage V ref Correction voltage V amej Addition circuit 244 j The present invention is not limited to this. For example, as shown in FIG. 13(a), when the reference voltage V ref to the correction voltage V amej A subtraction circuit 244 that subtracts ajIn the present invention, the subtraction circuit is a form of the addition circuit in the sense that it adds a negative value, and is included in the addition circuit. j The reference voltage V ref Correction voltage +V amej By adding refj can be obtained, the subtraction circuit 244 aj The reference voltage V ref to correction voltage -V amej By subtracting the appropriate effective reference voltage EV refj can be obtained.

[0176] In the above embodiment, the physical characteristic to be corrected is set to a reference voltage V ref As a result, the sense amplifier 241 j The physical characteristic to be corrected is not limited to this, and can be customized for each bit line voltage V bj , the bit line voltage V bj The sense amplifier 241 j For example, the bit line voltage V bj Addition circuit 244 bj The correction voltage V amej and the effective bit line voltage EV bj and the sense amplifier 241 j The sense amplifier 241 may be supplied to j is the effective bit line voltage EV bj and the reference voltage V ref Compare with the data j The adder circuit 244 outputs j The reference voltage V ref Correction voltage +V amej By adding refj can be obtained, the summing circuit 244 bj The bit line voltage V bj to the correction voltage -V amej By adding bj In addition, the adder circuit 244 bjAs described above, in the present invention, the subtraction circuit is one aspect of the addition circuit.

[0177] As shown in FIGS. 13(c) and 13(d), the adder circuit 244 cj (including subtraction circuit) or addition circuit 244 dj (including the subtraction circuit) to the sense amplifier 241 j This may be implemented inside the sense amplifier 241 as a physical characteristic to be corrected. j Offset voltage ΔV offset This also corresponds to adjusting the

[0178] 14(a) to (d), instead of the adder circuit (including the subtractor circuit), an amplifier circuit 247 fj ~247 ij The amplifier circuit 247 may be arranged. ej and 247 hj is the reference voltage V, which is the physical characteristic to be compensated for. ref The correction signal V amej The effective reference voltage EV refj The amplifier circuit 247 outputs gj and 247 ij is the physical characteristic to be corrected, the bit line voltage V bj The correction signal V amej The effective bit line voltage EV bj Output.

[0179] The present invention is not limited to these methods, and the correction memory 242 of the j-th column j The reference voltage V ref or bit line voltage V bj can be adjusted to a suitable voltage level, in other words, the sense amplifier 241 j As long as the potential difference between the two input voltages can be adjusted, the configuration is arbitrary. For example, the load resistors (transistors RT j ) into the j-th column correction memory 242 j Correction data D stored in jBy controlling the bit line BL j The bit line voltage V bj In this case, for example, as shown in FIG. 15(a), the load transistor RT j Instead, the load resistance circuit 248 j Place the load resistor circuit 248 j is the bit line BL of the jth column. j and read voltage V R and the terminal to which the voltage is applied.

[0180] Load resistance circuit 248 j When the read enable signal / RE is at a low level, the bit line BL j and read voltage V R The resistance value is stored in the correction memory 242. j Correction data D stored in j Change according to.

[0181] Bit line voltage V bj is V R (Memory cell MC ij Resistance value of the select transistor ST ij On-resistance value of the grounded transistor RQ j (combined resistance value with the on-resistance value of the load resistor circuit 248) / ( j Resistance value of memory cell MC ij Resistance value of the select transistor ST ij On-resistance value of the grounded transistor RQ j Therefore, the load resistance circuit 248 j By increasing the resistance of bj To reduce the load resistance, j By reducing the resistance of bj can be made larger.

[0182] As shown in FIG. 15(b), the j-th row of grounded transistors RQ j Instead, ground resistance circuit 249 j and the correction memory 242j Correction data D output by j The same function can be achieved by changing the resistance value according to the

[0183] Load resistance circuit 248 j and ground resistance circuit 249 j is the correction voltage V amej The resistance value may be changed depending on the voltage.

[0184] In the configurations shown in FIGS. 15(a) and 15(b), the read voltage V R is an example of a first reference voltage, the ground voltage is an example of a second reference voltage, and the load resistor circuit 248 j and ground resistance circuit 249 j is the correction data D j By changing its own resistance value, i.e., the voltage dividing resistor, according to j This is an example of a voltage dividing resistor changing means for correcting the physical characteristics of the voltage dividing resistor.

[0185] In the above embodiment, the correction voltage V ame In the example shown, the correction voltage V is set to 7 levels, with 3 levels each around 0V. ame The number of is arbitrary.

[0186] Also, the reference voltage V ref is set to a low voltage in advance, and the correction voltage V ame Similarly, the reference voltage V ref is set to a higher voltage in advance, and the correction voltage V ame may be only a negative voltage.

[0187] In the above embodiment, in the read operation, the stored data of all the memory cells MC in the selected row are read in parallel and discriminated. The present invention is not limited to this embodiment, and it is also possible to read and access only the memory cells designated by the row address and column address, and to discriminate the bit line voltage V b may be read out and the stored data may be determined.

[0188] In the above embodiment, the test operation is described as being performed after the completion of the memory circuit 11, but this is not limiting. For example, the test operation may be performed at regular intervals to deal with deterioration over time. Furthermore, the test operation may be performed periodically, such as every six months.

[0189] Furthermore, after the read operation is completed, the read data may be automatically written back to the memory cell MC.

[0190] In the above embodiment, data "0" is assigned to the low resistance of the MTJ element and data "1" is assigned to the high resistance, but data "1" may be assigned to the low resistance of the MTJ element and data "0" to the high resistance.

[0191] In addition, in the configuration of FIG. 1 etc., the selection transistor ST ij memory cell MC ij Source line SL j The memory cells MC are arranged in any order. ij than the bit line BL j Similarly, the redundant selection transistor RST i , redundant memory cell RMC i Similarly, in the configuration of FIG. i is the reference cell RC i than the reference source line SL R The reference cell RC i It may be arranged closer to the first reference bit line BLR1 than the first reference bit line BLR1.

[0192] The test device 100 may have any configuration as long as it can achieve the same functions. Furthermore, the test sequence is merely an example, and the procedure itself is arbitrary as long as optimal correction data can be identified for each column and set in the correction memory 242. 1, the redundant memory cells RMC are arranged in one column, but the number of columns of the redundant memory cells RMC is arbitrary. Also, although the redundant memory cells RMC are arranged in columns, the redundant memory cells RMC may be arranged in rows.

[0193] When the memory cell MC is a multi-level memory, multiple reference voltages V ref1 ~V refs , a common correction voltage V ame Alternatively, multiple reference voltages V ref1 ~V refs Each optimized correction voltage V ame1 ~V ames may be configured to add

[0194] In the above explanation, a circuit that uses a voltage as an electrical signal or operates with a voltage has been described. However, some resistance variable memory devices operate with a current as an electrical signal. The present invention can also be applied to a memory circuit that operates with a current. The following explanation will be given with reference to FIG. 16.

[0195] Fig. 16 shows the basic configuration of a memory circuit 12 equipped with a current-driven sense amplifier, and shows three rows and two columns of memory cells MC. Memory cell MC ij and the select transistor ST ij The configuration is the same as that shown in FIG.

[0196] Sense Amplifier 341 j is the bit line BL connected to the positive input terminal. j Then, a read voltage is applied to the bit line BL j The selected memory cell MC ij The bit line current I bj The bit line current I bj The magnitude of corresponds to the signal level of the electrical signal.

[0197] Sense Amplifier 341 j A constant current source 323 is connected to the negative input terminal of the reference current line BL. Ris a plurality of sense amplifiers 341 j and a reference current I ref The reference current I ref corresponds to the signal level of the reference signal.

[0198] Sense Amplifier 341 j Current correction circuit 345 j The current correction circuit 345 is arranged. j is the reference current I, which is an example of a physical property to be compensated for. ref is corrected, and the effective reference current EI refj The current correction circuit 345 outputs j is the correction memory 342 j and correction D / A conversion circuit 343 j and correction current source 344 j It has.

[0199] Correction memory 342 j is the correction memory 242 j The correction data D set by the upper device (test device) corresponds to j The correction D / A conversion circuit 343 stores the j converts the correction data into a correction voltage. j is a correction D / A conversion circuit 343 j The correction current I corresponding to the correction voltage generated by amej The correction current I amej current correction circuit 345 j is the reference current I ref The correction current I amej Depending on the direction of the current correction circuit 345 j functions as a current adder or current subtracter.

[0200] Sense Amplifier 341 j The negative terminal of ref and the correction current I amej The effective reference current EI corresponds to the sum of refj The reference current I ref is the sense amplifier 341 of the selected column. jOn the other hand, the correction current I amej are the individual sense amplifiers 341 j is specific to

[0201] Sense Amplifier 341 j is the bit line current I bj and the effective reference current EI refj The difference between bj -EI refj ) is amplified, latched and output. j and correction current source 344 j The read column selection signal CLR j is supplied to the memory cell MC in the j-th column. ij This occurs when a file is selected for reading.

[0202] In this configuration, the correction memory 342 j Correction data D according to the characteristics of each column j By setting the jth column reference current I ref Correction current I amej and correct it with the sense amplifier 341 j The effective reference current EI supplied to refj can be optimized for each column. Meanwhile, the reference current I ref Multi-column sense amplifier 341 j It can be shared by

[0203] 17(a) and 17(b), a current amplifier 346 is used instead of the current correction circuit 345. a , current amplifier 346 b A current amplifier 346 may be provided. a is the reference current I, which is an example of a physical property to be compensated for. ref The correction signal V amej By amplifying the current with a gain corresponding to the effective reference current EI refj The current amplifier 346 outputs b is the physical characteristic to be corrected, the bit line current I bj The correction signal V amej By amplifying the current with an amplification factor according tobj Output.

[0204] Next, specific circuit examples of each part of the memory circuit 11 according to the embodiment will be described. First, the voltage-driven sense amplifier 241 shown in FIG. 4 and FIGS. 13(a) to 13(d) j An example of this circuit will be described with reference to FIG.

[0205] As shown in FIG. 18, the sense amplifier 241 j The latch circuit includes a latch body 111, a reset circuit 112, and an output circuit 113.

[0206] The latch body 111 is composed of PMOS transistors P1 to P5 and NMOS transistors N1 to N2. Functionally, the latch body 111 includes an input transistor circuit 111A that receives an input voltage at its gate, a CMOS latch 111B, and a PMOS transistor P5 that activates / deactivates the latch circuit.

[0207] The input transistor circuit 111A is composed of PMOS transistors P1 and P2. The gate of the PMOS transistor P1 is connected to the bit line voltage V bj or effective bit line voltage EV bj The source of the PMOS transistor P1 is connected to the drain of the PMOS transistor P5, and the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P3. The gate of the PMOS transistor P2 is connected to the effective reference voltage EV ref or reference voltage V ref The source of the PMOS transistor P2 is connected to the drain of the PMOS transistor P5, and the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P4.

[0208] The CMOS latch 111B is composed of a CMOS circuit including PMOS transistors P3 and P4 and NMOS transistors N1 and N2. The drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N1. The source of the NMOS transistor N1 is grounded. The drain of the PMOS transistor P4 is connected to the drain of the NMOS transistor N2. The source of the NMOS transistor N2 is grounded.

[0209] The source of the PMOS transistor P5 is connected to the read voltage V R is applied to the sense amplifier enable signal / SAE, and the gate of the sense amplifier enable signal / SAE is applied to the sense amplifier enable signal / SAE.

[0210] The gates of the PMOS transistor P3 and NMOS transistor N1 and the connection node between the PMOS transistor P4 and NMOS transistor N2 are interconnected. The gates of the PMOS transistor P4 and NMOS transistor N2 and the connection node between the PMOS transistor P3 and NMOS transistor N1 are also interconnected.

[0211] A reset circuit 112 is made up of NMOS transistors N3 and N4 and resets this sense amplifier.

[0212] One end of the current path of the NMOS transistor N3 is connected to a connection node LA1 between the drain of the PMOS transistor P3 and the drain of the NMOS transistor N1, and the other end of the current path is grounded. One end of the current path of the NMOS transistor N4 is connected to a connection node LA2 between the drain of the PMOS transistor P4 and the drain of the NMOS transistor N2, and the other end of the current path is grounded. Furthermore, a sense amplifier reset signal SARESET is applied to the gates of the NMOS transistors N3 and N4. The sense amplifier reset signal SARESET is normally maintained at a high level, and this sense amplifier 241 j is kept in a reset state (connection nodes LA1 and LA2 are both at the ground level), and the sense amplifier 241 jThis signal goes low when the

[0213] The output circuit 113 is composed of NMOS transistors N5 to N8. A connection node LA1 is connected to the gate of the NMOS transistor N5. One end of the current path of the NMOS transistor N5 is grounded, and the other end is connected to one end of the current path of the NMOS transistor N7. The other end of the current path of the NMOS transistor N7 is pulled up, and outputs output data DATA.

[0214] The connection node LA2 is connected to the gate of the NMOS transistor N6. One end of the current path of the NMOS transistor N6 is grounded, and the other end is connected to one end of the current path of the NMOS transistor N8. The other end of the current path of the NMOS transistor N8 is pulled up and outputs the inverted output data / DATA. Therefore, the output data is DATA j and its complementary data / DATA j It is the counterpart of.

[0215] The gates of the NMOS transistors N7 and N8 are connected to a read column selection signal CLR j is supplied.

[0216] Sense Amplifier 241 j Another example of the configuration will be described with reference to FIG. In FIG. 19, the sense amplifier 241 j The circuit includes a sense circuit 121, a latch circuit 122, and an output circuit 123.

[0217] The sense circuit 121 is composed of cross-coupled NMOS transistors N11 and N12 and a grounded NMOS transistor N13. An inverted signal SAE of the sense amplifier enable signal / SAE is applied to the gate of the grounded transistor N13.

[0218] The latch circuit 122 is connected to the sense circuit 121 and includes cross-coupled PMOS transistors P11 and P12 and a sense amplifier 241.j and a PMOS transistor P13 that activates / deactivates the sense amplifier enable signal / SAE. A gate of the PMOS transistor P13 is applied with a sense amplifier enable signal / SAE.

[0219] When the sense amplifier enable signal / SAE changes to a low level, the NMOS transistor N13 and the PMOS transistor P13 are turned on. Then, the NMOS transistors N11 and N12 constituting the sense circuit 121 are turned on in response to the bit line voltage V bj (or effective bit line voltage EV bj ) and the effective reference voltage EV refj (Reference voltage V ref ) and amplifies the potential difference between them. Furthermore, the cross-coupled PMOS transistors P11 and P12 that form the latch circuit 122 latch the amplified voltage. The output circuit 123 outputs the data DATA latched in the latch circuit 122. j and its complementary data / DATA j Output.

[0220] In this way, the sense amplifier 241 j This is applicable to both a type in which a voltage signal is applied to the gate of a MOSFET (FIG. 18) and a type in which a voltage signal is applied to the drain (FIG. 19).

[0221] Next, an example of the configuration of the correction memory 242 shown in FIG. 4 will be described with reference to FIG. 20 shows the configuration of a memory element 242a for one bit of the correction memory 242. As shown in the figure, the memory element 242a is configured from a CMOS circuit including PMOS transistors P21 to P23 and NMOS transistors N21 and N22. The drain of the PMOS transistor P21 is connected to the drain of the NMOS transistor N21. The source of the NMOS transistor N21 is grounded. The drain of the PMOS transistor P22 is connected to the drain of the NMOS transistor N22. The source of the NMOS transistor N22 is grounded.

[0222] The connection node between the gates of the PMOS transistor P21 and NMOS transistor N21 and the connection node between the drains of the PMOS transistor P22 and NMOS transistor N22 are interconnected. Also, the connection node between the gates of the PMOS transistor P22 and NMOS transistor N22 and the connection node between the drains of the PMOS transistor P21 and NMOS transistor N21 are interconnected.

[0223] The source of the PMOS transistor P23 is connected to the read voltage V R is applied to this node, a memory enable signal / ME is applied to its gate, and its drain is connected to the sources of the PMOS transistors P21 and P22.

[0224] The connection node between the drain of the PMOS transistor P21 and the drain of the NMOS transistor N21 is connected to the data terminal / MOUT via the NMOS transistor N23 that forms a transfer gate. j The connection node between the drain of the PMOS transistor P22 and the drain of the NMOS transistor N22 is connected to the data terminal MOUT via the NMOS transistor N24 which constitutes a transfer gate. j is connected to.

[0225] PMOS transistor P21, NMOS transistor N21, and data terminal / MOUT j The connection node between these two is connected to one end of a memory cell MC1 via an NMOS transistor N25 that configures a selection transistor. The other end of the memory cell MC1 is connected to a bit line MBL.

[0226] PMOS transistor P22, NMOS transistor N22, and data terminal MOUT j The connection node between these two is connected to one end of a memory cell MC2 via an NMOS transistor N25 that configures a selection transistor. The other end of the memory cell MC2 is connected to a bit line MBL.

[0227] The gates of the NMOS transistors N23 and N24 are connected to a memory selection signal MSEL j The gates of the NMOS transistors N25 and N26 are applied with the memory cell selection signal MSELNV. j is applied.

[0228] The correction memory 242 shown in FIG. j Since there are three bits, three memory elements 242a are provided. For example, the data terminals MOUT j D / A conversion circuit 243 j is connected to the input terminal of

[0229] Memory selection signal MSEL j and memory enable signal / ME and memory cell select signal MSELNV j The jth column correction memory 242 j The bit line MBL is a signal common to the three memory elements 242a that make up the j-th column. j The memory cells MC1 and MC2 of the three memory elements 242a constituting the memory cell array 242 are commonly connected.

[0230] The memory cells MC1 and MC2 store complementary data.

[0231] Next, the operation of the memory element 242a will be described. The memory element 242a is composed of a volatile memory section that operates mainly while power is on, and a nonvolatile memory section that stores the data stored in the volatile memory section when the power is off. In other words, when writing correction data to the memory element 242a during the test operation shown in Figure 9, the correction data is first written to the volatile memory section. In this way, while power is on, the complementary data terminal MOUT j , / MOUT j(The non-volatile memory unit does not necessarily have to be used here.) When the power is turned off, the data in the volatile memory unit is transferred to the non-volatile memory unit so that it is not lost. When the power is turned on again, the data is transferred from the non-volatile memory unit to the volatile memory unit again to prepare for normal operation.

[0232] The volatile memory section is composed of PMOS transistors P21, P22, P23 and NMOS transistors N21, N22, N23, N24, and has the same circuit configuration as a general 6-transistor SRAM cell, and its operation is also the same as SRAM. That is, to write data, the memory enable signal / ME is set to low level and the memory select signal MSEL j After setting to high level, the complementary data terminal MOUT j , / MOUT j This is done by setting a voltage according to the data to be written.

[0233] To read data from the volatile memory, the memory enable signal / ME is set to low level and the memory select signal MSEL is set to low level. j When set to high level, the complementary data terminal MOUT j , / MOUT j A voltage corresponding to the stored data stored in the memory element appears, and this can be detected by sensing this voltage.

[0234] The nonvolatile memory section is composed of NMOS transistors N25 and N26 and memory cells MC1 and MC2, and has the same circuit configuration as a so-called 2T2MTJ MRAM cell, and its operation is also the same as that of a 2T2MTJ MRAM. That is, data is written in a state where the drain terminals of the NMOS transistors N25 and N26 (the common connection terminal of the MOS transistors P21, N23, and N21 of the volatile memory section, and the common connection terminal of the MOS transistors P22, N24, and N26, respectively) are at complementary voltages, the bit line MBL terminal is in a floating state, and the memory cell selection signal MSELNV jis set to high level. As a result, for example, if the drain terminals of NMOS transistors N25 and N26 are high and low, respectively, current flows through the path NMOS transistor N25 → memory cell MC1 → memory cell MC2 → NMOS transistor N26, and memory cell MC1 is written to a high resistance and memory cell MC2 to a low resistance. If the drain terminals of NMOS transistors N25 and N26 are reversed, memory cells MC1 and MC2 will have opposite resistance values.

[0235] During the above operation, instead of floating the bit line MBL terminal, a similar write operation can be performed by inputting a pulse that changes level from (1) low level to (2) high level to (3) low level once. This is because the following operations are performed in each of the periods (1) to (3). For example, if the drain terminals of NMOS transistors N25 and N26 are at high and low levels, respectively, first, during the period (1) (and (3)), current flows from NMOS transistor N25 to bit line MBL, and a write operation to memory cell MC1 is performed to set it to a high-resistance state. At this time, no current flows in memory cell MC2 because both the drain terminals of bit line MBL and NMOS transistor N26 are at the same low level, so no data write operation occurs. Next, during the period (2), current flows from bit line MBL to NMOS transistor N26, and a write operation to memory cell MC2 is performed to set it to a low-resistance state. At this time, the bit line MBL and the drain terminal of the NMOS transistor N25 are both at the same high level, so no current flows through the memory cell MC1, and no data write operation occurs. If the drain terminals of the NMOS transistors N25 and N26 are at the low and high levels, respectively, the memory cells MC1 and MC2 will also have opposite resistance values.

[0236] Reading data from the nonvolatile memory section involves transferring data from memory cells MC1 and MC2 of the nonvolatile memory to the SRAM, which is the volatile memory section. The memory enable signal / ME is set to a high level, and the memory cell selection signal MSELNV is set to a low level. jis set to low level and the bit line MBL is set to low level, first MSELNV j is set to high level, and then / ME is set to low level. By doing so, a voltage according to the resistance state of memory cells MC1 and MC2 is latched in memory element 242a, and data in the nonvolatile memory unit is transferred to the volatile memory unit.

[0237] Next, the amplifier circuit 247 shown in FIGS. ej and 247 hj A specific example of this will be described with reference to FIGS. 21(a) to 23(b). First, in the jth column, the reference voltage V ref to the effective reference voltage EV refj A first example of a correction circuit for generating a reference voltage V will be described with reference to FIG. ref is amplified to produce the effective reference voltage EV refj 1 is an example of a correction circuit that generates

[0238] As shown in FIG. 21(a), the amplifier circuit 247 for the j-th column j is an operational amplifier (OP) j and operational amplifier OP j and the resistance value between the negative input terminal and the reference voltage. j The amplification factor changing circuit is configured with p resistors RU(j,1) to RU(j,p), p resistors RL(j,1) to RL(j,p), p NMOS transistors TU(j,1) to TU(j,p), and p NMOS transistors TL(j,1) to TL(j,p).

[0239] Operational Amplifier OP j applies a reference voltage V to the positive input terminal. ref is applied to the operational amplifier OP j Between the negative input terminal of the operational amplifier OP, a series circuit of the first resistor RU(j,1) to the pth resistor RU(j,p) and the first NMOS transistor TU(j,1) to the pth NMOS transistor TU(j,p) is connected in parallel. jBetween the negative input terminal of the first input terminal and the ground, series circuits of the first resistor RL(j,1) to the pth resistor RL(j,p) and the NMOS transistors TL(j,1) to the pth NMOS transistors TL(j,p) are connected in parallel.

[0240] The NMOS transistors TU(j,k) and TL(j,k) (k=a natural number from 1 to p) each constitute a switch. j In this case, since the stored data is 3 bits, p=3.

[0241] The gate of the NMOS transistor TU(j,k) is connected to a correction memory 242. j The k-th bit signal SU(j, k) is applied to the gate of the NMOS transistor TL(j, k), and the correction memory 242 j The inverted signal SL(j, k) of the kth bit signal is applied, where SL(j, k)= / SU(j, k).

[0242] The resistance values ​​of the resistors RU(j,1) to RU(j,p) and RL(j,1) to RL(j,p) are arbitrary, and may be equal to one another, different from one another, or only some of them may be equal to one another and other parts may be different. By making the resistance values ​​different from one another, the effective reference voltage EV refj This is more desirable as it increases the number of possible values ​​of

[0243] According to this configuration, the correction memory 242 j Depending on whether the k-th bit signal is "1" or "0", one of the NMOS transistors TU(j,k) and TL(j,k) is turned on. j The gain of the amplifier circuit changes depending on the stored data, and the effective reference voltage EV refj Therefore, the reference voltage V ref can be customized.

[0244] As shown in FIG. 21(b), the reference voltage V ref Instead, the bit line voltage Vbj The amplifier circuit 247 j By supplying bj It is also possible to generate

[0245] In the above description, complementary signals are supplied to the gates of the NMOS transistors TU(j,k) and TL(j,k), but different bit signals may be supplied. In this case, the correction memory 242 j The number of bits is 2·p bits.

[0246] The gain of the amplifier circuit is corrected by the correction data D j By changing the effective reference voltage EV refj or the effective bit line voltage EV bj As long as it is possible to adjust the resistance, the circuit configuration is arbitrary. For example, as shown in FIG. 22, multiple resistors RU and RL may be connected to each NMOS transistor TU and TL. Note that FIG. 22 shows an example in which NMOS transistors TU and TL connected to only one resistor RU and RL coexist with NMOS transistors TU and TL connected to multiple resistors RU and RL. By using such a configuration, different resistance values ​​can be obtained using resistor elements of the same configuration, and the correction memory 242 j A weight can be assigned to each bit of

[0247] Furthermore, as shown in Figs. 23(a) and 23(b), the operational amplifier OP j It is also possible to connect the output terminal and the negative input terminal, and the negative input terminal and the ground with a series circuit of resistors RU and RL.

[0248] In the configuration of Figure 23(a), the current path of one NMOS transistor TU, TL is connected in parallel to one resistor RU, RL. By turning on the NMOS transistor TU, TL, both ends of the resistor are shorted, making it possible to adjust the resistance value of the series resistor circuit. This changes the gain of the amplifier circuit, and the effective reference voltage EV refj changes.

[0249] FIG. 23(b) shows an example in which one or more resistors RU, RL are connected to one NMOS transistor TU, TL.

[0250] In addition, in the configurations of Figures 22, 23(a), and 23(b), the reference voltage V ref Instead, the bit line voltage V bj By supplying bj It is also possible to generate

[0251] Next, the load resistance circuit 248 shown in FIG. j A specific example of this will be described with reference to FIGS. 24(a) and 24(b) and 25(a) and 25(b). FIG. 24(a) shows the bit line voltage V bj Adjust the load resistance circuit 248 j An example is shown below. In this configuration, the bit line BL j is a read voltage V R The gates of the PMOS transistors TP(j,1) to TP(j,p) are connected to the correction memory 242. j Correction data D stored in j , the voltages SB(j,1) to SB(j,p) obtained by converting the bit data of the corresponding bits of the memory cells MCij into analog data are applied. R (the terminal to which correction data D is applied) are electrically connected by the current paths of the plurality of transistors TP(j,1) to TP(j,p). j Turn on / off according to the instruction.

[0252] The on-resistance (current driving capability) of the PMOS transistors TP(j,1) to TP(j,p) may be the same or the same. By adjusting the number of PMOS transistors TP(j,1) to TP(j,p) to be turned on, or by selecting the PMOS transistors to be turned on, or by a combination of these, the correction memory 242 jThe bit line voltage V bj It is possible to adjust the correction data D so that at least one of the PMOS transistors TP(j,1) to TP(j,p) is turned on. j It is desirable to set

[0253] In addition, correction data D j The logical product of each bit of the input signal and the read enable signal / RE may be calculated, and the resulting voltage signal may be converted to analog and applied to the gate of the PMOS transistor TP(j, k). Also, as shown in FIG. 24(b), the load transistor RT j may be placed.

[0254] 25(a) and 25(b), a series circuit of a memory cell MC and a PMOS transistor may be arranged, and a normal resistance element may be used instead of the memory cell MC.

[0255] Next, the offset voltage ΔV shown in FIGS. offset An example of the configuration of a sense amplifier having a function of adjusting the voltage will be described with reference to FIG. The sense amplifier 241a shown in FIG. 26 includes gate receiving circuits 111C and 111D, a CMOS latch 111B, a bias circuit 111E, and an activation PMOS transistor P5.

[0256] The configuration of the CMOS latch 111B is the same as that shown in FIG.

[0257] On the other hand, the gate receiving circuit 111C includes p PMOS transistors P31 to P3p. The gates of the PMOS transistors P31 to P3p are connected to the bit line BL j and the bit line voltage V bj The drains of the PMOS transistors P31 to P3p are commonly connected to a connection node LA1.

[0258] The gate receiving circuit 111D also includes p PMOS transistors P41 to P4p. The gates of the PMOS transistors P41 to P4p are connected to the reference bit line BL R2 and the reference voltage V ref The drains of the PMOS transistors P41 to P4p are commonly connected to a connection node LA2. The sources of the PMOS transistors P41 to P4p are connected to the sources of the PMOS transistors P31 to P3p, respectively.

[0259] The drains of the PMOS transistors P51 to P5p constituting the bias circuit 111E are connected to the connection nodes between the sources of the corresponding PMOS transistors P31 to P3p and the sources of the corresponding PMOS transistors P41 to P4p. j Voltage signals SB(j,1) to SB(j,p) obtained by converting the bit data of the corresponding bits of the P1 and P2 into analog signals are applied to the P5 gate. A sense amplifier enable signal / SAE is applied to the gate of P5.

[0260] According to this configuration, the correction data D j In response to this, the bias transistors P51 to P5p are turned on and off, and the voltages of the connection nodes NA1 and LA2 are set to the read voltage V R The degree of pull-up is determined by the correction data D j It changes according to

[0261] The on-resistance of the PMOS transistors P31 to P3p is determined by the bit line voltage V bj Similarly, the on-resistance of the PMOS transistors P41 to P4p changes depending on the reference voltage V ref Therefore, the potential difference between the connection nodes LA1 and LA2 changes depending on the bit line voltage V bj and the reference voltage V ref and correction data D j This change is due to the offset voltage ΔV offset In this way, the correction data D j Therefore, the offset voltage ΔVoffset Therefore, the offset voltage ΔV of the sense amplifier 241a for each column can be adjusted. offset By adjusting the voltage, it becomes possible to appropriately determine the data stored in the memory cell.

[0262] In the above explanation, the reference voltage V ref In the memory circuit, a memory element is composed of a pair of memory cells that store complementary data, and complementary bit line voltages V are generated by the complementary data stored in the pair of memory cells. b and / V b There is a type of memory circuit that determines stored data by comparing the value of the bit and the value of the bit. The present invention is also applicable to this type of memory circuit.

[0263] Hereinafter, with reference to FIG. 27, an embodiment in which the present invention is applied to this type of memory circuit will be described. In FIG. 27, the jth column and mth row of memory elements MD ij ~MD mj are arranged. Memory element MD ij is a pair of memory cells MC ij and / MC ij The memory cell MC ij stores variable data, and memory cells / MC ij stores the complementary data.

[0264] Memory cell MC in the jth column ij One end of the bit line BL j are commonly connected to the bit line BL j is the load transistor RT j Therefore, the read voltage V R Each memory cell MC ij The other end of the select transistor ST ij One end of the current path of the select transistor ST ij At the other end of the current path, a source line SL j are commonly connected.

[0265] Similarly, the memory cell / MC in the jth column ij One end of the bit line / BL j are commonly connected to the bit line / BL j is the load transistor / RT j Therefore, the read voltage V R Each memory cell / MC ij The other end of the select transistor / ST ij One end of the current path of the jth column select transistor / ST is connected to the ij At the other end of the current path is the source line / SL j are commonly connected.

[0266] The i-th row select transistor ST ij and / ST ij The gate of i are commonly connected to

[0267] Source line SL of the jth column j and / SL j is the grounded transistor RQ j The transistor RQ is grounded. j The gates of the FETs 11 and 12 are commonly connected to an inverted signal of the read enable signal / RE.

[0268] Bit line BL j is connected to the positive input terminal of the sense amplifier. On the other hand, the bit line / BL j is the adder circuit 244 j The adder circuit 244 is connected to j is the bit line voltage / V bj and the correction voltage V amej and the effective bit line voltage / EV bj and this is input to the sense amplifier 241 j The negative input terminal of the sense amplifier 241 is supplied with j is the bit line voltage V bj and effective bit line voltage / EV bj is differentially amplified and latched to output data DATA j Output.

[0269] In this configuration, the bit line voltage / V bj Correction memory 242 j Correction data D stored in j This allows the bit line BL j and / BL j Memory cell MC connected to ij and / MC ij Even if the number of memory cells MC ij and / MC ij The data stored in the memory can be read out appropriately.

[0270] 20, it is also possible to apply the examples shown in FIGS. 13(a) to 14(d), 16, 17(a), (b), 21(a) to 23(b), and 26. That is, the correction memory 242 j Correction data D stored in j According to this, the bit line voltage V bj or / V bj or the sense amplifier 241 j Offset voltage ΔV offset Any circuit configuration may be adopted as long as it can adjust the

[0271] In the above explanation, the invention has been explained using positive logic, but the present invention can also be applied to a memory circuit using negative logic. Furthermore, the above-described multiple correction circuits may be combined. For example, the configuration of Fig. 4 may be adopted together with the configuration of Fig. 15(a).

[0272] Additionally, the memory element is not limited to an MTJ element, but may be a variable resistance memory element such as a ReRAM (Resistance Random Access Memory). In this case, the variable resistance element constituting the reference circuit has the same configuration as the variable resistance element constituting the memory cell and is set to a low resistance RL. Furthermore, the resistance value of the fixed resistor FR is set to be greater than 0 and smaller than the difference between the high resistance RH and the low resistance RL of the variable resistance element. In particular, it is desirable for the resistance value to be substantially equal to (α / 100) × RL. Here, α is the upper limit (%) of the resistance variation of the variable resistance element allowed by the resolution of the sense amplifier used in this memory circuit (the minimum value that can detect the difference between the voltage at the positive input terminal and the voltage at the negative input terminal). In this case, either a fixed resistor is provided for each reference cell, or a single fixed resistor is provided (shared) for multiple reference cells (variable resistance elements).

[0273] As described above, the present invention is not limited to the above-described embodiment and drawings, and appropriate modifications can be made to the above-described embodiment and drawings. [Explanation of symbols]

[0274] 11 Memory circuit 12 Current-type memory circuit 21 Memory Cell Array 22 Redundant memory cell array 23 Reference Cell Array 24 RW circuit array 31 Low Decoder 32 Column Decoder 33 Read / Write Controller 100 Test Equipment 101 CPU 102 memory 103 Interface (I / F device) 104 Auxiliary storage 105 Input / output device (I / O device) 240 Readout circuit 241 Sense Amplifier (SA) 241a Sense Amplifier 242 Correction Memory 243 D / A conversion circuit 244 Addition Circuit 244a Subtraction circuit 247 Amplifier Circuit 248 Load resistance circuit 249 Earth resistance circuit 245 Memory Controller 246 Write Circuit 323 constant current source 341 Sense Amplifier (SA) 342 Correction Memory 343 Correction D / A conversion circuit 344 Current Source 345 Current Compensation Circuit 346 a , 346 b Current Amplifier CLR Read column selection signal CLW Write column selection signal WL1~WL m Word Line BL1~BL n Bit Lines RBL Redundant Bit Line BL R Reference Bit Line BL R1 First Reference Bit Line BL R2 Second Reference Bit Line ST 11 ~ST mn Select transistor RST1~RST m Redundant Select Transistor AT R Select transistor SL1~SL n Source line RS L Redundant Source Lines SL R Reference Source Line RT1~RT n Load transistor RRT Redundant Load Transistor RT RReference Load Transistor RQ1~RQ n , RQ R Grounded transistor RRQ redundant ground transistor V b Bit Line Voltage V ref Reference Voltage

Claims

1. a memory cell array including memory cells arranged in a matrix, each memory cell being made up of a resistance variable element; a selection circuit for selecting the memory cell in the memory cell array; a conversion circuit that converts the resistance value of the memory cell selected by the selection circuit into an electric signal; a reference signal generating circuit for generating a reference signal for determining data stored in the memory cell; a sense amplifier arranged for each column of the memory cell array, for determining the stored data of the memory cell selected by the selection circuit; a correction data storage means for storing correction data for correcting physical characteristics for determining the stored data of the memory cells for each of the sense amplifiers; a correction circuit for correcting the physical characteristics for each of the sense amplifiers in accordance with the correction data stored in the correction data storage means; Equipped with the physical characteristic is a physical characteristic of one of the electrical signal converted by the conversion circuit and the reference signal; the correction circuit corrects the physical characteristics of the one signal in accordance with the correction data; the sense amplifier compares the one signal whose physical characteristics have been corrected by the correction circuit with the other signal, which is the electrical signal converted by the conversion circuit and the reference signal, to determine the stored data of the memory cell selected by the selection circuit; memory circuit.

2. the physical property is a physical property of the reference signal; the correction circuit corrects the physical characteristics of the reference signal in accordance with the correction data; the sense amplifier compares the reference signal, the physical characteristics of which have been corrected by the correction circuit, with the electrical signal converted by the conversion circuit to determine the stored data of the memory cell selected by the selection circuit; The memory circuit according to claim 1 .

3. the physical characteristic is a physical characteristic of the electrical signal converted by the conversion circuit; the correction circuit corrects the physical characteristics of the electrical signal converted by the conversion circuit in accordance with the correction data; the sense amplifier compares the electrical signal, the physical characteristics of which have been corrected by the correction circuit, with the reference signal to determine the stored data of the memory cell selected by the selection circuit; The memory circuit according to claim 1 .

4. a memory cell array including memory cells arranged in a matrix, each memory cell being made up of a resistance variable element; a selection circuit for selecting the memory cell in the memory cell array; a conversion circuit that converts the resistance value of the memory cell selected by the selection circuit into an electric signal; a reference signal generating circuit for generating a reference signal for determining data stored in the memory cell; a sense amplifier arranged for each column of the memory cell array, for comparing the electrical signal converted by the conversion circuit with the reference signal generated by the reference signal generation circuit to determine the stored data of the memory cell selected by the selection circuit; a correction data storage means for storing correction data for correcting physical characteristics for determining the stored data of the memory cells for each of the sense amplifiers; a correction circuit for correcting the physical characteristics for each of the sense amplifiers in accordance with the correction data stored in the correction data storage means; Equipped with the correction circuit corrects, as the physical characteristic, an offset voltage of the sense amplifier in accordance with the correction data; memory circuit.

5. the correction data storage means is configured to store or rewrite the correction data in accordance with a signal from an external device of the storage circuit. The memory circuit according to claim 1 .

6. the correction data storage means is a multi-bit digital memory, the correction circuit includes a D / A conversion circuit that converts the correction data stored in the correction data storage means into an analog correction signal, and corrects the physical characteristic in accordance with the analog correction signal output from the D / A conversion circuit. The memory circuit according to claim 1 .

7. The correction circuit a correction signal generating circuit for generating a correction signal for each of the sense amplifiers in accordance with the correction data stored in the correction data storage means; an adding circuit that adds the correction signal generated by the correction signal generating circuit to one of the electrical signal and the reference signal for each of the sense amplifiers to correct the electrical signal and the reference signal, and supplies the corrected electrical signal to the sense amplifier; The memory circuit according to claim 1 , comprising:

8. the correction circuit includes an amplifier circuit that corrects one of the electrical signal and the reference signal by amplifying it at an amplification factor in accordance with the correction data stored in the correction data storage means; The memory circuit according to claim 1 .

9. The amplifier circuit An operational amplifier and an amplification factor changing circuit that changes at least one of a resistance value between the output terminal and the negative input terminal of the operational amplifier and a resistance value between the negative input terminal of the operational amplifier and a reference voltage in accordance with the correction data; The memory circuit of claim 8 , comprising:

10. the correction circuit includes a voltage dividing resistor changing means for correcting the electrical signal output by the conversion circuit by changing at least one of a resistance value between one end of each of the memory cells and a first reference voltage and a resistance value between each of the memory cells and a second reference voltage in accordance with the correction data; The memory circuit according to claim 1 .

11. the correction circuit includes a plurality of transistors electrically connecting one end of each of the memory cells to the first reference voltage, and the plurality of transistors are turned on and off in accordance with the correction data stored in the correction data storage means; The memory circuit according to claim 10.

12. the correction circuit includes a resistor element connected in series to the current paths of the plurality of transistors; The memory circuit according to claim 11.

13. The memory cell has a resistance value corresponding to variable data to be stored, The reference signal generating circuit a matrix of second memory cells each configured as a pair with each of the memory cells and each configured as a resistance variable element for storing data complementary to the corresponding memory cell; and a reference signal having a signal level corresponding to the resistance value of the second memory cell selected by the selection circuit is generated; The memory circuit according to any one of claims 1 to 12.

14. 14. A test device for a memory circuit according to claim 1, a read circuit that controls the correction circuit to set a plurality of correction amounts for each of the memory cells and reads out stored data for each correction amount; a determining means for determining, for each of the memory cells, which correction amount is set so that stored data can be read correctly; a setting means for determining a correction amount for each column based on the result of the determination by the determining means for each column, and setting correction data corresponding to the determined correction amount for each column in the correction data storage means; A test device comprising:

15. the storage circuit includes a column of redundant memory cells; the setting means sets the selection circuit so as to replace an access to a memory cell from which stored data cannot be correctly read with an access to the redundant memory cell based on the result of the determination by the determining means.

15. A test device according to claim 14.

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