Semiconductor Devices

Abstract

To provide a semiconductor device capable of product-sum operation, in which the consumption power is reduced.SOLUTION: A semiconductor device includes first and second cells, a first circuit, and first to third wires. Each of the first and second cells includes a capacitor, and a first terminal of each capacitor is electrically connected to the third wire. Each of the first and second cells has a function of feeding current according to the potential held in a second terminal of the capacitor to the first and second wires. The first circuit is electrically connected to the first and second wires and stores currents I1 and I2 flowing to the first and second wires. When the potential of the third wire changes to cause the amount of current in the first wire change from I1 to I3 and the amount of current in the second wire change from I2 to I4, the first circuit generates current with the amount of I1-I2-I3+I4. The change of the third wire is caused by first inputting a reference potential to the third wire and then inputting a potential according to internal data or a potential according to information obtained by a sensor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, sensors, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] Currently, active development is underway on integrated circuits that mimic the workings of the human brain. These integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brain-morphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with significantly less power consumption than von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network with "neurons" and "synapses" is called an artificial neural network (ANN). By using an artificial neural network, it is possible to make inferences with accuracy comparable to or even exceeding that of humans. In an artificial neural network, the main operation is the weighted sum of neuron outputs, i.e., the sum-of-products operation.

[0005] An invention using a memory cell using an OS transistor as a circuit for performing a product-sum operation is disclosed, for example, in Patent Document 1. An OS transistor (sometimes referred to as an oxide semiconductor transistor) is a transistor having a metal oxide semiconductor in a channel formation region, and has been reported to have extremely small off-state current (for example, Non-Patent Documents 1 and 2). Various semiconductor devices using OS transistors have also been manufactured (for example, Non-Patent Documents 3 and 4). A manufacturing process for an OS transistor can be incorporated into a conventional CMOS process for Si transistors, and the OS transistor can be stacked on the Si transistor (for example, Non-Patent Document 4). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-168099 [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-patent document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-patent document 3] S. Amano et al., “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). [Non-patent document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol.79, pp.149-156 (2017). Summary of the Invention [Problem to be solved by the invention]

[0008] When a multiply-and-accumulate operation is performed using a digital circuit, a digital multiplier circuit multiplies digital data (multiplier data) that serves as a multiplier by digital data (multiplicand data) that serves as a multiplicand. Then, a digital adder circuit adds the digital data (product data) obtained by the multiplication, and obtains digital data (product-and-accumulate data) as the result of the multiply-and-accumulate operation. It is preferable that the digital multiplier circuit and the digital adder circuit are capable of handling multi-bit operations. However, in this case, the circuit size of each of the digital multiplier circuit and the digital adder circuit may become large, which may lead to an increase in the circuit area and power consumption of the entire operation circuit.

[0009] Furthermore, when a calculation is performed by a processor or the like, the calculation result data is temporarily stored in a digital memory, for example. For example, when a multiply-and-accumulate operation is performed, the product data obtained by a digital multiplication circuit is temporarily stored in a digital memory, and the product data is read out when the multiply-and-accumulate data is calculated by a digital addition circuit. After the multiply-and-accumulate data is calculated by the digital addition circuit, the product-and-accumulate data is stored in the digital memory. In other words, when a multiply-and-accumulate operation is performed, data access to the digital memory is performed each time digital data is multiplied and added. In particular, when performing calculations using an artificial neural network, digital data is multiplied and added repeatedly, resulting in extremely frequent data access to the digital memory. As a result, the speed of data writing and reading from the digital memory affects the processing speed of the calculation. Furthermore, the power consumption required for repeated calculations such as those using a neural network is largely consumed by the power consumption required for data writing and reading from the digital memory.

[0010] Furthermore, by combining a calculation circuit that performs neural network calculations with a sensor, it may be possible to enable electronic devices and the like to recognize various information. For example, by combining an optical sensor (e.g., a photodiode) as a sensor with the calculation circuit, pattern recognition such as face recognition and image recognition can be performed from image data obtained by the optical sensor. However, because the electrical signal obtained from the optical sensor is weak, it is necessary to amplify the electrical signal using an amplifier circuit in order to input the electrical signal to the calculation circuit. Furthermore, if the calculation circuit is composed of a digital circuit, it is necessary to convert the electrical signal into a digital signal using an analog-to-digital conversion circuit or the like. Therefore, in order to input the electrical signal obtained from the optical sensor to the calculation circuit, it is necessary to process the electrical signal using various circuits, which may result in high power consumption in the circuit.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device capable of performing a product-sum operation. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0012] Another object of one embodiment of the present invention is to provide a novel semiconductor device or an electronic device including the semiconductor device.

[0013] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0014] (1) One embodiment of the present invention is a semiconductor device having a first cell, a second cell, a first circuit, a second circuit, a third circuit, a fourth circuit, a first wiring, a second wiring, and a third wiring. The first cell has a first capacitance, and the second cell has a second capacitance. The first circuit also has a fifth circuit and a sixth circuit, and the third circuit has a sensor. The first cell is electrically connected to the first circuit via the first wiring, and a first terminal of the first capacitance of the first cell is electrically connected to the third wiring. The second cell is electrically connected to the first circuit via the second wiring, and a first terminal of the second capacitance of the second cell is electrically connected to the third wiring. The second circuit is electrically connected to the fourth circuit, the third circuit is electrically connected to the fourth circuit, and the third wiring is electrically connected to the fourth circuit. The fourth circuit has a function of setting the second circuit and the third wiring to one of a conductive state or a non-conductive state, and setting the third circuit and the third wiring to the other of a conductive state or a non-conductive state. The first cell has a function of holding a first potential at the second terminal of the first capacitance when a first input potential is input to the third wiring, and a function of causing a current corresponding to the first potential to flow between the first cell and the first wiring, and a function of changing the first potential held at the second terminal of the first capacitance to a second potential when the first input potential of the third wiring changes to a second input potential, causing a current corresponding to the second potential to flow between the first cell and the first wiring. The second cell has the following functions: when a first input potential is input to the third wiring, to hold a third potential at the second terminal of the second capacitance, to pass a current corresponding to the third potential between the second cell and the second wiring, and when the first input potential of the third wiring changes to the second input potential, to change the third potential held at the second terminal of the second capacitance to a fourth potential and pass a current corresponding to the fourth potential between the second cell and the second wiring. Note that when the potential of the third wiring is the first input potential, a first current flows between the first circuit and the first wiring, and a second current flows between the first circuit and the second wiring, and when the potential of the third wiring is the second input potential, a third current flows between the first circuit and the first wiring, and a fourth current flows between the first circuit and the second wiring.The fifth circuit has a function of causing a first current of I1 to flow through the first wiring when the potential of the third wiring is the second input potential, and the sixth circuit has a function of causing a second current of I2 to flow through the first wiring when the potential of the third wiring is the second input potential. The first circuit has a function of acquiring a third current of I3 and a fourth current of I4 and generating a current of I1-I2-I3+I4 when the potential of the third wiring is the second input potential. The second circuit has a function of generating a fifth potential, a function of generating a sixth potential according to internal data input to the second circuit, and a function of outputting the fifth potential as the first input potential or the sixth potential as the second input potential to the fourth circuit. The third circuit also has a function of generating a seventh potential before the sensor acquires information, a function of generating an eighth potential according to the information acquired by the sensor, and a function of outputting the seventh potential as a first input potential or the eighth potential as a second input potential to the fourth circuit.

[0015] (2) Alternatively, in one aspect of the present invention, in the above-mentioned (1), the third circuit may include a first transistor, a second transistor, a third transistor, and a fourth transistor. In particular, it is preferable that a first terminal of the sensor is electrically connected to a first terminal of the first transistor, a second terminal of the first transistor is electrically connected to a first terminal of the second transistor and a gate of the third transistor, and the first terminal of the third transistor and a first terminal of the fourth transistor are electrically connected to the third wiring via the fourth circuit.

[0016] (3) Alternatively, in the above-mentioned (2) aspect of the present invention, the sensor may include a photodiode. In particular, it is preferable that an output terminal of the photodiode is electrically connected to the first terminal of the sensor.

[0017] (4) Alternatively, in one aspect of the present invention, in any one of the above (1) to (3), the first cell may include a fifth transistor and a sixth transistor, and the second cell may include a seventh transistor and an eighth transistor. In particular, it is preferable that a first terminal of the fifth transistor is electrically connected to a second terminal of the first capacitor and a gate of the sixth transistor, a first terminal of the sixth transistor is electrically connected to a first wiring, a first terminal of the seventh transistor is electrically connected to a second terminal of the second capacitor and a gate of the eighth transistor, and a first terminal of the eighth transistor is electrically connected to a second wiring.

[0018] (5) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (4), the second circuit may include a digital-analog converter circuit. In particular, the digital-analog converter circuit preferably converts a digital signal corresponding to internal data input to the digital-analog converter circuit into a sixth potential and outputs the sixth potential to the fourth circuit.

[0019] (6) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (5), the third circuit may be located above the first cell and the second cell.

[0020] (7) Another embodiment of the present invention is an electronic device including the semiconductor device described in any one of (1) to (6) above and a housing, in which the semiconductor device has a function of performing a product-sum operation.

[0021] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, an electronic component in which a chip is housed in a package, etc. are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0022] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0023] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0024] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0025] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0026] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0027] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0028] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element, wiring, or the like having a resistance value higher than 0 Ω. Therefore, in this specification and the like, a "resistance element" is intended to include wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0029] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value greater than 0 F, a region of wiring having a capacitance value, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric between the electrodes, but also a parasitic capacitance appearing between wiring and one of the source or drain of a transistor and the gate, and the like. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0030] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain are interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0031] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0032] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0033] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0034] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0035] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0036] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0037] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0038] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0039] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" and "wiring" include cases where multiple "electrodes" and "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," and the like are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0040] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0041] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in defect level density in the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (including water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements excluding hydrogen, and oxygen.

[0042] In this specification and the like, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0043] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0045] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0046] According to one embodiment of the present invention, a semiconductor device capable of performing a product-sum operation can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0047] According to one embodiment of the present invention, a novel semiconductor device or the like can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the semiconductor device can be provided.

[0048] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0049] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 3] FIG. 3 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 4] FIG. 4 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 5] 5A and 5B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 6] FIG. 6 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 7] 7A and 7B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 8] FIG. 8 is a timing chart showing an example of the operation of the semiconductor device. [Figure 9] FIG. 9 is a timing chart showing an example of the operation of the semiconductor device. [Figure 10]FIG. 10 is a timing chart showing an example of the operation of the semiconductor device. [Figure 11] FIG. 11 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 12] FIG. 12 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 13] FIG. 13 is a block diagram showing a configuration example of a semiconductor device. [Figure 14] FIG. 14 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 15] FIG. 15 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 16] 16A and 16B are block diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 17] 17A and 17B are timing charts showing an example of the operation of a circuit included in a semiconductor device. [Figure 18] 18A and 18B are diagrams illustrating a hierarchical neural network. [Figure 19] FIG. 19 is a block diagram showing a configuration example of a semiconductor device. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 22] 22A to 22C are cross-sectional views showing examples of the structure of a transistor. [Figure 23] 23A and 23B are cross-sectional views showing examples of the structure of a transistor. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 25] 25A and 25B are cross-sectional views showing examples of the structure of a transistor. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 27]FIG. 27A is a top view showing an example of the configuration of a capacitive element, and FIGS. 27B and 27C are cross-sectional perspective views showing the example of the configuration of a capacitive element. [Figure 28] 28A is a top view showing an example of the configuration of a capacitive element, FIG. 28B is a cross-sectional view showing an example of the configuration of a capacitor, and FIG. 28C is a cross-sectional perspective view showing an example of the configuration of a capacitive element. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 30] FIG. 30A is a diagram illustrating the classification of IGZO crystal structures, FIG. 30B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 30C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 31] FIG. 31A is a perspective view showing an example of a semiconductor wafer, FIG. 31B is a perspective view showing an example of a chip, and FIGS. 31C and 31D are perspective views showing an example of an electronic component. [Figure 32] 32A to 32F are perspective views of a package and a module that house an imaging device. [Figure 33] FIG. 33 is a perspective view showing an example of an electronic device. [Figure 34] 34A to 34C are perspective views showing an example of an electronic device. [Figure 35] 35A to 35C are schematic diagrams showing examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0050] In an artificial neural network (hereafter referred to as a neural network), the strength of synaptic connections can be changed by providing existing information to the neural network. This process of providing existing information to a neural network and determining connection strengths is sometimes called "learning."

[0051] Furthermore, by providing some information to a neural network that has undergone "learning" (with connection strengths determined), new information can be output based on the connection strengths. In this way, the process of outputting new information based on the provided information and connection strengths in a neural network is sometimes called "inference" or "cognition."

[0052] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are sometimes called "deep neural networks" (DNNs), and machine learning using deep neural networks is sometimes called "deep learning."

[0053] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0054] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0055] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0056] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0057] Note that the content described in the embodiments refers to the content described in each embodiment (or example) using various figures, or the content described using text in the specification.

[0058] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0059] The embodiments described in this specification will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0060] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m,n]” may be added to the symbol.

[0061] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0062] (Embodiment 1) In this embodiment, an example of an arithmetic circuit, which is a semiconductor device of one embodiment of the present invention, will be described.

[0063] <Configuration example 1 of an arithmetic circuit> The arithmetic circuit MAC1 shown in Fig. 1 is a configuration example of an arithmetic circuit capable of performing a product-sum operation and a function operation. The arithmetic circuit MAC1 is a circuit that performs a product-sum operation on first data stored in a memory cell (described later) and input second data, and performs an activation function operation using the result of the product-sum operation. Note that the first data and the second data can be, for example, analog data or multi-valued data (discrete data).

[0064] The arithmetic circuit MAC1 also has a sensor, and the information obtained by sensing the sensor can be used as second data for the product-sum operation. The sensor can be an optical sensor using a photodiode, a pressure sensor, a gyro sensor, an acceleration sensor, an auditory sensor, a temperature sensor, a humidity sensor, or the like.

[0065] Furthermore, the arithmetic circuit MAC1 can handle data (hereinafter referred to as internal data) stored in advance in a storage device or the like as the second data, rather than the information obtained by the sensor. In other words, the arithmetic circuit MAC1 has a function of selecting either the information obtained from the sensor or the internal data as the second data.

[0066] The arithmetic circuit MAC1 includes, for example, a memory cell array CA, a circuit CMS, a circuit WDD, a circuit XLD, a circuit SCA, a circuit SWC, a circuit WLD, a circuit IVTC, and a circuit ACTV.

[0067] The memory cell array CA includes memory cells AM[1,1] to AM[m,n] and memory cells AMr[1] to AMr[m]. In the memory cell array CA, the memory cells AM[1,1] to AM[m,n] are arranged in a matrix of m rows and n columns (m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1). The memory cells AMr[1] to AMr[m] are arranged in the (n+1)th column of the memory cell array CA.

[0068] The memory cells AM[1,1] to AM[m,n] have a function of storing first data, and the memory cells AMr[1] to AMr[m] have a function of storing reference data required for performing a multiply-and-accumulate operation. Note that the reference data can be analog data or multi-valued data (discrete data) like the first data and the second data.

[0069] The memory cell AM[1,1] is electrically connected to the wiring WD[1], the wiring BL[1], the wiring WL[1], and the wiring XL[1]. The memory cell AM[m,1] is electrically connected to the wiring WD[1], the wiring BL[1], the wiring WL[m], and the wiring XL[m]. The memory cell AM[1,n] is electrically connected to the wiring WD[n], the wiring BL[n], the wiring WL[1], and the wiring XL[1]. The memory cell AM[m,n] is electrically connected to the wiring WD[n], the wiring BL[n], the wiring WL[m], and the wiring XL[m]. The memory cell AMr[1] is electrically connected to the wiring WDr, the wiring BLr, the wiring WL[1], and the wiring XL[1]. The memory cell AMr[m] is electrically connected to the wiring WDr, the wiring BLr, the wiring WL[m], and the wiring XL[m].

[0070] An example of a detailed circuit configuration of each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] will be described later.

[0071] The circuit CMS is electrically connected to the wirings BL[1] to BL[n] and the wiring BLr. The circuit CMS has a function of supplying a current from the wiring BL[1] to each of the memory cells AM[1,1] to AM[m,1] and a function of setting the current to a constant current. The circuit CMS also has a function of supplying a current from the wiring BL[n] to each of the memory cells AM[1,n] to AM[m,n] and a function of setting the current to a constant current. The circuit CMS also has a function of supplying a current from the wiring BLr to each of the memory cells AMr[1] to AMr[m] and a function of setting the current to a constant current. The circuit CMS also has a function of subtracting the amount of constant current flowing through the wiring BLr from the amount of constant current flowing through each of the wirings BL[1] to BL[n].

[0072] The circuit WDD is electrically connected to the wirings WD[1] to WD[n] and the wiring WDr. The circuit WDD has a function of transmitting data to be stored in each memory cell of the memory cell array CA. For example, the circuit WDD can transmit first data as the data to the wirings WD[1] to WD[n] and can transmit reference data as the data to the wiring WDr.

[0073] The circuit WLD is electrically connected to the wirings WL[1] to WL[m]. The circuit WLD has a function of selecting a memory cell to which data is to be written when writing data to a memory cell included in the memory cell array CA. As a specific example, when writing data to a memory cell in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) of the memory cell array CA, the circuit WLD applies a high-level potential to the wiring WL[i] and a low-level potential to the wirings WL[1] to WL[m] other than the wiring WL[i], thereby selecting the memory cells AM[i,1] to AM[i,n] and AMr[i] to which data is to be written.

[0074] As an example, the circuit SWC includes circuits SWT[1] to SWT[m].

[0075] Moreover, the circuit SCA includes, for example, circuits RPC[1] to RPC[m].

[0076] The first terminal of the circuit SWT[1] is electrically connected to the wiring XL[1], the second terminal of the circuit SWT[1] is electrically connected to the circuit XLD, and the third terminal of the circuit SWT[1] is electrically connected to the circuit RPC[1]. Also, the first terminal of the circuit SWT[m] is electrically connected to the wiring XL[m], the second terminal of the circuit SWT[m] is electrically connected to the circuit XLD, and the third terminal of the circuit SWT[m] is electrically connected to the circuit RPC[m].

[0077] As an example, each of circuits SWT[1] to SWT[m] has the function of bringing the first terminal and the second terminal into one of a conductive state and a non-conductive state, and bringing the first terminal and the third terminal into the other of a conductive state and a non-conductive state.

[0078] Each of the circuits RPC[1] to RPC[m] has a sensor that generates second data corresponding to information obtained by sensing. Therefore, the circuit RPC[1] has a function of applying a voltage corresponding to the second data to the third terminal of the circuit SWT[1]. Similarly, the circuit RPC[m] has a function of applying a voltage corresponding to the second data to the third terminal of the circuit SWT[m].

[0079] 1 illustrates a circuit SCA in which the circuits RPC[1] to RPC[m] are arranged in a single column, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the circuits RPC[1] to RPC[m] may be arranged in a matrix instead of in a single column. Similarly, the circuits SWT[1] to SWT[m] may be arranged in a matrix instead of in a single column.

[0080] The configuration of the arithmetic circuit MAC1 including the circuit SCA in which the circuits RPC[1] to RPC[m] are arranged in a matrix and the circuit SWC in which the circuits SWT[1] to SWT[m] are arranged in a matrix may be, for example, the configuration example shown in Fig. 2. Note that Fig. 2 shows only the circuit SA, the circuit SWC, and the circuit SCA.

[0081] 2 has a configuration in which a circuit SWC in which circuits SWT[1] to SWT[m] are arranged in a matrix form is located above a memory cell array CA, and a circuit SCA in which circuits RPC[1] to RPC[m] are arranged in a matrix form is located above the circuit SWC. Note that the circuit SWC may be located below the memory cell array CA instead of above it (not shown).

[0082] The circuit XLD has a function of inputting a voltage according to the second data to the memory cells AM[1,1] to AM[1,n] and the memory cell AMr[1] included in the memory cell array CA via the first terminal of the circuit SWT[1] and the second terminal of the circuit SWT[1]. The circuit XLD also has a function of inputting a voltage according to the second data to the memory cells AM[m,1] to AM[m,n] and the memory cell AMr[m] included in the memory cell array CA via the first terminal of the circuit SWT[m] and the second terminal of the circuit SWT[m].

[0083] The circuit IVTC is electrically connected to the wirings BL[1] to BL[n] and the wirings OL[1] to OL[n]. The circuit IVTC has, for example, a function of converting the amount of current flowing from the wiring BL[1] to the circuit IVTC into a voltage or the like and a function of outputting the voltage to the wiring OL[1]. The circuit IVTC also has, for example, a function of converting the amount of current flowing from the wiring BL[n] to the circuit IVTC into a voltage or the like and a function of outputting the voltage to the wiring OL[n].

[0084] The circuit ACTV is electrically connected to the wiring OL[1] to wiring OL[n] and the wiring NIL[1] to wiring NIL[n]. The voltage output from the circuit IVTC is input to the circuit ACTV via the wiring OL[1]. The circuit ACTV has a function of performing calculations on the voltage according to a predefined function system. Examples of the function system that can be used include a sigmoid function, a tanh function, a softmax function, a ReLU function, and a threshold function. These functions are used as activation functions in the neural network.

[0085] <<Memory cell configuration example>> Next, a configuration example of the memory cells AM[1,1] to AM[m,n] and memory cells AMr[1] to AMr[m] included in the memory cell array CA will be described.

[0086] 3 is a circuit diagram showing an example of the configuration of the memory cell array CA and the circuit CMS. The memory cell array CA and the circuit CMS have a function of calculating the sum of products of the first data and the second data.

[0087] In the memory cell array CA shown in FIG. 3, each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] includes a transistor Tr11, a transistor Tr12, and a capacitor C1.

[0088] The sizes (e.g., channel length, channel width, transistor configuration, etc.) of the transistors Tr11 included in the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] are preferably equal to each other. The sizes of the transistors Tr12 included in the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] are preferably equal to each other.

[0089] By making the sizes of the transistors equal to each other, the electrical characteristics of the transistors can be made approximately equal. Therefore, by making the sizes of the transistors Tr11 included in each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] equal and by making the sizes of the transistors Tr12 included in each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] equal, the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m] can perform approximately the same operation under the same conditions. Here, the same conditions refer to, for example, the potentials of the source, drain, gate, etc. of the transistor Tr11, the potentials of the source, drain, gate, etc. of the transistor Tr12, and the voltages input to each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m].

[0090] Unless otherwise specified, the transistor Tr11 is assumed to function as a switching element. That is, the gate voltage, source voltage, and drain voltage of the transistor Tr11 are assumed to be appropriately biased within a range in which the transistor Tr11 operates as a switching element. Therefore, the transistor Tr11 may operate in the saturation region when on, or may operate in both the linear region and the saturation region.

[0091] Unless otherwise specified, the transistor Tr12 is assumed to operate in the saturation region when on, which means that the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are appropriately biased to voltages within the range in which they operate in the saturation region.

[0092] Note that the transistor Tr11 is preferably an OS transistor. In addition, the channel formation region of the transistor Tr11 more preferably contains an oxide containing at least one of indium, gallium, and zinc. Alternatively, the channel formation region of the transistor Tr11 may be an oxide containing at least one of indium, an element M (for example, the element M may be one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.), and zinc. Furthermore, the transistor Tr11 more preferably has the structure of the transistor described in Embodiment 5.

[0093] By using an OS transistor as the transistor Tr11, the leakage current of the transistor Tr11 can be suppressed, which may result in realizing a product-sum operation circuit with high calculation accuracy. Furthermore, by using an OS transistor as the transistor Tr11, the leakage current from the retention node (e.g., node N[1,1], node N[m,1], node N[1,n], node N[m,n], node Nr[1], node Nr[m], etc., which will be described later) to the write word line (e.g., wiring WD[1] to wiring WD[n], wiring WDr, etc.) when the transistor Tr11 is in a non-conductive state can be significantly reduced. In other words, the number of refresh operations of the potentials of the retention nodes can be reduced, which reduces the power consumption of the product-sum operation circuit.

[0094] Furthermore, by using an OS transistor for the transistor Tr12, the transistor Tr12 can be manufactured simultaneously with the transistor Tr11, which may shorten the manufacturing process of the product-sum operation circuit. The channel formation region of the transistor Tr12 may contain silicon instead of oxide (in this specification, a transistor containing silicon in its channel formation region is referred to as a Si transistor). Silicon may be, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or single crystal silicon.

[0095] Incidentally, when semiconductor devices and the like are highly integrated on a chip, the chip may generate heat due to the operation of the circuit. This heat increases the temperature of the transistor, which may change the characteristics of the transistor, resulting in a change in field-effect mobility and a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, so they are less likely to experience changes in field-effect mobility due to temperature changes and are less likely to experience a decrease in operating frequency. In other words, OS transistors are more likely to maintain their electrical characteristics even at high temperatures. Therefore, by using OS transistors, it is easier to perform calculations, processing, and the like, even in high-temperature environments. Therefore, when configuring a semiconductor device that is resistant to heat generation due to operation, it is preferable to use OS transistors as the transistors.

[0096] 3, the back gates of the transistors Tr11 and Tr12 are illustrated. Although the connection configuration of the back gates is not illustrated, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and the back gate of the transistor Tr11 may be electrically connected, or the gate and the back gate of the transistor Tr12 may be electrically connected. Furthermore, in a transistor having a back gate, for example, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring may be provided to electrically connect the back gate of the transistor to an external circuit or the like, and a potential may be applied to the back gate of the transistor from the external circuit or the like.

[0097] 3 includes a back gate, the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistors Tr11 and Tr12 in FIG. 3 may have a structure without a back gate, that is, may have a single-gate structure. Furthermore, some of the transistors may have a back gate, and other transistors may have a structure without a back gate.

[0098] 3, the transistors Tr11 and Tr12 are n-channel transistors, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, some or all of the transistors Tr11 and Tr12 may be replaced with p-channel transistors.

[0099] The above-described modifications to the transistor structures and polarities are not limited to the transistors Tr11 and Tr12, but also apply to, for example, transistors Tr33, Tr34, and Tr41 to Tr44 described later, as well as to transistors described elsewhere in the specification or illustrated in other drawings.

[0100] In each of the memory cells AM[1,1] to [m,n] and the memory cells AMr[1] to AMr[m], a first terminal of the transistor Tr11 is electrically connected to a gate of the transistor Tr12. A first terminal of the transistor Tr12 is electrically connected to a wiring VR. A first terminal of the capacitor C1 is electrically connected to the gate of the transistor Tr12.

[0101] In the memory cell AM[1,1], the second terminal of the transistor Tr11 is electrically connected to the wiring WD[1], and the gate of the transistor Tr11 is electrically connected to the wiring WL[1]. The second terminal of the transistor Tr12 is electrically connected to the wiring BL[1], and the second terminal of the capacitor C1 is electrically connected to the wiring XL[1]. In the memory cell AM[1,1], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is referred to as a node N[1,1].

[0102] In the memory cell AM[m,1], the second terminal of the transistor Tr11 is electrically connected to the wiring WD[1], and the gate of the transistor Tr11 is electrically connected to the wiring WL[m]. The second terminal of the transistor Tr12 is electrically connected to the wiring BL[1], and the second terminal of the capacitor C1 is electrically connected to the wiring XL[m]. In the memory cell AM[m,1], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is defined as a node N[m,1].

[0103] In the memory cell AM[1,n], the second terminal of the transistor Tr11 is electrically connected to the wiring WD[n], and the gate of the transistor Tr11 is electrically connected to the wiring WL[1]. The second terminal of the transistor Tr12 is electrically connected to the wiring BL[n], and the second terminal of the capacitor C1 is electrically connected to the wiring XL[1]. In the memory cell AM[1,n], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is referred to as a node N[1,n].

[0104] In the memory cell AM[m,n], the second terminal of the transistor Tr11 is electrically connected to the wiring WD[n], and the gate of the transistor Tr11 is electrically connected to the wiring WL[m]. The second terminal of the transistor Tr12 is electrically connected to the wiring BL[n], and the second terminal of the capacitor C1 is electrically connected to the wiring XL[m]. In the memory cell AM[m,n], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is referred to as a node N[m,n].

[0105] In the memory cell AMr[1], the second terminal of the transistor Tr11 is electrically connected to the wiring WDr, and the gate of the transistor Tr11 is electrically connected to the wiring WL[1]. The second terminal of the transistor Tr12 is electrically connected to the wiring BLr, and the second terminal of the capacitor C1 is electrically connected to the wiring XL[1]. In the memory cell AMr[1], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is the node Nr[1]. In addition, the current flowing from the wiring BLr to the second terminal of the transistor Tr12 is I AMr[1] Let's say.

[0106] In the memory cell AMr[m], the second terminal of the transistor Tr11 is electrically connected to the wiring WDr, and the gate of the transistor Tr11 is electrically connected to the wiring WL[m]. The second terminal of the transistor Tr12 is electrically connected to the wiring BLr, and the second terminal of the capacitor C1 is electrically connected to the wiring XL[m]. In the memory cell AMr[m], the electrical connection point between the first terminal of the transistor Tr11, the gate of the transistor Tr12, and the first terminal of the capacitor C1 is defined as a node Nr[m]. In addition, the current flowing from the wiring BLr to the second terminal of the transistor Tr12 is defined as I AMr[2] Let's say.

[0107] The above-mentioned nodes N[1], N[m], Nr[1], and Nr[m] function as retention nodes for the respective memory cells.

[0108] The wiring VR is a wiring for passing current between the first terminal and the second terminal of the transistor Tr12 of each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m]. Therefore, the wiring VR functions as a wiring for applying a predetermined potential. Note that in this embodiment, the potential applied by the wiring VR can be, for example, a low-level potential, a ground potential, or a potential lower than the ground potential.

[0109] <<Circuit CMS configuration example>> Next, an example of the configuration of the circuit CMS will be described.

[0110] In FIG. 3, the circuit CMS includes circuits CS1[1] to CS1[n], circuits CS2[1] to CS2[n], a circuit CM, and switches SW3[1] to SW3[n].

[0111] Further, the control terminals of the switches SW3[1] to SW3[n] are electrically connected to the line SL3.

[0112] The wiring SL3 functions as a wiring that supplies a voltage for switching the switches SW3[1] to SW3[n] between a conductive state and a non-conductive state.

[0113] Each of the circuits CS1[1] to CS1[n] functions as, for example, a current source circuit that supplies a constant current. As will be described in detail later, each of the circuits CS1[1] to CS1[n] has a function of setting the amount of the constant current.

[0114] Each of the circuits CS1[1] to CS1[n] includes a p-channel transistor Tr33, a capacitor C6, and a switch SW1.

[0115] The transistor Tr33 is preferably a Si transistor. The silicon contained in the channel formation region of the transistor Tr33 may be, for example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or single-crystal silicon.

[0116] Furthermore, it is preferable that the transistors Tr33 included in each of the circuits CS1[1] to CS1[n] have the same electrical characteristics. To achieve this, for example, it is preferable that the transistors Tr33 included in each of the circuits CS1[1] to CS1[n] have the same size.

[0117] Unless otherwise specified, the transistor Tr33 of each of the circuits CS1[1] to CS1[n] is assumed to operate in the saturation region when on, i.e., the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are assumed to be appropriately biased to voltages within the range in which they operate in the saturation region.

[0118] In each of the circuits CS1[1] to CS1[n], a first terminal of the transistor Tr33 is electrically connected to the wiring VHE, a gate of the transistor Tr33 is electrically connected to a first terminal of the capacitor C6 and a first terminal of the switch SW1, and a second terminal of the transistor Tr33 is electrically connected to the second terminal of the switch SW1. The second terminal of the capacitor C6 is electrically connected to the wiring VHE. The control terminal of the switch SW1 is electrically connected to the wiring SL1.

[0119] In the circuit CS1[1], the second terminal of the transistor Tr33 and the second terminal of the switch SW1 are electrically connected to the first terminal of the switch SW3[1] and the wiring BL[1].

[0120] In the circuit CS1[n], the second terminal of the transistor Tr33 and the second terminal of the switch SW1 are electrically connected to the first terminal of the switch SW3[n] and the wiring BL[n].

[0121] The wiring VHE functions as a wiring that applies a constant voltage, which is preferably, for example, a high-level potential.

[0122] The wiring SL1 functions as a wiring that supplies a voltage for switching the conductive state and non-conductive state of the switches SW1 of the circuits CS1[1] to CS1[n].

[0123] Each of the circuits CS1[1] to CS1[n] has a function of maintaining a constant amount of current flowing between the source and drain of the transistor Tr33, even if the source-drain voltage of the transistor Tr33 changes. Specifically, in each of the circuits CS1[1] to CS1[n], the switch SW1 is turned on to configure the transistor Tr33 as a diode. At this time, a current corresponding to the source-drain (gate) voltage of the transistor Tr33 flows between the source and drain of the transistor Tr33. The gate potential of the transistor Tr33 is approximately equal to the drain potential. Here, by turning off the switch SW1 and maintaining the gate potential of the transistor Tr33 by the first terminal of the capacitor C6, the gate-source voltage of the transistor Tr33 can be maintained constant. Therefore, when the transistor Tr33 operates in the saturation region, the amount of current flowing between the source and drain of the transistor Tr33 can be maintained constant, the same as the amount of current flowing when the switch SW1 is turned on, even if the drain potential changes.

[0124] In this specification and the like, temporarily connecting a transistor in a diode-connected configuration, making the potential of the gate of the transistor approximately equal to the potential of the drain, and then turning off the gate and drain of the transistor to keep the amount of source-drain current of the transistor constant is described as "setting (programming) the amount of current flowing between the source and drain of the transistor," etc. Also, when the transistor is included in a circuit such as each of circuits CS1[1] to CS1[n], it is described as "setting (programming) the amount of current flowing into the circuit," "setting (programming) the amount of current flowing out of (into) the circuit," etc.

[0125] Each of the circuits CS2[1] to CS2[n] functions as a current source circuit that supplies a constant current, for example. Similarly to the circuits CS1[1] to CS1[n], each of the circuits CS2[1] to CS2[n] also has the function of setting the amount of the constant current.

[0126] Each of the circuits CS2[1] to CS2[n] includes a transistor Tr34, which is an n-channel transistor, a capacitor C7, and a switch SW2.

[0127] The transistor Tr34 may be, for example, an OS transistor or a Si transistor that can be used for the transistor Tr11. When a Si transistor is used for the transistor Tr34, the silicon contained in the channel formation region of the transistor Tr34 may be, for example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like.

[0128] Furthermore, it is preferable that the transistors Tr34 included in each of the circuits CS2[1] to CS2[n] have the same electrical characteristics. To achieve this, for example, it is preferable that the transistors Tr34 included in each of the circuits CS2[1] to CS2[n] have the same size.

[0129] Unless otherwise specified, the transistors Tr34 of the circuits CS2[1] to CS2[n] are assumed to operate in the saturation region when on, i.e., the gate voltage, source voltage, and drain voltage of each of the above-described transistors are assumed to be appropriately biased to voltages within the range in which they operate in the saturation region.

[0130] In each of the circuits CS2[1] to CS2[n], a first terminal of the transistor Tr34 is electrically connected to the wiring VLE, ​​a gate of the transistor Tr34 is electrically connected to a first terminal of the capacitor C7 and a first terminal of the switch SW2, and a second terminal of the transistor Tr34 is electrically connected to the second terminal of the switch SW2. The second terminal of the capacitor C7 is electrically connected to the wiring VLE. The control terminal of the switch SW2 is electrically connected to the wiring SL2.

[0131] In the circuit CS2[1], the second terminal of the transistor Tr34 and the second terminal of the switch SW2 are electrically connected to the second terminal of the switch SW3[1].

[0132] In the circuit CS2[n], the second terminal of the transistor Tr34 and the second terminal of the switch SW2 are electrically connected to the second terminal of the switch SW3[n].

[0133] The line VLE functions as a line that applies a constant voltage, which is preferably, for example, a low-level potential.

[0134] The wiring SL2 functions as a wiring that supplies a voltage for switching the conductive state and non-conductive state of the switches SW2 of each of the circuits CS2[1] to CS2[n].

[0135] Like the circuits CS1[1] to CS1[n], each of the circuits CS2[1] to CS2[n] has the function of maintaining a constant amount of current flowing between the source and drain of the transistor Tr34, even when the source-drain voltage of the transistor Tr34 changes. Specifically, in each of the circuits CS2[1] to CS2[n], the switch SW2 is turned on to configure the transistor Tr34 as a diode. At this time, a current corresponding to the source-drain (gate) voltage of the transistor Tr34 flows between the source and drain of the transistor Tr34. The gate potential of the transistor Tr34 is approximately equal to the drain potential. Here, by turning off the switch SW2 and maintaining the gate potential of the transistor Tr34 by the first terminal of the capacitor C7, the gate-source voltage of the transistor Tr34 can be maintained constant. Therefore, when the transistor Tr34 operates in the saturation region, the amount of current flowing between the source and drain of the transistor Tr34 can be maintained constant, the same as the amount of current flowing when the switch SW2 is turned on, even when the drain potential changes.

[0136] The circuit CM functions as, for example, a current mirror circuit, and includes, for example, a transistor Tr31 and transistors Tr32[1] to Tr32[n].

[0137] Furthermore, since the circuit CM functions as a current mirror circuit, it is preferable that the transistor Tr31 and the transistors Tr32[1] to Tr32[n] have the same electrical characteristics. To achieve this, for example, it is preferable that the transistor Tr31 and the transistors Tr32[1] to Tr32[n] have the same size.

[0138] Unless otherwise specified, the transistor Tr31 and the transistors Tr32[1] to Tr32[n] are considered to operate in the saturation region when on, i.e., the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are considered to be appropriately biased to voltages within the range in which they operate in the saturation region.

[0139] A first terminal of the transistor Tr31 and each of the transistors Tr32[1] to Tr32[n] is electrically connected to the wiring VHE. A second terminal of the transistor Tr31 is electrically connected to the gate of the transistor Tr31, the gates of the transistors Tr31[1] to Tr31[n], and the wiring BLr.

[0140] The second terminal of the transistor Tr32[1] is electrically connected to the second terminal of the switch SW3[1], the second terminal of the transistor Tr34 of the circuit CS2[1], and the second terminal of the switch SW2 of the circuit CS2[1]. The second terminal of the transistor Tr32[n] is electrically connected to the second terminal of the switch SW3[n], the second terminal of the transistor Tr34 of the circuit CS2[n], and the second terminal of the switch SW2 of the circuit CS2[n].

[0141] By configuring the circuit CM as shown in Figure 3, a current amount approximately equal to the current flowing between the first terminal and the second terminal of transistor Tr31 can be flowed between the first terminal and the second terminal of each of transistors Tr32[1] to Tr32[n].

[0142] The switches SW1, SW2, and SW3[1] to SW3[n] may be, for example, electrical switches such as analog switches or transistors. The switches SW1, SW2, and SW3[1] to SW3[n] may be, for example, mechanical switches. When transistors are used as the switches SW1, SW2, and SW3[1] to SW3[n], the transistors may be OS transistors or Si transistors.

[0143] Furthermore, the configuration of the circuit CM is not limited to the configuration shown in Fig. 3. The configuration of the circuit CM may be, for example, as shown in the circuit CM shown in Fig. 4, in which the transistors Tr31 and Tr35 are cascode-connected, and the transistors Tr32[1] to Tr32[n] are cascode-connected, respectively, to the transistors Tr36[1] to Tr36[n]. By cascode-connecting the transistors included in the current mirror circuit as in the circuit CM shown in Fig. 4, the operation of the current mirror circuit can be made more stable.

[0144] In this embodiment, each of the switches SW1, SW2, and SW3[1] to SW3[n] is turned on when a high-level potential is input to the control terminal, and turned off when a low-level potential is input.

[0145] <<Configuration example of circuit IVTC>> Next, a configuration example of the circuit IVTC will be described.

[0146] 5A is a circuit diagram showing an example of the configuration of the circuit IVTC. The circuit IVTC includes, as an example, resistors RE[1] to RE[n], operational amplifiers OP[1] to OP[n], and switches SW4[1] to SW4[n].

[0147] The first terminal of the switch SW4[1] is electrically connected to the wiring BL[1], and the second terminal of the switch SW4[1] is electrically connected to the first terminal of the resistor RE[1] and the inverting input terminal of the operational amplifier OP[1]. The non-inverting input terminal of the operational amplifier OP[1] is electrically connected to the wiring VdL, and the output terminal of the operational amplifier OP[1] is electrically connected to the second terminal of the resistor RE[1] and the wiring OL[1]. In other words, the resistor RE[1] and the operational amplifier OP[1] form a current-voltage conversion circuit.

[0148] Similarly, a first terminal of the switch SW4[n] is electrically connected to the wiring BL[n], and a second terminal of the switch SW4[n] is electrically connected to the first terminal of the resistor RE[n] and the inverting input terminal of the operational amplifier OP[n]. In addition, each control terminal of the switches SW4[1] to SW4[n] is electrically connected to the wiring SL4.

[0149] For example, the wiring SL4 functions as a wiring that supplies a voltage for switching the switches SW4[1] to SW4[n] between a conductive state and a non-conductive state.

[0150] The non-inverting input terminal of the operational amplifier OP[n] is electrically connected to the wiring VdL, and the output terminal of the operational amplifier OP[n] is electrically connected to the second terminal of the resistor RE[n] and the wiring OL[n].

[0151] The wiring VdL functions as a wiring that applies a constant voltage, for example, which may be a ground potential or a low-level potential.

[0152] That is, in the circuit IVTC, n current-voltage conversion circuits are configured by the resistors RE[1] to RE[n], the operational amplifiers OP[1] to OP[n], and the wiring VdL.

[0153] Note that switches SW4[1] to SW4[n] can be, for example, switches that can be applied to switches SW1, SW2, SW3[1] to SW3[n], etc. In this specification, each of switches SW4[1] to SW4[n] is assumed to be turned on when a high-level potential is input to a control terminal and turned off when a low-level potential is input to the control terminal, similar to switches SW1, SW2, and SW3[1] to SW3[n].

[0154] Note that the circuit IVTC applicable to the arithmetic circuit MAC1 is not limited to the circuit IVTC shown in Fig. 5A. For example, as in the circuit IVTC shown in Fig. 5B, the resistors RE[1] to RE[n] provided in the circuit IVTC of Fig. 5A may be changed to loads LE[1] to LE[n], respectively. For example, diodes, transistors, etc. may be used as the loads LE[1] to LE[n]. Even when these circuit elements are used, n current-voltage conversion circuits can be configured by the loads LE[1] to LE[n] and the operational amplifiers OP[1] to OP[n].

[0155] <<Example of circuit SWC configuration>> Next, a configuration example of the circuit SWC will be described.

[0156] 6 is a circuit diagram showing an example configuration of the circuit SWC, the circuit SCA, and the circuit XLD. In the circuit SWC shown in FIG. 6, each of the circuits SWT[1] to SWT[m] has a switch SW5a and a switch SW5b.

[0157] In the circuit SWT[1], a first terminal of the switch SW5a is electrically connected to the line XL[1] and a first terminal of the switch SW5b. A control terminal of the switch SW5a is electrically connected to the line SL5, and a control terminal of the switch SW5b is electrically connected to the line SL5B.

[0158] In the circuit SWT[m], a first terminal of the switch SW5a is electrically connected to the line XL[m] and a first terminal of the switch SW5b. A control terminal of the switch SW5a is electrically connected to the line SL5, and a control terminal of the switch SW5b is electrically connected to the line SL5B.

[0159] For example, the wiring SL5 functions as a wiring that supplies a voltage for switching the switch SW5a of each of the circuits SWT[1] to SWT[m] between a conductive state and a non-conductive state. For example, the wiring SL5B functions as a wiring that supplies a voltage for switching the switch SW5b of each of the circuits SWT[1] to SWT[m] between a conductive state and a non-conductive state. When the voltages supplied to the wiring SL5 and the wiring SL5B are digital signals, the signal supplied to the wiring SL5 can be a signal whose logic is inverted from that of the signal supplied to the wiring SL5B.

[0160] The switches SW5a and SW5b may be, for example, switches that can be applied to the switches SW1, SW2, SW3[1] to SW3[n], etc. In the present embodiment, the switches SW5a and SW5b are each turned on when a high-level potential is input to a control terminal, and turned off when a low-level potential is input, similar to the switches SW1, SW2, and SW3[1] to SW3[n].

[0161] <<Example of circuit SCA configuration>> Next, an example of the configuration of the circuit SCA will be described.

[0162] In the circuit SCA shown in FIG. 6, each of the circuits RPC[1] to RPC[m] includes, for example, a transistor Tr41, a transistor Tr42, a transistor Tr43, a transistor Tr44, and a circuit SNC.

[0163] The sizes (e.g., channel length, channel width, transistor configuration, etc.) of the transistors Tr41 included in the circuits RPC[1] to RPC[m] are preferably equal to each other. The sizes of the transistors Tr42 included in the circuits RPC[1] to RPC[m] are preferably equal to each other. The sizes of the transistors Tr43 included in the circuits RPC[1] to RPC[m] are preferably equal to each other. The sizes of the transistors Tr44 included in the circuits RPC[1] to RPC[m] are preferably equal to each other. As described above, by making the transistor sizes equal to each other, the electrical characteristics of each transistor can be made approximately equal. This allows each of the circuits RPC[1] to RPC[m] to perform approximately the same operation under the same conditions. Here, the same conditions refer to, for example, the potentials of the sources, drains, gates, etc. of the transistors Tr41 to Tr44, the voltages input to each of the circuits RPC[1] to RPC[m], etc.

[0164] Unless otherwise specified, the transistors Tr41 and Tr42 are considered to function as switching elements. That is, the gate voltage, source voltage, and drain voltage of the transistors Tr41 and Tr42 are considered to function as switching elements. Therefore, the transistors Tr41 and Tr42 may operate in the saturation region when on, or may operate in both the linear region and the saturation region.

[0165] Unless otherwise specified, the transistors Tr43 and Tr44 are assumed to operate in the saturation region when on, i.e., the gate voltage, source voltage, and drain voltage of each of the above-described transistors are assumed to be appropriately biased to voltages within the range in which they operate in the saturation region.

[0166] The transistors Tr41 to Tr44 can be, for example, n-channel transistors. The transistors Tr41 to Tr44 can be, for example, OS transistors that can be used as the transistor Tr12 or Si transistors.

[0167] The circuit SNC also includes a sensor that converts information obtained by sensing into a current amount and outputs the current amount. As described above, the sensor can be, for example, an optical sensor using a photodiode, a pressure sensor, a gyro sensor, an acceleration sensor, an auditory sensor, a temperature sensor, or a humidity sensor. In particular, by applying an optical sensor to the circuit SNC, the circuit SCA can function as part of an image sensor. FIG. 7A shows a configuration example in which a circuit SNC including a photodiode PD is applied to the circuit SCA of FIG. 6. Specifically, the input terminal of the photodiode PD is electrically connected to a first terminal of the circuit SNC, and the output terminal of the photodiode PD is electrically connected to a second terminal of the circuit SNC. Note that FIG. 7A also illustrates a circuit SWC to show its electrical connection with each of the circuits RPC[1] to RPC[m].

[0168] The amount of current induced in the photodiode PD included in the circuit SCA of Fig. 7A is determined according to the intensity of the received light. Furthermore, since the photodiode PD is driven by applying a reverse bias, the current induced in the photodiode PD in Fig. 7A flows from the output terminal to the input terminal of the photodiode PD. Note that the circuit configuration of Fig. 7A is merely an example, and in some cases, the circuit SCA may be configured such that the input terminal of the photodiode PD is electrically connected to the second terminal of the circuit SNC, and the output terminal of the photodiode PD is electrically connected to the first terminal of the circuit SNC.

[0169] In each of the circuits RPC[1] to RPC[m], the first terminal of the circuit SNC is electrically connected to the wiring VBE, and the second terminal of the circuit SNC is electrically connected to the first terminal of the transistor Tr41. The gate of the transistor Tr41 is electrically connected to the wiring TXL, and the second terminal of the transistor Tr41 is electrically connected to the first terminal of the transistor Tr42 and the gate of the transistor Tr43. The gate of the transistor Tr42 is electrically connected to the wiring RSL, and the second terminal of the transistor Tr42 is electrically connected to the wiring VRS. The first terminal of the transistor Tr43 is electrically connected to the wiring VDE, the first terminal of the transistor Tr44 is electrically connected to the wiring VSE, and the gate of the transistor Tr44 is electrically connected to the wiring VBE. In particular, the electrical connection point between the gate of the transistor Tr43, the first terminal of the transistor Tr42, and the second terminal of the transistor Tr41 is referred to as a node NS.

[0170] In the circuit RPC[1], the second terminal of the transistor Tr43 is electrically connected to the second terminal of the transistor Tr44 and the second terminal of the switch SW5b of the circuit SWT[1].

[0171] In the circuit RPC[m], the second terminal of the transistor Tr43 is electrically connected to the second terminal of the transistor Tr44 and the second terminal of the switch SW5b of the circuit SWT[m].

[0172] For example, the wiring VDE functions as a wiring that supplies a constant voltage. Also, for example, the wiring VSE functions as a wiring that supplies a constant voltage. Note that the potential applied by the wiring VDE is higher than the potential applied by the wiring VSE.

[0173] The transistors Tr43 and Tr44 function as a source follower circuit depending on the connection configuration of the transistors Tr43 and Tr44 and the potentials applied by the wirings VDE and VSE.

[0174] For example, the line TXL functions as a line for switching the transistor Tr41 between a conductive state and a non-conductive state.

[0175] For example, the wiring RSL functions as a wiring for switching the transistor Tr42 between a conductive state and a non-conductive state.

[0176] For example, the wiring VBE functions as a wiring that supplies a constant voltage. In each of the circuits RPC[1] to RPC[m], the transistor Tr44 preferably functions as a constant current source that causes a constant current to flow between the first terminal and the second terminal. Therefore, the potential applied by the wiring VBE is preferably set so that the difference between the potential applied by the wiring VBE and the potential applied by the wiring VSE is greater than the threshold voltage of the transistor Tr44.

[0177] For example, the wiring AND functions as a wiring that supplies a constant voltage. Specifically, the wiring AND functions as a wiring that supplies a voltage for driving the circuit SNC. For example, as shown in FIG. 7A, when the circuit SNC includes a photodiode PD, it is necessary to apply a reverse bias to the photodiode PD. Therefore, it is preferable that the constant voltage provided by the wiring AND is a voltage lower than the reset potential.

[0178] For example, the wiring VRS functions as a wiring for supplying a constant voltage. Specifically, the wiring VRS functions as a wiring for supplying an initialization potential (hereinafter referred to as a reset potential) to the node NS.

[0179] Each of the circuits RPC[1] to RPC[m] performs an initial operation before sensing. For example, in the initial operation, a low-level potential is input to the wiring TXL and a high-level potential is input to the wiring RSL. This turns off the transistor Tr41 and turns on the transistor Tr42. Therefore, the gate of the transistor Tr43 (node ​​NS) and the wiring VRS are electrically connected, and a reset potential is input to the gate of the transistor Tr43 (node ​​NS).

[0180] At this time, the source follower circuit of transistor Tr43 and transistor Tr44 outputs a potential corresponding to the reset potential of the gate (node ​​NS) of transistor Tr43 from the electrical connection point between the second terminal of transistor Tr43 and the second terminal of transistor Tr44 to the second terminal of switch SW5b.

[0181] When each of the circuits RPC[1] to RPC[m] performs sensing, for example, a high-level potential is input to the wiring TXL and a low-level potential is input to the wiring RSL. This turns on the transistor Tr41 and turns off the transistor Tr42. As a result, the gate (node ​​NS) of the transistor Tr43 and the second terminal of the circuit SNC are conductive, and an amount of charge corresponding to the information obtained by sensing the circuit SNC is supplied to the gate (node ​​NS) of the transistor Tr43.

[0182] Then, a potential corresponding to the amount of charge on the gate (node ​​NS) of the transistor Tr43 is output from the electrical connection point between the second terminal of the transistor Tr43 and the second terminal of the transistor Tr44 to the second terminal of the switch SW5b by the source follower circuit of the transistor Tr43 and the transistor Tr44. In other words, the potential is treated as second data to be input to the memory cell array CA.

[0183] Note that the circuit configurations of the circuits RPC[1] to RPC[m] in FIG. 6 included in the semiconductor device of one embodiment of the present invention may be changed depending on the situation. For example, each of the circuits RPC[1] to RPC[m] in FIG. 6 may have a configuration in which a capacitor C8 is provided at the node NS. In each of the circuits RPC[1] to RPC[m] shown in FIG. 7B, a first terminal of the capacitor C8 is electrically connected to the node NS, and a second terminal of the capacitor C8 is electrically connected to a wiring CVL. By providing the capacitor C8 in each of the circuits RPC[1] to RPC[m], the potential input to the node NS can be held for a long time. Note that, similar to FIG. 7A, FIG. 7B also illustrates a circuit SWC to show the electrical connection to each of the circuits RPC[1] to RPC[m].

[0184] The line CVL functions as a line that applies a constant voltage, for example. The line CVL may be the same line as any one of the lines VDE, VSE, AND, VBE, and VRS.

[0185] <<Example of circuit XLD configuration>> Next, a configuration example of the circuit XLD will be described.

[0186] The circuit XLD shown in FIG. 6 includes, as an example, a circuit LGC, a circuit LS, and a circuit MUX.

[0187] The circuit LGC is electrically connected to the circuit LS by wirings LXS[1] to LXS[m]. The circuit LS is electrically connected to the circuit MUX by wirings DXS[1] to DXS[m]. The wirings LXS[1] to LXS[m] and DXS[1] to DXS[m] may function as bus wirings for transmitting digital signals.

[0188] The circuit MUX has a function of supplying a voltage corresponding to the reference data or a voltage (digital signal) corresponding to the second data to the second terminals of the circuits SWT[1] to SWT[m]. Specifically, for example, the circuit MUX can be a digital-to-analog conversion circuit that outputs a potential corresponding to the digital signal input to the wiring DXS[1] to the second terminal of the switch SW5a of the circuit SWT[1]. Furthermore, for example, the circuit MUX can be a digital-to-analog conversion circuit that outputs a potential corresponding to the digital signal input to the wiring DXS[m] to the second terminal of the switch SW5a of the circuit SWT[m].

[0189] For example, the circuit LS has a function of level-shifting an input potential to a desired potential. Specifically, for example, the circuit LS level-shifts a potential input from the wiring LXS[1] to a desired potential and outputs the level-shifted potential to the wiring DXS[1]. Therefore, the number of wirings for the wiring LXS[1] can be the same as the number of wirings DXS[1]. Similarly, for example, the circuit LS level-shifts a potential input from the wiring LXS[m] to a desired potential and outputs the level-shifted potential to the wiring DXS[m]. Therefore, the number of wirings for the wiring LXS[m] can be the same as the number of wirings DXS[m].

[0190] For example, the circuit LGC has a function of sequentially holding data DT input to the circuit LGC and outputting the data DT to the wirings LXS[1] to LXS[m] in parallel simultaneously or sequentially at a desired timing. The data DT here can be, for example, reference data or second data input to the wirings XCL[1] to XCL[m] via the circuit SWC. That is, the circuit LGC holds the reference data or second data received from outside the circuit LGC and outputs the reference data or second data to the wirings LXS[1] to LXS[m] at a predetermined timing in order to supply a voltage corresponding to the reference data or the second data to the wirings XCL[1] to XCL[m]. Note that a specific circuit configuration example of the circuit LGC will be described later.

[0191] If there is no need to level-shift the voltage output from the circuit LGC, the circuit LS may be omitted from the circuit XLD shown in Figure 6, and each of the wirings LXS[1] to LXS[m] may be directly and electrically connected to each of the wirings DXS[1] to DXS[m].

[0192] <Operation example 1 of the arithmetic circuit> Next, an example of the operation of the arithmetic circuit MAC1 will be described.

[0193] 8 shows a timing chart of an operation example of the arithmetic circuit MAC1. The timing chart of FIG. 8 shows fluctuations in potentials of the wiring WL[1], wiring WL[2], wiring WL[m] (in this operation example, m is an integer of 4 or more), wiring SL1, wiring SL2, wiring SL3, wiring SL4, wiring SL5, wiring SL5B, wiring RSL, wiring TXL, wiring WD[1], wiring WDr, node N[1,1], node N[2,1], node N[m,1], node Nr[1], node Nr[2], node Nr[m], wiring XL[1], wiring XL[2], and wiring XL[m] from time T01 to time T15 and around those times. Note that in FIG. 8, high-level potential is represented as "High" and low-level potential is represented as "Low."

[0194] <<From time T01 to time T02>> Between time T01 and time T02, a low-level potential is input to the wirings WL[1] to WL[m]. A low-level potential is input to the wirings SL1 to SL4, a high-level potential is input to the wiring SL5, and a low-level potential is input to the wiring SL5B. In addition, a ground potential (denoted as GND in FIG. 8) is input to the wirings WD[1] and WDr.

[0195] Since a high-level potential is input to the wiring SL5 and a low-level potential is input to the wiring SL5B, in the circuit SWC, the switch SW5a included in the circuits SWT[1] to SWT[m] is turned on, and the switch SW5b included in the circuits SWT[1] to SWT[m] is turned off. Therefore, each of the wirings XL[1] to XL[m] is brought into conduction with the circuit XLD and into non-conduction with the circuit SCA. As a result, a voltage from the circuit XLD is supplied to each of the wirings XL[1] to XL[m]. Here, for example, the voltage supplied to each of the wirings XL[1] to XL[m] from the circuit XLD is set to a reference potential (V RFP It is written as follows.)

[0196] Between time T01 and time T02, the potentials of the nodes N[1,1] to N[m,n] and the potentials of the nodes Nr[1] to Nr[m] are set to the ground potential (denoted as GND in FIG. 8).

[0197] <<From time T02 to time T03>> Between time T02 and time T03, a high-level potential is input to the wirings SL1 and SL2, which turns on the switches SW1 included in each of the circuits CS1[1] to CS1[n] and SW2 included in each of the circuits CS2[1] to CS2[n] in the circuit CMS.

[0198] Furthermore, between time T02 and time T03, a low-level potential is continuously input to the wiring SL3 and the wiring SL4 from before time T02, a high-level potential is continuously input to the wiring SL5 from before time T02, and a low-level potential is continuously input to the wiring SL5 from before time T02.

[0199] <<From time T03 to time T04>> Between time T03 and time T04, a high-level potential is input to the wiring WL[1], so that a high-level potential is applied to the gates of the transistors Tr11 included in each of the memory cells AM[1,1] to AM[1,n] and AMr[1] in the memory cell array CA, turning on the transistors Tr11.

[0200] In addition, between time T03 and time T04, the wiring WD[1] is at a potential higher than the ground potential V PR -V W[1,1] At this time, the transistor Tr11 of the memory cell AM[1,1] is in the on state, so that the line WD[1] and the node N[1,1] are in a conductive state, and the first terminal (node ​​N[1,1]) of the capacitor C1 of the memory cell AM[1,1] is V PR -V W[1,1] A large potential is input.

[0201] In this example, V PR is the potential corresponding to the reference data, and V W[1,1] is a potential corresponding to the first data stored in the memory cell AM[1,1].

[0202] In addition, between time T03 and time T04, the wiring WDr is charged with a potential higher than the ground potential V PR At this time, the transistor Tr11 of the memory cell AMr[1] is in the on state, so that the line WDr and the node Nr[1] are in a conductive state, and the first terminal (node ​​Nr[1]) of the capacitor C1 of the memory cell AMr[1] is V PRA large potential is input.

[0203] Furthermore, between time T03 and time T04, the transistors Tr11 of the memory cells AM[1,2] to AM[1,n] are also in the on state, and therefore, at this timing, by inputting the first data from the wirings WD[2] to WD[n] to the memory cells AM[1,2] to AM[1,n], potentials corresponding to the first data can be written to the nodes N[1,2] to N[1,n]. Note that in this operation example, the description focuses on the memory cells AM[1,1] to AM[m,1] electrically connected to the wiring WD[1] and the memory cells AMr[1] to AMr[m] electrically connected to the wiring WDr, and therefore, description of the operations of the other memory cells will be omitted.

[0204] Furthermore, between time T03 and time T04, a low-level potential continues to be input to the wirings WL[2] to WL[m] from before time T03. Therefore, in the memory cell array CA, a low-level potential is applied to the gates of the transistors Tr11 included in the memory cells AM[2,1] to AM[m,1] and the memory cells AMr[2] to AMr[m] arranged in the second to m-th rows, and each transistor Tr11 is in an off state. As a result, the data input to the wirings WD[1] and WDr is not written to the nodes N[2,1] to N[m,1] and the nodes Nr[2] to Nr[m].

[0205] Here, consider the current flowing from the second terminal to the first terminal of the transistor Tr12 of each of the memory cells AM[1,1] and AMr[1]. Let I be the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr12 of the memory cell AM[1,1]. AM[1,1],1 When I AM[1,1],1 can be expressed by the following formula:

[0206]

number

[0207] k is a constant determined by the channel length, channel width, mobility, and capacitance of the gate insulating film of the transistor Tr12. th is the threshold voltage of the transistor Tr12. Note that the constant k can be applied not only to the memory cell AM[1,1] but also to the other memory cells AM and AMr. In addition, the threshold voltages of the transistors Tr12 of not only the memory cell AM[1,1] but also the other memory cells AM and AMr are V th Let's say.

[0208] The current flowing from the wiring BLr to the first terminal via the second terminal of the transistor Tr12 of the memory cell AMr[1] is I AMr[1],2 Similarly, when AMr[1],2 can be expressed by the following formula:

[0209]

number

[0210] <<From time T04 to time T05>> Between time T04 and time T05, a low-level potential is input to the wiring WL[1], so that a low-level potential is applied to the gates of the transistors Tr11 included in each of the memory cells AM[1,1] to AM[1,n] and AMr[1] in the memory cell array CA, turning off the transistors Tr11.

[0211] In the memory cell AM[1,1], the transistor Tr11 is turned off, so that the first terminal (node ​​N[1,1]) of the capacitor C1 of the memory cell AM[1,1] is V PR -V W[1,1]In addition, in the memory cell AMr[1], the transistor Tr11 is turned off, and a potential V higher than the ground potential is held at the first terminal (node ​​Nr[1]) of the capacitor C1 of the memory cell AMr[1]. PR A large potential is maintained.

[0212] <<From time T05 to time T06>> Between time T05 and time T06, a high-level potential is input to the wiring WL[2], which causes a high-level potential to be applied to the gates of the transistors Tr11 included in each of the memory cells AM[2,1] to AM[2,n] and AMr[2] in the memory cell array CA, turning on the transistors Tr11.

[0213] In addition, between time T05 and time T06, the wiring WD[1] is at a potential higher than the ground potential V PR -V W[2,1] At this time, the transistor Tr11 of the memory cell AM[2,1] is in the on state, so that the line WD[1] and the node N[2,1] are in a conductive state, and the first terminal (node ​​N[2,1]) of the capacitor C1 of the memory cell AM[2,1] is V PR -V W[2,1] A large potential is input.

[0214] In this example, V W[2,1] is a potential corresponding to the first data stored in the memory cell AM[2,1].

[0215] Between time T05 and time T06, the wiring WDr is charged to a potential V PR At this time, the transistor Tr11 of the memory cell AMr[2] is in the on state, so that the line WDr and the node Nr[2] are in a conductive state, and the first terminal (node ​​Nr[2]) of the capacitor C1 of the memory cell AMr[2] is supplied with a potential higher than the ground potential V PR A large potential is input.

[0216] Between time T05 and time T06, the wiring WL[1] and the wirings WL[3] to WL[m] continue to be supplied with a low-level potential since before time T05. Therefore, in the memory cell array CA, a low-level potential is applied to the gates of the transistors Tr11 included in the memory cells AM[1,1], AM[3,1] to AM[m,1], AMr[1], and AMr[3] to AMr[m] arranged in the first row and the third to mth rows, and each transistor Tr11 is in an off state. As a result, the data input to the wirings WD[1] and WDr is not written to the nodes N[1,1], N[3,1] to N[m,1], Nr[1], and Nr[3] to Nr[m].

[0217] Here, consider the current flowing from the second terminal to the first terminal of the transistor Tr12 of each of the memory cells AM[2,1] and AMr[2]. Let I be the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr12 of the memory cell AM[2,1]. AM[2,1],1 When I AM[2,1],1 can be expressed by the following formula:

[0218]

number

[0219] The current flowing from the wiring BLr to the first terminal via the second terminal of the transistor Tr12 of the memory cell AMr[2] is I AMr[2],2 Similarly, when AMr[2],2 can be expressed by the following formula:

[0220]

number

[0221] <<From time T06 to time T07>> Between time T06 and time T07, a low-level potential is input to the wiring WL[2], so that a low-level potential is applied to the gates of the transistors Tr11 included in each of the memory cells AM[2,1] to AM[2,n] and AMr[2] in the memory cell array CA, turning off the transistors Tr11.

[0222] In the memory cell AM[2,1], when the transistor Tr11 is turned off, the first terminal (node ​​N[2,1]) of the capacitor C1 of the memory cell AM[2,1] is V PR -V W[2,1] In addition, in the memory cell AMr[2], the transistor Tr11 is turned off, and a potential V higher than the ground potential is held at the first terminal (node ​​Nr[2]) of the capacitor C1 of the memory cell AMr[2]. PR A large potential is maintained.

[0223] Also, between time T06 and time T07, similar to the operation between time T03 and time T05 described above, a potential corresponding to the first data is held at the first terminal of the capacitance C1 of each of the memory cells AM[3,1] to AM[m-1,n]. Specifically, for example, the first terminal (node ​​N[3,1]) of the capacitance C1 of the memory cell AM[3,1] is held at a potential V higher than the ground potential. PR -V W[3,1] A higher potential is maintained, and the first terminal (node ​​N[m-1,1]) of the capacitor C1 of the memory cell AM[m-1,1] is V PR -V W[m-1,1] A high potential is maintained.

[0224] In this example, V W[3,1] is the potential corresponding to the first data stored in the memory cell AM[3,1], and V W[m-1,1] is a potential corresponding to the first data stored in the memory cell AM[m-1,1].

[0225] <<From time T07 to time T08>> Between time T07 and time T08, a high-level potential is input to the wiring WL[m], so that a high-level potential is applied to the gates of the transistors Tr11 included in each of the memory cells AM[m,1] to AM[m,n] and AMr[m] in the memory cell array CA, turning on the transistors Tr11.

[0226] In addition, between time T07 and time T08, the wiring WD[1] is at a potential higher than the ground potential V PR -V W[m,1] At this time, since the transistor Tr11 of the memory cell AM[m,1] is in the on state, the line WD[1] and the node N[m,1] are in a conductive state, and the first terminal (node ​​N[m,1]) of the capacitor C1 of the memory cell AM[m,1] is supplied with a potential V higher than the ground potential. PR -V W[m,1] A large potential is input.

[0227] In this example, V W[m,1] is a potential corresponding to the first data stored in the memory cell AM[m,1].

[0228] Between time T07 and time T08, the wiring WDr is charged to a potential V PR At this time, since the transistor Tr11 of the memory cell AMr[m] is in the on state, the line WDr and the node Nr[m] are in a conductive state, and the first terminal (node ​​Nr[m]) of the capacitor C1 of the memory cell AMr[m] is supplied with a potential V higher than the ground potential. PR A large potential is input.

[0229] Furthermore, between time T07 and time T08, a low-level potential continues to be input to the wirings WL[1] to WL[m-1] from before time T07. Therefore, in the memory cell array CA, a low-level potential is applied to the gates of the transistors Tr11 included in the memory cells AM[1,1] to AM[m-1,1] and memory cells AMr[1] to AMr[m-1] arranged in the first to m-1th rows, and each transistor Tr11 is in an off state. As a result, the data input to the wirings WD[1] and WDr is not written to the nodes N[1,1] to N[m-1,1] and the nodes Nr[1] to Nr[m-1].

[0230] Here, consider the current flowing from the second terminal to the first terminal of the transistor Tr12 of each of the memory cells AM[m,1] and AMr[m]. Let I be the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr12 of the memory cell AM[m,1]. AM[m,1],1 When I AM[m,1],1 can be expressed by the following formula:

[0231]

number

[0232] Also, the current flowing from the wiring BLr to the first terminal via the second terminal of the transistor Tr12 of the memory cell AMr[m] is I AMr[m],2 Similarly, when AMr[m],2 can be expressed by the following formula:

[0233]

number

[0234] <<From time T08 to time T09>> Between time T08 and time T09, a low-level potential is input to the wiring WL[m], so that in the memory cell array CA, a low-level potential is applied to the gates of the transistors Tr11 included in each of the memory cells AM[m,1] to AM[m,n] and AMr[m], turning off the transistors Tr11.

[0235] In the memory cell AM[m,1], when the transistor Tr11 is turned off, a potential V higher than the ground potential is applied to the first terminal (node ​​N[m,1]) of the capacitor C1 of the memory cell AM[m,1]. PR -V W[m,1] In addition, in the memory cell AMr[m], the transistor Tr11 is turned off, and a potential V higher than the ground potential is held at the first terminal (node ​​Nr[m]) of the capacitor C1 of the memory cell AMr[m]. PR A large potential is maintained.

[0236] Now, consider the current flowing between the first and second terminals of the transistor Tr33 in the circuit CS1[1] included in the circuit CMS. In this operation example, the amount of this current is denoted as I1.

[0237] Between time T08 and time T09, the switch SW1 of the circuit CS1[1] is on, the switch SW3[1] is off, and the switch SW4[1] of the circuit IVTC is off. Therefore, the amount of current I1 flowing between the first terminal and the second terminal of the transistor Tr33 of the circuit CS1[1] can be expressed by the following equation using Kirchhoff's law.

[0238]

number

[0239] In addition, the transistor Tr33 of the circuit CS1[1] is configured as a diode connection, and the first terminal of the transistor Tr33 of the circuit CS1[1] is electrically connected to a wiring VHE that provides a high-level potential as a constant voltage, so the potential of the gate (second terminal) of the transistor Tr33 of the circuit CS1[1] is determined by the amount of current I1 flowing between the first terminal and the second terminal of the transistor Tr33.

[0240] Next, consider the current flowing between the first and second terminals of the transistor Tr34 of the circuit CS2[1] included in the circuit CMS. In this operation example, the amount of this current is represented as I2.

[0241] Between time T08 and time T09, switch SW2 of circuit CS2[1] is on and switch SW3[1] is off, so the amount of current flowing between the first terminal and the second terminal of transistor Tr34 of circuit CS2[1] is approximately equal to the amount of current flowing between the first terminal and the second terminal of transistor Tr32[1].

[0242] Furthermore, since the circuit CM is configured as a current mirror circuit, the amount of current flowing between the first and second terminals of the transistor Tr32[1] is approximately equal to the amount of current flowing between the first and second terminals of the transistor Tr31.

[0243] Since the amount of current flowing between the first terminal and the second terminal of transistor Tr31 is the sum of the currents flowing from wiring BLr to memory cells AMr[1] to AMr[m], the amount of current I2 flowing between the first terminal and the second terminal of transistor Tr34 in circuit CS2[1] can be expressed as follows:

[0244]

number

[0245] In addition, the transistor Tr34 of the circuit CS2[1] is configured as a diode connection, and the first terminal of the transistor Tr34 of the circuit CS2[1] is electrically connected to a wiring VLE that provides a high-level potential as a constant voltage, so the potential of the gate (second terminal) of the transistor Tr34 of the circuit CS2[1] is determined by the amount of current I2 flowing between the first terminal and the second terminal of the transistor Tr34.

[0246] <<From time T09 to time T10>> Between time T09 and time T10, a low-level potential is input to the wiring SL1, and a low-level potential is input to the wiring SL2. As a result, in the circuit CMS, the switches SW1 included in each of the circuits CS1[1] to CS1[n] are turned off, and the switches SW2 included in each of the circuits CS2[1] to CS2[n] are turned off.

[0247] Therefore, between time T09 and time T10, the gate potential of transistor Tr33 in circuit CS1[1] is held by the first terminal of capacitor C6, and the gate potential of transistor Tr34 in circuit CS2[1] is held by the first terminal of capacitor C7. This maintains the gate-source voltage of transistor Tr33 in circuit CS1[1], so that a current I1 always flows between the first and second terminals of transistor Tr33. Similarly, the gate-source voltage of transistor Tr34 in circuit CS2[1] is maintained, so that a current I2 always flows between the first and second terminals of transistor Tr34. In other words, the amount of current I1 flowing out of circuit CS[1] is set for circuit CS[1], and the amount of current I2 flowing into circuit CS[2] is set for circuit CS[2].

[0248] <<From time T10 to time T11>> Between time T10 and time T11, a high-level potential is input to the wiring RSL, which turns on the transistors Tr42 of the circuits RPC[1] to RPC[m] included in the circuit SCA.

[0249] When the transistor Tr42 of each of the circuits RPC[1] to RPC[m] is turned on, a reset potential is supplied from the wiring VRS to the node NS of each of the circuits RPC[1] to RPC[m].

[0250] <<From time T11 to time T12>> Between time T11 and time T12, a low-level potential is input to the wiring RSL, which turns off the transistor Tr42 included in each of the circuits RPC[1] to RPC[m] included in the circuit SCA.

[0251] When the transistor Tr42 of each of the circuits RPC[1] to RPC[m] is turned off, the supply of the reset potential from the wiring VRS to the node NS of each of the circuits RPC[1] to RPC[m] is stopped.

[0252] The circuits RPC[1] to RPC[m] included in the circuit SCA are initialized by the operation between time T10 and time T12 described above.

[0253] At this time, the source follower circuits of the transistors Tr43 and Tr44 output potentials corresponding to the potential of the node NS from the second terminals of the transistors Tr43 and Tr44. That is, potentials corresponding to the reset potential are output from the second terminals of the transistors Tr43 and Tr44. As an example, the potentials output from the second terminals of the transistors Tr43 and Tr44 are the potentials corresponding to the V RFPSpecifically, for example, by adjusting the potentials applied to the wirings VRS, VDE, VSE, VBE, and the like, the wirings XL[1] to XL[m] are set to a potential approximately equal to V RFP A potential approximately equal to

[0254] <<From time T12 to time T13>> Between time T12 and time T13, a high-level potential is input to the wiring TXL, which turns on the transistors Tr41 of the circuits RPC[1] to RPC[m] included in the circuit SCA.

[0255] When the transistor Tr41 of each of the circuits RPC[1] to RPC[m] is turned on, a current corresponding to the information sensed by the circuit SNC flows between the first terminal and the second terminal of the transistor Tr41. As a result, an amount of charge corresponding to the information is stored in the node NS of each of the circuits RPC[1] to RPC[m].

[0256] <<From time T13 to time T14>> Between time T13 and time T14, a low-level potential is input to the wiring TXL, which turns off the transistor Tr41 included in each of the circuits RPC[1] to RPC[m] included in the circuit SCA.

[0257] By turning off the transistor Tr41 of each of the circuits RPC[1] to RPC[m], the current from the circuit SNC to the node NS of each of the circuits RPC[1] to RPC[m] is stopped.

[0258] The operation between time T12 and time T14 described above allows the node NS to hold an amount of charge according to the information sensed by the circuit SNC.

[0259] At this time, the source follower circuit of the transistors Tr43 and Tr44 outputs a potential corresponding to the potential of the node NS from the second terminal of the transistor Tr43 and the second terminal of the transistor Tr44. That is, a potential corresponding to the information sensed by the circuit SNC is output from the second terminal of the transistor Tr43 and the second terminal of the transistor Tr44.

[0260] <<From time T14 to time T15>> Between time T14 and time T15, a high-level potential is input to the wiring SL3, a high-level potential is input to the wiring SL4, a low-level potential is input to the wiring SL5, and a high-level potential is input to the wiring SL5B. As a result, in the circuit CMS, the switches SW3[1] to SW3[n] are turned on. In the circuit IVTC, the switches SW4[1] to SW4[n] are turned on. In the circuit SWC, the switches SW5a included in the circuits SWT[1] to SWT[m] are turned off, and the switches SW5b included in the circuits SWT[1] to SWT[m] are turned on.

[0261] When the switch SW5a included in the circuits SWT[1] to SWT[m] is turned off and the switch SW5b included in the circuits SWT[1] to SWT[m] is turned on, each of the wirings XL[1] to XL[m] is brought out of conduction with the circuit XLD and brought into conduction with the circuit SCA. Therefore, a potential corresponding to information acquired by the circuit SNC included in each of the circuits RPC[1] to RPC[m] is input to each of the wirings XL[1] to XL[m]. Here, for example, the potential input from the circuit RPC[1] to the wiring XL[1] is set to V higher than the ground potential. RFP +V X[1] The potential input from the circuit RPC[2] to the wiring XL[2] is V higher than the ground potential. RFP +V X[2] The potential input from the circuit RPC[m] to the wiring XL[m] is V higher than the ground potential. RFP+V X[m] A high potential is used.

[0262] In this example, the potential V X[1] ~V X[m] is a potential corresponding to the second data.

[0263] Between time T14 and time T15, the potential of the wiring XL[1] is V RFP From V RFP +V X[1] Therefore, the second terminal of the capacitor C1 of each of the memory cell AM[1] and the memory cell AMr[1] is V RFP +V X[1] At this time, since the nodes N[1,1] and Nr[1] are in an electrically floating state, the potentials of the nodes N[1,1] and Nr[1] change due to the capacitive coupling of the capacitor C1.

[0264] In each of memory cells AM[1] and AMr[1], the increase in the potential of the gate of transistor Tr12 is equal to the potential change of line XL[1] multiplied by a capacitive coupling coefficient determined by the configuration of the memory cell. This capacitive coupling coefficient is calculated based on the capacitance of capacitor C1, the gate capacitance of transistor Tr12, parasitic capacitance, etc. In this operation example, to avoid complexity, the increase in the potential of line XL[1] and the increase in the potential of the gate of transistor Tr12 are described as having the same value. This corresponds to the capacitive coupling coefficient of each of memory cells AM[1,1] and AMr[1] being 1. In this operation example, the capacitive coupling coefficient of each of memory cells other than memory cell AM[1,1] and memory cell AMr[1] included in the memory cell array CA is also described as 1.

[0265] Since the capacitance coupling coefficient is set to 1, the potential of the second terminal of the capacitance C1 of each memory cell AM[1,1] and memory cell AMr[1] is V RFP From V RFP +V X[1]As a result, the potentials of the node N[1,1] and the node Nr[1] are V X[1] Rise.

[0266] Here, the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr12 of the memory cell AM[1,1] is I AM[1,1],3 When I AM[1.1],3 can be expressed by the following formula:

[0267]

number

[0268] Similarly, the current flowing from the wiring BLr to the first terminal via the second terminal of the transistor Tr12 of the memory cell AMr[1] is I AMr[1],4 When I AMr[1],4 can be expressed by the following formula:

[0269]

number

[0270] In addition, the capacitive coupling coefficient of the memory cell AM[2,1] and the memory cell AMr[2] is set to 1, so the potential of the second terminal of the capacitance C1 included in each is V RFP From V RFP +V X[2] By changing to V, the potentials of the node N[2,1] and the node Nr[2] are V X[2] Rise.

[0271] Here, the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr12 of the memory cell AM[2,1] is I AM[2,1],3 When I AM[2.1],3 can be expressed by the following formula:

[0272]

number

[0273] Similarly, the current flowing from the wiring BLr to the first terminal via the second terminal of the transistor Tr12 of the memory cell AMr[2] is I AMr[2],4 When I AMr[2],4 can be expressed by the following formula:

[0274]

number

[0275] In addition, the capacitive coupling coefficient of the memory cell AM[m,1] and the memory cell AMr[m] is set to 1, so the potential of the second terminal of the capacitance C1 included in each is V RFP From V RFP +V X[m] By changing to V, the potentials of the node N[m,1] and the node Nr[m] are V X[m] Rise.

[0276] Here, the current flowing from the wiring BL to the first terminal via the second terminal of the transistor Tr12 of the memory cell AM[m,1] is I AM[m,1],3 When I AM[m.1],3 can be expressed by the following formula:

[0277]

number

[0278] Similarly, the current flowing from the wiring BLr to the first terminal via the second terminal of the transistor Tr12 of the memory cell AMr[2] is I AMr[m],4 When I AMr[m],4 can be expressed by the following formula:

[0279]

number

[0280] If the total amount of current flowing from wiring BL[1] to memory cells AM[1,1] to AM[m,1] between time T14 and time T15 is I3, the amount of current I3 can be expressed as follows:

[0281]

number

[0282] Furthermore, since the circuit CM is configured as a current mirror circuit, the amount of current flowing between the first and second terminals of the transistor Tr32[1] included in the circuit CM is approximately equal to the amount of current flowing between the first and second terminals of the transistor Tr31. Furthermore, the amount of current flowing between the first and second terminals of the transistor Tr31 is the sum of the currents flowing from the wiring BLr to the memory cells AMr[1] to AMr[m]. If the amount of current flowing between the first and second terminals of the transistor Tr32[1] included in the circuit CM between time T14 and time T15 is I4, the amount of current I4 can be expressed as follows:

[0283]

number

[0284] Furthermore, between time T14 and time T15, the switches SW3[1] to SW3[n] and the switches SW4[1] to SW4[n] are turned on, so that current flows from the circuit CMS and the memory cell array CA to the circuit IVTC via the wiring BL. Specifically, for example, a current I1 flows out from the circuit CS1[1], a current I2 flows into the circuit CS2[1], and a current I4 flows between the source and drain of the transistor Tr32[1] of the circuit CM. The sum of the currents flowing through the memory cells AM[1,1] to AM[m,1] is I3. Here, the amount of current flowing from the wiring BL[1] to the wiring OL[1] is I S When [1] is set, the amount of current I S[1] can be written as follows using Kirchhoff's law:

[0285]

number

[0286] From equation (1.17), the amount of current I input from wiring BL[1] to circuit IVTC S [1] is the potential V according to the first data W[1,1] ~V W[m,1] and the potential V according to the second data X[1] ~V X[m] In other words, the sum of the products of the first data and the second data is proportional to the amount of current I S It can be expressed as [1].

[0287] <Operation example 2 of the arithmetic circuit> The operation of the semiconductor device of one embodiment of the present invention is not limited to the operation illustrated in the timing chart of Figure 8. The operation of the semiconductor device of one embodiment of the present invention can be changed depending on the situation.

[0288] The operation shown in the timing chart of FIG. 8 is performed by the circuit XLD supplying V to the wirings XL[1] to XL[m] between time T01 and time T14. RFP However, between time T01 and time T14, each of the circuits RPC[1] to RPC[m] included in the circuit SNC may apply a potential to the wirings XL[1] to XL[m].

[0289] Specifically, for example, the semiconductor device of one embodiment of the present invention may operate as shown in the timing chart in Figure 9. The operation of the timing chart in Figure 9 differs from the operation of the timing chart in Figure 8 in that a low-level potential is always input to the wiring SL5 and a high-level potential is always input to the wiring SL5B. Therefore, the wirings XL[1] to XL[m] are always in a non-conduction state with the circuit XLD, and the wirings XL[1] to XL[m] are always in a continuity state with the circuit SCA.

[0290] In the operation of the timing chart of FIG. 9, a high-level potential is input to the wiring RSL between time T01 and time T02. That is, a reset potential is supplied to the nodes NS of the circuits RPC[1] to RPC[m] included in the circuit SCA. Furthermore, a low-level potential is input to the wiring RSL between time T02 and time T12, and the reset potential is held at the nodes NS of the circuits RPC[1] to RPC[m]. Furthermore, between time T01 and time T12, the source follower circuits of the transistors Tr43 and Tr44 output potentials corresponding to the reset potential of the node NS from the second terminals of the transistors Tr43 and Tr44. Because a high-level potential is applied to the wiring SL5B and the switch SW5b is turned on, potentials corresponding to the reset potential of the node NS are output to the wirings XL[1] to XL[m]. In the timing chart of FIG. 9, the potentials output to the wirings XL[1] to XL[m] are set to V, which is the same as the potential output from the circuit XLD in the timing chart of FIG. RFP It states that:

[0291] 9, a high-level potential is input to the wiring TXL between time T12 and time T13. That is, the nodes NS of the circuits RPC[1] to RPC[m] included in the circuit SCA are charged with an amount of charge corresponding to the information sensed by the circuit SNC. After time T13, a low-level potential is input to the wiring TXL, and the nodes NS of the circuits RPC[1] to RPC[m] are held with the amount of charge. After time T13, the source follower circuits of the transistors Tr43 and Tr44 output potentials corresponding to the amount of charge held in the nodes NS from the second terminals of the transistors Tr43 and Tr44. A high-level potential is applied to the wiring SL5B, and the switch SW5b is turned on. Therefore, a potential corresponding to the amount of charge held in the nodes NS is output to the wirings XL[1] to XL[m]. In the timing chart of FIG. 9, the potential output to the wiring XL[1] is V RFP +V X[1] The potential output to the wiring XL[2] is V RFP +V X[2] The potential output to the wiring XL[m] is V RFP +V X[m] It states that:

[0292] <Operation example 3 of the arithmetic circuit> Further, the operation of the semiconductor device of one embodiment of the present invention may be the operation shown in the timing chart in FIG. 10 instead of the operation shown in the timing chart in FIGS.

[0293] 10 differs from the operation of the timing chart of Fig. 8 in that a high-level potential is always input to the wiring SL5 and a low-level potential is always input to the wiring SL5B. Therefore, the wirings XL[1] to XL[m] and the circuit XLD are always in a conductive state, and the wirings XL[1] to XL[m] and the circuit SCA are always in a non-conductive state.

[0294] Since the wirings XL[1] to XL[m] and the circuit SCA are always in a non-conductive state, the circuits RPC[1] to RPC[m] included in the circuit SCA do not operate in the operation of the timing chart of Figure 10. Therefore, in the operation of the timing chart of Figure 10, for example, a low-level potential is always input to the wirings RSL and TXL.

[0295] The operation of the timing chart in FIG. 10 differs from the operation of the timing charts in FIGS. 8 and 9 in that the potential is always supplied to each of the wirings XL[1] to XL[m] by the circuit XLD.

[0296] In the operation of the timing chart of FIG. 10, from before time T01 to time T14, the potential V RFP is being supplied.

[0297] In the operation of the timing chart of FIG. 10, after time T14, the wiring XL[1] receives a voltage V RFP +V X[1] Similarly, the wiring XL[2] is supplied with V from the circuit XLD via the circuit SWC. RFP +V X[2] Similarly, V is supplied from the circuit XLD via the circuit SWC. RFP +V X[m] is being supplied.

[0298] As described above, in the semiconductor device of one embodiment of the present invention, the circuit SWC can select a circuit that outputs a potential to be input to the wirings XL[1] to XL[m] from the circuit XLD or the circuit SWC. In other words, the semiconductor device of one embodiment of the present invention can select whether the second data is information acquired from a sensor or the like included in the circuit SWC or internal data stored in a memory device or the like provided outside the arithmetic circuit, and perform arithmetic.

[0299] Furthermore, by performing either the above-described operation example 2 of the arithmetic circuit or the operation example 3 of the arithmetic circuit, and then performing the other of the operation example 2 of the arithmetic circuit or the operation example 3 of the arithmetic circuit without updating the first data written to the memory cell array CA (without performing the operations from time T03 to time T08), it is possible to compare the results output from the wirings NIL[1] to NIL[n] in each operation example. For example, when a circuit SNC including a photodiode PD is applied as the circuit SNC as shown in FIG. 7A, it is possible to compare an image captured by the photodiode PD in operation example 2 of the arithmetic circuit with an image corresponding to the internal data input from the circuit XLD in operation example 3 of the arithmetic circuit. In particular, when performing image recognition or the like using a hierarchical neural network described in embodiment 4, by relatively comparing the results output in operation example 2 of the arithmetic circuit and operation example 3 of the arithmetic circuit, it is possible to optimize the settings of the voltages of each wiring in operation example 2 of the arithmetic circuit (for example, the voltages applied by wiring VBE, wiring VDE, wiring VSE, and wiring VRS, the voltages input to each of wirings XL[1] to XL[n], etc.), and it is also possible to reduce the signal amplitude (amount of current, voltage, etc.), allowing inference to be performed in a short time.

[0300] In the above-described second operation example of the arithmetic circuit, when the potential of the node NS of the circuits RPC[1] to RPC[m] is the reset potential, the potential supplied from the second terminal of the transistor Tr43 and the second terminal of the transistor Tr44 is V RFP 7A, when a circuit SNC including a photodiode PD is applied as the circuit SNC, and light of a certain intensity is incident on the photodiode PD, the potentials supplied from the second terminals of the transistors Tr43 and Tr44 change approximately in proportion to time (between time T12 and time T13). That is, the potentials of the wirings XL[1] to XL[m] of the arithmetic circuit MAC1 are changed by the data obtained by the photodiode PD, and the potential V RFPIt changes in proportion to time from time T12. Therefore, the difference in output increases in proportion to the time it takes for the photodiode PD to acquire data (from time T12 to time T13). Therefore, if a relative difference in the output signals occurs to an extent sufficient for determining the inference, the inference can be terminated at that point, and the inference can sometimes be completed in a short time.

[0301] Although the transistors included in the arithmetic circuit MAC1 are OS transistors or Si transistors in this embodiment, one embodiment of the present invention is not limited thereto. The transistors included in the arithmetic circuit MAC1 may be, for example, transistors having an active layer made of Ge or the like, transistors having an active layer made of a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe, transistors having an active layer made of a carbon nanotube, or transistors having an active layer made of an organic semiconductor.

[0302] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0303] (Embodiment 2) In this embodiment, an arithmetic circuit having a different configuration from the arithmetic circuit MAC1 described in the first embodiment will be described.

[0304] <Configuration example 2 of arithmetic circuit> The arithmetic circuit MAC2 shown in FIG. 11 differs from the arithmetic circuit MAC1 in that it has memory cells AMb[1] to AMb[n] in the memory cell array CA.

[0305] The memory cell AMb[1] is electrically connected to the wiring BL[1], the wiring WD[1], the wiring XLb, and the wiring WLb. The memory cell AMb[n] is electrically connected to the wiring BL[n], the wiring WD[n], the wiring XLb, and the wiring WLb.

[0306] A specific configuration example of memory cells AMb[1] to AMb[n] is shown in Fig. 12. Note that Fig. 12 also illustrates memory cells AM[1,1] to AM[m,n], memory cells AMr[1] to AMr[m], a circuit WDD, a circuit CMS, a circuit IVTC, and a circuit ACTV in order to show electrical connections with each of memory cells AMb[1] to AMb[n].

[0307] 12, the memory cells AMb[1] to AMb[n] can have substantially the same configuration as the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m]. Therefore, in the arithmetic circuit MAC2 in FIG. 12, each of the memory cells AMb[1] to AMb[n] includes a transistor Tr11, a transistor Tr12, and a capacitor C1.

[0308] In each of the memory cells AMb[1] to AMb[n], the first terminal of the transistor Tr12 is electrically connected to the wiring VRA.

[0309] In memory cell AMb[1], the electrical connection point between the first terminal of transistor Tr11, the gate of transistor Tr12, and the first terminal of capacitor C1 is defined as node Nb[1]. In memory cell AMb[n], the electrical connection point between the first terminal of transistor Tr11, the gate of transistor Tr12, and the first terminal of capacitor C1 is defined as node Nb[n].

[0310] The wiring WLb functions as a wiring that supplies a selection signal from the circuit WLD to the memory cells AMb[1] to AMb[n] when writing data to the memory cells AMb[1] to AMb[n]. The wiring XLb functions as a wiring that applies a constant potential to the second terminals of the capacitors C1 of the memory cells AMb[1] to AMb[n], for example. The constant potential is preferably a ground potential, a low-level potential, a high-level potential, or the like. Alternatively, the wiring XLb may function as a wiring that supplies an arbitrary potential from the circuit XLD.

[0311] The wiring VRA of each of the memory cells AMb[1] to AMb[n] can be set to a low-level potential, a ground potential, or a potential lower than the ground potential, similar to the wiring VR of each of the memory cells AM[1,1] to AM[m,n] and the memory cells AMr[1] to AMr[m]. Alternatively, the wiring VRA of each of the memory cells AMb[1] to AMb[n] may be set to a wiring that applies a high-level potential in some cases. For example, if a positive current is to flow from the memory cell AMb[1] to the wiring BL[1], the wiring VRA of the memory cell AMb[1] may be set to a wiring that applies a high-level potential.

[0312] 8, from time T01 to time T14, the nodes Nb[1] to Nb[n] are held at ground potential, low-level potential, or potential applied by the wiring VR so that the transistors Tr12 of the memory cells AMb[1] to AMb[n] are turned off. Also, from time T14 to time T15 in the timing chart of FIG. 8, an arbitrary amount of current I flows between the first terminal and the second terminal of the transistor Tr12 of each of the memory cells AMb[1] to AMb[n]. BIAS [1]~I BIAS potential V BIAS [1]~V BIAS [n]. For example, in this case, IBIAS [1] is expressed by the following formula:

[0313]

number

[0314] Therefore, between time T14 and time T15, for example, the amount of current I S [1] is expressed as follows:

[0315]

number

[0316] Equation (2.2) corresponds to an operation that further applies an arbitrary bias to the result of a product-sum operation. As will be explained in detail in the fourth embodiment, an operation that further applies an arbitrary bias to the result of a product-sum operation is used in the operation of a hierarchical neural network. For this reason, the arithmetic circuit MAC2 is suitable for performing the operation of a hierarchical neural network.

[0317] <Configuration example 3 of an arithmetic circuit> Next, a configuration example of an arithmetic circuit which is a semiconductor device of one embodiment of the present invention and which is different from the arithmetic circuit MAC1 in FIG. 1 and the arithmetic circuit MAC2 in FIG. 11 will be described.

[0318] The arithmetic circuit MAC3 shown in FIG. 13 differs from the arithmetic circuits MAC1 and MAC2 in that it is configured such that a current related to the result of the product-sum operation flows from the circuit CMS to the circuit IVTC and the circuit ACTV.

[0319] 13, the circuit CMS is electrically connected to the circuit IVTC through wirings BLO[1] to BLO[n]. Note that the description of the arithmetic circuit MAC1 in FIG. 1 should be referred to for other circuit configurations.

[0320] A specific example of the configuration of the circuit CMS is shown in Fig. 14. In Fig. 14, the circuit IVTC is also shown to show the connection configuration with the circuit CMS.

[0321] The circuit CMS shown in Figure 14 is configured such that, in the circuit CMS of Figure 3 described in embodiment 1, a wiring BLO[1] is electrically connected to the second terminal of the switch SW3[1], the second terminal of the transistor Tr32[1], and the second terminal of the transistor Tr34 of the circuit CS2[1], and a wiring BLO[n] is electrically connected to the second terminal of the switch SW3[n], the second terminal of the transistor Tr32[n], and the second terminal of the transistor Tr34 of the circuit CS2[n].

[0322] The circuit IVTC shown in Fig. 14 has almost the same configuration as the circuit IVTC in Fig. 5A, except that the wirings BL[1] to BL[n] shown in Fig. 5A are replaced with wirings BLO[1] to BLO[n], respectively. The wirings BLO[1] to BLO[n] are electrically connected to the first terminals of the switches SW4[1] to SW4, respectively, included in the circuit IVTC in Fig. 5A.

[0323] By applying the circuit CMS and the circuit IVTC configured as shown in FIG. 14 to the arithmetic circuit MAC3 in FIG. 13, it is possible to perform the same operation as the arithmetic circuit MAC1 described in the first embodiment.

[0324] Furthermore, the configurations of the circuit CMS and the circuit IVTC included in the arithmetic circuit MAC3 in Fig. 13 are not limited to the configuration shown in Fig. 14. For example, the circuit CMS and the circuit IVTC included in the arithmetic circuit MAC3 in Fig. 13 may have the configuration example shown in Fig. 15.

[0325] 15 is configured by adding switches SW6[1] to SW6[n] to the circuit CMS of FIG. 3 described in Embodiment 1. Specifically, the first terminal of the switch SW6[1] is electrically connected to the second terminal of the switch SW3[1], the second terminal of the transistor Tr32[1], and the second terminal of the transistor Tr34. The second terminal of the switch SW6[1] is electrically connected to the wiring BLO[1]. The control terminals of the switches SW6[1] to SW6[n] are electrically connected to the wiring SL6.

[0326] Note that switches SW6[1] to SW6[n] can be, for example, switches that can be applied to switches SW1, SW2, SW3[1] to SW3[n], etc. In this specification, each of switches SW6[1] to SW6[n] is assumed to be turned on when a high-level potential is input to a control terminal and turned off when a low-level potential is input to the control terminal, similar to switches SW1, SW2, and SW3[1] to SW3[n].

[0327] 15 does not include the switches SW4[1] to SW4[n] in the circuit IVTC of FIG. 5A. Therefore, wirings BLO[1] to BLO[n] are electrically connected to the inverting input terminals of the operational amplifiers OP[1] to OP[n] included in the circuit IVTC of FIG.

[0328] That is, the circuit CMS of FIG. 15 is configured such that switches SW6[1] to SW6[n] are provided in place of the switches SW4[1] to SW4[n] included in the circuit IVTC of FIG. 14, respectively.

[0329] Furthermore, when the operation of the timing charts of FIGS. 8 to 10 described in embodiment 1 is performed using the circuit CMS of FIG. 15 and the arithmetic circuit MAC3 to which the circuit IVTC is applied, the timing at which the switches SW3[1] to SW3[n] and the switches SW6[1] to SW6[n] are turned on or off is the same, so the wiring SL3 and the wiring SL6 may be combined into a single wiring.

[0330] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0331] (Embodiment 3) In this embodiment mode, a configuration example of the circuit LGC included in the circuit XLD of the arithmetic circuits MAC1 to MAC3 described in Embodiment Mode 1 and Embodiment Mode 2 will be described.

[0332] 16A shows a specific example of the circuit configuration of the circuit LGC. When one of the wirings LXS[1] to LXS[m] is a bus wiring for transmitting a digital signal, it is preferable that the data DT (reference data and the second data) input to the circuit LGC be input as a digital signal. By treating the data DT as a digital signal, the circuit LGC can be configured as a logic circuit.

[0333] The circuit LGC shown in FIG. 16A includes a shift register SR, latch circuits LTA[1] to LTA[m], latch circuits LTB[1] to LTB[m], and switches SW8[1] to SW8[m].

[0334] The shift register SR is electrically connected to the wirings SPL, SCL, and SEL[1] to SEL[m].

[0335] The control terminals (sometimes referred to as clock input terminals, enable signal input terminals, etc.) of the latch circuits LTA[1] to LTA[m] are electrically connected to the wirings SEL[1] to SEL[m], and the control terminals of the latch circuits LTB[1] to LTB[m] are electrically connected to the wirings LAT. The input terminals D of the latch circuits LTA[1] to LTA[m] are electrically connected to the wirings DAT, and the output terminals Q of the latch circuits LTA[1] to LTA[m] are electrically connected to the wirings DL[1] to DL[m], respectively. The input terminals D of the latch circuits LTB[1] to LTB[m] are electrically connected to the wirings DL[1] to DL[m], and the output terminals Q of the latch circuits LTB[1] to LTB[m] are electrically connected to the first terminals of the switches SW8[1] to SW8[m]. The second terminals of the switches SW8[1] to SW8[m] are electrically connected to the wirings LXS[1] to LXS[m], respectively, and the control terminals of the switches SW8[1] to SW8[m] are electrically connected to the wirings SL8[1] to SL8[m], respectively.

[0336] Furthermore, switches SW8[1] to SW8[m] can be, for example, switches that can be applied to switches SW1, SW2, SW3[1] to SW3[n], etc. In this specification, each of switches SW8[1] to SW8[m] is assumed to be turned on when a high-level potential is input to a control terminal and turned off when a low-level potential is input to the control terminal, similar to switches SW1, SW2, and SW3[1] to SW3[n].

[0337] The wirings SL8[1] to SL8[m] function as wirings for switching the switches SW8[1] to SW8[m] between a conductive state and a non-conductive state, for example.

[0338] For example, the wiring SPL functions as a wiring that transmits a start pulse signal to the shift register SR.

[0339] Moreover, the line SCL functions as a line for transmitting a clock signal to the shift register SR, for example.

[0340] Moreover, the wiring DAT functions as a wiring for transmitting data DT to the circuit LGC, for example.

[0341] The wirings SEL[1] to SEL[m], the wirings DL[1] to DL[m], and the wiring DAT can be used as wirings for transmitting digital signals. Therefore, the wirings SEL[1] to SEL[m], the wirings DL[1] to DL[m], and the wiring DAT can be used as bus wirings. Furthermore, the wirings SL8[1] to SL8[m] can also be used as bus wirings.

[0342] For example, the shift register SR has a function of sequentially outputting a high-level potential to the wirings SEL[1] to SEL[m] in accordance with a change in the potential input to the wirings SPL and SCL. Note that the shift register SR cannot output a high-level potential to two or more of the wirings SEL[1] to SEL[m], and when any one of the wirings SEL[1] to SEL[m] outputs a high-level potential, the remaining wirings SEL[1] to SEL[m] output a low-level potential.

[0343] For example, when a high-level potential is input to the wiring SPL as a start pulse signal and the potential rises from a low-level potential to a high-level potential in response to a clock signal from the wiring SCL, the wiring SEL[1] outputs a high-level potential. Subsequently, when a low-level potential is input to the wiring SPL and the potential rises again from a low-level potential to a high-level potential in response to a clock signal from the wiring SCL, the wiring SEL[1] outputs a low-level potential and the wiring SEL[2] outputs a high-level potential. Furthermore, after that, when a low-level potential is input to the wiring SPL and the potential rises for the third time in response to a clock signal from the wiring SCL, the wirings SEL[1] and SEL[2] output low-level potentials and the wiring SEL[3] outputs a high-level potential.

[0344] In this way, each time a potential rise occurs in the clock signal from the wiring SCL, the shift register SR can sequentially output a high-level potential to one of the wirings SEL[1] to SEL[m] and output a low-level potential to the other wirings.

[0345] Each of the latch circuits LTA[1] to LTA[m] and the latch circuits LTB[1] to LTB[m] has the function of becoming enabled when a high-level potential is input to the control terminal, holding the data input to the input terminal D, and outputting the data to the output terminal Q. Note that each of the latch circuits LTA[1] to LTA[m] and the latch circuits LTB[1] to LTB[m] becomes disabled when a low-level potential is input to the control terminal, not holding the data input to the input terminal D, and not outputting the data to the output terminal Q.

[0346] An example of the operation of the circuit LGC will now be described.

[0347] 17A is a timing chart showing an operation example of the circuit LGC. The timing chart shows changes in potentials of the wirings SPL, SCL, SEL[1], SEL[2], SEL[m-1], SEL[m], wirings SL8[1] to SL8[m], and wiring LAT, and also shows data input to the wirings DAT, LXS[1], LXS[2], LXS[m-1], and LXS[m]. Note that in the wirings SPL, SCL, SEL[1], SEL[2], SEL[m], SEL[m-1], wirings SL8[1] to SL8[m], and wiring LAT, high-level potentials are indicated as "High" and low-level potentials are indicated as "Low."

[0348] 17A shows an example of an operation in which the circuit LGC simultaneously outputs data DT to each of the wirings LXS[1] to LXS[m] between time T31 and time T40 and at times around that time. This example of an operation is assumed to be performed between time T14 and time T15 in the timing chart of FIG.

[0349] Also, assume that, prior to time T31, a low-level potential is input to the wiring LAT, and a low-level potential is input to each of the wirings SL8[1] to SL8[m]. Also, assume that the shift register SR outputs a low-level potential to each of the wirings SEL[1] to SEL[m].

[0350] Between time T31 and time T32, a high-level potential is input to the line SPL as a start pulse signal. Also, a pulse voltage is input to the line SCL as a clock signal. When the rising edge of the pulse voltage of the clock signal is input, the shift register SR acquires the high-level potential, which is the start pulse signal input to the line SPL.

[0351] Between time T32 and time T33, data DT[1] is input to the line DAT. Also, a second pulse voltage is input to the line SCL as a clock signal. When the rising edge of the second pulse voltage of the clock signal is input, the shift register SR outputs a high-level potential to the line SEL[1].

[0352] At this time, the latch circuit LTA[1] is enabled, so it holds the data DT[1] input to its input terminal D and outputs the data DT[1] to its output terminal Q. The data DT[1] is input to the input terminal D of the latch circuit LTB[1]. At this time, a low-level potential is input to the control terminal of the latch circuit LTB[1], so the latch circuit LTB[1] does not hold the data DT[1] input to the input terminal D of the latch circuit LTB[1], and does not output the data DT[1] input to the output terminal Q of the latch circuit LTB[1].

[0353] Between time T33 and time T34, data DT[2] is input to the line DAT. Also, a third pulse voltage is input to the line SCL as a clock signal. When the rising edge of the third pulse voltage of the clock signal is input, the shift register SR outputs a low-level potential to the line SEL[1] and a high-level potential to the line SEL[2].

[0354] At this time, the latch circuit LTA[1] is disabled and does not hold the data DT[2] input to the input terminal D of the latch circuit LTA[1]. Furthermore, the latch circuit LTA[1] continues to hold the data DT[1] from before time T33 and outputs the data DT[1] from the output terminal Q.

[0355] Furthermore, the latch circuit LTA[2] is enabled, so it holds the data DT[2] input to its input terminal D and outputs the data DT[2] to its output terminal Q. The data DT[2] is input to the input terminal D of the latch circuit LTB[2]. At this time, a low-level potential is input to the control terminal of the latch circuit LTB[2], so the latch circuit LTB[2] does not hold the data DT[2] input to the input terminal D of the latch circuit LTB[2], and does not output the data DT[2] input to the output terminal Q of the latch circuit LTB[2].

[0356] Between time T34 and time T35, data DT[3] to DT[m-2] are sequentially input to the wiring DAT, and high-level potentials are sequentially input to the wirings SEL[3] to SEL[m-2] by the shift register SR. As a result, data DT[3] to DT[m-2] are held in the latches LTA[3] to LTA[m-2], respectively. Furthermore, data DT[3] to DT[m-2] are output from the output terminals Q of the latches LTA[3] to LTA[m-2], respectively.

[0357] Between time T35 and time T36, data DT[m-1] is input to the line DAT. Also, the m-th pulse voltage is input to the line SCL as a clock signal. When the rising edge of the m-th pulse voltage of the clock signal is input, the shift register SR outputs a low-level potential to the line SEL[m-2] and a high-level potential to the line SEL[m-1].

[0358] At this time, the latch circuit LTA[m-2] is disabled and does not hold the data DT[m-1] input to the input terminal D of the latch circuit LTA[m-2]. Furthermore, the latch circuit LTA[m-2] continues to hold the data DT[m-2] from before time T35 and outputs the data DT[m-2] from the output terminal Q.

[0359] Furthermore, the latch circuit LTA[m-1] is enabled, so it holds the data DT[m-1] input to its input terminal D and outputs the data DT[m-1] to its output terminal Q. The data DT[m-1] is input to the input terminal D of the latch circuit LTB[m-1]. At this time, because a low-level potential is input to the control terminal of the latch circuit LTB[m-1], the latch circuit LTB[m-1] does not hold the data DT[m-1] input to the input terminal D of the latch circuit LTB[m-1], and does not output the data DT[m-1] input to the output terminal Q of the latch circuit LTB[m-1].

[0360] Between time T36 and time T37, data DT[m] is input to the line DAT. Also, the (m+1)th pulse voltage is input to the line SCL as a clock signal. When the rising edge of the (m+1)th pulse voltage of the clock signal is input, the shift register SR outputs a low-level potential to the line SEL[m-1] and a high-level potential to the line SEL[m].

[0361] At this time, the latch circuit LTA[m-1] is disabled and does not hold the data DT[m] input to the input terminal D of the latch circuit LTA[m-1]. Furthermore, the latch circuit LTA[m-1] continues to hold the data DT[m-1] from before time T36 and outputs the data DT[m-1] from the output terminal Q.

[0362] Furthermore, the latch circuit LTA[m] is enabled, so it holds the data DT[m] input to its input terminal D and outputs the data DT[m] to its output terminal Q. The data DT[m] is input to the input terminal D of the latch circuit LTB[m]. At this time, a low-level potential is input to the control terminal of the latch circuit LTB[m], so the latch circuit LTB[m] does not hold the data DT[m] input to the input terminal D of the latch circuit LTB[m], and does not output the data DT[m] input to the output terminal Q of the latch circuit LTB[m].

[0363] Between time T38 and time T39, a high-level potential is input to the line LAT. As a result, a high-level potential is input to each control terminal of the latch circuits LTB[1] to LTB[m], and each of the latch circuits LTB[1] to LTB[m] is enabled. As a result, the latch circuits LTB[1] to LTB[m] hold the data DT[1] to DT[m] input to their respective input terminals D and output the data DT[1] to DT[m] from their respective output terminals Q.

[0364] Between time T39 and time T40, a high-level potential is input to the wirings SL8[1] to SL8[m]. This turns on the switches SW8[1] to SW8[m], and electrical continuity is established between the output terminals Q of the latch circuits LTB[1] to LTB[m] and the wirings LXS[1] to LXS[m]. This allows the circuit LGC to simultaneously output data DT[1] to DT[m] from the wirings LXS[1] to LXS[m].

[0365] By performing the operation of the timing chart shown in Figure 17A, the circuit LGC can simultaneously output data DT[1] to data DT[m] sequentially input to the circuit LGC in parallel to wiring LXS[1] to wiring LXS[m].

[0366] 17A shows an example of operation in which the circuit LGC simultaneously outputs the data DT to each of the wirings LXS[1] to LXS[m], but the circuit LGC may also sequentially output the data DT to each of the wirings LXS[1] to LXS[m]. The timing chart of FIG. 17B shows an example of operation in which the circuit LGC sequentially outputs the data DT to each of the wirings LXS[1] to LXS[m]. Note that the operation before time T39 in the timing chart of FIG. 17B is assumed to be the operation example from before time T31 to time T39 in the timing chart of FIG. 17A.

[0367] 17B shows changes in the potentials of the wirings SL8[1], SL8[2], SL8[m-1], and SL8[m], and also shows data input to the wirings LXS[1], LXS[2], LXS[m-1], and LXS[m]. Note that in the wirings SL8[1], SL8[2], SL8[m-1], and SL8[m], high-level potentials are indicated as "High" and low-level potentials are indicated as "Low."

[0368] Between time T39 and time T40, a high-level potential is input to the line SL8[1], which turns on the switch SW8[1], establishing electrical continuity between the output terminal Q of the latch circuit LTB[1] and the line LXS[1], thereby transmitting the data DT[1] output from the output terminal Q of the latch circuit LTB to the line LXS[1].

[0369] Between time T40 and time T41, a low-level potential is input to the line SL8[1] and a high-level potential is input to the line SL8[2]. As a result, the switch SW8[1] is turned off and the switch SW8[2] is turned on. Because there is no conduction between the output terminal Q of the latch circuit LTB[1] and the line LXS[1], the data DT[1] output from the output terminal Q of the latch circuit LTB is not transmitted to the line LXS[1]. In addition, there is conduction between the output terminal Q of the latch circuit LTB[2] and the line LXS[2], so the data DT[2] output from the output terminal Q of the latch circuit LTB is transmitted to the line LXS[2].

[0370] Between time T41 and time T42, high-level potentials are sequentially input to the wirings SL8[3] to SL8[m-2], and the switches SW8[3] to SW8[m-2] are sequentially turned on. As a result, the data DT[3] to DT[m-2] output to the output terminals Q of the latch circuits LTB[3] to LTB[m-2] are sequentially output from the wirings LXS[3] to LXS[m-2], respectively.

[0371] Between time T42 and time T43, a low-level potential is input to the line SL8[m-2] and a high-level potential is input to the line SL8[m-1]. As a result, the switch SW8[m-2] is turned off and the switch SW8[m-1] is turned on. Because there is no conduction between the output terminal Q of the latch circuit LTB[m-2] and the line LXS[m-2], the data DT[m-2] output from the output terminal Q of the latch circuit LTB is not transmitted to the line LXS[m-2]. In addition, there is conduction between the output terminal Q of the latch circuit LTB[m-1] and the line LXS[m-1], so the data DT[m-1] output from the output terminal Q of the latch circuit LTB is transmitted to the line LXS[m-1].

[0372] Between time T43 and time T44, a low-level potential is input to the line SL8[m-1] and a high-level potential is input to the line SL8[m]. As a result, the switch SW8[m-1] is turned off and the switch SW8[m] is turned on. Because there is no conduction between the output terminal Q of the latch circuit LTB[m-1] and the line LXS[m-1], the data DT[m-1] output from the output terminal Q of the latch circuit LTB is not transmitted to the line LXS[m-1]. Furthermore, because there is conduction between the output terminal Q of the latch circuit LTB[m] and the line LXS[m], the data DT[m] output from the output terminal Q of the latch circuit LTB is transmitted to the line LXS[m].

[0373] The circuit LGC operates up to time T39 in the timing chart shown in Figure 17A, and then operates as shown in the timing chart of Figure 17B, thereby allowing the data DT[1] to data DT[m] sequentially input to the circuit LGC to be sequentially output to the wirings LXS[1] to LXS[m].

[0374] In the operation example of the timing chart shown in Figure 17B, an example is shown in which each of the wirings SL8[1] to SL8[m] is sequentially turned on and data DT[1] to data DT[m] is sequentially output to the wirings LXS[1] to LXS[m]. However, the operation may also be such that a switch to be turned on is selected from the wirings SL8[1] to SL8[m] and data DT is output to the wiring selected from the wirings LXS[1] to LXS[m].

[0375] According to the above-described operation example, for example, between time T14 and time T15 in the timing chart of FIG. 8, a potential corresponding to the data DT can be supplied to any one of the wirings XCL[1] to XCL[m] of the arithmetic circuit MAC1, the arithmetic circuit MAC2, or the arithmetic circuit MAC3.

[0376] 6 included in the semiconductor device of one embodiment of the present invention may be the circuit LGC illustrated in FIG. 16A , but may have a circuit configuration modified from that of the circuit LGC illustrated in FIG. 16A depending on the situation. For example, the circuit LGC illustrated in FIG. 16A may have a configuration in which buffer circuits are provided between each of the switches SW8[1] to SW8[m] and the wirings LXS[1] to LXS[m] illustrated in FIG. 16A . The circuit LGC illustrated in FIG. 16B has a configuration in which buffer circuits BF[1] to BF[m] are provided between each of the switches SW8[1] to SW8[m] and the wirings LXS[1] to LXS[m], respectively. As illustrated in FIG. 16B, providing the buffer circuits BF[1] to BF[m] in the circuit LGC stabilizes the electric signals (potentials) output from the circuit LGC to the wirings LXS[1] to LXS[m].

[0377] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0378] (Fourth embodiment) In this embodiment, a structure of a hierarchical neural network that can perform an operation using a semiconductor device of one embodiment of the present invention will be described.

[0379] As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, for a total of three or more layers. The hierarchical neural network 100 shown in FIG. 18A is an example of such a network, and the neural network 100 has layers 1 through R (where R can be an integer equal to or greater than 4). In particular, the first layer corresponds to the input layer, the R layer corresponds to the output layer, and the other layers correspond to intermediate layers. Note that FIG. 18A illustrates only the (k-1)th layer and the kth layer (where k is an integer equal to or greater than 3 and equal to or less than R-1) as intermediate layers.

[0380] Each layer of the neural network 100 has one or more neurons. In FIG. 18A, the first layer is made up of neurons N1 (1) Neuron N p (1) (where p is an integer equal to or greater than 1), and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 (k) Neuron N n (k) (where n is an integer greater than or equal to 1), and the Rth layer has neurons N1 (R) Neuron N q (R) (where q is an integer equal to or greater than 1).

[0381] In addition, in Figure 18A, neuron N1 (1) , neuron N p (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R)In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j (k) (where j is an integer between 1 and n) is shown in the figure.

[0382] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output at each neuron. j (k) We are focusing on the following.

[0383] Figure 18B shows the k-th layer neuron N j (k) and neuron N j (k) and the signal input to neuron N j (k) 10 shows the signal output from the

[0384] Specifically, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) The output signal z1 (k-1) ~z m (k-1) But neuron N j (k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0385] The degree of signal transmission for a signal input from a neuron in the previous layer to a neuron in the next layer is determined by the connection strength (hereinafter referred to as a weighting coefficient) of the synapse connecting those neurons. In the neural network 100, the signal output from a neuron in the previous layer is multiplied by the corresponding weighting coefficient and then input to a neuron in the next layer. i (k-1) and the k-th layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the k-th layer neuron N j (k) The signal input to can be expressed by equation (4.1).

[0386]

number

[0387] That is, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) From each of these, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients (w1 (k-1) j (k) Or even w m (k-1) j (k) ) is multiplied by the k-th layer neuron N j (k) has w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) z m (k-1) is input. At this time, the k-th layer neuron Nj (k) The sum of the signals input to j (k) is expressed as equation (4.2).

[0388]

number

[0389] Also, the weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and the neuron signal z1 (k-1) ~z m (k-1) The result of the sum of products of and can be given a bias. When the bias is b, equation (4.2) can be rewritten as the following equation.

[0390]

number

[0391] Neuron N j (k) u j (k) Depending on j (k) where neuron N j (k) Output signal z from j (k) is defined as follows:

[0392]

number

[0393] The function f(u j (k)) is an activation function in a hierarchical neural network, and can be a step function, a linear ramp function, a sigmoid function, etc. The activation function can be the same for all neurons or different for each layer. In addition, the activation functions of neurons can be the same or different for each layer.

[0394] The signals, weight coefficients w, or biases b output by neurons in each layer may be analog or digital values. Digital values ​​may be, for example, binary or ternary. Values ​​with even larger bit counts may also be used. For example, in the case of analog values, activation functions such as linear ramp functions or sigmoid functions may be used. In the case of binary digital values, for example, a step function that outputs -1 or 1, or 0 or 1 may be used. Furthermore, signals output by neurons in each layer may be ternary or more. In this case, activation functions with more than three values ​​may be used, such as a step function that outputs -1, 0, or 1, or a step function that outputs 0, 1, or 2. Furthermore, for example, an activation function that outputs five values ​​may be used, such as a step function that outputs -2, -1, 0, 1, or 2. By using digital values ​​for at least one of the signals output by neurons in each layer, the weighting coefficient w, or the bias b, it is possible to reduce the circuit size, reduce power consumption, or increase the calculation speed, etc. Furthermore, by using analog values ​​for at least one of the signals output by neurons in each layer, the weighting coefficient w, or the bias b, it is possible to improve the accuracy of calculations.

[0395] When an input signal is input to the first layer (input layer), neural network 100 generates an output signal in each layer, from the first layer (input layer) to the last layer (output layer), based on the signal input from the previous layer, using equations (4.1), (4.2) (or (4.3)), and (4.4), and outputs the output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result of calculation by neural network 100.

[0396] The calculations performed in the first layer (input layer), hidden layer, and last layer (output layer) of the neural network 100 can be performed using the calculation circuits MAC1 to MAC3 described in the first and second embodiments.

[0397] In particular, when it is desired to add a bias to the result of the sum of products as in equation (4.3), the arithmetic circuit MAC2 described in the second embodiment can be used. In this case, the bias b in equation (4.3) is calculated by subtracting I from equations (2.1) and (2.2). BIAS Equivalent to [1].

[0398] The circuit XLD or the circuit SCA of the arithmetic circuits MAC1 to MAC3 described in the first and second embodiments can be applied as an example to the input layer described in this embodiment. (2) Neuron N r (2) (r is an integer equal to or greater than 1), and consider a case where a signal is sent from a neuron included in the first layer to a neuron included in the second layer. In this case, the memory cell array CA of the arithmetic circuits MAC1 to MAC3 has memory cells AM arranged in a matrix of p rows and r columns.

[0399] Neuron N in the first layer (input layer) s[1] (1) (s[1] is an integer between 1 and p) is the received signal z s[1] (1)is output to all neurons in the second layer (hidden layer). s[1] (1) By setting the potential (second data) output from the circuit XLD or the circuit SCA, the signal z output from the first layer (input layer) s[1] (1) can be input to the memory cells AM[s[1],1] to AM[s[1],r] and the memory cell AMr[s[1]] included in the memory cell array CA via the wiring XL[s[1]].

[0400] At this time, a weighting coefficient w s[1] (1) s[2] (2) is stored as the first data, and the neuron N s[2] (2) In the signal z s[1] (1) and weighting factor w s[1] (1) s[2] (2) Specifically, the current I flowing through the circuit IVTC S [s[2]] to signal z s[1] (1) and weighting factor w s[1] (1) s[2] (2) In addition, the activation function value is calculated from the result of the product sum by the circuit ACTV, and the activation function value is transmitted to the neuron N in the second layer. s[2] (2) The output signal z s[2] (2) and can be output from the wiring NIL[s[2]].

[0401] Furthermore, the arithmetic circuits MAC1 to MAC3 described in the first and second embodiments can be applied as the hidden layer. Here, a case is considered in which a signal is sent from a neuron included in the (k-1)th layer to a neuron included in the kth layer. In this case, the memory cell array CA included in the arithmetic circuits MAC1 to MAC3 is configured such that memory cells AM are arranged in a matrix of m rows and n columns.

[0402] Neuron N in the (k-1)th layer i (k-1) is the signal z i (k-1) The k-th layer neuron N1 (k) Neuron N n (k) The signal z is output. i (k-1) is the potential (second data) output from the circuit XLD, the signal z i (k-1) can be input to the memory cells AM[i,1] to AM[i,n] and the memory cell AMr[i] included in the memory cell array CA via the wiring XL[i].

[0403] At this time, a weighting coefficient w i (k-1) j (k) is stored as the first data, and the kth layer neuron N j (k) In the signal z i (k-1) and weighting factor w i (k-1) j (k) Specifically, the current I flowing through the circuit IVTC S [j] to signal z i (k-1) and weighting factor w i (k-1) j (k)In addition, the activation function value can be calculated from the result of the product sum using the circuit ACTV, and the activation function value can be transmitted to the neuron N in the kth layer. j (k) The output signal z j (k) and can be output from the wiring NIL[j].

[0404] The arithmetic circuits MAC1 to MAC3 described in the first and second embodiments can be applied to the output layer. Here, the (R-1)th layer includes a neuron N1 (R-1) Neuron N v (R-1) (v is an integer equal to or greater than 1), and consider a case where a signal is sent from a neuron included in the (R-1)th layer to a neuron included in the Rth layer. In this case, the memory cell array CA of the arithmetic circuits MAC1 to MAC3 has memory cells AM arranged in a matrix of v rows and q columns.

[0405] Neuron N in the (R-1) layer s[R-1] (R-1) (s[R-1] is an integer between 1 and v.) s[R-1] (R-1) neuron N1 in layer R (R) Neuron N q (R) The signal z is output. s[R-1] (R-1) By setting the potential (second data) output from the circuit XLD, the signal z output from the (R-1)th layer s[R-1] (R-1) can be input to the memory cells AM[s[R-1],1] to AM[s[R-1],n] and memory cell AMr[s[R-1]] included in the memory cell array CA via wiring XL[s[R-1]].

[0406] At this time, a weighting coefficient w s[R-1](R-1) s[R] (R) is stored as the first data, and the Rth layer neuron N s[R] (R) In the signal z s[R-1] (R-1) and weighting factor w s[R-1] (R-1) s[R] (R) Specifically, the current I flowing through the circuit IVTC S [s[R]] to signal z s[R-1] (R-1) and weighting factor w s[R-1] (R-1) s[R] (R) In addition, the activation function value is calculated from the result of the product sum using the circuit ACTV, and the activation function value is sent to the neuron N in the Rth layer. s[R] (R) The output signal z s[R] (R) and can be output from the wiring NIL[s[R]].

[0407] In the arithmetic circuit described in this embodiment, the number of rows of memory cells AM corresponds to the number of neurons in the previous layer. In other words, the number of rows of memory cells AM corresponds to the number of output signals of neurons in the previous layer that are input to one neuron in the next layer. In addition, in the arithmetic circuit described in this embodiment, the number of columns of memory cells AM corresponds to the number of neurons in the next layer. In other words, the number of columns of memory cells AM corresponds to the number of output signals output from neurons in the next layer. In other words, the number of rows and columns of the memory cell array of the arithmetic circuit is determined by the number of neurons in the previous layer and the next layer, so the number of rows and columns of the memory cell array can be determined and designed according to the neural network to be configured.

[0408] For example, when the arithmetic circuit MAC1 described in the first embodiment is used as the hidden layer, the weighting coefficient w i (k-1) j (k)is used as the first data, and potentials corresponding to the first data are stored in the memory cells AM of the same column, and the neuron N in the (k-1)th layer i (k-1) Output signal z from i (k-1) is used as the second data, and a potential according to the second data is supplied from the circuit XLD or the circuit SCA to the wiring XL of each row, thereby controlling the amount of current I S From signal z i (k-1) and weighting factor w i (k-1) j (k) The value of the sum of products of the activation function and the activation function corresponding to the sum of products are calculated by the ACTV circuit. j (k) The output signal z j (k) In addition, the circuit ACTV is configured to output a potential according to the value of the activation function, and the k-th layer neuron N j (k) The output signal z j (k) is input to another arithmetic circuit MAC1, the neuron N output from the (k+1)th layer in the other arithmetic circuit MAC1 s[k+1] (k+1) (where s[k+1] is an integer greater than or equal to 1 and less than or equal to the total number of neurons in the k+1th layer.) s[k+1] (k+1) can be calculated.

[0409] Specifically, the above-described calculation can be performed by using the arithmetic circuit MAC4 shown in FIG. 19. The arithmetic circuit MAC4 of FIG. 19 includes, as an example, an arithmetic circuit MAC1-1 having the same configuration as the arithmetic circuit MAC1 of FIG. 1, and an arithmetic circuit MAC1-2 having the same configuration as the arithmetic circuit MAC1 of FIG. 1 except for the circuits XLD, SCA, and SWC. The memory cell array CA of the arithmetic circuit MAC1-1 has m×n memory cells AM and m memory cells AMr arranged in a matrix, and the memory cell array CA of the arithmetic circuit MAC1-2 has n×t (t is an integer equal to or greater than 1 and represents the number of all neurons in the (k+1)th layer) memory cells AM and n memory cells AMr arranged in a matrix. The wirings NIL[1] to NIL[n] of the arithmetic circuit MAC1-1 are electrically connected to the wirings XL[1] to XL[n] of the arithmetic circuit MAC1-2, respectively.

[0410] For example, in the arithmetic circuit MAC1-1 of FIG. 19, the weight coefficient between the neuron in the (k-1)th layer and the neuron in the kth layer is stored as first data in the memory cells AM[1,1] to AM[m,n] of the memory cell array CA, and the weight coefficient between the neuron in the (k-1)th layer and the neuron in the kth layer is stored as first data in the memory cells AM[1,1] to AM[m,n] of the memory cell array CA. s[k-1] (k-1) Output signal z from s[k-1] (k-1) is used as second data, and a potential corresponding to the second data is applied from the circuit XLD or the circuit SCA to the wiring XL of each row, so that the k-th layer neuron N1 (k) Neuron N n (k) Output signal z1 (k) ~z n (k) The output signal z1 (k) ~z n (k) Each value can be expressed as a potential output from the circuit ACTV to each of the wirings NIL[1] to NIL[n].

[0411] Here, in the arithmetic circuit MAC1-2 of FIG. 19, the weight coefficient between the neuron of the kth layer and the neuron of the (k+1)th layer is held as the first data in the memory cells AM[1,1] to AM[n,t] of the memory cell array CA, and the potential supplied to the wiring XL of each row, that is, the neuron N1 of the kth layer (k) Neuron N n (k) Output signal z1 (k) ~z n (k) By using this as the second data, the (k+1)th layer neuron N1 (k+1) Neuron N t (k+1) Each output signal z1 (k+1) ~z t (k+1) can be output.

[0412] As described above, the number of rows and columns of the memory cell array CA can be determined for the arithmetic circuits MAC1 to MAC3 depending on the scale of the hierarchical neural network. Also, by using at least one of the arithmetic circuits MAC1 to MAC3 and connecting them as shown in Figure 19, it is possible to perform calculations according to the number of layers of the hierarchical neural network.

[0413] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0414] (Embodiment 5) In this embodiment, a structural example of the semiconductor device described in the above embodiment and a structural example of a transistor that can be applied to the semiconductor device described in the above embodiment will be described.

[0415] <Configuration example of semiconductor device> 20 is a cross-sectional view of any one of the arithmetic circuits MAC1 to MAC4 described in the above embodiments, illustrating a configuration in which a photoelectric conversion element is applied to the circuit SNC as a photodiode. Specifically, the semiconductor device illustrated in FIG. 20 includes a transistor 300, a transistor 500, a capacitor 600, and a photoelectric conversion element 700. FIG. 22A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 22B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 22C is a cross-sectional view of the transistor 300 in the channel width direction.

[0416] The transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. The transistor 500 has characteristics of low off-state current and a field-effect mobility that does not change even at high temperatures. By using the transistor 500 in a semiconductor device, such as a transistor included in the arithmetic circuits MAC1 to MAC4 described in the above embodiment, a semiconductor device whose operation performance is not degraded even at high temperatures can be realized. In particular, by utilizing the characteristics of low off-state current, applying the transistor 500 to the transistor Tr11 can hold a potential written to the memory cell AM, the memory cell AMr, or the like for a long time. Furthermore, by using the transistor 500 in the transistor Tr41, the transistor Tr42, or the like, a potential written to the node NS of the circuit RPC can be held for a long time. Furthermore, by using the transistor 500 in the transistor included in the switch SW1, a potential written to the first terminal of the capacitor C6 can be held for a long time. Furthermore, by using the transistor 500 in the transistor included in the switch SW2, a potential written to the first terminal of the capacitor C7 can be held for a long time.

[0417] The transistor 500 is provided above the transistor 300, for example, and the capacitor 600 is provided above the transistor 300 and the transistor 500, for example. The capacitor 600 can be a capacitor included in any of the arithmetic circuits MAC1 to MAC4 described in the above embodiment. Depending on the circuit configuration, the capacitor 600 shown in FIG. 20 is not necessarily provided.

[0418] The photoelectric conversion element 700 is provided above the capacitance element 600, for example.

[0419] The transistor 300 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 can be applied to, for example, the transistors included in the arithmetic circuits MAC1 to MAC4 described in the above embodiment. Specifically, the transistor 300 can be a transistor included in the operational amplifiers OP[1] to OP[n] included in the circuit IVTC in FIG. 5A or FIG. 5B. The transistor 300 can be, for example, transistors Tr31, Tr32[1] to Tr32[n], Tr33, Tr34, Tr35, and Tr36[1] to Tr36[n]. Note that Figure 20 shows a configuration in which the gate of the transistor 300 is electrically connected to one of the source and drain of the transistor 500 through a pair of electrodes of the capacitor 600. However, depending on the configuration of the arithmetic circuits MAC1 to MAC4, one of the source and drain of the transistor 300 may be electrically connected to one of the source and drain of the transistor 500 through a pair of electrodes of the capacitor 600, or one of the source and drain of the transistor 300 may be electrically connected to the gate of the transistor 500 through a pair of electrodes of the capacitor 600. Furthermore, each terminal of the transistor 300 may not be electrically connected to each terminal of the transistor 500 or each terminal of the capacitor 600.

[0420] Furthermore, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate) as the substrate 311.

[0421] 22C , the upper surface and the side surfaces in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this way, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 300. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300.

[0422] The transistor 300 may be either a p-channel type or an n-channel type.

[0423] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0424] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0425] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0426] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0427] 20 is just an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like. For example, when the semiconductor device is a unipolar circuit including only OS transistors, the structure of the transistor 300 may be the same as that of the transistor 500 including an oxide semiconductor, as shown in FIG. 21. The details of the transistor 500 will be described later.

[0428] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order to cover the transistor 300.

[0429] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0430] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0431] The insulator 322 may function as a planarizing film that flattens steps caused by the transistor 300 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the flatness.

[0432] The insulator 324 is preferably a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate 311, the transistor 300, or the like to a region where the transistor 500 is provided.

[0433] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0434] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0435] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0436] Conductors 328 and 330, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings. A plurality of conductors that function as plugs or wirings may be collectively denoted by the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integral. That is, a part of a conductor may function as a wiring, and a part of a conductor may function as a plug.

[0437] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0438] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 20 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0439] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0440] Note that, for example, tantalum nitride or the like is preferably used as the conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0441] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 20, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0442] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0443] Moreover, a wiring layer (not shown) may be provided on the insulator 364 and the conductor 366.

[0444] Although the above describes a wiring layer including the conductor 356 and a wiring layer including the conductor 366, the semiconductor device according to this embodiment is not limited to this. There may be one or less wiring layers similar to the wiring layer including the conductor 356, or there may be three or more wiring layers similar to the wiring layer including the conductor 356. Furthermore, there may be two or more wiring layers similar to the wiring layer including the conductor 366.

[0445] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 364. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably formed using a substance that has a barrier property against oxygen, hydrogen, and the like.

[0446] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or a region where the transistor 300 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0447] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0448] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0449] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0450] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0451] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0452] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor that has a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer that has a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0453] Above the insulator 516 is the transistor 500 .

[0454] As shown in Figures 22A and 22B, the transistor 500 has a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 arranged on the insulator 516 and the conductor 503, an insulator 522 arranged on the insulator 520, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged apart from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed therein overlapping with the conductors 542a and 542b, an oxide 530c arranged on the bottom and side surfaces of the opening, an insulator 550 arranged on the surface on which the oxide 530c is formed, and a conductor 560 arranged on the surface on which the insulator 550 is formed. In this specification and the like, the conductor 542a and the conductor 542b are collectively referred to as the conductor 542.

[0455] 22A and 22B, it is preferable that an insulator 544 be disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 include a conductor 560a disposed inside the insulator 550 and a conductor 560b disposed so as to be embedded inside the conductor 560a, as shown in FIGS. 22A and 22B, it is preferable that an insulator 574 be disposed on the insulator 580, the conductor 560, and the insulator 550.

[0456] In the following, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as the oxide 530.

[0457] Although the transistor 500 has a three-layer structure of oxides 530a, 530b, and 530c in and around a channel formation region, one embodiment of the present invention is not limited to this structure. For example, the transistor may have a single layer of oxide 530b, a two-layer structure of oxides 530b and 530a, a two-layer structure of oxides 530b and 530c, or a stacked structure of four or more layers. Although the transistor 500 has a two-layer structure, one embodiment of the present invention is not limited to this structure. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 illustrated in FIGS. 20, 22A, and 22B is merely an example, and the transistor is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0458] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangements of the conductors 560, 542a, and 542b are selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of semiconductor devices.

[0459] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0460] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 above 0 V and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to when a negative potential is not applied.

[0461] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered. In this specification and the like, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0462] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inward. Note that although the transistor 500 has a structure in which the conductor 503a and the conductor 503b are stacked, one embodiment of the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0463] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate). Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0464] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and its conductivity from decreasing.

[0465] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, when the conductivity of the wiring can be maintained at a high level, the conductor 503a is not necessarily provided. While the conductor 503b is illustrated as a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the above-mentioned conductive material.

[0466] The insulators 520, 522, and 524 function as a second gate insulating film.

[0467] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. That is, an excess oxygen region is preferably formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.

[0468] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as an insulator having an excess oxygen region. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0469] Alternatively, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the VOH bond, in other words, "V O H→V O +H" reaction occurs, resulting in dehydrogenation. Some of the generated hydrogen may combine with oxygen to form HO and be removed from the oxide 530 or the insulator near the oxide 530. Some of the hydrogen may also be diffused or captured (also called gettered) in the conductor 542a and the conductor 542b.

[0470] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. The microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0471] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0472] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, OFurthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0473] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (preferably making the oxygen less permeable).

[0474] The insulator 522 preferably has a function of suppressing diffusion of oxygen, impurities, and the like, which prevents oxygen contained in the oxide 530 from diffusing toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524, the oxide 530, and the like can be suppressed.

[0475] The insulator 522 is preferably a single-layer or multi-layer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulating film makes it possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0476] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., is difficult for oxygen to permeate), is preferably used. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0477] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0478] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable layered structure with a high dielectric constant.

[0479] 22A and 22B illustrate the insulator 520, the insulator 522, and the insulator 524 as the second gate insulating film having a three-layer stack structure, the second gate insulating film may have a single-layer, two-layer, or four or more-layer stack structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0480] In the transistor 500, a metal oxide functioning as an oxide semiconductor is preferably used for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used for the oxide 530. In particular, the In-M-Zn oxide that can be used for the oxide 530 is preferably a C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) or a Cloud-Aligned Composite Oxide Semiconductor (CAC-OS). Alternatively, an In-Ga oxide, an In-Zn oxide, an In oxide, or the like may be used for the oxide 530.

[0481] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. To lower the carrier concentration of a metal oxide, the impurity concentration in the metal oxide should be lowered to lower the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0482] In particular, hydrogen contained in the metal oxide reacts with oxygen that bonds with the metal atom to form water, which can cause oxygen vacancies in the metal oxide. When hydrogen enters an oxygen vacancy in the oxide 530, the oxygen vacancy and hydrogen bond to form V. O May form H. V OH functions as a donor and may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen, which is bonded to a metal atom, to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, since hydrogen in a metal oxide is easily moved by stresses such as heat and an electric field, the reliability of the transistor may be reduced if the metal oxide contains a large amount of hydrogen. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain metal oxides with sufficiently reduced H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment), and to supply oxygen to the metal oxide to compensate for oxygen deficiencies (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be achieved.

[0483] Defects in which hydrogen has entered oxygen vacancies can function as donors in metal oxides. However, it is difficult to quantitatively evaluate such defects. Therefore, metal oxides are sometimes evaluated using carrier concentration rather than donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of metal oxides, rather than donor concentration. In other words, the "carrier concentration" described in this specification and the like may sometimes be rephrased as "donor concentration."

[0484] Therefore, when a metal oxide is used for the oxide 530, it is preferable that the hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is set to 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0485] When a metal oxide is used for the oxide 530, the metal oxide has a wide band gap and is an intrinsic (also referred to as I-type) or substantially intrinsic semiconductor. The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably, it is less than 1 x 10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0486] Furthermore, when a metal oxide is used for the oxide 530, contact between the conductors 542a and 542b and the oxide 530 may cause oxygen in the oxide 530 to diffuse into the conductors 542a and 542b, resulting in the oxidation of the conductors 542a and 542b. The oxidation of the conductors 542a and 542b is likely to result in a decrease in the conductivity of the conductors 542a and 542b. The diffusion of oxygen in the oxide 530 to the conductors 542a and 542b can be rephrased as the conductors 542a and 542b absorbing the oxygen in the oxide 530.

[0487] Furthermore, oxygen in the oxide 530 diffuses into the conductor 542a and the conductor 542b, which may form a heterogeneous layer between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. Since the heterogeneous layer contains more oxygen than the conductor 542a and the conductor 542b, it is presumed that the heterogeneous layer has insulating properties. In this case, the three-layer structure of the conductor 542a or the conductor 542b, the heterogeneous layer, and the oxide 530b can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and may be referred to as a metal-insulator-semiconductor (MIS) structure or a diode junction structure based on the MIS structure.

[0488] Note that the above-mentioned different layer is not limited to being formed between the conductor 542a and the conductor 542b and the oxide 530b, and for example, the different layer may be formed between the conductor 542a and the conductor 542b and the oxide 530c.

[0489] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0490] The oxide 530 has the oxide 530a below the oxide 530b, which can prevent impurities from diffusing from structures formed below the oxide 530a to the oxide 530b. Also, the oxide 530 has the oxide 530c on the oxide 530b, which can prevent impurities from diffusing from structures formed above the oxide 530c to the oxide 530b.

[0491] The oxide 530 preferably has a stacked structure made up of multiple oxide layers with different atomic ratios of the metal atoms. Specifically, the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. The atomic ratio of the element M to In in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. The atomic ratio of In to M in the metal oxide used for the oxide 530b is preferably greater than the atomic ratio of In to M in the metal oxide used for the oxide 530a. The oxide 530c can be made up of the same metal oxide as that used for the oxide 530a or the oxide 530b.

[0492] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or 1:1:0.5. Oxide 530b may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or 1:1:1. Oxide 530c may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 and an atomic ratio of Ga to Zn of Ga:Zn=2:1 or Ga:Zn=2:5. Specific examples of the oxide 530c having a layered structure include layered structures in which the atomic ratios of In, Ga, and Zn are In:Ga:Zn=4:2:3 and In:Ga:Zn=1:3:4, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:1 and In:Ga:Zn=4:2:3, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:5 and In:Ga:Zn=4:2:3, and layered structures in which gallium oxide and In, Ga, and Zn are In:Ga:Zn=4:2:3.

[0493] Furthermore, for example, when the atomic ratio of In to element M in the metal oxide used for oxide 530a is smaller than the atomic ratio of In to element M in the metal oxide used for oxide 530b, an In-Ga-Zn oxide having a composition in which the atomic ratio of In to Ga to Zn is In:Ga:Zn=5:1:6 or thereabouts, In:Ga:Zn=5:1:3 or thereabouts, or In:Ga:Zn=10:1:3 or thereabouts, can be used as oxide 530b.

[0494] In addition to the compositions described above, oxide 530b may be a metal oxide having a composition of In:Zn=2:1, a composition of In:Zn=5:1, a composition of In:Zn=10:1, or a composition close to any one of these.

[0495] It is preferable to combine these oxides 530a, 530b, and 530c so that the atomic ratios satisfy the above relationship. For example, it is preferable that oxides 530a and 530c are metal oxides having a composition of In:Ga:Zn=1:3:4 or a composition close to that, and oxide 530b is a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition close to that. Note that the above compositions refer to the atomic ratios in the oxide formed on the substrate or in the sputtering target. Furthermore, increasing the In ratio in the composition of oxide 530b is preferable because it can increase the on-state current or field-effect mobility of the transistor.

[0496] The conduction band minimum energy of the oxide 530a and the oxide 530c is preferably higher than that of the oxide 530b. In other words, the electron affinity of the oxide 530a and the oxide 530c is preferably smaller than that of the oxide 530b.

[0497] Here, the energy level of the conduction band minimum changes gradually at the junction between the oxides 530a, 530b, and 530c. In other words, the energy level of the conduction band minimum at the junction between the oxides 530a, 530b, and 530c changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layers formed at the interface between the oxides 530a and 530b and at the interface between the oxides 530b and 530c.

[0498] Specifically, when the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and the oxide 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0499] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a and the oxide 530c as described above, the defect state density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0500] Conductors 542a and 542b, which function as a source electrode and a drain electrode, are provided on oxide 530b. Conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0501] 22A and 22B, the conductor 542a and the conductor 542b are shown as single-layer structures, but they may also have a stacked structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0502] Further, there are three-layer structures in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0503] 22A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0504] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0505] The insulator 544 is provided to cover the conductors 542a and 542b and suppresses oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided to cover the side surfaces of the oxide 530 and the insulator 524 and to be in contact with the insulator 522.

[0506] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0507] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in a later process. Note that the insulator 544 is not an essential component if the conductors 542a and 542b are made of oxidation-resistant materials or if their conductivity does not decrease significantly even when they absorb oxygen. The insulator 544 may be designed appropriately depending on the desired transistor characteristics.

[0508] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing to the oxide 530b through the oxide 530c and the insulator 550. The insulator 544 can also prevent the conductor 560 from being oxidized by excess oxygen contained in the insulator 580.

[0509] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably disposed in contact with the inside (top surface and side surface) of the oxide 530c. The insulator 550 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0510] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0511] By providing the insulator 550, which releases oxygen upon heating, in contact with the top surface of the oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Similar to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably 1 nm to 20 nm.

[0512] Furthermore, a metal oxide may be provided between the insulator 550 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0513] The insulator 550 may have a stacked structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Therefore, by using a stacked structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a stacked structure that is thermally stable and has a high dielectric constant can be achieved.

[0514] The conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 22A and 22B, but may have a single-layer structure or a stacked structure of three or more layers.

[0515] The conductor 560a is preferably made of a conductive material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and the like), and copper atoms. Alternatively, a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) is preferably used. The conductor 560a has the function of suppressing the diffusion of oxygen, which can suppress the oxidation of the conductor 560b due to oxygen contained in the insulator 550 and a decrease in conductivity. Examples of conductive materials that suppress the diffusion of oxygen include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Alternatively, the conductor 560a can be made of an oxide semiconductor that can be used for the oxide 530. In this case, the conductor 560b can be formed by sputtering to reduce the electrical resistance of the conductor 560a, thereby making it a conductor. This can be referred to as an OC (Oxide Conductor) electrode.

[0516] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0517] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of excess oxygen regions in a later step.

[0518] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580, from which oxygen is released by heating, in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0519] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0520] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0521] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 550. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 550 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0522] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0523] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0524] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0525] Furthermore, the conductor 540a and the conductor 540b are placed in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductor 540a and the conductor 540b are provided opposite each other with the conductor 560 interposed therebetween. The conductor 540a and the conductor 540b have the same structure as the conductor 546 and the conductor 548, which will be described later.

[0526] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0527] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0528] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0529] Furthermore, conductors 546, conductors 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0530] The conductor 546 and the conductor 548 function as a plug or a wiring that connects to the capacitor 600, the transistor 500, or the transistor 300. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0531] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be collectively surrounded by an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, it is preferable to form an opening that reaches the insulator 514 or the insulator 522 and form the insulator with high barrier properties in contact with the insulator 514 or the insulator 522, because this can serve as part of the manufacturing process of the transistor 500. For example, the insulator with high barrier properties against hydrogen or water may be made of a material similar to that of the insulator 522.

[0532] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0533] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0534] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), or the like can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.

[0535] 20, the conductor 612 and the conductor 610 are shown to have a single-layer structure, but are not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0536] The conductor 620 is provided to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. Furthermore, when the conductor 620 is formed simultaneously with other structures such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0537] An insulator 650 is provided over the conductor 620 and the insulator 630. The insulator 650 can be provided using a material similar to that of the insulator 320. The insulator 650 may also function as a planarizing film that covers the uneven shape underneath.

[0538] By using this structure, in a semiconductor device including a transistor having an oxide semiconductor, fluctuation in electrical characteristics can be suppressed and reliability can be improved, or miniaturization or high integration can be achieved in a semiconductor device including a transistor having an oxide semiconductor.

[0539] Next, another example of the structure of an OS transistor shown in FIGS. 20 and 21 will be described.

[0540] 23A and 23B illustrate modifications of the transistor 500 illustrated in FIGS. 22A and 22B. FIG. 23A is a cross-sectional view of the transistor 500 in the channel length direction, and FIG. 23B is a cross-sectional view of the transistor 500 in the channel width direction. Note that the structures illustrated in FIGS. 23A and 23B can also be applied to other transistors included in the semiconductor device of one embodiment of the present invention, such as the transistor 300.

[0541] 23A and 23B differs from the transistor 500 shown in FIGS. 22A and 22B in that the transistor 500 includes an insulator 402 and an insulator 404. The transistor 500 also differs from the transistor 500 shown in FIGS. 22A and 22B in that the insulator 552 is provided in contact with the side surface of the conductor 540a and the insulator 552 is provided in contact with the side surface of the conductor 540b. The transistor 500 also differs from the transistor 500 shown in FIGS. 22A and 22B in that the insulator 520 is not provided.

[0542] 23A and 23B, the insulator 402 is provided over the insulator 512. The insulator 404 is provided over the insulator 574 and the insulator 402.

[0543] 23A and 23B , the transistor 500 includes the insulators 514, 516, 522, 524, 544, 580, and 574, and the insulator 404 covers these. That is, the insulator 404 is in contact with the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 524, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the top surface of the insulator 402. As a result, the oxide 530 and the like are isolated from the outside by the insulators 404 and 402.

[0544] The insulators 402 and 404 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of a hydrogen atom and a hydrogen molecule) or water molecules. For example, silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties, are preferably used for the insulators 402 and 404. This can suppress diffusion of hydrogen and the like into the oxide 530, thereby suppressing deterioration in the characteristics of the transistor 500. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0545] The insulator 552 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably formed using an insulator with high hydrogen barrier properties, such as silicon nitride, aluminum oxide, or silicon nitride oxide. Silicon nitride is particularly suitable for use as the insulator 552 because it has high hydrogen barrier properties. Using a material with high hydrogen barrier properties for the insulator 552 can suppress diffusion of impurities such as water or hydrogen from the insulator 580 or the like to the oxide 530 through the conductors 540a and 540b. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b. Thus, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0546] 24 is a cross-sectional view showing an example of the configuration of a semiconductor device in which the transistor 500 and the transistor 300 have the configurations shown in FIGS. 23A and 23B. An insulator 552 is provided on the side surface of the conductor 546.

[0547] The transistor 500 shown in FIGS. 23A and 23B may have a different configuration depending on the situation. For example, the transistor 500 shown in FIGS. 23A and 23B may be modified to the transistor shown in FIGS. 25A and 25B as a modified example. FIG. 25A is a cross-sectional view of the transistor in the channel length direction, and FIG. 25B is a cross-sectional view of the transistor in the channel width direction. The transistor shown in FIGS. 25A and 25B differs from the transistor shown in FIGS. 23A and 23B in that the oxide 530c has a two-layer structure of oxides 530c1 and 530c2.

[0548] The oxide 530c1 contacts the top surface of the insulator 524, the side surface of the oxide 530a, the top surface and side surface of the oxide 530b, the side surfaces of the conductors 542a and 542b, the side surface of the insulator 544, and the side surface of the insulator 580. The oxide 530c2 contacts the insulator 550.

[0549] Oxide 530c1 can be, for example, an In-Zn oxide. Oxide 530c2 can be made of the same material as that used for oxide 530c when oxide 530c has a single-layer structure. For example, oxide 530c2 can be made of a metal oxide with an atomic ratio of In:Ga:Zn=1:3:4, Ga:Zn=2:1, or Ga:Zn=2:5.

[0550] By forming the oxide 530c as a two-layer structure of the oxide 530c1 and the oxide 530c2, the on-state current of the transistor can be increased compared to when the oxide 530c has a single-layer structure. Therefore, the transistor can be used as, for example, a power MOS transistor. The oxide 530c of the transistor having the configuration shown in FIGS. 22A and 22B can also have a two-layer structure of the oxide 530c1 and the oxide 530c2.

[0551] 25A and 25B can be applied to, for example, the transistor 300 illustrated in FIGS. 20 and 21. As described above, the transistor 300 can be applied to the semiconductor device described in the above embodiment, such as the transistors included in the arithmetic circuits MAC1 to MAC4 described in the above embodiment. Note that the transistors illustrated in FIGS. 25A and 25B can also be applied to transistors other than the transistor 300 and the transistor 500 included in the semiconductor device of one embodiment of the present invention.

[0552] 26 is a cross-sectional view illustrating a structural example of a semiconductor device in which the transistor 500 has the transistor structure illustrated in FIG. 22A and the transistor 300 has the transistor structure illustrated in FIG. 25A. Note that, similar to FIG. 24, an insulator 552 is provided on the side surface of the conductor 546. As illustrated in FIG. 26, in the semiconductor device of one embodiment of the present invention, the transistors 300 and 500 are both OS transistors, but the transistors 300 and 500 can have different structures.

[0553] Next, a capacitive element that can be applied to the semiconductor devices of FIGS. 20, 21, 24, and 26 will be described.

[0554] Fig. 27 shows a capacitive element 600A as an example of the capacitive element 600 that can be applied to the semiconductor devices shown in Fig. 20, Fig. 21, Fig. 24, and Fig. 26. Fig. 27A is a top view of the capacitive element 600A, Fig. 27B is a perspective view showing a cross section of the capacitive element 600A taken along dashed dotted line L3-L4, and Fig. 27C is a perspective view showing a cross section of the capacitive element 600A taken along dashed dotted line W3-L4.

[0555] The conductor 610 functions as one of a pair of electrodes of the capacitor 600A, and the conductor 620 functions as the other of the pair of electrodes of the capacitor 600A. The insulator 630 functions as a dielectric sandwiched between the pair of electrodes.

[0556] The insulator 630 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, zirconium oxide, or the like, and can be formed as a stacked layer or a single layer.

[0557] In this specification, hafnium oxynitride refers to a material whose composition contains more oxygen than nitrogen, and hafnium nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0558] Furthermore, for example, a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material may be used for the insulator 630. With this configuration, the capacitive element 600A can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the insulator with high dielectric strength improves the dielectric strength, thereby suppressing electrostatic breakdown of the capacitive element 600A.

[0559] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0560] Alternatively, the insulator 630 may be a single layer or a stack of insulators containing high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO), or (Ba,Sr)TiO (BST). For example, when the insulator 630 is a stack, a three-layer stack of zirconium oxide, aluminum oxide, and zirconium oxide may be used, or a four-layer stack of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide may be used. Alternatively, the insulator 630 may be a compound containing hafnium and zirconium. As semiconductor devices become smaller and more highly integrated, thinner dielectric films used in gate insulators and capacitors may cause problems such as leakage current in transistors and capacitors. By using high-k materials for the gate insulator and the insulator that functions as the dielectric used in the capacitor element, it is possible to reduce the gate potential during transistor operation and ensure the capacitance of the capacitor element while maintaining the physical film thickness.

[0561] The capacitor 600 is electrically connected to the conductor 546 and the conductor 548 below the conductor 610. The conductors 546 and 548 function as plugs or wiring for connecting to other circuit elements. In addition, in FIGS. 27A to 27C, the conductors 546 and 548 are collectively referred to as the conductor 540.

[0562] Also, in order to clarify the illustration, Figure 27 omits the insulator 586 in which the conductors 546 and 548 are embedded, and the insulator 650 covering the conductor 620 and the insulator 630.

[0563] 20, 21, 24, 26, 27A, 27B, and 27C are planar capacitors, but the shape of the capacitor is not limited to this. For example, the capacitor 600 may be a cylindrical capacitor 600B shown in FIGS. 28A to 28C.

[0564] 28A is a top view of the capacitive element 600B, FIG. 28B is a cross-sectional view of the capacitive element 600B taken along the dashed dotted line L3-L4, and FIG. 28C is a perspective view showing the cross-section of the capacitive element 600B taken along the dashed dotted line W3-L4.

[0565] In Figure 28B, the capacitor element 600B has an insulator 631 on an insulator 586 in which a conductor 540 is embedded, an insulator 651 having an opening, a conductor 610 that functions as one of a pair of electrodes, and a conductor 620 that functions as the other of the pair of electrodes.

[0566] Also, in FIG. 28C, for clarity, insulator 586, insulator 650, and insulator 651 are omitted.

[0567] The insulator 631 can be formed using, for example, a material similar to that of the insulator 586.

[0568] Furthermore, a conductor 611 is embedded in the insulator 631 so as to be electrically connected to the conductor 540. The conductor 611 can be made of the same material as the conductors 330 and 518, for example.

[0569] The insulator 651 can be formed using, for example, a material similar to that of the insulator 586.

[0570] As described above, the insulator 651 has an opening that overlaps with the conductor 611.

[0571] The conductor 610 is formed on the bottom and side surfaces of the opening. That is, the conductor 610 overlaps with the conductor 611 and is electrically connected to the conductor 611.

[0572] The conductor 610 is formed by forming an opening in the insulator 651 by etching or the like, and then depositing the conductor 610 by sputtering, ALD, or the like. Thereafter, the conductor 610 deposited on the insulator 651 may be removed by chemical mechanical polishing (CMP) or the like, leaving the conductor 610 deposited in the opening.

[0573] The insulator 630 is located on the insulator 651 and on the surface on which the conductor 610 is formed. Note that the insulator 630 functions as a dielectric sandwiched between a pair of electrodes in the capacitor element.

[0574] The conductor 620 is formed on the insulator 630 so that the opening of the insulator 651 is filled.

[0575] The insulator 650 is formed to cover the insulator 630 and the conductor 620 .

[0576] The cylindrical capacitive element 600B shown in FIG. 28 can have a higher capacitance value than the planar capacitive element 600A.

[0577] Next, the photoelectric conversion element 700 provided above the capacitance element 600 in FIGS. 20, 21, 24, and 26 will be described.

[0578] The photoelectric conversion element 700 includes, for example, a layer 767a, a layer 767b, a layer 767c, a layer 767d, and a layer 767e.

[0579] 20, 21, 24, and 26 is an example of an organic photoconductive film, in which layer 767a is a lower electrode, layer 767e is a light-transmitting upper electrode, and layers 767b, 767c, and 767d correspond to a photoelectric conversion unit. Note that, instead of photoelectric conversion element 700 shown in FIGS. 20, 21, 24, and 26, for example, a pn junction photodiode, an avalanche photodiode, or the like may be used.

[0580] The layer 767a serving as the lower electrode can be either an anode or a cathode, and the layer 767b serving as the upper electrode can be either an anode or a cathode. In this embodiment, the layer 767a serves as the cathode, and the layer 767b serves as the anode.

[0581] Layer 767a is preferably a low-resistance metal layer, etc. Specifically, layer 767a may be made of, for example, aluminum, titanium, tungsten, tantalum, silver, or a laminate of these.

[0582] The layer 767e is preferably formed using, for example, a conductive layer that has a high light-transmitting property to visible light. Specifically, the layer 767e can be formed using, for example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like. Note that the layer 767e may be omitted.

[0583] One of the layers 767b and 767d of the photoelectric conversion portion can be a hole transport layer, and the other can be an electron transport layer. The layer 767c can be a photoelectric conversion layer.

[0584] For example, molybdenum oxide can be used as the hole transport layer. For example, C 60 , C 70 or derivatives thereof can be used.

[0585] The photoelectric conversion layer may be a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor.

[0586] 20, 21, 24, and 26, the insulator 751 is provided over the insulator 650, and the layer 767a is provided over the insulator 751. The insulator 752 is provided over the insulator 751 and the layer 767a. The layer 767b is provided over the insulator 752 and the layer 767a.

[0587] Moreover, a layer 767c, a layer 767d, a layer 767e, and an insulator 753 are stacked in this order on the layer 767b.

[0588] The insulator 751 functions as an interlayer insulating film, for example. For the insulator 751, an insulator having a barrier property against hydrogen, like the insulator 324, is preferably used. Using an insulator having a barrier property against hydrogen for the insulator 751 can suppress diffusion of hydrogen into the transistor 500. Therefore, for example, a material that can be used for the insulator 324 can be used for the insulator 751.

[0589] The insulator 752 functions as an element isolation layer, for example. Although not shown, the insulator 752 is provided to prevent a short circuit with another photoelectric conversion element located adjacent to the insulator 752. For example, an organic insulator or the like is preferably used as the insulator 752.

[0590] For example, the insulator 753 functions as a light-transmitting planarization film. The insulator 753 can be formed using a material such as silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride.

[0591] Above the insulator 753, for example, a light-shielding layer 771, an optical conversion layer 772, and a microlens array 773 are provided.

[0592] The light-shielding layer 771 provided on the insulator 753 can prevent light from flowing into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 771. The metal layer may be stacked with a dielectric film that functions as an anti-reflection film.

[0593] A color filter can be used for the optical conversion layer 772 provided on the insulator 753 and the light-shielding layer 771. A color image can be obtained by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filter for each pixel.

[0594] Furthermore, if a wavelength cut filter is used in the optical conversion layer 772, an imaging device that can obtain images in various wavelength regions can be obtained.

[0595] For example, an infrared imaging device can be formed by using a filter that blocks light having a wavelength shorter than that of visible light in the optical conversion layer 772. Alternatively, a far-infrared imaging device can be formed by using a filter that blocks light having a wavelength shorter than that of near-infrared light in the optical conversion layer 772. Alternatively, an ultraviolet imaging device can be formed by using a filter that blocks light having a wavelength longer than that of visible light in the optical conversion layer 772.

[0596] Furthermore, if a scintillator is used for the optical conversion layer 772, an imaging device can be provided that obtains an image that visualizes the intensity of radiation, such as for use in an X-ray imaging device. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting the light with the photoelectric conversion element 700. An imaging device having such a configuration may also be used for a radiation detector or the like.

[0597] Scintillators contain a substance that, when irradiated with radiation such as X-rays or gamma rays, absorbs the energy and emits visible light, ultraviolet light, etc. For example, Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used.

[0598] A microlens array 773 is provided on the light-shielding layer 771 and the optical conversion layer 772. Light passing through each lens of the microlens array 773 passes through the optical conversion layer 772 directly below and is irradiated onto the photoelectric conversion element 700. By providing the microlens array 773, concentrated light can be incident on the photoelectric conversion element 700, thereby enabling efficient photoelectric conversion. The microlens array 773 is preferably formed from a resin or glass that is highly translucent to visible light.

[0599] 20, 21, 24, and 26 show the structures of the semiconductor device in which the photoelectric conversion element 700 using an organic photoconductive film is provided above the transistor 300 and the transistor 500. However, the semiconductor device of one embodiment of the present invention is not limited to this. For example, the semiconductor device of one embodiment of the present invention may have a back-illuminated pn junction photoelectric conversion element instead of the photoelectric conversion element 700.

[0600] 29 illustrates a configuration example of a semiconductor device in which a back-illuminated pn junction photoelectric conversion element 700A is provided above the transistor 300 and the transistor 500. The semiconductor device illustrated in FIG. 29 has a configuration in which a structure SA having the photoelectric conversion element 700A is attached above a substrate 311 on which the transistor 300, the transistor 500, and the capacitor 600 are provided.

[0601] The structural body SA includes a light-shielding layer 771, an optical conversion layer 772, and a microlens array 773, and the above-mentioned explanations should be referred to for the explanations of these.

[0602] Photoelectric conversion element 700A is a pn junction photodiode formed on a silicon substrate, and has layer 765b corresponding to a p-type region and layer 765a corresponding to an n-type region. Photoelectric conversion element 700A is a buried photodiode, and a thin p-type region (part of layer 765b) provided on the surface side (current extraction side) of layer 765a can suppress dark current and reduce noise.

[0603] The insulator 701, the conductor 741, and the conductor 742 function as bonding layers. The insulator 754 functions as an interlayer insulating film and a planarizing film. The insulator 755 functions as an element isolation layer. The insulator 756 functions to suppress the outflow of carriers.

[0604] Grooves separating pixels are provided in the silicon substrate, and insulators 756 are provided on the upper surface of the silicon substrate and in the grooves. By providing the insulators 756, it is possible to prevent carriers generated in the photoelectric conversion element 700A from flowing into adjacent pixels. The insulators 756 also have the function of suppressing the intrusion of stray light. Therefore, the insulators 756 can suppress color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulators 756.

[0605] The element isolation layer can be formed by using a LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed by using a STI (Shallow Trench Isolation) method or the like. For example, the insulator 756 may be an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic. The insulator 756 may have a multilayer structure.

[0606] Layer 765a (n-type region, corresponding to the cathode) of photoelectric conversion element 700A is electrically connected to conductor 741. Layer 765b (p-type region, corresponding to the anode) is electrically connected to conductor 742. Conductor 741 and conductor 742 have regions embedded in insulator 701. Furthermore, the surfaces of insulator 701, conductor 741, and conductor 742 are flattened so that they are all at the same height.

[0607] An insulator 691 and an insulator 692 are stacked in this order above the insulator 650. Openings are provided in the insulators 691 and 692, and a conductor 743 is formed to fill the openings.

[0608] As the insulator 691, for example, a material that can be used for the insulator 751 can be used.

[0609] As the insulator 692, for example, a material that can be used for the insulator 650 can be used.

[0610] The insulators 693 and 701 each function as part of the bonding layer. The conductors 741, 742, and 743 each also function as part of the bonding layer.

[0611] For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulators 693 and 701. In particular, in order to bond the insulators 693 and 701 to each other, the insulators 693 and 701 are preferably made of the same component.

[0612] For example, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold can be used for the conductor 741, the conductor 742, and the conductor 743. In particular, to easily bond the conductor 741 and the conductor 743, and the conductor 742 and the conductor 743, it is preferable to use copper, aluminum, tungsten, or gold.

[0613] Note that the conductor 741, the conductor 742, and the conductor 743 may each have a multilayer structure including multiple layers. For example, a first conductor may be formed on a side surface of an opening where the conductor 741, the conductor 742, or the conductor 743 is to be provided, and then a second conductor may be formed to fill the opening. The first conductor may be, for example, a conductor having a barrier property against hydrogen, such as tantalum nitride, and the second conductor may be, for example, tungsten, which has high conductivity.

[0614] In a pre-process for bonding the bonding layer on the substrate 311 side to the bonding layer on the structural body SA side, the surfaces of the insulator 693 and the conductor 743 on the substrate 311 side are planarized so that they are at the same height. Similarly, the surfaces of the insulator 701, the conductor 741, and the conductor 742 on the structural body SA side are planarized so that they are at the same height.

[0615] In the bonding process, when bonding the insulator 693 and the insulator 701, that is, bonding insulating layers together, a hydrophilic bonding method can be used in which high flatness is achieved by polishing or the like, then surfaces that have been hydrophilically treated with oxygen plasma or the like are brought into contact with each other to temporarily bond them, and then the final bonding is performed by dehydrating them through heat treatment. The hydrophilic bonding method also produces bonds at the atomic level, so it can obtain mechanically excellent bonds.

[0616] Furthermore, for example, when bonding conductors 741 and 743, and conductors 742 and 743, that is, when bonding conductors together, a surface activated bonding method can be used in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and cleaned and activated surfaces are brought into contact and bonded. Alternatively, a diffusion bonding method can be used in which surfaces are bonded using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0617] By performing the above-described bonding process, the conductor 743 on the substrate 311 side can be electrically connected to the conductors 741 and 742 on the structure SA side. Also, a connection having sufficient mechanical strength can be obtained between the insulator 693 on the substrate 311 side and the insulator 701 on the structure SA side.

[0618] When bonding the substrate 311 and the structure SA, since an insulating layer and a metal layer are mixed on each bonding surface, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0619] For example, a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. Alternatively, the surface of the metal layer may be made of a resistant metal such as gold and then subjected to a hydrophilic treatment. Note that bonding methods other than those described above may also be used.

[0620] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0621] (Sixth embodiment) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0622] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0623] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 30A. Fig. 30A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0624] As shown in FIG. 30A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0625] The structure within the bold frame in Figure 30A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as a structure that is completely different from the energetically unstable "Amorphous" and "Crystal."

[0626] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 30B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." (The vertical axis represents intensity in arbitrary units (au).) The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 30B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 30B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 30B is 500 nm.

[0627] As shown in Figure 30B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 30B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0628] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 30C. Figure 30C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 30C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In nanobeam electron diffraction, electron diffraction is performed using a probe diameter of 1 nm.

[0629] As shown in FIG. 30C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0630] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from those shown in FIG. 30A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0631] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0632] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0633] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0634] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0635] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0636] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0637] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0638] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0639] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the decrease in electron mobility due to crystal grain boundaries is unlikely to occur in CAAC-OS. Furthermore, since the crystallinity of oxide semiconductors can be reduced by the inclusion of impurities or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using CAAC-OS for OS transistors enables greater flexibility in the manufacturing process.

[0640] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of these microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0641] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0642] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0643] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0644] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0645] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0646] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0647] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0648] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0649] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0650] Oxide semiconductors have a variety of structures and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0651] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0652] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0653] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0654] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0655] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0656] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0657] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0658] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by SIMS) are calculated as follows: 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0659] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0660] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0661] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0662] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0663] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0664] (Embodiment 7) This embodiment mode will describe an example of a semiconductor wafer on which the semiconductor device or the like shown in the above embodiment mode is formed, and an electronic component in which the semiconductor device is incorporated.

[0665] <Semiconductor wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. 31A.

[0666] 31A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of wafer 4801. Note that on the upper surface of wafer 4801, a portion where circuit portions 4802 are not present is spacing 4803, which is an area for dicing.

[0667] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0668] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0669] By performing a dicing process, chips 4800a as shown in FIG. 31B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. Note that spacing 4803a is preferably made as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0670] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Figure 31A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the device for manufacturing the element.

[0671] <Electronic components> FIG. 31C shows a perspective view of electronic component 4700 and a substrate (mounting substrate 4704) on which electronic component 4700 is mounted. Electronic component 4700 shown in FIG. 31C has chip 4800a in mold 4711. Note that, as shown in FIG. 31C, chip 4800a may have a configuration in which circuit section 4802 is stacked. FIG. 31C omits a portion to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a by wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. Mounting substrate 4704 is completed by combining a plurality of such electronic components and electrically connecting them on printed circuit board 4702.

[0672] 31D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0673] The electronic component 4730 includes a semiconductor device 4710. The semiconductor device 4710 can be, for example, any of the semiconductor devices described in the above embodiments or a high bandwidth memory (HBM). The semiconductor device 4735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0674] A ceramic substrate, a plastic substrate, a glass epoxy...

Claims

[Claim 1] a first cell, a second cell, a first circuit, a second circuit, a third circuit, a fourth circuit, a first wiring, a second wiring, and a third wiring; the first cell has a first capacity; the second cell has a second capacity; the third circuit includes a sensor; the first cell is electrically connected to the first circuit via the first wiring; a first terminal of the first capacitor of the first cell is electrically connected to the third wiring; the second cell is electrically connected to the first circuit via the second wiring; a first terminal of the second capacitor of the second cell is electrically connected to the third wiring; the second circuit is electrically connected to the fourth circuit; the third circuit is electrically connected to the fourth circuit; the third wiring is electrically connected to the fourth circuit, the fourth circuit has a function of setting one of a conductive state and a non-conductive state between the second circuit and the third wiring, and a function of setting the other of a conductive state and a non-conductive state between the third circuit and the third wiring, The first cell is a function of holding a first potential at a second terminal of the first capacitor when a first input potential is input to the third wiring; a function of causing a current corresponding to the first potential to flow between the first cell and the first wiring; when the first input potential of the third wiring changes to a second input potential, the first potential held at the second terminal of the first capacitor changes to a second potential, and a current corresponding to the second potential flows between the first cell and the first wiring; The second cell is a function of holding a third potential at a second terminal of the second capacitor when the first input potential is input to the third wiring; a function of causing a current corresponding to the third potential to flow between the second cell and the second wiring; a function of changing the third potential held at the second terminal of the second capacitor to a fourth potential when the first input potential of the third wiring changes to the second input potential, and causing a current corresponding to the fourth potential to flow between the second cell and the second wiring; When the potential of the third wiring is the first input potential, a first current flows between the first circuit and the first wiring, and a second current flows between the first circuit and the second wiring, When the potential of the third wiring is the second input potential, a third current flows between the first circuit and the first wiring, and a fourth current flows between the first circuit and the second wiring, The first circuit supplies the first current I to the first wiring when the potential of the third wiring is the second input potential. １ a fifth circuit having a function of causing the second current amount I to flow in the first wiring when the potential of the third wiring is the second input potential; ２ and a sixth circuit having a function of passing The first circuit generates the third current I when the potential of the third wiring is the second input potential. ３ and the amount of the fourth current I ４ and obtain I １ -I ２ -I ３ +I ４ and generating a current in an amount of The second circuit is generating a fifth potential; a function of generating a sixth potential according to internal data input to the second circuit; a function of outputting the fifth potential as the first input potential or the sixth potential as the second input potential to the fourth circuit, The third circuit is generating a seventh potential before the sensor acquires information; generating an eighth potential in response to information acquired by the sensor; a function of outputting the seventh potential as the first input potential or the eighth potential as the second input potential to the fourth circuit, the first cell includes a transistor having one of a source and a drain connected to a first terminal of the first capacitor; the transistor has a metal oxide in a channel formation region; Semiconductor device.

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