Semiconductor Devices

Abstract

To provide a semiconductor device which can flow a surface into an internal element and has a compact shape in the case where a plurality of transistors having a different operation voltage is mixed and loading.SOLUTION: A semiconductor device (1) contains a transistor (2) and a protection element (10) in a semiconductor substrate (101). A proof pressure of the protection element (10) is determined in accordance with a specified distance in a specified construction in the protection element (10), and is set to a proof pressure smaller than that of a transistor (20).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Power supply circuits require high-voltage transistors to handle the power supply voltage. Furthermore, to improve efficiency and reduce chip size, low on-resistance is required for medium- to high-voltage transistors. Typical low-on-resistance medium- to high-voltage transistors are LDMOS (Lateral Diffused MOS) and EDMOS (Extended Drain MOS), which use the gate oxide film of a low-voltage element and increase the concentration of the well that serves as the channel to reduce the channel size.

[0003] When a high voltage such as an electrostatic discharge (ESD) surge is applied to these transistors, a voltage higher than the breakdown voltage is forcibly applied unless the gate is open. This causes the surge current to concentrate in the low-resistance region, which can lead to breakdown. Therefore, measures to protect against such surges are required.

[0004] As a countermeasure against surges, for example, a technology is known that protects against ESD surges while maintaining the characteristics of high-voltage active elements by adjusting the widths of the N+ diffusion for well contact and the source P+ diffusion (see, for example, Patent Document 1).

[0005] Another known technique for dealing with surges is to place a PNP-type protection element between the power supply and ground. This technique eliminates the need to provide separate protection elements for the positive and negative electrostatic pulses applied to the ground potential pad, thereby minimizing the increase in layout area. Furthermore, this technique is also capable of discharging ESD applied to the power supply potential pad (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-27622 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-60349 Summary of the Invention [Problem to be solved by the invention]

[0007] In the technology described in Patent Document 1, the withstand voltage of the protection element and the internal element is the same, so that an ESD surge may flow to the internal element as well, potentially destroying the internal circuit.

[0008] In the technology described in Patent Document 2, as in the technology described in Patent Document 1, ESD surges may flow to internal elements and destroy the internal circuitry. In addition, in the technology described in Patent Document 2, negative surges from the power supply are released at a high voltage. This increases heat generation and requires larger element sizes.

[0009] An object of one aspect of the present invention is to provide a compact semiconductor device that can prevent a surge from flowing into an internal element when a plurality of transistors with different operating voltages are mounted together. [Means for solving the problem]

[0010] In order to solve the above problems, a semiconductor device according to one embodiment of the present invention is a semiconductor device including a transistor and a protection element in the same semiconductor substrate, the semiconductor substrate is of a first conductivity type; The protection element is a second conductivity type well region formed in a surface layer portion of the semiconductor substrate; a first active region formed in a surface layer portion of the semiconductor substrate and electrically connected to a source electrode; a second active region formed in a surface layer portion of the semiconductor substrate and electrically connected to a drain electrode; an element isolation region formed in the surface layer portion of the semiconductor substrate and overlapping a part of the second active region but not overlapping the first active region; and a gate portion including a gate electrode and formed on the surface of the semiconductor substrate and overlapping a part of the element isolation region and a part of the first active region, and connected to the source electrode in the first active region. First first conductivity typea portion connected to the drain electrode in the second active region; Second first conductivity type Part and teeth same Conductivity type and a third first conductivity type portion in the second active region adjacent to the second first conductivity type portion connected to the drain electrode is formed in the well region, the third first conductivity type portion has a lower impurity concentration than the second first conductivity type portion connected to the drain electrode, the second conductivity type well region has a conductivity type different from that of the third first conductivity type portion, and the element isolation region is formed across one end of the third first conductivity type portion in a direction along the surface of the semiconductor substrate and a portion of the second conductivity type well region adjacent to the one end side; The breakdown voltage of the protection element is smaller than the breakdown voltage of the transistor by setting one or both of the distance from the end of the element isolation region on the first active region side to the end of the second active region side in the direction along the surface of the semiconductor substrate, and the distance from the end of the element isolation region on the second active region side to the end of the second active region on the first active region side in the direction along the surface of the semiconductor substrate. [Effects of the Invention]

[0011] According to one aspect of the present invention, it is possible to realize a compact semiconductor device that can prevent a surge from flowing into an internal element when a plurality of transistors with different operating voltages are mounted together. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a diagram schematically showing an element structure of a semiconductor device according to a first embodiment of the present invention; [Figure 2] FIG. 2 is a diagram schematically illustrating the structure of a protection element according to the first embodiment of the present invention. [Figure 3] 3A to 3C are diagrams schematically illustrating a first state in a manufacturing process of the protection element according to the first embodiment of the present invention. [Figure 4] 5A to 5C are diagrams schematically illustrating a second state in the manufacturing process of the protection element according to the first embodiment of the present invention. [Figure 5] 5A to 5C are diagrams schematically illustrating a third state in the manufacturing process of the protection element according to the first embodiment of the present invention. [Figure 6] 10A to 10C are diagrams schematically illustrating a fourth state in the manufacturing process of the protection element according to the first embodiment of the present invention. [Figure 7] 10A to 10C are diagrams schematically illustrating a fifth state in the manufacturing process of the protection element according to the first embodiment of the present invention. [Figure 8]FIG. 10 is a diagram schematically showing a sixth state in the manufacturing process of the protection element according to the first embodiment of the present invention. [Figure 9] FIG. 10 is a diagram schematically illustrating a seventh state in the manufacturing process of the protection element according to the first embodiment of the present invention. [Figure 10] FIG. 10 is a diagram schematically illustrating an eighth state in the manufacturing process of the protection element according to the first embodiment of the present invention. [Figure 11] FIG. 10 is a diagram schematically showing a ninth state in the manufacturing process of the protection element according to the first embodiment of the present invention. [Figure 12] FIG. 10 is a diagram schematically illustrating a tenth state in the manufacturing process of the protection element according to the first embodiment of the present invention. [Figure 13] FIG. 2 is a diagram schematically illustrating an example of current-voltage characteristics of the protection element and the transistor according to the first embodiment of the present invention. [Figure 14] 3 is a diagram schematically illustrating an example of the relationship between the distance A and the breakdown voltage of the protection element according to the first embodiment of the present invention. FIG. [Figure 15] 3 is a diagram schematically illustrating an example of the relationship between the distance B and the breakdown voltage of the protection element according to the first embodiment of the present invention. FIG. [Figure 16] FIG. 10 is a diagram schematically illustrating an example of the relationship between the breakdown voltage and the on-resistance depending on the element structure of the transistor according to the second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] [Summary of the embodiment of the present invention] In the following description, the same components are denoted by the same reference numerals. However, when there are multiple components of the same type, an alphabet may be added to the reference numeral to distinguish between the individual components. Furthermore, "~" indicates a numerical range inclusive of both ends.

[0014] First Embodiment [Configuration of semiconductor device] 1, a semiconductor device 1 according to a first embodiment of the present invention includes a protection element 10 and a transistor 20. The protection element 10 and the transistor 20 are formed on the same semiconductor substrate 101. The protection element 10 is, for example, an ESD protection element, and the transistor 20 is an internal element. The transistor 20 is, for example, a medium- to high-voltage transistor, and has a withstand voltage of about 40 to 100V.

[0015] [Protection element configuration] 1 and 2, a well region 105, a drift region 107, an N-type diffusion layer 113, an isolation region 102, an LDD (lightly doped diffusion layer) region 117, and a P+ region 119 are formed in this order from the bottom side of the semiconductor substrate 101 inside the semiconductor substrate 101. The semiconductor substrate 101 is, for example, a P-type semiconductor substrate. The well region 105 is an N- region and is formed in the surface layer portion of the semiconductor substrate 101.

[0016] Drift region 107 is a P- region and is formed in well region 105 in the surface layer portion of semiconductor substrate 101. N-type diffusion layer 113 is an N- region and is formed in well region 105 in the surface layer portion of semiconductor substrate 101. N-type diffusion layer 113 is located away from drift region 107 in the direction along the surface of semiconductor substrate 101 (hereinafter also referred to as the "surface direction"). Element isolation region 102 is formed closer to the surface of semiconductor substrate 101 than drift region 107 and N-type diffusion layer 113.

[0017] The element isolation region 102 is made of, for example, oxide (SiO2). Three element isolation regions 102 are formed in the surface layer of the semiconductor substrate 101. The element isolation region 102A is formed across the N-type diffusion layer 113 and the well region 105 at one end side in the surface direction. The element isolation region 102B is formed across one end side of the drift region 107 in the surface direction and a portion of the well region 105 adjacent to one end side of the drift region 107. The element isolation region 102C is formed across the other end side of the drift region 107 in the surface direction and a portion of the well region 105 adjacent to the other end side of the drift region 107.

[0018] The LDD region 117 is a P- region and is formed in a surface layer portion within the N-type diffusion layer 113. The LDD region 117 is disposed adjacent to the element isolation region 102A on the other end side.

[0019] Two P+ regions 119 are formed. P+ region 119A is formed in a surface layer portion within LDD region 117. P+ region 119A is disposed adjacent to the other end side of element isolation region 102A. P+ region 119B is formed in a surface layer portion within drift region 107. P+ region 119B is formed between element isolation region 102B and element isolation region 102C, adjacent to the other end side of element isolation region 102B and adjacent to one end side of element isolation region 102C.

[0020] Gate oxide films 110 and 114, a polysilicon layer 115, an interlayer insulating film 121, and an electrode 123 are arranged in this order on the surface of the semiconductor substrate 101. The gate oxide film 110 is formed on the surface of the semiconductor substrate 101, straddling the well region 105 and the element isolation region 102B at the other end of the element isolation region 102B in the surface direction. The gate oxide film 114 is formed on the surface of the semiconductor substrate 101 in a portion other than the gate oxide film 110 in the surface direction.

[0021] The polysilicon layer 115 is made of, for example, polycrystalline silicon. The polysilicon layer 115 is formed on the gate oxide films 110 and 114, from the other end of the gate oxide film 110 to the other end of the LDD region 117 in the surface direction. Each side of the polysilicon layer 115 is covered with a GP sidewall 118. The GP sidewall 118 is made of, for example, an oxide.

[0022] The interlayer insulating film 121 is made of, for example, an oxide. Two electrodes 123 are formed on the interlayer insulating film 121. The electrode 123A is located above the P+ region 119A, and the electrode 123B is located above the P+ region 119B. The electrode 123A is, for example, a source electrode, and the electrode 123B is, for example, a drain electrode.

[0023] Interlayer insulating film 121 has contact holes 122 that communicate between electrode 123 and P+ region 119. Two contact holes 122 are formed corresponding to electrode 123 and P+ region 119, contact hole 122A communicates between electrode 123A and P+ region 119A, and contact hole 122B communicates between electrode 123B and P+ region 119B.

[0024] In the protection device 10, the N-type diffusion layer 113 and the P+ region 119 are formed in the surface layer of the semiconductor substrate 101 and correspond to a first active region electrically connected to the source electrode. The drift region 107 and the P+ region 119 are formed in the surface layer of the semiconductor substrate 101 and correspond to a second active region electrically connected to the drain electrode. The element isolation region 102B is formed in the surface layer of the semiconductor substrate and is located so as to overlap a portion of the second active region but not the first active region. The polysilicon layer 115 corresponds to a gate electrode, and the gate oxide film 110 and the polysilicon layer 115 are formed on the surface of the semiconductor substrate 101 and correspond to a gate portion overlapping a portion of the element isolation region 102 and a portion of the first active region. The P+ region 119A is connected to the source electrode in the first active region, and the P+ region 119B is connected to the drain electrode in the second active region, both of which have the same P+ activity.

[0025] Furthermore, a gate oxide film 110 is formed on the element isolation region 102B, and a polysilicon layer 115 is integrally formed on the first active region, the surface of the semiconductor substrate 101, and the gate oxide film 110. Furthermore, the gate oxide film 110 is disposed at the end of the gate portion on the second active region side.

[0026] [Transistor configuration] The transistor 20 has the same configuration as the protection element 10 described above, except that it further includes a drift region 112, an N-type diffusion region 120, and a contact hole 122C.

[0027] Drift region 112 is a P- region and is formed in the surface layer portion of semiconductor substrate 101 so as to overlap drift region 107. Drift region 112 is formed wider than drift region 107 in the surface direction, but separated from N-type diffusion layer 113. With this structure, transistor 20 includes drift regions 107 and 112 in the surface layer portion of semiconductor substrate 101, and the drift region has a region with a higher impurity concentration on the surface side of semiconductor substrate 101.

[0028] The N-type diffusion region 120 is formed in the LDD region 117 in the surface layer portion of the semiconductor substrate 101. The N-type diffusion region 120 is formed between the element isolation region 102A and the P+ region 119A in the surface direction.

[0029] The contact hole 122C penetrates the interlayer insulating film 121 and connects the electrode 123A and the N-type diffusion region 120 to each other.

[0030] [Manufacturing method] 3 to 12 are diagrams schematically illustrating the manufacturing process of the protection element 10. The transistor 20 can be manufactured on the same substrate as the protection element 10, except for the configuration that differs from the protection element 10.

[0031] First, as shown in Figure 3, an isolation region 102 having a depth of 0.3 to 1.0 µm is formed on the surface of a semiconductor substrate 101 using STI (shallow trench isolation) technology. The isolation region 102 has a flat surface on the surface of the semiconductor substrate 101, and is formed by embedding a CVD film, so that the edge of the surface does not have a bird's beak like the well-known LOCOS process. In this way, the isolation region 102 is formed by STI.

[0032] 4, a sacrificial oxide film 103 is formed on the surface of the semiconductor substrate 101 to a thickness of 10 to 30 nm. Next, a resist mask 104 is fabricated using photolithography. Next, an N-type impurity, for example, P (phosphorus ions), is implanted through the resist mask 104 at a dose of 6.0×10 12 ~1×10 13 ions / cm 2 Ion implantation is performed at an energy of 80 to 3000 KeV, and heat treatment is performed at 1000 to 1200° C. In this way, an N − well region 105 is formed.

[0033] Next, as shown in FIG. 5, a P-type impurity, for example, B (boron ions), is introduced through a resist mask 106 at a dose of 6.0×10 12 ~1×1013 ions / cm 2 The ions are implanted at an energy of 100 to 1000 KeV, and then heat treated at 1000 to 1100° C. In this way, a P − drift region 107 is formed in the surface layer of the well region 105.

[0034] The conditions for ion implantation for forming the drift region 107 can be adjusted appropriately according to the breakdown voltage specifications of the protection element 10. The element isolation region 102 may be formed after the well region 105 and the drift region 107 are formed.

[0035] 6, a SiN film 108 is formed on the sacrificial oxide film 103 to a thickness of 50 to 200 nm. A resist mask 109 is then formed, and the SiN film 108 and the sacrificial oxide film 103 are etched. A gate oxide film 110 is then formed on the P-type semiconductor substrate 101 in an oxygen atmosphere at a temperature of 800 to 1100°C to a thickness of 20 to 100 nm.

[0036] The SiN film 108 and the sacrificial oxide film 103 may be etched by either dry etching or wet etching.

[0037] Alternatively, the gate oxide film 110 may be formed from an oxide film formed by a CVD (chemical vapor deposition) method instead of forming the sacrificial oxide film 103 and the SiN film 108. In this case, the oxide film is formed to a thickness of 20 to 100 nm on the surface of the semiconductor substrate 101 by a well-known CVD method. Next, a resist mask is formed so as to cover the region where the gate oxide film 110 is to be formed, and the region not covered by the resist mask is dry-etched or wet-etched to form the gate oxide film 110.

[0038] The manufacturing process up to this point is the same for both the protection element 10 and the transistor 20.

[0039] Next, as shown in FIG. 7, a resist mask 111 is formed. Then, an N-type impurity, for example, B (boron ions), is implanted through the resist mask 111 at a dose of 6.0×10 12 ~8×10 12 ions / cm 2 Then, ions are implanted at an energy of 100 to 250 KeV, and heat treatment is performed at 900°C to 1100°C. In this way, a P- drift region (112 in FIG. 1) is formed on the surface side of the drift region 107 in the region where the transistor 20 is manufactured. A reduction in on-resistance is not usually required for the protection element 10. Therefore, as shown in FIG. 7, the drift region 112 is not formed in the region where the protection element 10 is manufactured.

[0040] The above ion implantation can be adjusted appropriately according to the breakdown voltage specifications of the transistor 20. The drift region 112 may be formed by multi-stage implantation, in which only ions are implanted multiple times.

[0041] 8, an N-type diffusion layer 113 is formed in the surface portion of the well region 105 at a position away from the gate oxide film 110 in the surface direction of the semiconductor substrate 101 by a known multi-stage implantation method or a known drive well. The sacrificial oxide film 103 is then removed. Oxidation is then performed in an oxygen atmosphere at a temperature of 800 to 900°C to form a gate oxide film 114 for a low-voltage transistor with a thickness of 3 to 15 nm. The gate oxide film 114 may be a dielectric film formed by a CVD method. When a transistor of 5V or less is fabricated on the same substrate, the N-type diffusion layer 113 can also serve as a PMOS well.

[0042] 9, a polysilicon layer 115 having a thickness of 100 to 200 nm, which will become the gate electrode, is deposited on the gate oxide film 110 by a CVD method. The polysilicon layer 115 is formed in a predetermined region extending from the gate oxide film 110 to the N-type diffusion layer 113 in the surface direction of the semiconductor substrate 101. The polysilicon layer 115 will become the gate electrode of the transistor 20. The gate electrodes of the transistors 20 are patterned in a predetermined pattern according to the type of transistor based on its withstand voltage.

[0043] 10, a low concentration of P-type ion species is implanted into the low-voltage transistor portion through the resist mask 116 to form an LDD region 117. The LDD region 117 is formed in the surface layer of the N-type diffusion layer 113 using the resist mask 116, the polysilicon layer 115, and the element isolation region 102 as masks. Halo implantation using N-type ion species may be performed simultaneously with the formation of the LDD region 117 to suppress short channel effects.

[0044] 11, an oxide film having a thickness of 100 nm is deposited on the entire surface by CVD, and then the entire surface is etched back to form GP sidewalls 118 that will become the side walls of the gate electrode. The oxide film may be a dielectric film.

[0045] Next, as shown in FIG. 12, B (boron ions) for the source and drain regions of the transistor 20 are implanted at a dose of 1.0×10 15 ~5.0×10 15 ions / cm 2 Ion implantation is performed with an energy of 2 to 10 KeV to form P+ regions 119. The P+ regions 119 are formed in the surface layers of the LDD region 117 and the drift region 107 using the element isolation region 102 as a mask. The P+ regions 119 become the source region or drain region of the transistor 20.

[0046] In the case of manufacturing the transistor 20, which is a medium- to high-voltage transistor, after forming the P+ region 119, As (arsenic ions) for the well contact region are implanted at a dose of 1.0×10 15~5.0×10 15 ions / cm 2 Ion implantation is performed under the conditions of a dopant concentration of 0.01% and an energy of 2 to 10 KeV. In this way, an N-type diffusion region (reference numeral 120 in FIG. 1) is further formed in the surface layer portion of the LDD region 117. The N-type diffusion region is formed adjacent to a predetermined P+ region 119.

[0047] It is also possible to form silicide on the gate electrode and the source or drain regions by well-known techniques to reduce their resistance. In this case, the silicide is preferably formed at a distance of 1 μm to 3 μm from the ends of the element isolation regions 102B and 102C to mitigate the concentration of ESD surges on the protection element 10.

[0048] Next, for example, P-SiO is deposited on the gate oxide film 114 and the polysilicon layer 115 by CVD. Then, planarization is performed by CMP (chemical mechanical polishing) to form an interlayer insulating film 121 with a thickness of 1000 nm. Next, a contact hole 122 is formed in the interlayer insulating film 121, and an electrode 123 is formed on the interlayer insulating film 121 by a well-known technique. In this way, the protection element 10 and the transistor 20 as shown in FIG. 1 are fabricated on the same semiconductor substrate 101.

[0049] [Electrical properties of semiconductor devices] <Current-voltage characteristics of protection elements and transistors> The following describes the current-voltage characteristics of the protection element 10 and the transistor 20. Fig. 13 is a diagram schematically showing an example of the current-voltage characteristics of the protection element 10 and the transistor 20. Line A1 in Fig. 13 represents the current-voltage characteristics of the protection element 10, line B in Fig. 13 represents the current-voltage characteristics of the transistor 20, and point X represents the withstand voltage of the protection element.

[0050] The reverse currents flowing through the protection element 10 and the transistor 20 are both substantially constant up to the power supply voltage. When a voltage exceeding the trigger voltage is applied to the transistor 20, as shown by line B, the current flowing through the transistor 20 increases as the voltage increases. When a voltage below the trigger voltage is applied to the protection element 10, as shown by line A1, the current flowing through the protection element 10 also increases as the voltage increases. In the event of an ESD surge, accumulated charge is released, causing current to flow into the device. When excessive current Ix is applied to the protection element 10, the PN junction of the protection element 10 breaks down at voltage Vx at point X on line A1. The same is true for the transistor 20; when a current flows through the transistor 20 such that an excessive voltage exceeding the trigger voltage is applied, the PN junction may be broken down.

[0051] In the semiconductor device 1, the protection element 10 shares a power supply side with the transistor 20, for example, and the output side is connected to the outside. Therefore, if an excessive current or voltage is suddenly applied to the wiring leading to the transistor 20 due to static electricity or a lightning strike, the excessive current or voltage is supplied to the protection element 10 before the transistor 20. The current-voltage characteristics of the protection element 10 are reversible within a range that does not exceed the current Ix. Therefore, in the semiconductor device 1, the protection element 10 ensures that the transistor 20 is only subjected to a voltage (maximum Vx) that is equal to or lower than the trigger voltage of the HVPMOS that becomes the transistor 20, and therefore the transistor 20 is protected from destruction due to a sudden supply of electricity.

[0052] <First breakdown voltage control by protective element> In the semiconductor device 1, the breakdown voltage of the protection element 10 is set to be smaller than the breakdown voltage of the transistor 20 by the distance indicated by arrow A in Fig. 2. The distance A is the distance from the end of the isolation region on the first active region side to the end of the isolation region on the second active region side in the surface direction of the semiconductor substrate 101. More specifically, the distance A is the width of the isolation region between the second active region on the drain side of the protection element 10 and the first active region including the gate and source, i.e., the width of the isolation region 102B.

[0053] The distance A may be any value that can be specified as the width of the element isolation region 102B, and may be the width of the element isolation region 102B at a specific position on the semiconductor substrate 101, for example, the width of the element isolation region 102B at a position on the surface of the semiconductor substrate 101. The position and shape of the element isolation region 102B can be confirmed by observing the cross section of the semiconductor device 1. More specifically, the oxide film on the cross section of the semiconductor device 1 is etched (wet etching with a chemical solution or dry etching), thereby etching the element isolation region 102B and forming a step portion. The distance A can be measured at the step portion on the cross section of the semiconductor device 1 using an SEM or the like.

[0054] 14 is a diagram schematically illustrating an example of the relationship between the distance A in the protection element 10 and the breakdown voltage of the protection element 10. Line A2 in FIG. 14 shows the behavior of the breakdown voltage of the protection element 10 between the distance A and the voltage applied to the protection element 10. The breakdown voltage of the protection element 10 has a linear positive correlation between the distance A and the voltage. In this case, the position of the end of the element isolation region 102B on the N-type diffusion layer 113 side in the surface direction of the semiconductor substrate 101 is constant.

[0055] When the distance A is made sufficiently small, the voltage at the rise of the current in the current-voltage characteristics of the protection device 10 becomes smaller. This is believed to be due to the following reason. That is, when the distance A is made sufficiently small, the width of the depletion layer extending between the N-type diffusion layer 113 (N-) and the P+ region 119B (P+) becomes narrower. Therefore, due to the relationship of electric field strength = voltage / depletion layer width, the electric field strength at the edge of the P+ region 119B (P+) becomes stronger. In addition, the critical electric field strength (Ecri) at which avalanche breakdown occurs is constant, and the withstand voltage is determined by the voltage at which the electric field strength exceeds Ecri. Therefore, when the distance A is made sufficiently small, the electric field strength increases, resulting in a decrease in the withstand voltage.

[0056] Therefore, it becomes easier for an overcurrent to flow to the protection element 10, and at the same time, the current and voltage values ​​of the withstand voltage X also become smaller, making the protection element 10 more susceptible to destruction by the overcurrent. When the distance A is increased, the voltage at the rise of the current in the current-voltage characteristics of the protection element 10 becomes larger and closer to the trigger voltage of the transistor 20. Therefore, the possibility of an overcurrent flowing to the transistor 20 increases, and the function of the protection element 10 may become substantially insufficient.

[0057] The current-voltage characteristics of the protection element 10 depending on the distance A can be determined by measuring experimental values ​​using semiconductor devices in which only the distance A is changed, or by calculation based on the type of material and geometric information of the layer structure of the protection element 10. For example, in the case of the above-described semiconductor device 1, the withstand voltage of the protection element 10 can be suitably adjusted when the distance A is in the range of 1.0 to 4.0 μm.

[0058] <First breakdown voltage control by protective element> In the semiconductor device 1, the breakdown voltage of the protection element 10 is set to be smaller than the breakdown voltage of the transistor 20 by the distance indicated by arrow B in Fig. 2. The distance B is the distance from the end of the isolation region on the second active region side to the end of the second active region on the first active region side in the surface direction of the semiconductor substrate 101. More specifically, the distance B is the distance from the second active region on the drain side of the protection element 10 to one end of the drift region 107 in the surface direction, i.e., the distance from the other end of the isolation region 102B to the drift region 107.

[0059] The distance B may be any value that can be specified as the distance from the other end of the element isolation region 102B to one end of the drift region 107, and may be the above-mentioned distance at a specific position on the semiconductor substrate 101, for example, at a position on the surface of the semiconductor substrate 101. The positions and shapes of the element isolation region 102B and the drift region 107 can be confirmed by observing a cross section of the semiconductor device 1. More specifically, in the cross section of the semiconductor device 1, a step is formed between the P-diffusion and the N-diffusion by wet etching the drift region 107 (P-diffusion) or the well region 105 (N-diffusion). Therefore, the distance B can be measured as the distance from the step to the other end of the element isolation region 102B in the cross section of the semiconductor device 1 by observing the cross section using an SEM or the like.

[0060] Alternatively, the distance B can be measured by checking the element distribution of the cross section by EDX (energy dispersive X-ray analysis) using contrast by well-known SCM (scanning capacitance microscopy).

[0061] 15 is a diagram schematically illustrating an example of the relationship between the distance B in the protection element 10 and the breakdown voltage of the protection element 10. Line A3 in Fig. 15 shows the behavior of the breakdown voltage X of the protection element 10 between the distance A and the voltage applied to the protection element 10. The breakdown voltage X of the protection element 10 has a linear positive correlation between the distance B and the voltage. In this case, the position of the end of the drift region 107 on the N-type diffusion layer 113 side in the surface direction of the semiconductor substrate 101 is constant.

[0062] That is, if the distance B is made sufficiently small, the voltage at the rise of the current in the current-voltage characteristics of the protection element 10 becomes smaller. This is thought to be due to the following reason. If the distance B is made sufficiently small, for example, if one end of the drift region 107 is brought closer to the P+ region 119B side, the concentration gradient of the P-type impurities on the P-type diffusion side (drift region 107 and P+ region 119B) becomes steeper. This narrows the extent of the depletion layer in the P-type diffusion region. As a result, the electric field relaxation by the drift region 107 (P-) weakens, and the electric field strength increases. Therefore, avalanche breakdown becomes more likely to occur.

[0063] Therefore, it becomes easier for an overcurrent to flow to the transistor 20 through the protection element 10, while at the same time, the current and voltage values ​​of the withstand voltage X also become smaller, making the protection element 10 more susceptible to destruction by the overcurrent. When the distance B is increased, the voltage at the rise of the current in the current-voltage characteristics of the protection element 10 becomes larger and closer to the trigger voltage of the transistor 20. Therefore, the possibility of an overcurrent flowing to the transistor 20 increases, and the function of the protection element 10 may become substantially insufficient.

[0064] The current-voltage characteristics of the protection element 10 depending on the distance B can be determined by measuring experimental values ​​using a semiconductor device in which only the distance B is changed, or by calculation based on the type of material and geometric information of the layer structure of the protection element 10. For example, in the case of the above-described semiconductor device 1, the withstand voltage of the protection element 10 can be suitably adjusted when the distance B is in the range of 0.5 to 6.0 μm.

[0065] In this embodiment, the withstand voltage of the protection element 10 may be set by only the distance A, or by only the distance B, or by both of these distances.

[0066] [Major effects of this embodiment] As is clear from the above description, the semiconductor device 1 relates to a semiconductor device incorporating a low-voltage transistor and a MOS-type medium- to high-voltage transistor. The semiconductor device 1 can be configured using a lateral PNP transistor structure that exists parasitically on the medium- to high-voltage PMOS transistor. The breakdown voltage of the protection element 10 can be adjusted to be equal to or less than the power supply voltage and the breakdown voltage of the transistor 20 by adjusting the drift length (A), the distance (B) between the well region 105 and the drift region 107, or both. Therefore, operation of the semiconductor device 1 does not place a load on the transistor 20, which is an internal active element.

[0067] Furthermore, in the semiconductor device 1, for example, the drain is connected to a power supply terminal, and the source, gate, and well are connected to a ground terminal. Therefore, in response to ESD noise between the power supply and ground, the protection element 10 operates as a PNP bipolar device due to a current flowing through the protection element 10 due to the voltage (trigger voltage) of the noise. This allows the ESD protection structure to be smaller than a diode, which normally has a low breakdown current resistance, and the protection structure can be made smaller.

[0068] The protection element 10 has a simpler configuration than the transistor 20. Therefore, the protection element 10 can be manufactured without adding any additional manufacturing steps by removing the drift region 112 from the structure of the transistor 20, adjusting the dimensions of the element isolation region 102A in the surface direction, and changing the source diffusion (P+ region 119A) to P+ only. Therefore, the protection element 10 can be easily manufactured on the same semiconductor substrate 101 as the transistor 20.

[0069] Furthermore, the protection element 10 can be a high-voltage ESD protection element that does not apply a voltage load to the transistor 20. Conventional technology (prior patents) protects against ESD surges while maintaining the characteristics of the active element by adjusting the widths of the N+ diffusion for well contact and the source P+ diffusion. In this case, the breakdown current capacity of the entire element is the sum of the current of the lateral PNP (drain P+·P- / N-body / source P+) operation parasitic to the PMOS and the current of the P+ diode (P+ / P- / Nbody·N+) operation, compared to a PMOS structure (PNP operation only) without an N+ at the GP terminal on the source side. This reduces the current capacity of the transistor.

[0070] The withstand voltage of the protection element is the same as that of the transistor. As a result, ESD surges also flow through the transistor, potentially damaging its internal circuitry (PN junction, etc.). In addition, the width of the P+ diffusion region on the source side of the transistor is reduced, reducing the effective power W and increasing the on-resistance.

[0071] In the first embodiment, the trigger voltage of the protection element 10 is adjusted by adjusting the drain diffusion structure and drift width of the protection element 10. Therefore, the trigger voltage of the protection element 10 can be set to be lower than that of the transistor 20. Therefore, according to the first embodiment, an ESD protection element can be provided that does not impose a voltage load on the internal circuit of the transistor 20. Furthermore, the influence of the protection element 10 on the characteristics of active elements such as the transistor 20 can be substantially eliminated. Furthermore, no additional process is required when fabricating the protection element 10 on the same semiconductor substrate 101. Furthermore, the size of the protection element 10 can be made smaller than that of a diode.

[0072] Furthermore, the semiconductor device 1 allows the width of the transistor 20 in the surface direction to be smaller than that of conventional semiconductor devices. Destruction of the internal circuit of the transistor 20 is usually caused by heat generation due to overcurrent, and the amount of heat generation is proportional to the product of the current and voltage. Therefore, the breakdown current value decreases when the voltage is high. Furthermore, since a total charge Q flows into the semiconductor device 1 during an ESD surge, the width of the transistor 20 must be increased to allow the same current value dQ / dt to flow. This increases the size of the transistor 20. Assuming that the breakdown current value is 1, the trigger voltage of the protection element 10 is 60 V, and that of the conventional technology is 80 V, and the amount of heat generated by destruction is the same, the size (width) of the protection element 10 is 1 × 60 / 80 = 0.75. In other words, in this case, the width of the protection element 10 is 0.75 times that of the conventional semiconductor device.

[0073] As is clear from the above description, according to the first embodiment of the present invention, it is possible to provide a high-voltage semiconductor device that operates between a high power supply voltage and the withstand voltage of the transistor.

[0074] Second Embodiment In the first embodiment, the manufacture of transistor 20 includes two steps: forming drift region 107 and forming drift region 112. In this embodiment, transistor 20 does not have drift region 112, and drift region 107 extends further toward the first active region in the surface direction. Other than that, the semiconductor device of this embodiment has the same configuration as that of the first embodiment.

[0075] In this embodiment, the drift region 107 of the transistor 20 is formed by performing ion implantation for producing the drift region 107 so that the ions diffuse to a region beyond the element isolation region 102B in the surface direction.

[0076] Fig. 16 is a diagram showing an example of the relationship between breakdown voltage and on-resistance of the drift region structure of a transistor according to an embodiment of the present invention. In Fig. 16, the solid line shows the relationship between breakdown voltage and on-resistance of the transistor according to the second embodiment, i.e., in the case where the drift region is configured with only one ion inflow (having only drift region 107). The dotted line in Fig. 16 shows the relationship between breakdown voltage and on-resistance of the transistor according to the first embodiment, i.e., in the case where the drift region is configured with only two ion inflows (having both drift regions 107 and 112).

[0077] In this embodiment, the drift region is formed by a single ion implantation, which is effective from the viewpoint of simplifying the manufacturing process.

[0078] On the other hand, when the drift region is formed by two ion implantations, as in the first embodiment, the impurity concentration increases closer to the surface of the drift region, thereby making it possible to further reduce the on-resistance of the transistor.

[0079] Other Embodiments In the first embodiment, the protection element 10 and the transistor 20 serving as a high-voltage transistor are fabricated on the same semiconductor substrate 101. In an embodiment of the present invention, two or more types of transistors with different characteristics and withstand voltages may be mounted on the semiconductor substrate. For example, in an embodiment of the present invention, in addition to the high-voltage transistor, a low-voltage transistor may also be mounted on the semiconductor substrate 101. The low-voltage transistor has a withstand voltage of 5 V or less.

[0080] In this case, the semiconductor device may have a first protection element corresponding to the low-voltage transistor and a second protection element corresponding to the medium- to high-voltage transistor, or may have protection elements corresponding to both the low-voltage transistor and the medium- to high-voltage transistor.

[0081] In embodiments of the present invention, the isolation region may be fabricated using a technique other than STI. For example, the isolation region may be fabricated by local oxidation of silicon (LOCOS). Note that fabricating the isolation region using STI is preferable from the viewpoint of more precise control of the dimensions of the isolation region in the surface direction.

[0082] 〔summary〕 A semiconductor device (1) according to a first aspect of the present invention is a semiconductor device including a transistor (20) and a protection element (10) on the same semiconductor substrate (101), the protection element including a first active region formed in a surface layer portion of the semiconductor substrate and electrically connected to a source electrode, a second active region formed in the surface layer portion of the semiconductor substrate and electrically connected to a drain electrode, an element isolation region (102) formed in the surface layer portion of the semiconductor substrate and overlapping a portion of the second active region but not the first active region, and a gate electrode, which is formed on the surface of the semiconductor substrate and overlaps a portion of the element isolation region and and a gate portion overlapping a part of the first active region, wherein the activity of a portion of the first active region connected to the source electrode and the activity of a portion of the second active region connected to the drain electrode are the same, and the breakdown voltage of the protection element is smaller than the breakdown voltage of the transistor by setting one or both of the distance (A) from the end of the element isolation region on the first active region side to the end of the second active region side in the direction along the surface of the semiconductor substrate and the distance (B) from the end of the element isolation region on the second active region side to the end of the second active region on the first active region side in the direction along the surface of the semiconductor substrate.

[0083] According to the above configuration, it is possible to manufacture the internal element and the protection element in the same process, and it is possible to appropriately set the withstand voltage of the protection element according to the withstand voltage of the internal element by adjusting the position or size of the component in the protection element. Therefore, according to the above configuration, it is possible to realize a compact semiconductor device that can prevent a surge from flowing into the internal element when multiple transistors with different operating voltages are mounted together.

[0084] A semiconductor device according to a second aspect of the present invention may further include a gate insulating film in which a gate portion is formed on an element isolation region in the above-mentioned first aspect, and the gate electrode may be integrally formed on the first active region, the semiconductor substrate, and the gate insulating film.

[0085] The above configuration is even more effective in terms of reducing the leakage of gate current.

[0086] A semiconductor device according to a third aspect of the present invention may be configured in the second aspect as described above, such that the gate insulating film is disposed at an end of the gate portion on the second active region side.

[0087] The above configuration is even more effective in terms of reducing the leakage of gate current.

[0088] A semiconductor device according to a fourth aspect of the present invention may be configured as in any one of the first to third aspects, in which the element isolation region is formed by STI technology.

[0089] According to the above configuration, it is possible to manufacture the element isolation region more precisely, which is even more effective from the viewpoint of precisely setting the breakdown voltage of the protection element.

[0090] A semiconductor device according to a fifth aspect of the present invention is any one of the first to fourth aspects, and the transistor may include a high-to-medium voltage transistor.

[0091] The above configuration is even more effective in terms of facilitating driving of the internal elements and saving power.

[0092] A sixth aspect of the present invention relates to a semiconductor device according to the fifth aspect, and the transistor may further include a low-voltage transistor having a lower breakdown voltage than the medium- or high-voltage transistor.

[0093] The above configuration is even more effective in terms of configuring a semiconductor device in which various internal elements are mounted on the same semiconductor substrate.

[0094] A semiconductor device according to a seventh aspect of the present invention is any one of the first to sixth aspects, wherein the transistor includes a drift region in a surface layer portion of the semiconductor substrate, and the drift region may have a region with a higher impurity concentration on the surface side of the semiconductor substrate.

[0095] The above configuration is even more effective in terms of reducing the on-resistance of the internal elements.

[0096] According to the semiconductor device of the embodiment of the present invention, it is possible to provide a miniaturized medium-to-high voltage ESD protection element having a trigger voltage and a hold voltage that are equal to or higher than the power supply voltage and equal to or lower than the withstand voltage of the medium-to-high voltage active element, without changing the performance of the medium-to-high voltage active element inside the circuit and without adding any processes or circuits.

[0097] Furthermore, the above-described configuration makes it possible to provide appropriate, simple, and space-saving protection against ESD surges in semiconductor devices incorporating multiple types of internal elements, which is expected to contribute to the development of a foundation for industry and technological innovation and contribute to the achievement of the Sustainable Development Goals (SDGs).

[0098] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment. [Explanation of symbols]

[0099] 1. Semiconductor device 10 Protection element 20 transistors 101 Semiconductor substrate 102 Element isolation region 103 Sacrificial oxide film 104, 106, 109, 111, 116 Resist mask 105 well area 107, 112 Drift region 108 SiN film 110, 114 Gate oxide 113 N-type diffusion layer 115 Polysilicon layer (gate electrode) 117 LDD area 118 GP sidewall 119 P+ area 120 N-type diffusion region 121 Interlayer insulating film 122 Contact Hole 123 Electrode

Claims

1. A semiconductor device including a transistor and a protection element on the same semiconductor substrate, the semiconductor substrate is of a first conductivity type; The protection element is a second conductivity type well region formed in a surface layer portion of the semiconductor substrate; a first active region formed in a surface layer portion of the semiconductor substrate and electrically connected to a source electrode; a second active region formed in a surface layer portion of the semiconductor substrate and electrically connected to a drain electrode; an isolation region formed in a surface layer portion of the semiconductor substrate, the isolation region overlapping a portion of the second active region but not overlapping the first active region; a gate portion including a gate electrode, the gate portion being formed on the surface of the semiconductor substrate and overlapping a part of the element isolation region and a part of the first active region; a first first conductivity type portion in the first active region connected to the source electrode and a second first conductivity type portion in the second active region connected to the drain electrode have the same conductivity type; a third first conductivity type portion in the second active region adjacent to the second first conductivity type portion connected to the drain electrode is formed in the well region; the third first-conductivity-type portion has a lower impurity concentration than the second first-conductivity-type portion connected to the drain electrode, the second conductivity type well region has a conductivity type different from that of the third first conductivity type portion; the element isolation region is formed across one end of the third first-conductivity-type portion in a direction along the surface of the semiconductor substrate and a portion of the second-conductivity-type well region adjacent to the one end, the breakdown voltage of the protection element is smaller than the breakdown voltage of the transistor by setting one or both of a distance from an end of the element isolation region on the first active region side to an end of the second active region side in a direction along the surface of the semiconductor substrate and a distance from an end of the element isolation region on the second active region side to an end of the second active region on the first active region side in a direction along the surface of the semiconductor substrate; Semiconductor device.

2. A semiconductor device as described in claim 1, wherein the gate portion further includes a gate oxide film that overlaps a portion of the element isolation region but does not overlap the first active region.

3. A semiconductor device as described in Claim 2, wherein the gate electrode is integrally formed on the first active region, on the semiconductor substrate, and on the gate oxide film.

4. 4. The semiconductor device according to claim 1, wherein said element isolation region is formed by shallow trench isolation technology.

5. The transistor includes a high-voltage transistor. The semiconductor device according to any one of claims 1 to 4.

6. The transistors further include a low-voltage transistor having a lower breakdown voltage than the medium- or high-voltage transistor. The semiconductor device according to claim 5 .

7. 7. The semiconductor device according to claim 1, wherein the transistor includes a drift region in a surface layer portion of the semiconductor substrate, and the drift region has a region with a higher concentration of impurities on the surface side of the semiconductor substrate.

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