Wiring board, electronic device, and electronic module

Abstract

This wiring substrate comprises: an insulating substrate; a first line and a second line that are located on the insulating substrate and that are adjacent to each other; and an earth membrane conductor and an earth via conductor that are located on the insulating substrate and that surround the first line and the second line. Further, in a plan perspective view, a first line conductor and a third line conductor each have a section in which a space increases in size towards a first via conductor and a third via conductor, and a second line conductor and a fourth line conductor each have a section in which a space decreases in size towards a second via conductor and a fourth via conductor.

Description

[Technical Field]

[0001] The present disclosure relates to a wiring board, an electronic device, and an electronic module. [Background technology]

[0002] Japanese Patent Application Laid-Open No. 2009-212400 discloses a wiring board having a signal line extending from one surface of the board to the other surface of the board. Summary of the Invention [Means for solving the problem]

[0003] <1> In accordance with the present disclosure In one embodiment The wiring board is an insulating substrate; a first line and a second line located on the insulating substrate and adjacent to each other; a ground film conductor and a ground via conductor located on the insulating substrate and surrounding the first line and the second line; Equipped with The first line is a first line conductor; a first via conductor connected to the first line conductor; a second line conductor connected to the first via conductor and extending to an opposite side of the first line conductor across the first via conductor in a planar perspective view; and a second via conductor connected to the second line conductor and extending to a layer different from a layer on which the first via conductor is located; The second line is a third line conductor; a third via conductor connected to the third line conductor; a fourth line conductor connected to the third via conductor and extending to an opposite side of the third line conductor across the third via conductor in a planar perspective view; and a fourth via conductor connected to the fourth line conductor and extending to a layer different from a layer on which the third via conductor is located; In a planar perspective view, the first line conductor and the third line conductor have a portion where the distance therebetween increases toward the first via conductor and the third via conductor, and the second line conductor and the fourth line conductor have a portion where the distance therebetween decreases toward the second via conductor and the fourth via conductor. death, The ground film conductor is a first ground film conductor having a first opening; a second ground film conductor having a second opening; Including, At least a portion of the first via conductor and the third via conductor is located within the first opening, at least a portion of the second via conductor and the fourth via conductor is located within the second opening; The first opening is smaller than the second opening. . <2> Another aspect of the wiring board according to the present disclosure includes: an insulating substrate; a first line and a second line located on the insulating substrate and adjacent to each other; a ground film conductor and a ground via conductor located on the insulating substrate and surrounding the first line and the second line; Equipped with The first line is a first line conductor; a first via conductor connected to the first line conductor; a second line conductor connected to the first via conductor and extending to an opposite side of the first line conductor across the first via conductor in a planar perspective view; and a second via conductor connected to the second line conductor and extending to a layer different from a layer on which the first via conductor is located; The second line is a third line conductor; a third via conductor connected to the third line conductor; a fourth line conductor connected to the third via conductor and extending to an opposite side of the third line conductor across the third via conductor in a planar perspective view; and a fourth via conductor connected to the fourth line conductor and extending to a layer different from a layer on which the third via conductor is located; In a planar perspective view, the first line conductor and the third line conductor have a portion where the distance therebetween increases toward the first via conductor and the third via conductor, and the second line conductor and the fourth line conductor have a portion where the distance therebetween decreases toward the second via conductor and the fourth via conductor, The first line is further including a fifth line conductor connected to the second via conductor and extending to an opposite side of the second line conductor across the second via conductor in planar perspective; a fifth via conductor connected to the fifth line conductor and extending to a layer different from the layer on which the second via conductor is located; a sixth line conductor connected to the fifth via conductor and extending to an opposite side of the fifth line conductor across the fifth via conductor in planar perspective; and a sixth via conductor connected to the sixth line conductor and extending to a layer different from the layer on which the fifth via conductor is located; The second line is further including a seventh line conductor connected to the fourth via conductor and extending to an opposite side of the third line conductor across the fourth via conductor in planar perspective; a seventh via conductor connected to the seventh line conductor and extending to a layer different from the layer on which the fourth via conductor is located; an eighth line conductor connected to the seventh via conductor and extending to an opposite side of the seventh line conductor across the seventh via conductor in planar perspective; and an eighth via conductor connected to the eighth line conductor and extending to a layer different from the layer on which the seventh via conductor is located; In a planar perspective view, the fifth line conductor and the seventh line conductor have a portion where the distance between them increases toward the fifth via conductor and the seventh via conductor, and the sixth line conductor and the eighth line conductor have a portion where the distance between them decreases toward the sixth via conductor and the eighth via conductor.

[0004] The electronic device according to the present disclosure comprises: The above wiring board; an electronic element mounted on the wiring board; Equipped with.

[0005] The electronic module according to the present disclosure comprises: The electronic device; a module substrate on which the electronic device is mounted; Equipped with. [Brief explanation of the drawings]

[0006] [Figure 1A] 1 is a planar perspective view of a wiring board according to a first embodiment of the present disclosure. [Figure 1B]1 is a longitudinal cross-sectional view of a wiring board according to a first embodiment of the present disclosure, taken along a signal line. [Figure 2] 1 is a plan view perspective view showing a main part of a wiring board according to a first embodiment seen from above. [Figure 3A] FIG. 3 is a cross-sectional view showing a third layer in the main part of FIG. 2. [Figure 3B] FIG. 3 is a cross-sectional view showing a fourth layer in the main part of FIG. 2. [Figure 3C] 3 is a cross-sectional view showing the fifth to tenth layers in the main part of FIG. 2. FIG. [Figure 4A] FIG. 3 is a cross-sectional view showing the 11th layer in the main part of FIG. 2. [Figure 4B] FIG. 3 is a cross-sectional view showing the 12th layer in the main part of FIG. 2. [Figure 4C] FIG. 3 is a cross-sectional view showing the 13th layer in the main part of FIG. 2. [Figure 5A] FIG. 3 is a cross-sectional view showing the 14th layer in the main part of FIG. 2. [Figure 5B] FIG. 3 is a view showing the back side of the main part of FIG. 2. [Figure 6A] FIG. 3C is a vertical cross-sectional view taken along line AA in FIG. 3B. [Figure 6B] FIG. 3C is a vertical cross-sectional view taken along line BB in FIG. 3B. [Figure 6C] FIG. 5B is a vertical cross-sectional view taken along line CC in FIG. 5A. [Figure 6D] FIG. 5B is a longitudinal cross-sectional view taken along line DD in FIG. 5A. [Figure 7A] 4 is a graph showing the reflection loss of the wiring board according to the first embodiment and the comparative example. [Figure 7B] 4 is a graph showing insertion loss of the wiring board according to the first embodiment and a comparative example. [Figure 8A] FIG. 10 is a plan view perspective view showing a main part of a wiring board according to a second embodiment of the present disclosure. [Figure 8B] FIG. 10 is a longitudinal cross-sectional view of a main part of a wiring board according to a second embodiment of the present disclosure, taken along a signal line. [Figure 9A] FIG. 8B is a cross-sectional view showing the third layer in the main part of FIG. 8A. [Figure 9B]FIG. 8B is a cross-sectional view showing the fourth layer in the main part of FIG. 8A. [Figure 9C] FIG. 8B is a cross-sectional view showing the fifth to ninth layers in the main part of FIG. 8A. [Figure 10A] FIG. 8B is a cross-sectional view showing the tenth layer in the main part of FIG. 8A. [Figure 10B] FIG. 8B is a cross-sectional view showing the 11th layer in the main part of FIG. 8A. [Figure 10C] FIG. 8B is a cross-sectional view showing the 12th layer in the main part of FIG. 8A. [Figure 11A] FIG. 8B is a cross-sectional view showing the 13th layer in the main part of FIG. 8A. [Figure 11B] FIG. 8B is a cross-sectional view showing the 14th layer in the main part of FIG. 8A. [Figure 11C] 8B is a diagram showing the back side of the main part of FIG. 8A. FIG. [Figure 12A] FIG. 9C is a vertical cross-sectional view taken along line AA in FIG. 9B. [Figure 12B] FIG. 9C is a vertical cross-sectional view taken along line BB in FIG. 9B. [Figure 12C] FIG. 10D is a vertical cross-sectional view taken along line CC in FIG. 10C. [Figure 13A] FIG. 10D is a longitudinal cross-sectional view taken along line DD in FIG. 10C. [Figure 13B] FIG. 11C is a vertical cross-sectional view taken along line EE in FIG. 11B. [Figure 13C] FIG. 11C is a longitudinal cross-sectional view taken along line FF in FIG. 11B. [Figure 14] 1 illustrates an electronic device and an electronic module according to an embodiment of the present disclosure. [Figure 15A] FIG. 10 is a planar perspective view showing a wiring board according to a third embodiment of the present disclosure. [Figure 15B] FIG. 11 is a longitudinal cross-sectional view of the wiring board according to the third embodiment, taken along a signal line. [Figure 16] 11 is a plan view perspective view showing a main part of a wiring board according to a third embodiment, seen from above. FIG. [Figure 17A] FIG. 10 is a planar perspective view showing a wiring board according to a fourth embodiment of the present disclosure. [Figure 17B]FIG. 10 is a longitudinal cross-sectional view of the wiring board according to the fourth embodiment, taken along a signal line. [Figure 18] 10 is a plan view perspective view showing a main part of a wiring board according to a fourth embodiment seen from above. FIG. [Figure 19A] FIG. 19 is a cross-sectional view showing the third layer in the main part of FIG. 18. [Figure 19B] FIG. 19 is a cross-sectional view showing the fourth layer in the main part of FIG. 18. [Figure 19C] FIG. 19 is a cross-sectional view showing the fifth to tenth layers in the main part of FIG. [Figure 19D] FIG. 19 is a cross-sectional view showing the 11th layer in the main part of FIG. 18. [Figure 19E] FIG. 19 is a cross-sectional view showing the 12th layer in the main part of FIG. 18. [Figure 19F] FIG. 19 is a cross-sectional view showing the 13th layer in the main part of FIG. 18. [Figure 19G] FIG. 19 is a cross-sectional view showing the 14th layer in the main part of FIG. 18. [Figure 19H] FIG. 19 is a view showing the back side of the main part of FIG. 18. [Figure 20A] FIG. 10 is a planar perspective view showing a wiring board according to a fifth embodiment of the present disclosure. [Figure 20B] FIG. 10 is a longitudinal cross-sectional view of the wiring board according to the fifth embodiment, taken along the signal line. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings.

[0008] (Embodiment 1) 1A and 1B illustrate a wiring board according to a first embodiment of the present disclosure, with FIG. 1A being a planar perspective view of the wiring board and FIG. 1B being a longitudinal cross-sectional view of the wiring board cut along a signal line.

[0009] The wiring board 1 according to the first embodiment includes an insulating substrate 2 having a first surface S1 and a second surface S2 located on the opposite side of the first surface S1, and a first line 10 and a second line 20 located on the insulating substrate 2 and adjacent to each other. The insulating substrate 2 is an insulating substrate made of ceramic, resin, or the like, and may have a laminated structure. The first line 10 and the second line 20 are a pair of differential lines through which differential signals are transmitted, and may be lines that transmit wideband signals. The wideband may be a band of 1 GHz to 60 GHz.

[0010] The wiring board 1 may further include a plurality of ground film conductors 31 and a plurality of ground via conductors 32 located on the insulating substrate 2 and surrounding the first line 10 and the second line 20. The plurality of ground film conductors 31 and the plurality of ground via conductors 32 may have a configuration that collectively surrounds the first line 10 and the second line 20.

[0011] The first line 10 may include, in order from the first surface S1 to the second surface S2 of the insulating substrate 2, a third electrode T3, an ith via conductor Vi, an ith line conductor Li, a first parallel line conductor H1, a first line conductor L1, a first via conductor V1, a second line conductor L2, a second via conductor V2, an nth line conductor Ln, an nth via conductor Vn, and a first electrode T1. The first electrode T1 is located on the second surface S2 of the insulating substrate 2. The third electrode T3 is located on the first surface S1 of the insulating substrate 2.

[0012] The second line 20 may include, in order from the first surface S1 to the second surface S2 of the insulating substrate 2, a fourth electrode T4, an (i+1)-th via conductor Vi+1, an (i+1)-th line conductor Li+1, a second parallel line conductor H2, a third line conductor L3, a third via conductor V3, a fourth line conductor L4, a fourth via conductor V4, an (n+1)-th line conductor Ln+1, an (n+1)-th via conductor Vn+1, and a second electrode T2. The second electrode T2 is located on the second surface S2 of the insulating substrate 2. The fourth electrode T4 is located on the first surface S1 of the insulating substrate 2.

[0013] In the following description, the first surface S1 side will be referred to as the "upper side" and the second surface S2 side will be referred to as the "lower side" in the thickness direction of the wiring board 1. In addition, in the direction in which the parallel line conductors (H1, H2) extend, the side where the third electrode T3 and the fourth electrode T4 are located will be referred to as the "left side," and the side where the first electrode T1 and the second electrode T2 are located will be referred to as the "right side."

[0014] The wiring board 1 may have multiple layers (first layer y1 to fifteenth layer y15) on which electrodes (first electrode T1 to fourth electrode T4), line conductors (i-th line conductor Li to n+1-th line conductor Ln+1), or any of multiple ground film conductors 31 are located. The first layer y1 is the surface layer on the first surface S1 side, and the fifteenth layer y15 is the surface layer on the second surface S2 side. The multiple layers are arranged vertically.

[0015] In the first line 10, when viewed from a plane perspective (viewed from a direction perpendicular to the first surface S1), the third electrode T3, the ith line conductor Li, the first parallel line conductor H1, the first line conductor L1, the second line conductor L2, the nth line conductor Ln, and the first electrode T1 may be connected in this order from left to right.

[0016] Of the multiple line conductors (conductors extending in a direction along the first surface S1) included in the first line 10, the ith line conductor Li, the first parallel line conductor H1, and the first line conductor L1 may be located on the same layer. The first line conductor L1, the second line conductor L2, and the nth line conductor Ln may be located in this order from top to bottom.

[0017] The multiple line conductors included in the first line 10 (the i-th line conductor Li, the first parallel line conductor H1, the first line conductor L1, the second line conductor L2, and the n-th line conductor Ln) may have the same line width.

[0018] The ith via conductor Vi may be located from the layer of the third electrode T3 to the layer of the ith line conductor Li. The first via conductor V1 may be located from the layer of the first line conductor L1 to the layer of the second line conductor L2. The second via conductor V2 may be located from the layer of the second line conductor L2 to the layer of the nth line conductor Ln. The nth via conductor Vn may be located from the layer of the nth line conductor Ln to the layer of the first electrode T1 (the layer of the second surface S2).

[0019] The third electrode T3 may be located on the first layer y1. The ith line conductor Li, the first parallel line conductor H1, and the first line conductor L1 may be located on the fourth layer y4. The second line conductor L2 may be located on the twelfth layer y12. The nth line conductor Ln may be located on the fourteenth layer y14.

[0020] The third electrode T3 may be connected to the upper part of the ith via conductor Vi. The lower part of the ith via conductor Vi may be connected to the left part of the ith line conductor Li. The right part of the ith line conductor Li may be connected to the left part of the first parallel line conductor H1. The right part of the first parallel line conductor H1 may be connected to the left part of the first line conductor L1. The right part of the first line conductor L1 may be connected to the upper part of the first via conductor V1. The lower part of the first via conductor V1 may be connected to the left part of the second line conductor L2. The right part of the second line conductor L2 may be connected to the upper part of the second via conductor V2. The lower part of the second via conductor V2 may be connected to the left part of the nth line conductor Ln. The right part of the nth line conductor Ln may be connected to the upper part of the nth via conductor Vn. The lower part of the nth via conductor Vn may be connected to the first electrode T1. The connection positions of the upper and lower parts may also be referred to as the upper end and the lower end, respectively. The connection positions of the left and right portions may be rephrased as the left end and the right end, respectively.

[0021] In the second line 20, when viewed from a plane perspective (viewed from a direction perpendicular to the first surface S1), the fourth electrode T4, the (i+1)th line conductor Li+1, the second parallel line conductor H2, the third line conductor L3, the fourth line conductor L4, the (n+1)th line conductor Ln+1, and the second electrode T2 may be connected in this order from left to right.

[0022] Of the multiple line conductors (conductors extending in a direction along the first surface S1) included in the second line 20, the (i+1)-th line conductor Li+1, the second parallel line conductor H2, and the third line conductor L3 may be located on the same layer. The third line conductor L3, the fourth line conductor L4, and the (n+1)-th line conductor Ln+1 may be located in that order from top to bottom.

[0023] The multiple line conductors included in the second line 20 (the (i+1)th line conductor Li+1, the second parallel line conductor H2, the third line conductor L3, the fourth line conductor L4, and the (n+1)th line conductor Ln+1) may have the same line width. The multiple line conductors included in the second line 20 may have the same line width as the multiple line conductors included in the first line 10.

[0024] The (i+1)-th via conductor Vi+1 may be located from the layer of the fourth electrode T4 (the layer of the first surface S1) to the layer of the second parallel line conductor H2 and the third line conductor L3. The third via conductor V3 may be located from the layer of the third line conductor L3 to the layer of the fourth line conductor L4. The fourth via conductor V4 may be located from the layer of the fourth line conductor L4 to the layer of the (n+1)-th line conductor Ln+1. The (n+1)-th via conductor Vn+1 may be located from the layer of the (n+1)-th line conductor Ln+1 to the layer of the second electrode T2 (the layer of the second surface S2).

[0025] The fourth electrode T4 may be located on the first layer y1. The (i+1)th line conductor Li+1, the second parallel line conductor H2, and the third line conductor L3 may be located on the fourth layer y4. The fourth line conductor L4 may be located on the twelfth layer y12. The (n+1)th line conductor Ln+1 may be located on the fourteenth layer y14.

[0026] The fourth electrode T4 may be connected to the upper part of the (i+1)th via conductor Vi+1. The lower part of the (i+1)th via conductor Vi+1 may be connected to the left part of the (i+1)th line conductor Li+1. The right part of the (i+1)th line conductor Li+1 may be connected to the left part of the second parallel line conductor H2. The right part of the second parallel line conductor H2 may be connected to the left part of the third line conductor L3. The right part of the third line conductor L3 may be connected to the upper part of the third via conductor V3. The lower part of the third via conductor V3 may be connected to the left part of the fourth line conductor L4. The right part of the fourth line conductor L4 may be connected to the upper part of the fourth via conductor V4. The lower part of the fourth via conductor V4 may be connected to the left part of the (n+1)th line conductor Ln+1. The right part of the (n+1)th line conductor Ln+1 may be connected to the upper part of the (n+1)th via conductor Vn+1. The lower portion of the (n+1)-th via conductor Vn+1 may be connected to the second electrode T2. The connection positions of the upper and lower portions may be rephrased as the upper end and the lower end, respectively. The connection positions of the left and right portions may be rephrased as the left end and the right end, respectively.

[0027] In the first line 10 and the second line 20, the i-th line conductor Li, the (i+1)-th line conductor Li+1, the first parallel line conductor H1, the second parallel line conductor H2, the first line conductor L1, and the third line conductor L3 may be located on the same layer. The second line conductor L2 and the fourth line conductor L4 may be located on the same layer. The n-th line conductor Ln and the (n+1)-th line conductor Ln+1 may be located on the same layer.

[0028] The first parallel line conductor H1 and the second parallel line conductor H2 may be parallel to each other. The first parallel line conductor H1 and the second parallel line conductor H2 may be straight or partially curved.

[0029] In the first line 10 and the second line 20, the i-th via conductor Vi and the (i+1)-th via conductor Vi+1 may be located across the same layer. The first via conductor V1 and the third via conductor V3 may be located across the same layer. The second via conductor V2 and the fourth via conductor V4 may be located across the same layer. The n-th via conductor Vn and the (n+1)-th via conductor Vn+1 may be located across the same layer.

[0030] The third electrode T3 and the fourth electrode T4 may be aligned in the front-to-rear direction (a direction perpendicular to the left-to-right direction and along the first surface S1 or the second surface S2). The first electrode T1 and the second electrode T2 may be aligned in the front-to-rear direction. The areas of the first electrode T1 and the second electrode T2 may be larger than the areas of the third electrode T3 and the fourth electrode T4. The distance between the center of the first electrode T1 and the center of the second electrode T2 may be longer than the distance between the center of the third electrode T3 and the center of the fourth electrode T4.

[0031] The plurality of ground film conductors 31 may be located on all layers (the second layer y2 to the fourteenth layer y14) of the insulating substrate 2 except for the surface layer. The plurality of ground film conductors 31 may include one or more ground film conductors 31i having an opening Oi surrounding the ith via conductor Vi and the (i+1)th via conductor Vi+1, one or more ground film conductors 31h having a strip-shaped opening Oh surrounding the first parallel line conductor H1 and the second parallel line conductor H2, and a plurality of first ground film conductors 31a and a plurality of second ground film conductors 31b having a first opening O1 and a second opening O2 described below. The opening Oh of the ground film conductor 31h on the fourth layer y4 may have a shape in which a strip-shaped portion along the first parallel line conductor H1 and the second parallel line conductor H2, a portion shaped like the opening Oh, and a portion shaped like the first opening O1 are integrated together.

[0032] The plurality of ground via conductors 32 may be positioned to surround at least the openings Oi, Oh, the first opening O1, and the second opening O2. Two adjacent ground via conductors 32 among the plurality of ground via conductors 32 may be positioned with an interval therebetween.

[0033] The wiring substrate 1 may further include a third ground electrode Tg3 surrounding the third electrode T3 and a fourth ground electrode Tg4 surrounding the fourth electrode T4. The third ground electrode Tg3 and the fourth ground electrode Tg4 may be located on the first surface S1 of the insulating substrate 2 and connected to the ground film conductor 31 through the ground via conductor 32.

[0034] The wiring substrate 1 may further include a plurality of first ground electrodes Tg1 and a plurality of second ground electrodes Tg2 surrounding the first electrode T1 and the second electrode T2. The plurality of first ground electrodes Tg1 and the plurality of second ground electrodes Tg2 may be located on the second surface S2 and may be located around the first electrode T1 and the second electrode T2 with spaces between them.

[0035] The area of ​​each of the plurality of first ground electrodes Tg1 and the plurality of second ground electrodes Tg2 may be larger than the area of ​​each of the third ground electrode Tg3 and the fourth ground electrode Tg4. Also, the area of ​​the region surrounded by the first ground electrode Tg1 and the second ground electrode Tg2 may be larger than the area of ​​the region surrounded by the third ground electrode Tg3 and the fourth ground electrode Tg4. This configuration enables dense wiring connections on the first surface S1 and large wiring connections on the second surface S2. This configuration is such that electronic elements are connected to the third electrode T3 and the fourth electrode T4 on the first surface S1, and the first and fourth electrodes T1 and T4 on the second surface S2 are connected to the third and fourth electrodes T3 and T4 on the first surface S1. 2nd electrode T2 In a configuration in which the electrodes are connected to the electrodes of the module substrate, wiring connection becomes easy.

[0036] According to the wiring board 1 having the above configuration, wideband differential signals can be transmitted between the first surface S1 and the second surface S2 of the insulating substrate 2.

[0037] <Details of the First Line 10 and the Second Line 20> FIG. 2 is a planar perspective view of a main part of the wiring board according to the first embodiment seen from above. FIGS. 3A to 3C are cross-sectional views showing the third, fourth, and fifth to tenth layers, respectively, of the main part of FIG. 2. FIGS. 4A to 4C are cross-sectional views showing the eleventh, twelfth, and thirteenth layers, respectively, of the main part of FIG. 2. FIG. 5A is a cross-sectional view showing the fourteenth layer of the main part of FIG. 2. FIG. 5B is a diagram showing the back surface of the main part of FIG. 2. FIG. 5B depicts the back surface seen from above. FIG. 6A is a vertical cross-sectional view taken along line AA of FIG. 3B, FIG. 6B is a vertical cross-sectional view taken along line BB of FIG. 3B, FIG. 6C is a vertical cross-sectional view taken along line CC of FIG. 5A, and FIG. 6D is a vertical cross-sectional view taken along line DD of FIG. 5A.

[0038] In the following description, the first surface S1 (FIG. 1B) side will be referred to as the "upper side" and the second surface S2 side as the "lower side" in the thickness direction of the wiring board 1. In addition, in the direction in which the parallel line conductors (H1, H2) extend, the side where the third electrode T3 and the fourth electrode T4 are located will be referred to as the "left side," and the side where the first electrode T1 and the second electrode T2 are located will be referred to as the "right side."

[0039] The distance between the first conductor L1 and the third conductor L3 may gradually increase toward the right (FIG. 3B). The distance between the second conductor L2 and the fourth conductor L4 may gradually decrease toward the right (FIG. 4B). With this configuration, the distance between the second via conductor V2 and the fourth via conductor V4 is narrower than the distance between the first via conductor V1 and the third via conductor V3 (FIGS. 6B and 6C). This increases the inductance components of the first line 10 and the second line 20 near the first electrode T1 and the second electrode T2. This large inductance component cancels out the capacitance components of the first electrode T1 and the second electrode T2, resulting in excellent signal transmission characteristics from low to high frequencies.

[0040] The first conductor L1 and the third conductor L3 may have a configuration in which the distance between them increases toward the first via conductor V1 and the third via conductor V3 in a plan view. That is, the first conductor L1 may have, in a plan view, an arc or a circle convex toward the third conductor L3, an arc or a circle concave toward the third conductor L3, a broken line bent at a right angle or a certain angle at one or more locations, a stepped shape, or a combination of these shapes. Similarly, the third conductor L3 may have, in a plan view, an arc or a circle convex toward the first conductor L1, an arc or a circle concave toward the first conductor L1, a broken line bent at a right angle or a certain angle at one or more locations, a stepped shape, or a combination of these shapes.

[0041] Furthermore, the second conductor L2 and the fourth conductor L4 may have a configuration in which the distance between them decreases toward the second via conductor V2 and the fourth via conductor V4 in a plan view. That is, the second conductor L2 may have, in a plan view, an arc or a circle convex toward the fourth conductor L4 side, an arc or a circle concave toward the fourth conductor L4 side, a broken line bent at a right angle or a certain angle at one or more locations, a stepped shape, or a combination of these shapes. Similarly, the fourth conductor L4 may have, in a plan view, an arc or a circle convex toward the second conductor L2 side, an arc or a circle concave toward the second conductor L2 side, a broken line bent at a right angle or a certain angle at one or more locations, a stepped shape, or a combination of these shapes.

[0042] In the above configuration, the distance between the second via conductor V2 and the fourth via conductor V4 is smaller than the distance between the first via conductor V1 and the third via conductor V3, and the inductance components of the first line 10 and the second line 20 can be increased near the first electrode T1 and the second electrode T2. The large inductance components act to cancel out the capacitance components of the first electrode T1 and the second electrode T2, thereby achieving good signal transmission characteristics from low frequencies to high frequencies.

[0043] The first and third conductors L1 and L3 may be spaced apart from the second and fourth conductors L2 and L4 (FIGS. 6B and 6C). According to this configuration, the first and third via conductors V1 and V3 are located on a layer above the second and fourth conductors L2 and L4, and the second and fourth via conductors V2 and V4 are located on a layer below the second and fourth conductors L2 and L4. Therefore, the portions with large inductance components (the second and fourth via conductors V2 and V4, which are closely spaced apart) are closer to the first and second electrodes T1 and T2, which tends to cancel out the capacitance components of the first and second electrodes T1 and T2. This allows for better signal transmission characteristics across a wide frequency range.

[0044] The first line conductor L1 and the third line conductor L3 may be located closer to the first surface S1 than the center in the thickness direction of the insulating substrate 2. The second line conductor L2 and the fourth line conductor L4 may be located closer to the second surface S2 than the center in the thickness direction of the insulating substrate 2. With this configuration, the widely spaced first via conductor V1 and the third via conductor V3 are located over a long range including the center in the vertical direction of the insulating substrate 2, while the closely spaced second via conductor V2 and the fourth via conductor V4 are located closer to the first electrode T1 and the second electrode T2. Furthermore, the vertical lengths of the closely spaced second via conductor V2 and the fourth via conductor V4 are shorter than the vertical lengths of the widely spaced first via conductor V1 and the third via conductor V3. Therefore, the large inductance components associated with the second via conductor V2 and the fourth via conductor V4 act to cancel out the capacitive components associated with the first electrode T1 and the second electrode T2. On the other hand, it is possible to reduce the inductance component from interfering with impedance matching at locations distant from the first electrode T1 and the second electrode T2, thereby achieving better signal transmission characteristics from low frequencies to high frequencies.

[0045] The plurality of ground film conductors 31 may include a first ground film conductor 31a having a first opening O1 (FIGS. 4A and 1B) and a second ground film conductor 31b having a second opening O2 (FIGS. 4B-5A and 1B). The first via conductor V1 and the third via conductor V3 may be located within the first opening O1, and the third via conductor V3 and the fourth via conductor V4 may be located within the second opening O2. The first opening O1 may be smaller than the second opening O2. According to this configuration, the second via conductor V2 and the fourth via conductor V4, which have large inductance components, are located within the larger second opening O2, so that the second via conductor V2 and the fourth via conductor V4 can be further separated from the ground potential. Therefore, the capacitance components of the second via conductor V2 and the fourth via conductor V4, which have large inductance components, are reduced, and the effect of canceling out the capacitance components of the first electrode T1 and the second electrode T2 is enhanced. Therefore, the impedance can be better matched, and better signal transmission characteristics can be obtained from low frequencies to high frequencies.

[0046] The first electrode T1, the second electrode T2, the plurality of first ground electrodes Tg1, and the plurality of second ground electrodes Tg2 may have larger areas than the third electrode T3 and the fourth electrode T4. With this configuration, the capacitance component increases near the first electrode T1 and the second electrode T2, but the increase in inductance caused by the first via conductor V1 and the third via conductor V3, which are arranged at close intervals, can offset this increase in capacitance component. Therefore, according to the wiring board 1 of the first embodiment, the first electrode T1, the second electrode T2, the plurality of first ground electrodes Tg1, and the plurality of second ground electrodes Tg2 can be enlarged without impairing the signal transmission characteristics, thereby improving the ease of mounting on the second surface S2 side.

[0047] In a planar perspective view, the center P1 of the first opening O1 (corresponding to the central portion) may be located between the center P2 of the second opening O2 (corresponding to the central portion) and the first and second parallel line conductors H1 and H2 (FIG. 2). With this configuration, the first and third via conductors V1 and V3 can be arranged near the center of the first opening O1, and the second and fourth via conductors V2 and V4 can be arranged near the center of the second opening O2. This allows impedance matching at the first opening O1 and the second opening O2, resulting in better signal transmission characteristics.

[0048] The second opening O2 of the ground film conductor 31 on the 14th layer y14 may be referred to as the third opening O3 (FIG. 5A). At least a portion of the n-th via conductor Vn connected to the first electrode T1 and the (n+1)-th via conductor Vn+1 connected to the second electrode T2 are located within the third opening O3. In the first embodiment, the third opening O3 has the same size and position as the second opening O2 located on a layer above the 14th layer y14 in a perspective plan view. However, the second opening O2 and the third opening O3 may differ in size and position in a perspective plan view. The third opening O3 may be larger than the first opening O1. The third opening O3 may be smaller, larger, or the same size as the second opening O2.

[0049] The first via conductor V1 and the third via conductor V3 may be located at the center of the first opening O1 in the left-right direction (corresponding to the X direction in the present disclosure). The nth via conductor Vn and the (n+1)th via conductor Vn+1 may be located at the center of the third opening O3 in the left-right direction. With this configuration, in the first opening O1 and the third opening O3, the ground conductors are located symmetrically with respect to the conductors through which signals are transmitted, thereby achieving better impedance matching.

[0050] Of the via conductors (i-th via conductor Vi, first via conductor V1, second via conductor V2, and n-th via conductor Vn) of the first line 10, the first via conductor counting from the side closest to the first electrode T1 is the n-th via conductor Vn, and the second via conductor is the second via conductor V2 (corresponding to the (n+2)th via conductor according to the present disclosure). Similarly, of the via conductors (i+1)th via conductor Vi+1, third via conductor V3, fourth via conductor V4, and n+1) via conductor Vn+1 of the second line 20, the first via conductor counting from the side closest to the second electrode T2 is the (n+1)th via conductor Vn+1, and the second via conductor is the fourth via conductor V4 (corresponding to the (n+3)th via conductor according to the present disclosure). Furthermore, the distance between the second via conductor V2 and the fourth via conductor V4, which are the second closest to the first electrode T1 and the second electrode T2, may be narrower than the distance between the nth via conductor Vn and the n+1th via conductor Vn+1, which are the first closest to the first electrode T1 and the second electrode T2.

[0051] According to this configuration, the second via conductor V2 and the fourth via conductor V4 (corresponding to the (n+2)th and (n+3)th via conductors according to the present disclosure) that are closely spaced can be arranged near the first electrode T1 and the second electrode T2. Therefore, the large inductance components associated with the second via conductor V2 and the fourth via conductor V4 act to cancel out the capacitance components associated with the first electrode T1 and the second electrode T2. Meanwhile, the effect of the inductance components causing impedance mismatch at locations distant from the first electrode T1 and the second electrode T2 can be reduced. Therefore, better signal transmission characteristics can be obtained from low to high frequencies. Furthermore, while increasing the areas of the first electrode T1 and the second electrode T2, the nth via conductor Vn can be brought closer to the center of the first electrode T1, and the (n+1)th via conductor Vn+1 can be brought closer to the center of the second electrode T2. Therefore, better signal transmission characteristics can be obtained.

[0052] <Signal transmission characteristics> 7A and 7B are graphs showing the reflection loss and insertion loss of the wiring board 1 according to the first embodiment and the comparative example, respectively. The graphs in FIGS. 7A and 7B show simulation results for the wiring board 1 according to the first embodiment and the wiring board according to the comparative example. The wiring board according to the comparative example has a configuration in which the following components 1 to 4 are changed from the configuration of the first embodiment. Component 1: The second line conductor L2, the second via conductor V2, the nth line conductor Ln, the nth via conductor Vn, the fourth line conductor L4, the fourth via conductor V4, the n+1th line conductor Ln+1, and the n+1th via conductor Vn+1 are removed. Component 2: In a planar perspective view, the first via conductor V1 of the first embodiment is located at the center of the first electrode T1, and the first via conductor V1 extends to the first electrode T1. Component 3: In a planar perspective view, the second via conductor V2 is located at the center of the second electrode T2, and the second via conductor V2 extends to the second electrode T2. Element 4: In a planar perspective view, the center of the first opening O1, the center of the second opening O2, the center of the first via conductor V1, and the center of the second via conductor V2 overlap.

[0053] The simulation results in Figures 7A and 7B show that, compared to the comparative example, the reflection loss of the wiring board 1 of embodiment 1 is small even in high frequency bands, and the insertion loss of embodiment 1 is small even in high frequency bands, and therefore good signal transmission characteristics can be obtained from low to high frequencies.

[0054] The wiring board 1 of the first embodiment has been described above with reference to the drawings. However, the wiring board 1 of the first embodiment is not limited to the configuration shown in the drawings. For example, in the wiring board 1, the distance between the second via conductor V2 and the fourth via conductor V4 may be larger, the same as, or smaller than the distance between the first parallel line conductor H1 and the second parallel line conductor H2. Furthermore, the distance between the first via conductor V1 and the third via conductor V3 may be larger, the same as, or smaller than the distance between the n-th via conductor Vn and the (n+1)-th via conductor Vn+1. Furthermore, in the first embodiment, an example has been shown in which the second line conductor L2 and the fourth line conductor L4 are located on the twelfth layer y12, and the n-th line conductor Ln and the (n+1)-th line conductor Ln+1 are located on the fourteenth layer y14. However, the second line conductor L2 and the fourth line conductor L4 may be located on any of the eighth layer y8 to the thirteenth layer y13, and the nth line conductor Ln and the (n+1)th line conductor Ln+1 may be located on any of the ninth layer y9 to the thirteenth layer y13, which is a layer below the second line conductor L2 and the fourth line conductor L4. In the first embodiment, the first line 10 and the second line 20 are connected between the first parallel line conductor H1 and the second parallel line conductor H2. top and bottom Although an example of plane symmetry with respect to a plane extending in the vertical and horizontal directions has been shown, it is also possible to have portions that are not plane symmetric. Furthermore, instead of the stripline structure described in the first embodiment, a so-called microstripline structure may be used in which the third electrode T3 is connected to the ith line conductor Li and the first parallel line conductor H1 on the first surface S1 except for the ith via conductor Vi, and similarly the fourth electrode T4 is connected to the (i+1)th line conductor Li+1 and the second parallel line conductor H2 on the first surface S1 except for the (i+1)th via conductor Vi+1. This also applies to the second embodiment described below.

[0055] (Embodiment 2) FIG. 8A is a planar perspective view showing a main portion of a wiring board according to a second embodiment of the present disclosure. FIG. 8B is a longitudinal cross-sectional view of a main portion of the wiring board according to the second embodiment of the present disclosure, taken along a signal line. FIGS. 9A to 9C are cross-sectional views showing the third, fourth, and fifth to ninth layers, respectively, of the main portion of FIG. 8A. FIGS. 10A to 10C are cross-sectional views showing the tenth, eleventh, and twelfth layers, respectively, of the main portion of FIG. 8A. FIGS. 11A and 11B are cross-sectional views showing the thirteenth and fourteenth layers, respectively, of the main portion of FIG. 8A. FIG. 11C is a view showing the back surface of the main portion of FIG. 8A. FIG. 11C is a perspective view of the back surface from above. FIG. 12A is a longitudinal cross-sectional view taken along line AA in FIG. 9B. FIG. 12B is a longitudinal cross-sectional view taken along line BB in FIG. 9B. FIG. 12C is a longitudinal cross-sectional view taken along line CC in FIG. 10C. Fig. 13A is a longitudinal cross-sectional view taken along line DD in Fig. 10C, Fig. 13B is a longitudinal cross-sectional view taken along line EE in Fig. 11B, and Fig. 13C is a longitudinal cross-sectional view taken along line FF in Fig. 11B.

[0056] The wiring board 1A of embodiment 2 includes an insulating substrate 2, a first line 10A and a second line 20A located on the insulating substrate 2 and adjacent to each other, and a plurality of ground film conductors 31 and a plurality of ground via conductors 32 located on the insulating substrate 2 and surrounding the first line 10A and the second line 20A.

[0057] The first line 10A is similar to the first line 10 of embodiment 1 from the third electrode T3 to the second conductor L2 and from the first electrode T1 to the n-th conductor Ln. The second line 20A is similar to the second line 20 of embodiment 1 from the fourth electrode T4 to the fourth conductor L4 and from the second electrode T2 to the (n+1)th conductor Ln+1. Similar components are denoted by the same reference numerals as in embodiment 1, and detailed description thereof will be omitted.

[0058] The first line 10A may include a second via conductor V2, a fifth via conductor L5, a fifth via conductor V5, a sixth via conductor L6, and a sixth via conductor V6 between the second conductor L2 and the nth conductor Ln. The right portion of the second conductor L2 may be connected to the upper portion of the second via conductor V2, the lower portion of the second via conductor V2 may be connected to the left portion of the fifth conductor L5, and the right portion of the fifth conductor L5 may be connected to the upper portion of the fifth via conductor V5. Furthermore, the left portion of the sixth conductor L6 may be connected to the lower portion of the fifth via conductor V5, the right portion of the sixth conductor L6 may be connected to the upper portion of the sixth via conductor V6, and the lower portion of the sixth via conductor V6 may be connected to the left portion of the nth conductor Ln. The above right portion, left portion, upper portion, and lower portion may be rephrased as the right end, left end, upper end, and lower end, respectively.

[0059] The second line 20A may include a fourth via conductor V4, a seventh line conductor L7, a seventh via conductor V7, an eighth line conductor L8, and an eighth via conductor V8 between the fourth line conductor L4 and the (n+1)th line conductor Ln+1. The right portion of the fourth line conductor L4 may be connected to the upper portion of the fourth via conductor V4, the lower portion of the fourth via conductor V4 may be connected to the left portion of the seventh line conductor L7, and the right portion of the seventh line conductor L7 may be connected to the upper portion of the seventh via conductor V7. Furthermore, the left portion of the eighth line conductor L8 may be connected to the lower portion of the seventh via conductor V7, the right portion of the eighth line conductor L8 may be connected to the upper portion of the eighth via conductor V8, and the lower portion of the eighth via conductor V8 may be connected to the left portion of the (n+1)th line conductor Ln+1. The above right portion, left portion, upper portion, and lower portion may be rephrased as the right end, left end, upper end, and lower end, respectively.

[0060] The second conductor L2 and the fourth conductor L4 (FIG. 10B) may be located on the eleventh layer y11, with the distance therebetween gradually narrowing toward the right. The fifth conductor L5 and the seventh conductor L7 (FIG. 10C) may be located on the twelfth layer y12, with the distance therebetween gradually widening toward the right. The sixth conductor L6 and the eighth conductor L8 (FIG. 11A) may be located on the thirteenth layer y13, with the distance therebetween gradually narrowing toward the right. With this configuration, the distance between the second via conductor V2 and the fourth via conductor V4 is narrower than the distance between the first via conductor V1 and the third via conductor V3, and the inductance component can be increased in the area of ​​the second via conductor V2 and the fourth via conductor V4. Furthermore, the distance between the sixth via conductor V6 and the eighth via conductor V8 is narrower than the distance between the fifth via conductor V5 and the seventh via conductor V7, and the inductance component can be increased in the sixth via conductor V6 and the eighth via conductor V8. Therefore, the large inductance component cancels out the capacitance component of the first electrode T1 and the second electrode T2, thereby achieving good signal transmission characteristics from low to high frequencies.

[0061] Furthermore, with the above configuration, the wiring board 1A has multiple locations where the spacing between the via conductors can be narrowed (the spacing between the second via conductor V2 and the fourth via conductor V4, and the spacing between the sixth via conductor V6 and the eighth via conductor V8). This increases the degree of freedom in adjusting impedance when designing the wiring board 1A. This facilitates impedance matching, making it easier to achieve good signal transmission characteristics.

[0062] The second conductor L2 and the fourth conductor L4 may have a configuration in which the distance between them decreases toward the second via conductor V2 and the fourth via conductor V4 in a plan view. That is, the second conductor L2 may have an arc or circular convex shape toward the fourth conductor L4 side, an arc or circular convex shape toward the fourth conductor L4 side, a broken line shape bent at a right angle or a certain angle at one or more locations, a stepped shape, or a combination of these shapes in a plan view. Similarly, the fourth conductor L4 may have an arc or circular convex shape toward the second conductor L2 side, an arc or circular convex shape toward the second conductor L2 side, an arc or circular convex shape toward the second conductor L2 side, a broken line shape bent at a right angle or a certain angle at one or more locations, a stepped shape, or a combination of these shapes in a plan view.

[0063] Furthermore, the fifth conductor L5 and the seventh conductor L7 may have a configuration in which the distance between them increases toward the fifth via conductor V5 and the seventh via conductor V7 in a plan view. That is, the fifth conductor L5 may have, in a plan view, an arc or a circle convex toward the seventh conductor L7, an arc or a circle concave toward the seventh conductor L7, a broken line bent at a right angle or a certain angle at one or more locations, a stepped shape, or a combination of these shapes. Similarly, the seventh conductor L7 may have, in a plan view, an arc or a circle convex toward the fifth conductor L5, an arc or a circle concave toward the fifth conductor L5, a broken line bent at a right angle or a certain angle at one or more locations, a stepped shape, or a combination of these shapes.

[0064] Furthermore, the sixth conductor L6 and the eighth conductor L8 may have a configuration in which the distance between them becomes smaller toward the sixth via conductor V6 and the eighth via conductor V8 in a plan view. That is, the sixth conductor L6 may have, in a plan view, an arc or a circle convex toward the eighth conductor L8, an arc or a circle concave toward the eighth conductor L8, a broken line bent at a right angle or a certain angle at one or more locations, a stepped shape, or a combination of these shapes. Similarly, the eighth conductor L8 may have, in a plan view, an arc or a circle convex toward the sixth conductor L6, an arc or a circle concave toward the sixth conductor L6, a broken line bent at a right angle or a certain angle at one or more locations, a stepped shape, or a combination of these shapes.

[0065] Even in the above configuration, the distance between the second via conductor V2 and the fourth via conductor V4 is narrower than the distance between the first via conductor V1 and the third via conductor V3, thereby increasing the inductance component in the area between the second via conductor V2 and the fourth via conductor V4. Furthermore, the distance between the sixth via conductor V6 and the eighth via conductor V8 is narrower than the distance between the fifth via conductor V5 and the seventh via conductor V7, thereby increasing the inductance component in the area between the sixth via conductor V6 and the eighth via conductor V8. Therefore, the large inductance component cancels out the capacitance component of the first electrode T1 and the second electrode T2, thereby achieving good signal transmission characteristics from low to high frequencies. Furthermore, the degree of freedom in adjusting impedance during the design of the wiring board 1A is improved.

[0066] Of the via conductors of the first line 10A (the i-th via conductor Vi, the first via conductor V1, the second via conductor V2, the fifth via conductor V5, the sixth via conductor V6, and the n-th via conductor Vn), the first via conductor counting from the side closest to the first electrode T1 is the n-th via conductor Vn, and the second via conductor is the sixth via conductor V6 (corresponding to the (n+2)th via conductor according to the present disclosure). Similarly, of the via conductors of the second line 20A (the (i+1)th via conductor Vi+1, the third via conductor V3, the fourth via conductor V4, the seventh via conductor V7, the eighth via conductor V8, and the (n+1)th via conductor Vn+1), the first via conductor counting from the side closest to the second electrode T2 is the (n+1)th via conductor Vn+1, and the second via conductor is the eighth via conductor V8 (corresponding to the (n+3)th via conductor according to the present disclosure). Furthermore, the distance between the sixth via conductor V6 and the eighth via conductor V8, which are second from the side closest to the first electrode T1 and the second electrode T2, may be narrower than the distance between the nth via conductor Vn and the n+1th via conductor Vn+1, which are first from the side closest to the first electrode T1 and the second electrode T2.

[0067] According to this configuration, the sixth via conductor V6 and the eighth via conductor V8 (corresponding to the (n+2)th and (n+3)th via conductors according to the present disclosure) that are closely spaced can be arranged close to the first electrode T1 and the second electrode T2. Therefore, the large inductance components associated with the sixth via conductor V6 and the eighth via conductor V8 act to cancel out the capacitance components associated with the first electrode T1 and the second electrode T2. On the other hand, the large inductance components associated with the sixth via conductor V6 and the eighth via conductor V8 can be prevented from interfering with impedance matching at locations distant from the first electrode T1 and the second electrode T2. Therefore, better signal transmission characteristics can be obtained from low frequencies to high frequencies.

[0068] Similar to the first embodiment, the plurality of ground film conductors 31 are located on the second layer y2 to the fourteenth layer y14 of the insulating substrate 2. Furthermore, the openings Oi and Oh included in the plurality of ground film conductors 31 are similar to those of the first embodiment. Furthermore, the plurality of ground film conductors 31 according to the second embodiment may include a first ground film conductor 31a having a first opening O1 (FIGS. 8B, 9C, 10A), a second ground film conductor 31b having a second opening O2 (FIGS. 8B, 10B-11A), and a third ground film conductor 31c having a third opening O3 (FIGS. 8B, 11B).

[0069] The first opening O1 may be located in a layer (the fifth layer y5 to the tenth layer y10) through which the first via conductor V1 and the third via conductor V3 pass or are located. The second opening O2 may be located in a layer (the eleventh layer y11 to the thirteenth layer y13) through which the second via conductor V2 and the fourth via conductor V4, the fifth via conductor V5 and the seventh via conductor V7, the sixth via conductor V6 and the eighth via conductor V8 pass or are located. The third opening O3 may be located in a layer (the fourteenth layer y14) one layer above the layer on which the electrodes (T1, T2, Tg1, Tg2) are located.

[0070] The first opening O1 may have a size that achieves impedance matching in the first via conductor V1 and the third via conductor V3.

[0071] The third opening O3 may have a size corresponding to the arrangement of the multiple first ground electrodes Tg1 and the multiple second ground electrodes Tg2 so that the multiple first ground electrodes Tg1 and the multiple second ground electrodes Tg2 can be connected to the third ground film conductor 31c via the multiple ground via conductors 32.

[0072] The second opening O2 may be larger than the first opening O1. The second opening O2 may be larger than the third opening O3, may be the same size as the third opening O3, or may be smaller than the third opening O3.

[0073] Because the second opening O2 is larger than the first opening O1, the second via conductor V2 and the fourth via conductor V4, and the sixth via conductor V6 and the eighth via conductor V8, which have large inductance components, can be further separated from the ground potential. Therefore, the capacitance components of the second via conductor V2 and the fourth via conductor V4, and the sixth via conductor V6 and the eighth via conductor V8 become smaller, and the effect of canceling out the capacitance components of the first electrode T1 and the second electrode T2 becomes stronger.

[0074] In a planar perspective view (FIG. 8A), the center P1 of the first opening O1 (corresponding to the central portion) may be located between the center P2 of the second opening O2 (corresponding to the central portion) and the first and second parallel line conductors H1 and H2. With this configuration, the first and third via conductors V1 and V3 can be arranged near the center of the first opening O1, and the second and fourth via conductors V2 and V4 can be arranged near the center of the second opening O2. This allows impedance matching at the first opening O1 and the second opening O2 to be achieved, resulting in better signal transmission characteristics.

[0075] In a planar perspective view (FIG. 8A), the center P2 of the second opening O2 may be located between the center P3 of the third opening O3 and the center P1 of the first opening O1. With this configuration, the second via conductor V2 and the fourth via conductors V4 to V8 can be arranged near the center of the second opening O2, and the nth via conductor Vn and the (n+1)th via conductor Vn+1 can be arranged near the center of the third opening O3. This allows impedance matching at the second opening O2 and the third opening O3 to be achieved, resulting in better signal transmission characteristics.

[0076] The first via conductor V1 and the third via conductor V3 may be located at the center of the first opening O1 in the left-right direction (corresponding to the X direction in the present disclosure). The nth via conductor Vn and the (n+1)th via conductor Vn+1 may be located at the center of the third opening O3 in the left-right direction. With this configuration, in the first opening O1 and the third opening O3, the ground conductors are located symmetrically with respect to the conductors through which signals are transmitted, thereby achieving better impedance matching.

[0077] The wiring board 1A of the second embodiment has been described above with reference to the drawings. However, the wiring board 1A of the second embodiment is not limited to the configuration shown in the drawings. For example, in the wiring board 1A, the distance between the first parallel line conductor H1 and the second parallel line conductor H2, the distance between the second via conductor V2 and the fourth via conductor V4, and the distance between the sixth via conductor V6 and the eighth via conductor V8 may all be the same, all different, or some may be the same and the rest different. The order of the sizes of the above three distances may be any order. Furthermore, in the wiring board 1A, the distance between the first via conductor V1 and the third via conductor V3, the distance between the fifth via conductor V5 and the seventh via conductor V7, and the distance between the nth via conductor Vn and the (n+1)th via conductor Vn+1 may all be the same, all different, or some may be the same and the rest different. The order of the sizes of the above three distances may be any order.

[0078] (Embodiment 3) Fig. 15A is a planar perspective view showing a wiring board according to embodiment 3 of the present disclosure, Fig. 15B is a longitudinal cross-sectional view of the wiring board according to embodiment 3 cut along a signal line, and Fig. 16 is a planar perspective view of a main part of the wiring board according to embodiment 3 seen from above.

[0079] The wiring board 1B of the third embodiment is an example in which, in a plan view, the center P1 (corresponding to the central portion) of the first opening O1B is located to the right of the center P2 (corresponding to the central portion) of the second opening O2B. The wiring board 1B of the third embodiment differs from the first or second embodiment mainly in the relative arrangement of the first and second openings O1B and O2B, and the paths of the first and second lines 10B and 20B, but other elements may be similar to those of the first or second embodiment.

[0080] As described above, in a plan view, the center P1 of the first opening O1B is O2BThe center P2 of the second opening O2B may be located to the right of the center P2 of the first opening O1B. In other words, in a plan view, the center P2 of the second opening O2B may be located between the center P1 of the first opening O1B and the point P11 on the parallel line side. The point P11 on the parallel line side refers to the center P11 of the intersection between the edge of the second opening O2B and the first parallel line conductor H1 and the intersection between the edge of the second opening O2B and the second parallel line conductor H2. The first parallel line conductor H1 and the second parallel line conductor H2 may be parallel. The first parallel line conductor H1 and the second parallel line conductor H2 may be straight or partially curved. Even when the above arrangement is adopted, good signal transmission characteristics can be obtained from low frequencies to high frequencies.

[0081] In order to realize the above-described arrangement of the first opening O1B, the first via conductor V1 and the third via conductor V3 are arranged in a plane view such that the second via conductor V2 and the fourth via conductor V3 are arranged in a plane view such that ... conductor The nth via conductor Vn and the n+1th via conductor Vn+1 are located to the right of the second via conductor V2 and the fourth via conductor V4. As in the first and second embodiments, the distance between the first via conductor V1 and the third via conductor V3 is wider than the distance between the second via conductor V2 and the fourth via conductor V4. Furthermore, in a plan view, the nth via conductor Vn and the n+1th via conductor Vn+1 are located to the left of the second via conductor V2 and the fourth via conductor V4. The distance between the nth via conductor Vn and the n+1th via conductor Vn+1 is wider than the distance between the second via conductor V2 and the fourth via conductor V4.

[0082] The second conductor L2 and the fourth conductor L4 extend between the lower end of the first via conductor V1 and the upper end of the second via conductor V2, and between the lower end of the third via conductor V3 and the upper end of the fourth via conductor V4, respectively. That is, the second conductor L2 and the fourth conductor L4 extend so that the distance between them narrows toward the left. Furthermore, the nth conductor Ln and the (n+1)th conductor Ln+1 extend between the lower end of the third via conductor V3 and the upper end of the nth via conductor Vn, and between the lower end of the fourth via conductor V4 and the (n+1)th Beer The nth line conductor Ln and the (n+1)th line conductor Ln+1 extend between the upper ends of the conductors Vn+1 and Vn+1, respectively. That is, the nth line conductor Ln and the (n+1)th line conductor Ln+1 extend such that the gap between them increases toward the left.

[0083] In plan view, the first conductor L1 may overlap part or all of the second conductor L2, and the third conductor L3 may overlap part or all of the fourth conductor L4.

[0084] The wiring board 1B of the third embodiment also provides good signal transmission characteristics from low frequencies to high frequencies.

[0085] In the third embodiment, the first opening O1B and the second opening O2B each include two via conductors, two line conductors, and two step portions (see FIG. 15B) connected to the via conductors in the first line 10B and the second line 20B. However, four or more step portions may be included in each of the first and second lines. This configuration can also be configured such that the first via conductor V1 and the third via conductor V3 are located to the right of the n-th via conductor Vn and the (n+1)-th via conductor Vn+1 in a plan view. This configuration can also achieve good signal transmission characteristics from low to high frequencies.

[0086] (Embodiment 4) Fig. 17A is a planar perspective view showing a wiring board according to a fourth embodiment of the present disclosure. Fig. 17B is a longitudinal cross-sectional view of the wiring board according to the fourth embodiment cut along a signal line. Fig. 18 is a planar perspective view showing a main part of the wiring board according to the fourth embodiment seen from above. Figs. 19A to 19H are views showing the third, fourth, fifth to tenth, eleventh, twelfth, thirteenth, and fourteenth layers and the back surface of the main part of Fig. 18.

[0087] The wiring board 1C of the fourth embodiment is an example in which, in a plan view, the center P1 (corresponding to the central portion) of the first opening O1C coincides with the center P2 (corresponding to the central portion) of the second opening O2C. "Coincidence" does not necessarily mean exact coincidence, but also includes cases in which the difference in position is equal to or less than the minimum diameter of the via conductor. The fourth embodiment differs from the first, second, and third embodiments mainly in the relative arrangement of the first opening O1C and the second opening O2C, and the paths of the first line 10C and the second line 20C, but other elements may be similar to the first, second, and third embodiments.

[0088] As described above, in a plan view, the center P1 of the first opening O1C is O2C Even when this arrangement is adopted, good signal transmission characteristics can be obtained from low frequencies to high frequencies.

[0089] In order to realize the above-described arrangement of the first opening O1C, the second via conductor V2 and the fourth via conductor V3 are conductor V4 is positioned offset in the left-right direction from the first via conductor V1 and the third via conductor V3. As in the first and second embodiments, the distance between the first via conductor V1 and the third via conductor V3 is wider than the distance between the second via conductor V2 and the fourth via conductor V4. Furthermore, in a plan view, the n-th via conductor Vn and the (n+1)-th via conductor Vn+1 are positioned offset in the left-right direction from the second via conductor V2 and the fourth via conductor V4, and are positioned so as to overlap with the first via conductor V1 and the third via conductor V3, respectively. The distance between the n-th via conductor Vn and the (n+1)-th via conductor Vn+1 is wider than the distance between the second via conductor V2 and the fourth via conductor V4.

[0090] The second line conductor L2 and the fourth line conductor L4 extend between the lower end of the first via conductor V1 and the upper end of the second via conductor V2, and between the lower end of the third via conductor V3 and the upper end of the fourth via conductor V4, respectively. That is, the second line conductor L2 and the fourth line conductor L4 extend so that the distance between them becomes narrower as they approach the second via conductor V2 and the fourth via conductor V4. Furthermore, the nth line conductor Ln and the (n+1)th line conductor Ln+1 extend between the lower end of the second via conductor V2 and the upper end of the nth via conductor Vn, and between the lower end of the fourth via conductor V4 and the (n+1)th line conductor Ln+1. Beer That is, the nth line conductor Ln and the n+1st line conductor Ln+1 extend so that the spacing between them becomes wider as they approach the nth via conductor Vn and the n+1st via conductor Vn+1.

[0091] In plan view, the second conductor L2 may overlap part or all of the n-th conductor Ln, and the fourth conductor L4 may overlap part or all of the (n+1)-th conductor Ln+1.

[0092] The wiring board 1C of the fourth embodiment also provides good signal transmission characteristics from low frequencies to high frequencies.

[0093] In the first and second openings O1C and O2C of the fourth embodiment, two via conductors, two line conductors, and two step portions (see FIG. 17B) connected to the via conductors are included in each of the first and second lines 10C and 20C, respectively. However, a configuration in which four or more step portions are included in each of the first and second lines 10C and 20C and the n-th and n+1-th via conductors Vn and Vn+1 overlap with the first and second via conductors V1 and V2 in plan view may also be employed. Even with this configuration, good signal transmission characteristics can be obtained from low to high frequencies.

[0094] (Embodiment 5) Fig. 20A is a plan perspective view showing a wiring board according to a fifth embodiment of the present disclosure, and Fig. 20B is a longitudinal cross-sectional view of the wiring board according to the fifth embodiment taken along a signal line.

[0095] Similar to the fourth embodiment, the wiring board 1D of the fifth embodiment is an example in which, in a plan view, the center P1 (corresponding to the central portion) of the first opening O1D coincides with the center P2 (corresponding to the central portion) of the second opening O2D. Furthermore, the wiring board 1D of the fifth embodiment is an example in which, in the first opening O1D, the first line 10D and the second line 20D each include four via conductors, line conductors, and step portions (see FIG. 20B) connected to the via conductors. The fifth embodiment differs from the first, second, and third embodiments mainly in the relative arrangement of the first opening O1D and the second opening O2D and the paths of the first line 10D and the second line 20D, but other elements may be similar to the first, second, and third embodiments.

[0096] As described above, in a plan view, the center P1 of the first opening O1D is O2D Even when this arrangement is adopted, good signal transmission characteristics can be obtained from low frequencies to high frequencies.

[0097] As in the wiring board 1D of embodiment 5, the first via conductor V1, the fifth via conductor V5, and the n-th via conductor Vn may overlap in a planar view. Similarly, the third via conductor V3, the seventh via conductor V7, and the (n+1)-th via conductor Vn+1 may overlap in a planar view. Furthermore, the second via conductor V2 and the fourth via conductor V4 may be positioned offset from the first via conductor V1 and the third via conductor V3 in the left-right direction in a planar view. The distance between the second via conductor V2 and the fourth via conductor V4 may be narrower than the distance between the first via conductor V1 and the third via conductor V3.

[0098] Furthermore, the sixth via conductor V6 and the eighth via conductor V8 may be positioned offset in the left-right direction from the first via conductor V1 and the third via conductor V3. The sixth via conductor V6 and the eighth via conductor V8 may be positioned offset on the opposite side in the left-right direction from the second via conductor V2 and the fourth via conductor V4. The distance between the sixth via conductor V6 and the eighth via conductor V8 may be narrower than the distance between the first via conductor V1 and the third via conductor V3.

[0099] The second conductor L2 and the fourth conductor L4 extend between the lower end of the first via conductor V1 and the upper end of the second via conductor V2, and between the lower end of the third via conductor V3 and the upper end of the fourth via conductor V4, respectively. That is, the second conductor L2 and the fourth conductor L4 extend such that the distance between them decreases as they approach the second via conductor V2 and the fourth via conductor V4. Furthermore, the fifth conductor L5 and the seventh conductor L7 extend between the lower end of the second via conductor V2 and the upper end of the fifth via conductor V5, and between the lower end of the fourth via conductor V4 and the upper end of the seventh via conductor V7, respectively. That is, the distance between them increases as they approach the fifth via conductor V5 and the seventh via conductor V7.

[0100] In plan view, the second conductor L2 may overlap part or all of the fifth conductor L5, and the fourth conductor L4 may overlap part or all of the seventh conductor L7.

[0101] Furthermore, the sixth line conductor L6 and the eighth line conductor L8 extend between the lower end of the fifth via conductor V5 and the upper end of the sixth via conductor V6, and between the lower end of the seventh via conductor V7 and the upper end of the eighth via conductor V8, respectively. That is, the sixth line conductor L6 and the eighth line conductor L8 extend such that the distance between them becomes narrower as they are closer to the sixth via conductor V6 and the eighth via conductor V8. Furthermore, the nth line conductor Ln and the (n+1)th line conductor Ln+1 extend between the lower end of the sixth via conductor V6 and the upper end of the nth via conductor Vn, and between the lower end of the eighth via conductor V8 and the upper end of the (n+1)th via conductor Vn+1, respectively. That is, the nth line conductor Ln and the (n+1)th line conductor Ln+1 extend such that the distance between them becomes wider as they are closer to the nth via conductor Vn and the (n+1)th via conductor Vn+1.

[0102] In plan view, the sixth conductor L6 may overlap part or all of the nth conductor Ln, and the eighth conductor L8 may overlap part or all of the (n+1)th conductor Ln+1.

[0103] The wiring board 1D of the fifth embodiment also provides good signal transmission characteristics from low frequencies to high frequencies.

[0104] (Electronic Devices and Electronic Modules) 14 is a diagram showing an electronic device and an electronic module according to an embodiment of the present disclosure. An electronic device 80 according to this embodiment includes a wiring board 1 and an electronic element 82 mounted on the wiring board 1. The wiring board 1 may be replaced with wiring boards 1A to 1D. The electronic element 82 is an element that inputs, outputs, or inputs and outputs a high-frequency signal, and is electrically connected to the third electrode T3 and the fourth electrode T4 of the wiring board 1. The electronic element 82 may be a semiconductor element. The high-frequency signal may be a differential signal.

[0105] The electronic module 100 according to this embodiment includes a module substrate 110 and an electronic device 80 mounted on the module substrate 110. In addition to the electronic device 80, other electronic devices, electronic elements, electric elements, etc. may be mounted on the module substrate 110. The module substrate 110 has a plurality of electrodes 111 on a portion where the electronic device 80 is mounted, and the plurality of electrodes 111 may be connected to the first electrode T1, the second electrode T2, the first ground electrode Tg1, and the second ground electrode Tg2 of the wiring substrate 1 via conductive bonding materials 113, respectively.

[0106] The electronic device 80 and electronic module 100 according to this embodiment can obtain good characteristics from low frequencies to high frequencies by using the wiring board 1 (or wiring boards 1A to 1D) that has a wide bandwidth. [Industrial Applicability]

[0107] The present disclosure can be used for wiring boards, electronic devices, and electronic modules. [Explanation of symbols]

[0108] 1, 1A~1D wiring board 2. Insulating substrate S1 1st page S2 side 2 T1 1st electrode T2 2nd electrode T3 3rd electrode T4 4th electrode Tg1 1st ground electrode Tg2 2nd ground electrode Tg3 3rd ground electrode Tg4 4th ground electrode 10, 10A 1st line Vi i-th via conductor Li i-th line conductor H1 First parallel line conductor L1 First line conductor V1 First via conductor L2 Second line conductor V2 Second via conductor L5 Fifth line conductor V5 Fifth via conductor L6 6th line conductor V6 6th via conductor Ln nth line conductor Vn nth via conductor 20, 20A second line Vi+1 (i+1)th via conductor Li+1 (i+1)th line conductor H2 Second parallel line conductor L3 Third line conductor V3 Third via conductor L4 Fourth line conductor V4 Fourth via conductor L7 Seventh line conductor V7 Seventh via conductor L8 8th line conductor V8 8th via conductor Ln+1 (n+1)th line conductor Vn+1 (n+1)th via conductor 31, 31h, 31i Grounding film conductor 31a First ground film conductor 31b Second ground film conductor 31c Third ground film conductor 32 Ground via conductor O1, O1B~O1D First opening O2, O2B~O2D Second opening O3 Third opening P1, P2, P3 center (center) 80 Electronic equipment 82 Electronic Elements 100 Electronic Modules 110 Module board

Claims

1. an insulating substrate; a first line and a second line located on the insulating substrate and adjacent to each other; a ground film conductor and a ground via conductor located on the insulating substrate and surrounding the first line and the second line; Equipped with The first line is a first line conductor; a first via conductor connected to the first line conductor; a second line conductor connected to the first via conductor and extending to an opposite side of the first line conductor across the first via conductor in a planar perspective view; and a second via conductor connected to the second line conductor and extending to a layer different from a layer on which the first via conductor is located; The second line is a third line conductor; a third via conductor connected to the third line conductor; a fourth line conductor connected to the third via conductor and extending to an opposite side of the third line conductor across the third via conductor in a planar perspective view; and a fourth via conductor connected to the fourth line conductor and extending to a layer different from a layer on which the third via conductor is located; In a planar perspective view, the first line conductor and the third line conductor have a portion where the distance therebetween increases toward the first via conductor and the third via conductor, and the second line conductor and the fourth line conductor have a portion where the distance therebetween decreases toward the second via conductor and the fourth via conductor, The ground film conductor is a first ground film conductor having a first opening; a second ground film conductor having a second opening; Including, At least a portion of the first via conductor and the third via conductor is located within the first opening; at least a portion of the second via conductor and the fourth via conductor is located within the second opening; The first opening is smaller than the second opening. Wiring board.

2. an insulating substrate; a first line and a second line located on the insulating substrate and adjacent to each other; a ground film conductor and a ground via conductor located on the insulating substrate and surrounding the first line and the second line; Equipped with The first line is a first line conductor; a first via conductor connected to the first line conductor; a second line conductor connected to the first via conductor and extending to an opposite side of the first line conductor across the first via conductor in a planar perspective view; and a second via conductor connected to the second line conductor and extending to a layer different from a layer on which the first via conductor is located; The second line is a third line conductor; a third via conductor connected to the third line conductor; a fourth line conductor connected to the third via conductor and extending to an opposite side of the third line conductor across the third via conductor in a planar perspective view; and a fourth via conductor connected to the fourth line conductor and extending to a layer different from a layer on which the third via conductor is located; In a planar perspective view, the first line conductor and the third line conductor have a portion where the distance therebetween increases toward the first via conductor and the third via conductor, and the second line conductor and the fourth line conductor have a portion where the distance therebetween decreases toward the second via conductor and the fourth via conductor, The first line is The wiring board further includes a fifth line conductor connected to the second via conductor and extending to an opposite side of the second line conductor across the second via conductor in planar perspective, a fifth via conductor connected to the fifth line conductor and extending to a layer different from the layer on which the second via conductor is located, a sixth line conductor connected to the fifth via conductor and extending to an opposite side of the fifth line conductor across the fifth via conductor in planar perspective, and a sixth via conductor connected to the sixth line conductor and extending to a layer different from the layer on which the fifth via conductor is located, The second line is further including a seventh line conductor connected to the fourth via conductor and extending to an opposite side of the third line conductor across the fourth via conductor in planar perspective; a seventh via conductor connected to the seventh line conductor and extending to a layer different from the layer on which the fourth via conductor is located; an eighth line conductor connected to the seventh via conductor and extending to an opposite side of the seventh line conductor across the seventh via conductor in planar perspective; and an eighth via conductor connected to the eighth line conductor and extending to a layer different from the layer on which the seventh via conductor is located; In a planar perspective view, the fifth line conductor and the seventh line conductor have a portion where the distance therebetween increases toward the fifth via conductor and the seventh via conductor, and the sixth line conductor and the eighth line conductor have a portion where the distance therebetween decreases toward the sixth via conductor and the eighth via conductor. Wiring board.

3. the first line conductor and the second line conductor are spaced apart in a thickness direction of the insulating substrate, the third line conductor and the fourth line conductor are spaced apart in the thickness direction of the insulating substrate; The wiring board according to claim 1 or 2.

4. the insulating substrate has a first surface and a second surface located opposite to the first surface, the first line conductor and the third line conductor are located closer to the first surface than to the second surface; the second line conductor and the fourth line conductor are located closer to the second surface than to the first surface; The wiring board according to claim 3.

5. the first line further includes a first parallel line conductor connected to the first line conductor on the opposite side to the first via conductor; the second line further includes a second parallel line conductor connected to the third line conductor on the opposite side to the third via conductor; the first parallel line conductor and the second parallel line conductor are parallel to each other, In a planar perspective view, a center portion of the first opening is located between the first parallel line conductor and the second parallel line conductor and a center portion of the second opening. The wiring board according to claim 1.

6. In a planar perspective view, a center portion of the first opening and a center portion of the second opening coincide with each other. The wiring board according to claim 1.

7. the insulating substrate has a first surface and a second surface located on the opposite side to the first surface, the first line further includes a first electrode located on the second surface and an n-th via conductor connected to the first electrode, the second line further includes a second electrode located on the second surface and an (n+1)th via conductor connected to the second electrode; the ground film conductor includes a third ground film conductor having a third opening; When viewed in a direction in which the first electrode and the second electrode are aligned, the first via conductor and the third via conductor are located at the center of the first opening, and the nth via conductor and the (n+1)th via conductor are located at the center of the third opening. The wiring board according to claim 1.

8. the first line includes an n-th line conductor connected to the n-th via conductor on the opposite side to the first electrode, and an (n+2)-th via conductor connected to the n-th line conductor and extending to a layer different from a layer on which the n-th via conductor is located, the second line includes an (n+1)th line conductor connected to the (n+1)th via conductor on the opposite side to the second electrode, and an (n+3)th via conductor connected to the (n+1)th line conductor and extending to a layer different from a layer on which the (n+1)th via conductor is located, a distance between the (n+2) via conductor and the (n+3) via conductor is narrower than a distance between the n via conductor and the (n+1) via conductor; The wiring board according to claim 7 .

9. The wiring board according to claim 1 or 2; an electronic element mounted on the wiring board; An electronic device comprising:

10. An electronic device according to claim 9; a module substrate on which the electronic device is mounted; An electronic module comprising:

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