Wiring board and mounting structure

Abstract

A wiring board according to the present disclosure comprises: a first insulating layer; a first multilayer part; a second multilayer part; a second insulating layer; a third insulting layer; a first mounting region; a second mounting region; a planar first conductor layer; a second conductor layer; and a solder resist that has an opening from which a part of the first conductor layer is exposed. When perspectively viewed in plan, a through conductor which connects the first conductor layer and the second conductor layer to each other is positioned in a frame-like region between the outer peripheral edge of the first mounting region and the outer peripheral edge of the second mounting region so as to extend over the edge of the opening.

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a mounting structure using the same. [Background technology]

[0002] Known LSI packages in which an LSI chip is mounted on a wiring substrate include FC-BGA (Flip Chip Ball Grid Array), etc. Wiring substrates used in such LSI packages are provided with stiffeners for reinforcement, as described in Patent Document 1, for example. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 3173459 Summary of the Invention [Means for solving the problem]

[0004] The wiring board according to the present disclosure includes a first insulating layer having a first surface and a second surface opposite to the first surface, a first laminated portion including an insulating layer located on the first surface, a second laminated portion including an insulating layer located on the second surface, a second insulating layer located on the outermost layer of the insulating layers of the first laminated portion, a third insulating layer located on the outermost layer of the insulating layers of the second laminated portion, and a first outer surface of the second insulating layer opposite to the first surface. only a first mounting area located on the second insulating layer, and a first outer surface surrounding the first mounting area on the second insulating layer; onlyThe solder resist includes a second mounting area located on the second outer surface of the third insulating layer opposite the second surface, a plain first conductor layer located on the second outer surface of the third insulating layer opposite the second surface, a second conductor layer located on the second inner surface of the third insulating layer on the second surface side, and a solder resist covering the second outer surface of the third insulating layer and the first conductor and having an opening exposing a part of the first conductor layer. In a planar perspective view, a through conductor is located across the edge of the opening in a frame-shaped area between the outer peripheral edge of the first mounting area and the outer peripheral edge of the second mounting area, connecting the first conductor layer and the second conductor layer. The through conductor is located from a position where the edge of the opening overlaps the center of the through conductor to a position closer to the outside of the opening in a planar perspective view.

[0005] The mounting structure according to the present disclosure includes the above-described wiring board, an electronic component located in the first mounting area, a stiffener located in the second mounting area, and an external substrate having electrodes, the first conductor layer in the opening and the electrodes being connected via solder. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is an explanatory diagram illustrating a state in which an electronic component and a stiffener are mounted on a wiring board according to an embodiment of the present disclosure. [Figure 2] 2 is an explanatory diagram illustrating a wiring board according to an embodiment of the present disclosure as viewed in the direction of arrow A shown in FIG. 1. FIG. [Figure 3] 2 is an explanatory diagram illustrating a wiring board according to an embodiment of the present disclosure as viewed from the direction of arrow B shown in FIG. 1. FIG. [Figure 4] 1 is an explanatory diagram illustrating an example of a through conductor included in a wiring substrate according to an embodiment of the present disclosure. [Figure 5] 10A and 10B are explanatory diagrams for explaining modified examples of the through conductors. [Figure 6] 2 is an explanatory diagram illustrating a modified example of the shape of an opening formed in a solder resist when the wiring board according to the embodiment of the present disclosure is viewed from the direction of arrow B shown in FIG. 1. FIG. [Figure 7] 10 is a graph showing simulation results for a conventional mounting structure and a mounting structure according to the present disclosure. [Figure 8]10A and 10B show a cross-sectional view of a simulation model for a conventional mounting structure and a simulation result. [Figure 9] 10A and 10B show a cross-sectional view of a simulation model and simulation results in a case where two circular through conductors are provided for one opening in a planar perspective view in an embodiment of the present disclosure. [Figure 10] 10 shows a cross-sectional view of a simulation model and simulation results in a case where six circular through conductors are provided for one opening in a planar perspective view in one embodiment of the present disclosure. [Figure 11] 10A and 10B show a cross-sectional view of a simulation model and simulation results in a case where two arc-shaped through conductors are provided for one opening in a planar perspective view in an embodiment of the present disclosure. [Figure 12] 10A and 10B show a cross-sectional view of a simulation model and simulation results in the case where an arc-shaped through conductor is located near the outer side of an opening in an embodiment of the present disclosure. [Figure 13] 10A and 10B show a cross-sectional view of a simulation model and simulation results in the case where an arc-shaped through conductor is located closer to the inside of an opening in an embodiment of the present disclosure. [Figure 14] 10A and 10B show a cross-sectional view of a simulation model and simulation results when an annular through conductor is present in an embodiment of the present disclosure. [Figure 15] 2 shows a cross-sectional view of a simulation model and simulation results when an elliptical opening is present in a solder resist, as viewed from the direction of arrow B shown in FIG. 1, in one embodiment of the present disclosure. [Figure 16] In one embodiment of the present disclosure, a cross-sectional view of a simulation model and simulation results are shown in which there are six circular through conductors for one oval opening formed in a solder resist, as viewed from the direction of arrow B shown in Figure 1. [Figure 17]In one embodiment of the present disclosure, a cross-sectional view of a simulation model and simulation results are shown in which there are two arc-shaped through conductors for one elliptical opening formed in a solder resist, as viewed from the direction of arrow B shown in Figure 1. [Figure 18] In one embodiment of the present disclosure, a cross-sectional view of a simulation model and simulation results are shown in which an elliptical through conductor is present for one elliptical opening formed in a solder resist, as viewed from the direction of arrow B shown in Figure 1. [Figure 19] FIG. 19 is a diagram showing stress values ​​generated in an opening according to the simulation results shown in FIGS. 15 to 18. DETAILED DESCRIPTION OF THE INVENTION

[0007] Conventional wiring boards are prone to warping due to differences in the thermal expansion coefficients of the board, chip, and stiffener. In particular, warping tends to concentrate stress in the area between the chip and stiffener, which can easily cause cracks to form in the plane conductors (especially the plane conductors around the solder) on the surface facing this area (opposite surface). Therefore, there is a demand for a wiring board that is less likely to cause stress to concentrate in the area between the chip and stiffener, and less likely to cause cracks, even when used in an environment where high and low temperatures are repeatedly experienced.

[0008] As described in the section on "Means for Solving the Problems," the wiring board according to the present disclosure has, in a planar perspective view, a through conductor that is located across the edge of an opening in a frame-shaped region between the outer periphery of a first mounting region and the outer periphery of a second mounting region, and that connects the first conductor layer and the second conductor layer. Therefore, even when the wiring board according to the present disclosure is used in an environment where high and low temperatures are repeatedly experienced, stress is less likely to concentrate in the region between the chip and the stiffener, and cracks are less likely to occur.

[0009] A wiring board according to an embodiment of the present disclosure will be described with reference to Figures 1 to 4. Figure 1 is an explanatory diagram illustrating a state in which an electronic component and a stiffener are mounted on a wiring board according to an embodiment of the present disclosure. As shown in Figure 1, a wiring board 1 according to the embodiment includes a first insulating layer 21, a first laminate portion 11, a second laminate portion 12, and a solder resist 5.

[0010] First insulating layer 21 has first surface 211 and second surface 212 located on the opposite side to first surface 211. First surface 211 and second surface 212 correspond to the main surfaces of first insulating layer 21. In wiring board 1 according to one embodiment, first insulating layer 21 corresponds to a core insulating layer.

[0011] The first insulating layer 21 is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed. The thickness of the first insulating layer 21 is not particularly limited, and is, for example, 40 μm or more and 1800 μm or less.

[0012] The first insulating layer 21 may contain a reinforcing material. Examples of the reinforcing material include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more types of reinforcing materials may be used in combination. Furthermore, the first insulating layer 21 may have dispersed therein an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, or titanium oxide.

[0013] In the first insulating layer 21, a through-hole metal 2a is located to electrically connect the upper and lower surfaces of the first insulating layer 21. The through-hole metal 2a is located in a through-hole that penetrates from the first surface 211 to the second surface 212 of the first insulating layer 21. The through-hole metal 2a is formed by metal plating such as copper plating. The through-hole metal 2a is connected to the conductor layers 4 formed on both surfaces of the first insulating layer 21. The through-hole metal 2a may be formed only on the inner wall surface of the through-hole, or may fill the through-hole.

[0014] The first laminate section 11 is located on the first surface 211 of the first insulating layer 21. The first laminate section 11 has a structure in which conductor layers 4 and insulating layers are alternately laminated. In the first laminate section 11, at least two conductor layers 4 and one insulating layer are laminated. The conductor layer 4 is not limited as long as it is made of a conductor such as a metal. Specifically, the conductor layer 4 is made of a metal foil such as copper foil, a metal plating such as copper plating, or the like. The thickness of the conductor layer 4 is not particularly limited and is, for example, 10 μm or more and 30 μm or less.

[0015] The insulating layer, like the first insulating layer 21, is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed and used. The insulating layers may be made of the same resin or different resins. The insulating layer and the first insulating layer 21 may be made of the same resin or different resins.

[0016] Furthermore, the insulating layer may contain dispersed inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. The thickness of the insulating layer is not particularly limited and is, for example, 5 μm or more and 50 μm or less. The insulating layers may have the same thickness or different thicknesses.

[0017] A via-hole metal 2b for electrically connecting layers is formed in the insulating layer. The via-hole metal 2b is located in a via hole that penetrates the top and bottom surfaces of the insulating layer. The via-hole metal 2b is formed by metal plating such as copper plating. The via-hole metal 2b is connected to conductor layers 4 that are located on both sides of the insulating layer. The via-hole metal 2b may fill the via hole, or may be located only on the inner wall surface of the via hole.

[0018] Of the insulating layers of the first laminated unit 11, the insulating layer located at the outermost layer is defined as the second insulating layer 22. In other words, the insulating layer farthest from the first surface 211 is the second insulating layer 22. In the wiring board 1 shown in FIG. 1, the first laminated unit 11 includes two insulating layers, and therefore the upper insulating layer is the second insulating layer 22.

[0019] 1, a solder resist 5 may be located on the surface (first outer surface) of the first laminate portion 11. The solder resist 5 is made of a resin, such as an acrylic-modified epoxy resin. The solder resist 5 has an opening 51a for electrically connecting the conductor layer 4 and the electrode of the electronic component 7 via solder 6. The opening 51a is located in the first mounting region 31, for example.

[0020] The first mounting area 31 is an area for mounting the electronic components 7, and is located on the outermost surface on the first surface 211 side. As shown in FIG. 2, the first mounting area 31 has a rectangular shape when viewed from above. Examples of the electronic components 7 mounted in the first mounting area 31 include semiconductor integrated circuit elements and optoelectronic elements. The electronic components 7 are mounted so that the corners of the first mounting area 31 and the corners of the electronic components 7 overlap each other in a planar perspective view.

[0021] 1 and 2, wiring board 1 has second mounting area 32 located on the outermost surface on the first surface 211 side so as to surround first mounting area 31. FIG. 2 is an explanatory diagram illustrating wiring board 1 as viewed from the direction of arrow A shown in FIG. Second mounting area 32 is, for example, an area where stiffener 8 is provided to improve the rigidity of wiring board 1.

[0022] The second laminate section 12 is located on the second surface 212 of the first insulating layer 21. Similar to the first laminate section 11, the second laminate section 12 has a structure in which conductor layers 4 and insulating layers are alternately laminated. In the second laminate section 12, at least two conductor layers 4 and one insulating layer are laminated. The conductor layers 4 and insulating layers are as described above, and a detailed description thereof will be omitted.

[0023] Of the insulating layers of the second laminated portion 12, the insulating layer located at the outermost layer is defined as the third insulating layer 23. In other words, the insulating layer farthest from the second surface 212 is the third insulating layer 23. In the wiring board 1 shown in FIG. 1, the second laminated portion 12 includes two insulating layers, and therefore the lower insulating layer is the third insulating layer 23.

[0024] Of the conductor layers 4 of the second laminate section 12, the conductor layer 4 located on the outermost layer is defined as the first conductor layer 41. That is, in the third insulating layer 23, the conductor layer located on the second outer surface opposite the second surface 212 is the first conductor layer 41. The first conductor layer 41 is a plain conductor layer having a planar shape. On the other hand, in the third insulating layer 23, the conductor layer 4 located on the second inner surface on the second surface 212 side is defined as the second conductor layer 42.

[0025] 1, a solder resist 5 is located on the surface (second outer surface) of the second laminate section 12. Specifically, the solder resist 5 covers the second outer surface of the third insulating layer 23 and the first conductor layer 41. The solder resist 5 is as described above, and a detailed description thereof will be omitted.

[0026] 1, the solder resist 5 provided on the surface (second outer surface) of the second laminate portion 12 is located on the surface of the first conductor layer 41 and the second outer surface of the third insulating layer 23. The solder resist 5 located on the second outer surface of the third insulating layer 23 and on the surface of the first conductor layer 41 has openings 51b for electrically connecting the first conductor layer 41 to electrodes 61 of an external substrate 60 (such as a motherboard) via solder 6.

[0027] In a planar perspective view of the wiring board 1, a frame-shaped region 33 is located on the first conductor layer 41 between the outer periphery of the first mounting region 31 and the outer periphery of the second mounting region 32. Specifically, the frame-shaped region 33 is the hatched portion shown in Fig. 3. Fig. 3 is an explanatory diagram for explaining the state as viewed from the direction of arrow B shown in Fig. 1.

[0028] In a planar perspective, in the frame-shaped region 33, a through conductor 43 is positioned across the edge of the opening 51b of the solder resist 5, connecting the first conductor layer 41 and the second conductor layer 42. The through conductor 43 may be any conductor, and may be formed, for example, by metal plating such as copper plating. By locating the through conductor 43 in such a position, which has a higher rigidity than resin, the restraining force on the first conductor layer 41 is gradually alleviated. Therefore, even if warping occurs due to differences in the thermal expansion coefficients of the wiring board 1, the electronic component 7, and the stiffener 8, stress concentration around the periphery of the solder 6 connected to the first conductor layer 41 is alleviated. As a result, the wiring board 1 is less susceptible to cracking even when used in an environment where high and low temperatures are repeatedly experienced.

[0029] There are no limitations on the position of the through conductor 43 as long as it straddles the edge of the opening 51b in a planar perspective. In a planar perspective, the edge of the opening 51b may be located approximately in the center of the through conductor 43, or the through conductor 43 may be located closer to the outside or inside of the opening 51b. Since stress tends to be greater from the edge of the opening 51b to the outside than inside the opening 51b, the stress relaxation effect is further improved when the edge of the opening 51b is located approximately in the center of the through conductor 43 and when the through conductor 43 is located closer to the outside of the opening 51b.

[0030] It is sufficient that at least one through conductor 43 is located for one opening 51b. For example, the through conductors 43 may be located at positions that are point-symmetric with respect to the center of the opening 51b in the solder resist, as shown in Fig. 4. Fig. 4 is an explanatory diagram for explaining an example of the through conductor 43.

[0031] By arranging the through conductors 43 in this manner, even if warping occurs due to differences in the thermal expansion coefficients of the wiring board 1, the electronic component 7, and the stiffener 8, stress concentration around the periphery of the solder 6 connected to the first conductor layer 41 is further alleviated. As a result, the wiring board 1 is less susceptible to cracking even when used in an environment where high and low temperatures are repeated. The "point symmetrical with respect to the center of the opening 51b in the solder resist" can be defined as, for example, the midpoint of a line segment that bisects the length L (described later), the intersection of diagonals, or the center of gravity of each through conductor 43.

[0032] The shape of the frame-shaped region 33 is determined according to the shapes of the first mounting region 31 and the second mounting region 32. In the wiring board 1, as shown in Fig. 2, the first mounting region 31 and the second mounting region 32 both have a rectangular shape when viewed in a plan view. Therefore, as shown in Fig. 4, the frame-shaped region 33 has a rectangular frame shape with four corners R1 and four sides R2.

[0033] The through conductors 43 include first through conductors 431 located at corners R1 of the rectangular frame region 33, and second through conductors 432 located at sides R2 of the frame region 33. As shown in Fig. 4, the first through conductors 431 are arranged in a first direction along a diagonal line connecting the corners R1 of the frame region 33. As shown in Fig. 4, the second through conductors 432 are arranged in a second direction perpendicular to the side of the frame region 33 adjacent to the second through conductors 432.

[0034] When the frame region 33 has a rectangular frame shape, stress is likely to occur at the corners R1 in a first direction along the diagonal line connecting the corners R1, and stress is likely to occur at the sides R2 in a second direction perpendicular to the sides of the frame region 33. Therefore, by positioning the first through conductors 431 and the second through conductors 432 as described above, cracks are less likely to occur even when used in an environment where high and low temperatures are repeated.

[0035] The solder resist 5 has a plurality of openings 51b as shown in Fig. 4. The shape of the openings 51b may be, for example, circular when viewed from above as shown in Fig. 4, or may be a shape other than circular (for example, a polygonal shape such as a triangular shape or a rectangular shape, or an elliptical shape).

[0036] When the opening 51b has a circular shape, the through conductor 43 may have a circular shape in plan view, as shown in FIG. 4. In such a case, as shown in FIG. 5, a plurality of through conductors 43 each having a circular shape in plan view may be formed in an arc shape at positions symmetrical about the center of the opening 51b. In this case, the through conductors 43 may have a length such that the angle θ between the imaginary line connecting the center of the opening 51b and the through conductors 43 at both ends is at least 90°. When a plurality of through conductors 43 each having a circular shape are formed in an arc shape, a better balance between the stress relaxation effect and the electrical characteristics is achieved. FIG. 5 is an explanatory diagram illustrating a modified example of the through conductor 43.

[0037] If multiple through conductors 43 are provided at positions symmetrical about the center of opening 51b, the upper limit of angle θ should be approximately 135°. This is advantageous in terms of improving stress distribution. Multiple through conductors 43 may be provided without considering point-symmetric positions about the center of opening 51 or the angle θ.

[0038] When the opening 51b has a circular shape, the through conductor 43 may have an arc shape when viewed from above, as shown in FIG. 5. When the through conductor 43 has an arc shape, the width W of the through conductor 43 (the length in the direction perpendicular to the edge of the opening 51b) may be at least 50 μm. The upper limit of the width W of the through conductor 43 is preferably 80 μm, for example. If the width W is within this range, a better balance between the stress relaxation effect and the productivity of the through conductor 43 is achieved.

[0039] The length of the through conductor 43 (length L shown in FIG. 5) may be, for example, such that the angle θ between an imaginary line connecting the center of the opening 51b and the two ends of the through conductor 43 is at least 90°. There is no upper limit to the angle θ, and in order to provide an arc-shaped through conductor 43 at a point-symmetrical position with the center of the opening 51b as the symmetry point, the upper limit of the angle θ is preferably approximately 135°. If the through conductor 43 has an arc shape, the balance between the stress relaxation effect and the electrical characteristics will be better. Furthermore, as shown in FIG. 5, the through conductor 43 may have an annular shape without considering the angle θ. If the through conductor 43 has an annular shape, the stress reduction effect will be exerted regardless of the direction of the stress.

[0040] 6, openings 51b located at corners R1 between the outer periphery of first mounting region 31 and the inner periphery of second mounting region 32 may have a third opening length L3 in a third direction D3 orthogonal to first direction D1 that is greater than the first opening length L1 in the first direction, and openings 51b located at sides R2 may have a fourth opening length L4 in a fourth direction D4 orthogonal to second direction D2 that is greater than the second opening length L2 in the second direction D2. Figure 6 is an explanatory diagram illustrating modified shapes of openings 51b formed in solder resist 5 when wiring board 1 according to an embodiment of the present disclosure is viewed from the direction of arrow B shown in Figure 1.

[0041] When opening 51b has such a shape, tensile stress can be more effectively alleviated than when opening 51b has a circular shape as shown in Fig. 4. Tensile stress is likely to occur in the wiring board in the first direction D1 and the second direction D2 between the outer periphery of first mounting area 31 and the inner periphery of second mounting area 32. Therefore, by making the lengths of the opening edge (third length L3, fourth length L4) in the directions (third direction D3, fourth direction D4) perpendicular to the directions in which tensile stress occurs (first direction D1, second direction D2) longer than the lengths of the opening edge (first length L1, second length L2) in the directions in which tensile stress occurs, first conductor layer 41 below the opening edge can absorb the tensile stress over a wider range, and the stress per unit length acting on first conductor layer 41 below the opening edge can be dispersed. Specifically, opening 51b located between the outer periphery of first mounting area 31 and the inner periphery of second mounting area 32 may have a rectangular shape as shown in Fig. 6A when viewed from above, or may have an elliptical shape as shown in Fig. 6B. Opening 51b having a rectangular shape and opening 51b having an elliptical shape are formed, for example, in a portion between the outer periphery of first mounting area 31 and the inner periphery of second mounting area 32 where plane-like first conductor layer 41 is located.

[0042] As shown in FIG. 6A, when opening 51b has a rectangular shape, the aspect ratio of opening 51b (first length L1:third length L3, second length L2:fourth length L4) is not limited and may be, for example, 1:3.15 to 1:5. When the aspect ratio is in this range, tensile stress can be further alleviated. As shown in FIG. 6B, when opening 51b has an elliptical shape, the flattening ratio is not limited and may be, for example, 0.1 to 0.5. When the flattening ratio is in this range, tensile stress can be further alleviated.

[0043] All of the openings 51b formed in the solder resist 5 may have approximately the same opening area. If the openings 51b have approximately the same opening area, the amount of solder 6 can be made approximately constant when mounting the electronic component 7, thereby improving mounting reliability. In this specification, "approximately the same opening area" means an area within a range of ±10% of the reference opening area.

[0044] The wiring board 1 as described above is formed, for example, as follows. First, a first insulating layer 21 is prepared. Through-holes are formed in the first insulating layer 21 by drilling, blasting, or laser processing. Next, conductor layers 4 and insulating layers are alternately laminated on the first surface 211 side and the second surface 212 side of the first insulating layer 21. When forming the conductor layer 4 on the surface of the first insulating layer 21 by copper plating using, for example, a semi-additive method, the through-hole metal 2a may be formed in the through-hole, or the through-hole metal 2a may be formed in the through-hole in advance. The method for forming the conductor layer 4 and the through-hole metal 2a is as described above, and a detailed description thereof will be omitted.

[0045] The insulating layer is formed by applying a film made of a resin such as epoxy resin, bismaleimide-triazine resin, polyimide resin, or polyphenylene ether resin under vacuum and then thermally curing it. Next, the insulating layer is laser processed to form a via hole with the conductor layer 4 at the bottom. After the laser processing, Resin smear, Desmearing to remove carbides and the like improves the adhesive strength between the via hole and the via hole metal 2b. When forming the conductor layer 4 on the insulating layer surface by, for example, a semi-additive method, the via hole metal 2b is formed in the via hole by plating metal.

[0046] By repeating the steps of forming the conductor layer 4 and the insulating layer, a desired number of conductor layers 4 and insulating layers are formed, thereby forming the first laminated section 11 and the second laminated section 12. The insulating layer located at the outermost layer of the insulating layers of the first laminated section 11 is referred to as the second insulating layer 22, and the insulating layer located at the outermost layer of the insulating layers of the second laminated section 12 is referred to as the third insulating layer 23.

[0047] As described above, in the third insulating layer 23, the conductor layer 4 located on the second outer surface opposite the second surface 212 is the first conductor layer 41 having a planar shape. On the other hand, in the third insulating layer 23, the conductor layer 4 located on the second inner surface on the second surface 212 side is the second conductor layer 42.

[0048] When forming the above-described via holes, through holes for forming the through conductors 43 connecting the first conductor layer 41 and the second conductor layer 42 are also formed in the third insulating layer 23. The through holes are formed so as to straddle the edges of the openings 51b of the solder resist 5 described below. When forming the via-hole metal 2b, the through conductors 43 are formed of, for example, the same conductor as the via-hole metal 2b.

[0049] Next, the surface (first outer surface) of the first laminate section 11 and the surface (second outer surface) of the second laminate section 12 are covered with solder resist 5. The solder resist 5 covering the surface (first outer surface) of the first laminate section 11 has an opening 51a formed in an area that will become the first mounting area 31. The solder resist 5 covering the surface (second outer surface) of the second laminate section 12 has an opening 51b formed therein for electrically connecting the first conductor layer 41 and an electrode 61 of an external substrate 60 (such as a motherboard) via solder 6.

[0050] In this way, wiring board 1 according to one embodiment is obtained. By arranging through conductor 43 in wiring board 1, even if warping occurs due to differences in the thermal expansion coefficients of wiring board 1, electronic component 7, and stiffener 8, stress concentration around the periphery of solder 6 connected to first conductor layer 41 is alleviated. As a result, wiring board 1 is less likely to crack even when used in an environment where high and low temperatures are repeatedly experienced.

[0051] The mounting structure according to the present disclosure includes a wiring board 1 according to one embodiment, an electronic component 7 located in a first mounting region 31 of the wiring board 1, a stiffener 8 located in a second mounting region 32, and an external board having an electrode 61, and the first conductor layer 41 in the opening 51b of the solder resist 5 and the electrode 61 are connected via solder 6. As described above, examples of the electronic component 7 include a semiconductor integrated circuit element and an optoelectronic element.

[0052] Next, cross-sectional views of simulation models and simulation results (stress distribution diagrams) for the conventional mounting structure and the mounting structure according to the present disclosure, which differ in shape and position of the through conductor 43 included in the wiring board, are shown in Figures 8 to 18. These results were obtained under the conditions shown in Table 1 below. In the stress distribution diagram, the darker the color, the higher the stress value. ABF GL102F listed in Table 1 is a thermosetting build-up film manufactured by Ajinomoto Fine-Techno Co., Inc. "SR" listed in Table 1 stands for solder resist, and SR7300G is Resonac Inc. It is a photosensitive solder resist manufactured by

[0053] For the conventional mounting structure, a wiring board was used in which, when viewed from above, a circular through conductor 43 was located inside the opening 51b of the solder resist 5, as shown in Fig. 7. On the other hand, for the mounting structures according to the present disclosures 1 to 4, four types of wiring boards were used in which, when viewed from above, a circular through conductor 43 and through conductors 43 having an arc shape and an annular shape were located across the opening 51b of the solder resist 5, as shown in Fig. 7. In the conventional mounting structure, it can be seen that a large stress is applied to the conductor layer 4 below the edge of the opening in the solder resist 5, as shown in Fig. 8.

[0054] [Table 1]

[0055] 7 and 9, the mounting structure according to Disclosure 1 has a stress reduced by approximately 18.4 MPa compared to the conventional mounting structure, and the stress distribution diagram also shows that the stress applied to the first conductor layer 41 below the opening edge of the solder resist 5 is reduced. As shown in FIGS. 7 and 10, the mounting structure according to Disclosure 2 has a stress reduced by approximately 18.9 MPa compared to the conventional mounting structure, and the stress distribution diagram also shows that the stress applied to the first conductor layer 41 below the opening edge of the solder resist 5 is further reduced. Furthermore, as shown in FIGS. 7 and 11, the mounting structure according to Disclosure 3 has a stress reduced by approximately 121 MPa compared to the conventional mounting structure, and the stress distribution diagram also shows that the stress applied to the first conductor layer 41 below the opening edge of the solder resist 5 is even further reduced compared to Disclosures 1 and 2. As shown in Figures 7 and 14, the mounting structure of Disclosure 4 has a stress that is reduced by approximately 123.4 MPa compared to the conventional mounting structure, and the stress distribution diagram also shows that the stress applied to the first conductor layer 41 below the opening edge of the solder resist 5 is reduced compared to Disclosures 1, 2, and 3.

[0056] Furthermore, when the failure probability of the mounting structures according to Disclosures 1 to 4 was measured (calculated), assuming that the failure probability of the conventional mounting structure was 100%, the failure probability was reduced by more than 10%. In the example using a wiring board including through conductors 43 with arc and ring shapes, the failure probability was reduced by more than 70%. As can be seen, a reduction in stress of just a few percent significantly reduces the failure probability. The failure probability in the present disclosure is calculated by (stress value generated in the conductor layer below the edge of the opening in the disclosed structure - stress value generated in the island-shaped conductor layer below the edge of the opening) / (stress value generated in the conductor layer below the edge of the opening in the conventional structure - stress value generated in the island-shaped conductor layer below the edge of the opening). In other words, the stress value generated in the island-shaped conductor layer located below the edge of the opening in solder resist 5, separated from the surrounding conductor layers and free of cracks, is used as a reference. This is the ratio of the stress value in excess of the reference value applied to the conductor layer in the disclosed structure to the stress value in excess of the reference value applied to the conductor layer in the conventional structure, and is used as an index for estimating the probability of crack occurrence.

[0057] Next, we investigated the difference in stress relaxation effect depending on the position of the through conductor 43 for an example using a wiring board including a through conductor 43 with an arc shape. First, as shown in the present disclosure 3 in FIG. 7 and the cross-sectional view of the simulation model in FIG. 11, when the edge of the opening 51b was located approximately at the center of the through conductor 43 in a planar perspective, the stress was 613.8 MPa. On the other hand, as shown in the cross-sectional view of the simulation model in FIG. 12, when the through conductor 43 was located toward the outside of the opening 51b in a planar perspective, the stress was 617.3 MPa. On the other hand, as shown in the cross-sectional view of the simulation model in FIG. 13, when the through conductor 43 was located toward the inside of the opening 51b in a planar perspective, the stress was 685.4 MPa. These results show that the stress relaxation effect is superior when the edge of the opening 51b is located approximately at the center of the through conductor 43 and when the through conductor 43 is located toward the outside of the opening 51b compared to when the through conductor 43 is located toward the inside of the opening 51b.

[0058] The wiring board of the present disclosure is not limited to the above-described embodiment. In wiring board 1 according to one embodiment, first mounting area 31 has a rectangular shape when viewed in a plan view. However, the shape of the first mounting area in the wiring board of the present disclosure is appropriately set depending on the shape of the electronic component, and may be a polygonal shape such as a triangular, pentagonal, or hexagonal shape when viewed in a plan view, or may be a circular or elliptical shape.

[0059] In wiring board 1 according to one embodiment, second mounting area 32 has a rectangular frame shape when viewed in a plan view. However, the shape of the second mounting area in the wiring board of the present disclosure is not limited to a specific shape when viewed in a plan view, and may be a polygonal frame shape such as a triangular frame shape, a pentagonal frame shape, or a hexagonal frame shape, or may be a circular or elliptical ring shape.

[0060] 16 and 19, the mounting structure according to the present disclosure 5 has a stress reduced by approximately 45 MPa compared to the mounting structure according to the conventional technology 2, and the stress distribution diagram also shows that the stress applied to the first conductor layer 41 below the opening edge of the solder resist 5 is reduced.6 The mounting structure according to the present disclosure has a stress reduced by approximately 93.9 MPa compared to the mounting structure according to Conventional 2, and the stress distribution diagram also shows that the stress applied to the first conductor layer 41 under the edge of the opening in the solder resist 5 is further reduced. 7 The mounting structure of this invention has a stress that is reduced by approximately 98.5 MPa compared to the mounting structure of Conventional Example 2, and the stress distribution diagram also shows that the stress applied to the first conductor layer 41 below the opening edge of the solder resist 5 is even reduced compared to Disclosures 5 and 6.

[0061] In the wiring board 1 according to the embodiment, the pair of through conductors 43 located at positions symmetrical about the center of the opening 51b in the solder resist 5 have the same shape and size, but the shapes and sizes of the through conductors 43 may differ depending on the magnitude of the stress generated around the opening 51b. This makes it easier to maintain a balance between stress distribution and electrical characteristics. [Explanation of symbols]

[0062] 1. Wiring board 11 First lamination section 12 Second lamination section 21 First insulating layer 22 Second insulating layer 23 Third insulating layer 211 Page 1 212 2nd page 2a through-hole conductor 2b Via hole conductor 31 First Implementation Area 32 Second implementation area 33 Frame-shaped area 4 Conductor Layer 41 First conductor layer 42 Second conductor layer 43 Through conductor 431 First through conductor 432 Second through conductor 5 Solder resist 51b Opening (in solder resist on the third insulating layer side) 60 External board 61 Electrode 6 Solder 7. Electronic Components 8 Stiffna

Claims

1. a first insulating layer having a first surface and a second surface opposite the first surface; a first laminate portion located on the first surface and including an insulating layer; a second laminated portion located on the second surface and including an insulating layer; a second insulating layer located at the outermost layer of the insulating layers of the first laminated portion; a third insulating layer located at the outermost layer of the insulating layers of the second laminated portion; a first mounting area located only on a first outer surface of the second insulating layer opposite to the first surface; a second mounting region located only on the first outer surface of the second insulating layer so as to surround the first mounting region; a first conductor layer having a plane shape and located on a second outer surface of the third insulating layer opposite to the second surface; a second conductor layer located on a second inner surface of the third insulating layer on the second surface side; a solder resist covering the second outer surface of the third insulating layer and the first conductor layer, the solder resist having an opening exposing a portion of the first conductor layer; Including, a through conductor that is located across the edge of the opening and connects the first conductor layer and the second conductor layer in a frame-shaped region between an outer peripheral edge of the first mounting region and an outer peripheral edge of the second mounting region in a planar perspective view, the through conductor being located from a position where the edge of the opening overlaps with the center of the through conductor to an outer side of the opening in a planar perspective view; Wiring board.

2. The wiring board according to claim 1 , wherein the through conductors are positioned at positions symmetrical with respect to a center of the opening.

3. In a plan view, the frame-shaped region has a rectangular frame shape having four corners and four sides, the solder resist has a plurality of the openings, the through conductors are located corresponding to the plurality of openings, respectively; the through conductors include first through conductors located at the corners of the rectangular frame and second through conductors located at the sides of the rectangular frame, the first through conductors are arranged in a first direction along a diagonal line connecting the corners, The wiring board according to claim 1 , wherein the second through conductors are arranged in a second direction perpendicular to the side portion adjacent to the second through conductors.

4. The wiring board according to claim 1 , wherein the opening has a circular shape and the through conductor has a circular shape in a planar perspective view.

5. The wiring board according to claim 1 , wherein, in a planar perspective view, the opening has a circular shape and the through conductor has an arc shape.

6. The wiring board according to claim 1 , wherein, in a planar perspective view, the opening has a circular shape and the through conductor has an annular shape.

7. In a plan view, the frame-shaped region has a rectangular frame shape having four corners and four sides, the solder resist has a plurality of the openings, the through conductors are located corresponding to the plurality of openings, respectively; The wiring board according to claim 6 , wherein the through conductors include first through conductors located at the corners of the rectangular frame and second through conductors located at the sides of the rectangular frame.

8. In a planar perspective view, between the outer peripheral edge of the first mounting area and the inner peripheral edge of the second mounting area, 4. The wiring board according to claim 3, wherein, in the opening located at the corner portion, when the length in the first direction is defined as a first length, the length in the second direction is defined as a second length, the length in a third direction perpendicular to the first direction is defined as a third length, and the length in a fourth direction perpendicular to the second direction is defined as a fourth length, the third length is greater than the first length and the fourth length is greater than the second length.

9. 9. The wiring board according to claim 8, wherein the ratio of the first length to the third length and the ratio of the second length to the fourth length are in the range of 1:3.15 to 1:5, respectively.

10. The wiring board according to claim 8 , wherein the flatness of the opening is equal to or greater than 0.1 and equal to or less than 0.

5.

11. The wiring board according to claim 1 , wherein the plurality of openings each have the same area.

12. The wiring board according to claim 1 , wherein the through conductor has a length of at least 50 μm in a direction perpendicular to the edge of the opening.

13. A wiring board according to any one of claims 1 to 12, an electronic component located in the first mounting area; a stiffener located in the second mounting area; an external substrate having electrodes; Including, the first conductor layer in the opening and the electrode are connected via solder; Implementation structure.

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