Integrated Circuits

Abstract

To efficiently access memory areas which are discontinuously arranged.SOLUTION: An integrated circuit of an embodiment stores block numbers of blocks of a memory selectable as an object from which data is read, and a first end flag into a first table. Further, the integrated circuit stores block numbers of blocks selectable as an object to which data is written, and a second end flag into a second table. When acquiring a reading start request and a reading start line of the first table, the integrated circuit reads data from blocks of which the block numbers are stored in a range from the reading start line to a line to which the first end flag is set, in the first table out of the plurality of blocks of the memory. When acquiring a write start request, a reading start line of the second table, and data to be written to the memory, the integrated circuit writes the data to blocks of which the block numbers are stored in a range from the reading start line to a line to which the second end flag is set, in the second table.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to integrated circuits. [Background technology]

[0002] Traditionally, there are two known memory access protocols: PIO (Programmed Input / Output) and DMA (Direct Memory Access). In PIO, the CPU (Central Processing Unit) manages data transfers between each device inside the computer and memory. In contrast, DMA transfers data directly between each device and memory without going through the CPU, which allows for faster transfer speeds than PIO. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-165724 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional technology, when memory is accessed by DMA, only contiguous areas can be accessed in a single access, and access to non-contiguous memory areas must be performed multiple times. [Means for solving the problem]

[0005] When the integrated circuit of the embodiment receives registration of the block number of a block selectable as a target for reading data from among a plurality of blocks obtained by dividing the storage area of ​​a memory into blocks of a specified size and a first end flag indicating the final block to be read last among the blocks selectable as targets for reading, the integrated circuit associates the block number of the block selectable as a target for reading with the first end flag and stores it in a first table of a register. Also, when the integrated circuit receives registration of the block number of a block selectable as a target for writing data from among the plurality of blocks and a second end flag indicating the final block to be written last among the blocks selectable as targets for writing, the integrated circuit associates the block number of the block selectable as a target for writing with the first end flag and stores it in a first table of a register. 2 and stores the data in a second table of the register in association with the end flag. When the integrated circuit receives a read start request to read data from the memory and a read start row in the first table in the read start request, it reads data from a block in the memory that corresponds to a block number stored in the first table from the read start row to the row in which the first end flag is set. When the integrated circuit receives a write start request to the memory, a read start row in the second table in the write start request, and data to be written to the memory, it writes the data to be written to a block in the memory that corresponds to a block number stored in the second table from the read start row to the row in which the second end flag is set. The first table further has an area for storing the start address of the read area in which data to be read is stored in each block corresponding to each block number, and the data size of the read area. The second table further has an area for storing the start address of the write area in which data is written in each block corresponding to each block number, and the data size from the start address to the end of the write area. When the integrated circuit receives registration of the block numbers of blocks selectable as read targets, a first end flag, the start address of the read area in which data to be read is stored in each block corresponding to each block number, and the data size of the read area, it associates the block numbers of blocks selectable as read targets, the first end flag, the start address of the read area, and the data size of the read area in the first table. When the integrated circuit receives registration of block numbers of blocks selectable as write targets, second end flags, starting addresses of write areas where data is written in each block corresponding to each block number, and the data size of the write area, it associates and stores the block numbers of blocks selectable as write targets, second end flags, starting addresses of the write areas, and data sizes of the write areas in a second table.When the integrated circuit receives a read start request and a read start row in the first table in the read start request, it reads data stored in the read areas of each block in the memory that corresponds to the block numbers stored in the first table from the read start row to the row in which the first end flag is set.When the integrated circuit receives a write start request, a read start row in the second table in the write start request, and data to be written to the memory, it writes the data to be written to the write areas of the blocks in the memory that correspond to the block numbers stored in the second table from the read start row to the row in which the second end flag is set. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram illustrating an example of the overall configuration of a control system according to the first embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of the PLC and the transmission module according to the first embodiment. [Figure 3] FIG. 3 is a diagram showing an example of setting of a read DMA table by the DMA table setting API according to the first embodiment. [Figure 4] FIG. 4 is a flowchart showing an example of the processing flow of the DMA table setting API according to the first embodiment. [Figure 5] FIG. 5 is a flowchart showing an example of the processing flow of the DMA read execution API according to the first embodiment. [Figure 6] FIG. 6 is a flowchart showing an example of the flow of a DMA read process executed by the hardware logic of the FPGA according to the first embodiment. [Figure 7] 7 is a flowchart showing an example of the processing flow of the DMA write execution API according to the first embodiment. The processing of this flowchart is executed, for example, at regular intervals. [Figure 8] FIG. 8 is a flowchart showing an example of the flow of a DMA write process executed by the hardware logic of the FPGA according to the first embodiment. [Figure 9] FIG. 9 is a diagram illustrating an example of the configuration of a PLC and a transmission module according to the second embodiment. [Figure 10] FIG. 10 is a diagram illustrating an example of a method for identifying a read target block according to the first embodiment. [Figure 11] FIG. 11 is a diagram illustrating an example of the configuration of a PLC and a transmission module according to the third embodiment. [Figure 12] FIG. 12 is a diagram illustrating an example of a method for identifying a read target block according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] (First embodiment) FIG. 1 is a diagram showing an example of the overall configuration of a control system S according to a first embodiment. The control system S is a system that controls, for example, an industrial plant (hereinafter simply referred to as a "plant"). As shown in FIG. 1, the control system S includes PLC (Programmable Logic Controller) stations 1a and 1b, various sensors 6a and 6b, and an HMI (Human Machine Interface) 7. The HMI 7 and the PLC stations 1a and 1b are connected via a control network 5.

[0008] The HMI 7 is a device used by operators and engineers to monitor the status of the processes executed by the PLCs 2a and 2b.

[0009] PLC stations 1a and 1b are configured by combining multiple modules. Specifically, PLC stations 1a and 1b include PLCs 2a and 2b, I / O (Input / Output) transmission modules 3a and 3b, and transmission modules 4a and 4b. Hereinafter, when there is no need to distinguish between the individual PLC stations 1a and 1b, they will simply be referred to as PLC station 1.

[0010] The PLCs 2a and 2b are devices that control the operation of various devices installed in the plant using the functions of a software PLC 24. Hereinafter, when there is no need to distinguish between the individual PLCs 2a and 2b, they will simply be referred to as PLC 2. The PLCs 2a and 2b each include a CPU (Central Processing Unit) 20a and 20b, respectively. Hereinafter, when there is no need to distinguish between the individual CPUs 20a and 20b, they will simply be referred to as CPU 20.

[0011] The I / O transmission modules 3a and 3b input and output data to and from various sensors 6a and 6b under the control of the PLC 2. Hereinafter, when there is no need to distinguish between the individual I / O transmission modules 3a and 3b, they will simply be referred to as I / O transmission modules 3. Hereinafter, when there is no need to distinguish between the individual sensors 6a and 6b, they will simply be referred to as sensors 6. The I / O transmission module 3 may input and output data not only to the sensors 6 but also to various control devices. The I / O transmission modules 3a and 3b include field-programmable gate arrays (FPGAs) 31a and 31b, respectively. Hereinafter, when there is no need to distinguish between the FPGAs 31a and 31b of the individual I / O transmission modules 3a and 3b, they will simply be referred to as FPGAs 31.

[0012] The transmission modules 4a and 4b transmit data between the PLC stations 1a and 1b via the control network 5, and between the PLC stations 1a and 1b and the HMI 7. Hereinafter, when there is no need to distinguish between the individual transmission modules 4a and 4b, they will simply be referred to as transmission modules 4. The transmission modules 4a and 4b include FPGAs 41a and 41b, respectively. Hereinafter, when there is no need to distinguish between the FPGAs 41a and 41b of the individual transmission modules 4a and 4b, they will simply be referred to as FPGAs 41.

[0013] Data transmitted and received by the transmission modules 4a and 4b between the PLC stations 1a and 1b and between the PLC stations 1a and 1b and the HMI 7 is stored in a memory within the transmission module 4 and is written and read from the PLCs 2a and 2b.

[0014] FIG. 2 is a diagram illustrating an example of the configuration of the PLC 2 and the transmission module 4 according to the first embodiment.

[0015] The PLC 2 and the transmission module 4 are connected by a bus 10 that complies with standards such as PCI (Peripheral Component Interconnect) Express (registered trademark).

[0016] As shown in FIG. 2, the PLC 2 includes a CPU 20 and a storage unit 25.

[0017] The storage unit 25 is a storage device such as a ROM (Read Only Memory), a RAM (Random Access Memory), or an HDD (Hard Disk Drive). The storage unit 25 stores programs corresponding to various processes executed by the CPU 20.

[0018] In this embodiment, the CPU 20 executes various processes using a device driver 21, a DMA (Direct Memory Access) table setting API (Application Programming Interface) 231, a DMA read execution API 232, a DMA write execution API 233, and a software PLC 24, all of which are stored in the storage unit 25. The DMA table setting API 231, the DMA read execution API 232, and the DMA write execution API 233 are collectively referred to as a driver API 23.

[0019] The software PLC 24 controls various devices included in the plant using data acquired from the sensor 6. The software PLC 24 is a host that requests access to the memory 42 of the transmission module 4.

[0020] The device driver 21 is a program that mediates data transmission and reception between the transmission module 4 and the PLC 2. The CPU 20 executes the driver API 23, whereby access to the transmission module 4 is executed via the device driver 21.

[0021] The DMA table setting API 231 is an API that sets data in the read DMA table 421 and the write DMA table 422 in the FPGA 41 of the transmission module 4.

[0022] The DMA read execution API 232 is an API that requests the FPGA 41 of the transmission module 4 to read data from a specific area of ​​the memory 42 in the transmission module 4. In this embodiment, reading data from the memory 42 and writing data to the memory 42 are collectively referred to as accessing the memory 42.

[0023] The DMA write execution API 233 is an API that requests the FPGA 41 of the transmission module 4 to write data to a predetermined area of ​​the memory 42 in the transmission module 4 .

[0024] The transmission module 4 includes an FPGA 41 and a memory 42 .

[0025] The storage area (memory area) of the memory 42 is divided into a plurality of blocks of a specified size. In FIG. 1, as an example, the storage area of ​​the memory 42 includes blocks 1 to ZZ. The specified size of each block and the number of blocks included in one memory 42 are determined in advance. Data transmitted between the PLC stations 1a and 1b, and between the PLC stations 1a and 1b and the HMI 7, is stored in a specified block within the memory area.

[0026] The FPGA 41 includes a register 410, which is a storage area, and a buffer memory 430. The FPGA 41 is an example of an integrated circuit in this embodiment. A logic processing function can be implemented in the FPGA 41 using a hardware description language (hardware logic).

[0027] The register 410 has areas for storing a table read start row 411 , a size 412 , a read DMA table 421 , a write DMA table 422 , a block map 423 , and a DMA completion status 424 .

[0028] The table read start row 411 indicates the read start row of the read DMA table 421 and the write DMA table 422. In this embodiment, the table read start row 411 is exemplified as information indicating the read start position of the read DMA table 421 and the write DMA table 422, but the format of the information is not particularly limited as long as it indicates the read start position of the read DMA table 421 and the write DMA table 422.

[0029] Size 412 is the size of the data to be read or written.

[0030] The read DMA table 421 is a table that stores the block numbers of blocks in the memory 42 that are requested to be read by the DMA read execution API 232 of the PLC 2. The read DMA table 421 is an example of a first table in this embodiment.

[0031] The write DMA table 422 is a table that stores the block numbers of blocks in the memory 42 to which writing is requested by the DMA write execution API 233 of the PLC 2. The write DMA table 422 is an example of a second table in this embodiment.

[0032] The buffer memory 430 is a storage area in which data is temporarily stored when data is read from or written to the memory 42 .

[0033] The block map 423 is a table that registers the block numbers of the blocks that divide the memory area and the addresses of the memory areas corresponding to each block number. The correspondence between the block numbers of each block and the addresses of the memory areas is determined when the transmission module 4 is manufactured and stored in the block map 423.

[0034] The DMA completion status 424 is status information indicating whether the read DMA and the write DMA have been completed. For example, when the hardware logic of the FPGA 41 has completed a read process executed in response to a DMA read start request from the DMA read execution API 232 or a write process executed in response to a DMA write start request from the DMA write execution API 233, the hardware logic of the FPGA 41 registers the completion of the process in the DMA completion status 424. For example, the initial state of the DMA completion status 424 is "0" or null, and when the process is completed, the flag "1" is set.

[0035] 3 is a diagram showing an example of the setting of the read DMA table 421 by the DMA table setting API 231 according to the first embodiment. The DMA table setting API 231 has the fields "end flag" and "block number." Each record in the DMA table setting API 231 can be identified by a row code. Note that, although FIG. 3 uses row codes to indicate positions within the DMA table setting API 231, information other than row codes may be used as long as it indicates a position within the DMA table setting API 231.

[0036] In the initial state of the transmission module 4, no values ​​are registered in the read DMA table 421. The FPGA 41 accepts the setting of values ​​for each item in the read DMA table 421 by the DMA table setting API 231 of the PLC 2. Specifically, when the FPGA 41 receives the registration of an "end flag" and a "block number" by the DMA table setting API 231, it stores the received "end flag" and "block number" in the read DMA table 421 of the register 410.

[0037] The block numbers registered in the read DMA table 421 are the block numbers of blocks that can be selected as targets for reading data from among the multiple blocks obtained by dividing the storage area of ​​the memory 42 into blocks of specified sizes. The block numbers that can be selected as targets for reading are all block numbers that can be specified as targets for reading by the DMA read execution API 232.

[0038] When multiple blocks can be selected for reading, the multiple blocks may not be consecutive. For example, as shown in Figure 3, block number "3" may be specified after block number "1" instead of block number "2."

[0039] The end flag registered in the read DMA table 421 indicates the last block among the blocks selectable for reading. The last block in the read DMA table 421 is the block that will be read last when the FPGA 41 reads the blocks selectable for reading from the memory 42. In this embodiment, the FPGA 41 reads the blocks in the memory 42 in ascending order of block numbers, so the last block is the one with the largest block number among the blocks selectable for reading. In the example shown in FIG. 3, the end flag "0" is set for block numbers that are not the last block, and the end flag "1" is set for the block number of the last block. The end flag stored in the read DMA table 421 is an example of a first end flag in this embodiment.

[0040] 3 shows the read DMA table 421 as an example, but the write DMA table 422 also has similar items. The block numbers registered in the write DMA table 422 are the block numbers of blocks that can be selected as targets for writing data, among the multiple blocks obtained by dividing the storage area of ​​the memory 42 into blocks of specified sizes. The block numbers that can be selected as targets for writing are all block numbers that can be specified as targets for writing by the DMA write execution API 233.

[0041] The end flag set in the write DMA table 422 indicates the last block among the blocks selectable as the write target. The last block in the write DMA table 422 is the block to be written last when the FPGA 41 writes to the blocks selectable as the write target. In this embodiment, the FPGA 41 writes to the blocks in the memory 42 in ascending order of block number, so the last block is the block with the largest block number among the blocks selectable as the write target. The end flag set in the write DMA table 422 is an example of a second end flag in this embodiment. When the FPGA 41 receives registration of the "end flag" and "block number" by the DMA table setting API 231, it stores the received "end flag" and "block number" in the write DMA table 422 of the register 410.

[0042] Here, we will explain how the read DMA table 421 illustrated in FIG. 3 is used. The DMA read execution API 232 illustrated in the configuration of FIG. 2 specifies the read start row in the read DMA table 421. For example, assume that row code "AAA" in the read DMA table 421 shown in FIG. 3 is specified as the read start row. In this case, the FPGA 41 reads each record in the read DMA table 421 in order, starting with the record with row code "AAA." Then, the FPGA 41 reads data stored in blocks in the memory 42 corresponding to the block numbers stored from the record with row code "AAA" to the record with the end flag set to "1." A row somewhere in the read DMA table 421 may be specified as the table read start row. For example, the rows following row code "BBB" in FIG. 3 may be specified as the table read start row.

[0043] The FPGA 41 identifies the memory area corresponding to the block number read from the read DMA table 421 by referring to the block map 423 shown in Fig. 2, and reads the data from the identified memory area. For example, if the row code "AAA" in the read DMA table 421 shown in Fig. 3 is specified as the read start row, blocks 1, 3, 4, and YY of the multiple blocks in the memory 42 become the blocks to be read.

[0044] The write DMA table 422 is used in the same way as the read DMA table 421.

[0045] Next, the flow of processing executed by the PLC 2 and FPGA 41 of this embodiment configured as above will be described.

[0046] 4 is a flowchart showing an example of the processing flow of the DMA table setting API 231 according to the first embodiment. The processing of this flowchart is executed, for example, when a control program is downloaded to the PLC 2. In this case, blocks in which data used by the downloaded control program is saved or blocks used for writing by the downloaded control program are registered in the read DMA table 421 and the write DMA table 422. Note that the processing of this flowchart is executed before the DMA read execution API 232 and the DMA write execution API 233, which will be described later, are executed.

[0047] The DMA table setting API 231 receives from the software PLC 24 the block numbers selectable as targets for reading, the block numbers selectable as targets for writing, the final block numbers for reading and writing, and the table start rows for reading and writing (S1).

[0048] Then, the DMA table setting API 231 accesses the FPGA 41 of the transmission module 4 via the bus 10 and registers data in the read DMA table 421 and the write DMA table 422 (S2).

[0049] For example, the DMA table setting API 231 registers the block numbers that can be selected as the target for reading in the read DMA table 421 in order from the received table start row. The DMA table setting API 231 also registers “1” in the “end flag” that corresponds to the last block number to be read.

[0050] The DMA table setting API 231 also registers all block numbers to be written in the write DMA table 422 in order, starting from the received table start row. The DMA table setting API 231 also registers "1" in the "end flag" corresponding to the final block number to be written.

[0051] The process of this flowchart ends here. If the block to be read or written is changed due to a change in the software PLC 24, the process of this flowchart is executed again.

[0052] 5 is a flowchart showing an example of the processing flow of the DMA read execution API 232 according to the first embodiment. The processing of this flowchart is executed, for example, at regular intervals.

[0053] The DMA read execution API 232 accesses the FPGA 41 of the transmission module 4 via the bus 10 and sets a table read start row 411 and a size 412 of the data to be read in a register 410 of the FPGA 41 (S11). Specifically, the DMA read execution API 232 acquires the table read start row 411 and the size 412 of the data to be read from, for example, the software PLC 24. The size 412 is a value obtained by converting the size information received from the software PLC 24 into a transfer packet size and the number of transfer packets by the DMA read execution API 232. The number of transfer packets is the number of size units (packets) into which the target data is divided when data is accessed from the FPGA 41 to the memory 42. The number of transfer packets is determined from the data size of the target data and the size per packet.

[0054] Then, the DMA read execution API 232 transmits a DMA read start request to the FPGA 41 (S12).

[0055] Then, the DMA read execution API 232 waits until the DMA data read by the FPGA 41 is completed (S13 "No") The data read from the memory 42 by the FPGA 41 is stored in the buffer memory 430 of the FPGA 41.

[0056] When the DMA data read by the FPGA 41 is completed (S13 "Yes"), the DMA read execution API 232 retrieves the data read from the memory 42 by the FPGA 41 from the buffer memory 430 and transfers it to the PLC 2 via the bus 10 (S14). Specifically, the DMA read execution API 232 references the DMA completion status 424 in the register 410, and if the DMA completion status 424 indicates that the DMA read has been completed, it executes the process of S14. After transferring the read data to the PLC 2, the DMA read execution API 232 resets the DMA completion status 424 to its initial state. At this point, the process of this flowchart ends.

[0057] 6 is a flowchart showing an example of the flow of DMA read processing executed by the hardware logic of the FPGA 41 according to the first embodiment. The processing of this flowchart starts when the FPGA 41 receives a DMA read start request from the DMA read execution API 232 described in FIG.

[0058] First, the FPGA 41 obtains the table read start row 411 and size 412 from the register 410 (S31).

[0059] Then, the FPGA 41 starts reading from the table reading start row 411 of the read DMA table 421 (S32).

[0060] Then, the FPGA 41 reads data from the block in the memory area corresponding to the block number written in the read record by DMA, and stores the data in the buffer memory 430 (S33).

[0061] If the end flag "1" is not set in the read record (S34 "No"), the FPGA 41 reads the block number registered in the next row of the read DMA table 421 (S35). Then, the process returns to S33 and the FPGA 41 reads data from the memory 42.

[0062] Then, if the end flag "1" is set in the read record (S34 "Yes"), the FPGA 41 registers the fact that the DMA read has been completed in the DMA completion status 424 of the register 410 (S36). For example, the FPGA 41 sets the flag "1" in the DMA completion status 424. Here, the processing of this flowchart ends. After the processing of this flowchart ends, the processing of S14 is executed by the DMA read execution API 232 described in FIG. 5.

[0063] 7 is a flowchart showing an example of the processing flow of the DMA write execution API 233 according to the first embodiment. The processing of this flowchart is executed, for example, at regular intervals.

[0064] First, the DMA write execution API 233 accesses the FPGA 41 of the transmission module 4 via the bus 10 and sets the write data in the buffer memory 430 (S21).

[0065] Then, the DMA write execution API 233 sets the table read start row 411 and the size 412 of the data to be read in the register 410 of the FPGA 41 (S22).

[0066] Then, the DMA write execution API 233 transmits a DMA write start request to the FPGA 41 (S23).

[0067] Then, the DMA write execution API 233 waits until the DMA data writing by the FPGA 41 is completed (S24 "No").

[0068] When the DMA data write by the FPGA 41 is completed (S24 "Yes"), the processing of this flowchart ends. Specifically, the DMA write execution API 233 refers to the DMA completion status 424 in the register 410, and when the completion of the DMA write is registered in the DMA completion status 424, the DMA write execution API 233 returns the DMA completion status 424 to its initial state, and the processing of this flowchart ends.

[0069] 8 is a flowchart showing an example of the flow of DMA write processing executed by the hardware logic of the FPGA 41 according to the first embodiment. The processing of this flowchart starts when the FPGA 41 receives a DMA write start request from the DMA write execution API 233 described in FIG.

[0070] First, the FPGA 41 obtains the table read start row 411 and size 412 from the register 410 (S41).

[0071] Then, the FPGA 41 starts reading from the table reading start row 411 of the write DMA table 422 (S42).

[0072] Then, the FPGA 41 writes the write data from the buffer memory 430 to the block in the memory area corresponding to the block number written in the read record by DMA (S43).

[0073] If the end flag "1" is not set in the read record (S44 "No"), the FPGA 41 reads the block number registered in the next row of the write DMA table 422 (S45). Then, the FPGA 41 returns to the process of S43 and writes the write data to the memory 42.

[0074] Then, if the end flag "1" is set in the read record (S44 "Yes"), the FPGA 41 registers the fact that the DMA write has been completed in the DMA completion status 424 of the register 410 (S46). For example, the FPGA 41 sets the flag "1" in the DMA completion status 424. At this point, the processing of this flowchart ends.

[0075] In this way, when the FPGA 41 of this embodiment receives a DMA write start request or a DMA read start request from the driver API, it reads or writes data from or to a block corresponding to a block number stored in the read DMA table 421 or the write DMA table 422 from the table read start row 411 to the position where the end flag is set, among the multiple blocks included in the memory 42. Therefore, according to the FPGA 41 of this embodiment, a single DMA write start request or a DMA read start request can be used to read or write data from or to multiple blocks that are arranged discontinuously in the memory 42.

[0076] As a comparative example, when a PLC driver API individually specifies non-contiguous areas in the memory of a transmission module to perform DMA, a single DMA write start request or DMA read start request can only execute a read or write process targeting one contiguous memory area. Therefore, in this comparative example, in order to execute a read or write process targeting multiple non-contiguous areas in memory, the PLC driver API executes a DMA write start request or a DMA read start request as many times as the number of non-contiguous areas, and each time such a request is issued, communication is executed via a bus between the PLC and the transmission module using PCI Express (registered trademark) or the like.

[0077] In contrast to this, according to the FPGA 41 of this embodiment, as described above, a single DMA write start request or DMA read start request can execute read or write processing for multiple blocks that are discontinuously arranged in the memory 42, thereby reducing the number of communications via PCI Express (registered trademark) or the like via the bus 10 between the PLC 2 and the transmission module 4. This also reduces the time required for the PLC 2 to access the memory 42.

[0078] (Second embodiment) In the first embodiment described above, the memory area of ​​the memory 42 to be read or written is specified in units of blocks. In this second embodiment, memory access can be performed by specifying a partial area within each block.

[0079] 9 is a diagram illustrating an example of the configuration of the PLC 2 and the transmission module 4 according to the second embodiment. In FIG. 9, the shaded areas in each block of the memory 42 are ranges that are subject to reading or writing. As shown in FIG. 9, when data is stored in a block of the memory 42, the target data is not necessarily stored in the entire block, and the target data may be stored in only a portion of the block.

[0080] The transmission module 4 of this embodiment includes a read DMA table 421a and a write DMA table 422a.

[0081] 10 is a diagram showing an example of a method for specifying a read target block according to the first embodiment. The read DMA table 421a according to this embodiment includes, in addition to the "end flag" and "block number" similar to those in the first embodiment, a "data storage address from the start address of the block" and a "data storage address from the start address of the block." It has an item of "Data size up to the end of the area".

[0082] The values ​​of the items in the read DMA table 421a and the write DMA table 422a are set by the DMA table setting API 231, as in the first embodiment.

[0083] The starting address of a block is the address corresponding to the starting position of the block. The "data size from the starting address of the block to the end of the area to be accessed" is the data size from the starting address of the block that can be selected for reading to the end address of the read area in which the data to be read is stored. The end address of the read area is the address corresponding to the end position of the read area.

[0084] Note that while Figure 10 illustrates the read DMA table 421a as an example, the write DMA table 422a also has the following items: "end flag," "block number," and "data size from the first address of the block to the end of the area to be accessed."

[0085] In this embodiment, the processing of the DMA read execution API 232 and the DMA write execution API 233 is similar to the processing of the first embodiment described with reference to FIGS.

[0086] In addition, in this embodiment, the DMA read process executed by the hardware logic of FPGA 41 reads out the "block number" and the "data size from the starting address of the block to the end of the area to be accessed" stored in the read DMA table 421a from the table read start row to the row where the end flag is set to "1" one record at a time.

[0087] Then, the FPGA 41 identifies the end address of the range in which the data to be read is stored in the block of the memory 42 corresponding to the block number written in the read record, based on the "data size from the start of the block to the end of the area to be accessed." The FPGA 41 reads, by DMA, data stored in the range from the start address of the block corresponding to the block number read from the read DMA table 421a out of the multiple blocks in the memory 42 to the end address of the range in which the data to be read is stored, and saves the data in the buffer memory 430.

[0088] 10, the "data size from the start address of the block to the end of the area to be accessed" associated with block number "1" is "n1." In this case, the FPGA 41 reads data from the start address of block 1 in the memory 42 up to the area whose data size is "n1."

[0089] 10, the "data size from the start address of the block to the end of the area to be accessed" associated with block number "3" is "n7." In this case, the FPGA 41 reads data from the area starting from the start address of block 3 in the memory 42 up to the data size of "n7." Similarly, for blocks corresponding to other block numbers set in the read DMA table 421a, the FPGA 41 reads data of the "data size from the start address of the block to the end of the area to be accessed" from the start address of the block.

[0090] In this embodiment, the DMA write process executed by the hardware logic of the FPGA 41 reads, record by record, the "block number" and the "data size from the block's start address to the end of the area to be accessed" stored in the write DMA table 422a from the table read start row to the row with the end flag set to "1." The FPGA 41 then identifies the end address of the write range in the block in the memory 42 corresponding to the block number written in the read record based on the "data size from the block's start to the end of the area to be accessed." The FPGA 41 writes the data to be written in the range from the start address of the block corresponding to the block number read from the write DMA table 422a to the end address of the write range, among the multiple blocks in the memory 42.

[0091] Note that there may be a blank area between the start position of a block in memory 42 and the area where FPGA 41 actually writes data, but the write data of this embodiment takes into account the blank area included in the write area and is generated by software PLC 24. For example, if the "data size from the start of the block to the end of the area to be accessed" is 16 bytes and the first 8 bytes of the block are blank, the software PLC 24 creates a total of 16 bytes of write data, with the first 8 bytes being blank and the last 8 bytes being meaningful data.

[0092] As described above, the FPGA 41 of this embodiment includes a read DMA table 421a that includes the fields "data size from the start address of the block to the end of the area to be accessed" in addition to the "end flag" and "block number." When reading data from the memory 42, the FPGA 41 reads the data size from the start address of the block corresponding to the block number read from the read DMA table 421a to the end of the area to be accessed. With this configuration, the FPGA 41 of this embodiment can achieve the same effects as the first embodiment, and further reduce the size of the data to be read. Therefore, the FPGA 41 of this embodiment can reduce the amount of data transferred from the transmission module 4 to the PLC 2, thereby shortening the transfer time.

[0093] (Third embodiment) In the second embodiment described above, the memory area to be read from was specified by the data size from the start address of the block to be accessed to the end of the area to be accessed. In this third embodiment, the start address to be accessed when reading or writing to each block can be specified to be something other than the start address of the block.

[0094] 11 is a diagram illustrating an example of the configuration of the PLC 2 and the transmission module 4 according to the third embodiment. In this embodiment, as well as in the memory 42, the target data is not necessarily stored in an entire block, and the target data may be stored in only a partial area within a block.

[0095] The transmission module 4 of this embodiment includes a read DMA table 421b and a write DMA table 422b.

[0096] 12 is a diagram showing an example of a method for identifying a read target block according to the third embodiment. The read DMA table 421b according to this embodiment has the items of "access start address" and "data size from the access start address to the end of the access target area" in addition to the "end flag" and "block number" similar to those in the first embodiment.

[0097] The "access start address" in the read DMA table 421b is an address corresponding to the start position of the read area in which the data to be read is stored in the block corresponding to the block number. The start address is not limited to the start address of the block, but may be an address located in the middle of the block. For example, in the example shown in FIG. 11, in block 3 of memory 42, the area in which the data to be read is stored, which is shown shaded, starts in the middle of block 3.

[0098] The "data size from the access start address to the end of the area to be accessed" in the read DMA table 421b is the data size of the read area.

[0099] The values ​​of each item in the read DMA table 421b are set by the DMA table setting API 231, as in the first and second embodiments.

[0100] In this embodiment, the processing of the DMA read execution API 232 and the DMA write execution API 233 is similar to the processing of the first embodiment described with reference to FIGS.

[0101] In addition, in this embodiment, the DMA read process executed by the hardware logic of FPGA 41 reads out the "block number" and the "data size from the access start address to the end of the area to be accessed" stored in the read DMA table 421b from the table read start row to the position where the end flag "1" is set, one record at a time, from among the multiple blocks in memory 42.

[0102] Then, the FPGA 41 identifies the start address of the range in which the data to be read is stored in the block corresponding to the block number written in the read record, based on the "access start address." The FPGA 41 also identifies the end address of the range in which the data to be read is stored in the block, based on the "data size from the access start address to the end of the access target area." The FPGA 41 uses DMA to read the data stored in the range from the "access start address" of the block corresponding to the block number read from the read DMA table 421b to the end address of the range in which the data to be read is stored, and saves the data in the buffer memory 430.

[0103] 12, the "access start address" associated with block number "1" is "m1," and the "data size from the access start address to the end of the area to be accessed" is "n1." In this case, the FPGA 41 reads data from the area starting from address "m1" in block 1 of the memory 42 up to the data size of "n1."

[0104] 12, the "access start address" associated with block number "3" is "m6," and the "data size from the access start address to the end of the area to be accessed" is "n2." In this case, the FPGA 41 reads data from the area of ​​block 3 in the memory 42, from address "m6" to the area with a data size of "n2." Similarly, for blocks corresponding to other block numbers set in the read DMA table 421b, the FPGA 41 reads data from the "access start address" up to the "data size from the access start address to the end of the area to be accessed."

[0105] Note that while Figure 12 illustrates the read DMA table 421b as an example, the write DMA table 422b also has the following items: "end flag," "block number," "access start address," and "data size from the access start address to the end of the area to be accessed."

[0106] The "access start address" in the write DMA table 422b is an address indicating the start address of the write area where the write data is written in the block corresponding to the block number.

[0107] Furthermore, the "data size from the access start address to the end of the area to be accessed" in the write DMA table 422b is the data size of the write area into which the data to be written is written.

[0108] Furthermore, while Figure 12 illustrates an example of a method for identifying a block to be read, in the DMA write process executed by the hardware logic of FPGA 41, the block to be written and the area to be written in that block are identified based on the "block number," "end flag," "access start address," and "data size from the access start address to the end of the area to be accessed" set in the write DMA table 422b, just like the method described in Figure 12.

[0109] Thus, the FPGA 41 of this embodiment is provided with a read DMA table 421b and a write DMA table 422b, which have items for "access start address" and "data size from the access start address to the end of the area to be accessed" in addition to "end flag" and "block number," and when accessing memory 42, accesses data equal to the data size from the access start address of the block corresponding to the block number read from the read DMA table 421b or write DMA table 422b to the end of the area to be accessed. With this configuration, the FPGA 41 of this embodiment can further reduce the size of the data to be accessed than the second embodiment.

[0110] In each of the above-described embodiments, an example is illustrated in which the FPGA 41 has one read DMA table 421, 421a, 421b and one write DMA table 422, 422a, 422b. However, if there are multiple read processes and write processes on the PLC 2 side that target different blocks of the memory 42, multiple read DMA tables 421, 421a, 421b and multiple write DMA tables 422, 422a, 422b may be provided according to the set of blocks targeted by each process.

[0111] In the above-described embodiments, the DMA technique in block units has been described using the transmission module 4 as an example, but the I / O transmission module 3 may also execute DMA in block units using a configuration similar to that of the above-described transmission module 4. Furthermore, the transmission module 4 and the I / O transmission module 3 may be collectively referred to as transmission modules.

[0112] As described above, according to the first to third embodiments, it is possible to efficiently access memory areas that are arranged non-contiguously.

[0113] The various programs executed by the PLC 2 in each of the above-described embodiments may be downloaded from an engineering tool, or may be provided as installable or executable files recorded on a computer-readable recording medium such as a CD-ROM, a flexible disk (FD), a CD-R, or a digital versatile disk (DVD).

[0114] The various programs executed by the PLC 2 of each of the above-described embodiments may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. The various programs executed by the PLC 2 of each of the above-described embodiments may be provided or distributed via a network such as the Internet. The various programs executed by the PLC 2 of each of the above-described embodiments may be provided by being pre-installed in a ROM or the like.

[0115] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0116] 1,1a,1b PLC station 3, 3a, 3b I / O transmission module 4, 4a, 4b Transmission Module 5 Control Network 6, 6a, 6b Sensor 7. HMI 10 Bus 21 Device Drivers 23 Driver API 24 Software PLC 25 Memory section 41 FPGA 42 memory 231 DMA table setting API 232 DMA read execution API 233 DMA Write Execution API 410 Register 411 Table reading start row 412 size 421, 421a, 421b DMA table for reading 422,422a,422b Write DMA table 430 buffer memory S Control System

Claims

[Claim 1] when receiving registration of a block number of a block selectable as a data read target among a plurality of blocks obtained by dividing a storage area of ​​a memory into blocks of a specified size and a first end flag indicating a final block that will be read last among the blocks selectable as data read targets, storing the block number of the block selectable as a data read target and the first end flag in a first table of a register in association with each other; when receiving registration of a block number of a block selectable as a target for writing data from among the plurality of blocks and a second end flag indicating a final block that will be the last block in the order of writing from among the blocks selectable as targets for writing, storing the block number of the block selectable as a target for writing and the second end flag in a second table of the register in association with each other; when a read start request for reading data from the memory and a read start row of the first table in the read start request are acquired, read data from a block corresponding to a block number stored in the first table from the read start row to the row in which the first end flag is set, among the plurality of blocks in the memory; when a write start request for the memory, a read start row of the second table in the write start request, and data to be written to the memory are acquired, the write data is written to a block of the plurality of blocks in the memory that corresponds to a block number stored in the second table from the read start row to the row in which the second end flag is set, the first table further has an area for storing a start address of a read area in which data to be read is stored in each block corresponding to each block number, and a data size of the read area; the second table further has an area for storing a start address of a write area into which data is written in each block corresponding to each block number, and a data size from the start address to the end of the write area; when receiving registration of the block numbers of the blocks selectable as the read target, the first end flag, the start addresses of the read areas in which the data to be read is stored in the blocks corresponding to the block numbers, and the data size of the read areas, storing the block numbers of the blocks selectable as the read target, the first end flag, the start addresses of the read areas, and the data size of the read areas in the first table in association with each other; when receiving registration of the block numbers of the blocks selectable as the write target, the second end flag, the start addresses of the write areas into which data is written in the blocks corresponding to the block numbers, and the data sizes of the write areas, storing the block numbers of the blocks selectable as the write target, the second end flag, the start addresses of the write areas, and the data sizes of the write areas in association with each other in the second table; When the read start request and the read start row of the first table in the read start request are acquired, read data stored in the read area of ​​each block corresponding to a block number stored in the first table from the read start row to the row in which the first end flag is set, among the plurality of blocks of the memory; when the write start request, the read start row of the second table in the write start request, and the data to be written to the memory are acquired, the write data is written to the write area in a block corresponding to a block number stored in the second table from the read start row to the row in which the second end flag is set, among the plurality of blocks in the memory; Integrated circuit.

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