Switching control circuits, power supply circuits

Abstract

To provide a switching control circuit capable of improving power factor of a PFC circuit, and a power supply circuit.SOLUTION: A switching control circuit of a power supply circuit having an inductor and a transistor for controlling an inductor current includes: a first command value output circuit for outputting a first command value according to a difference between a feedback voltage according to an output voltage and a reference voltage Vref; a correction circuit for correcting the first command value to output a second command value; and a drive signal output circuit for outputting a drive signal Vdr for turning on a transistor and outputting the drive signal for turning off the transistor based on the second command value when the inductor current reaches a predetermined value and a first time period elapses from a first timing when the transistor turns on. The correction circuit corrects the first command value so that an ON period of the transistor becomes longer when the first time period have elapsed from the first timing after the inductor current reaches the predetermined value.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to a switching control circuit and a power supply circuit. [Background technology]

[0002] A typical power factor correction circuit (hereinafter referred to as a PFC (Power Factor Correction) circuit) that operates in critical mode improves the power factor of a power supply by making the waveform of the peak value of the inductor current flowing through the inductor similar to the rectified voltage obtained by rectifying an AC voltage (for example, Patent Documents 1 to 4). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-104218 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-85865 [Patent Document 3] JP 2018-64410 A [Patent Document 4] Japanese Patent Publication No. 2020-14325 Summary of the Invention [Problem to be solved by the invention]

[0004] In a PFC circuit operating in critical conduction mode, for example, the switching frequency of the power transistor may become high when the phase angle of the rectified voltage is small. As the switching frequency becomes higher, losses in the power transistor and inductor increase. Therefore, some PFC circuits have a limit on the switching frequency so that it does not exceed a certain value.

[0005] However, limiting the switching frequency of the PFC circuit lengthens the off period during which the power transistor is off, making it difficult to make the waveform of the peak value of the inductor current similar to the rectified voltage.

[0006] The present invention has been made in consideration of the above-mentioned conventional problems, and has an object to provide a switching control circuit that can improve the power factor of a PFC circuit. [Means for solving the problem]

[0007] A first aspect of the present invention that solves the above-mentioned problems includes a power supply circuit that generates an output voltage of a target level from the AC voltage, the power supply circuit including an inductor to which a voltage corresponding to an AC voltage is applied, and a transistor that controls an inductor current flowing through the inductor. The switching control circuit controls switching of the transistor and includes: a first command value output circuit that outputs a first command value corresponding to a difference between a feedback voltage corresponding to the output voltage and a reference voltage; a correction circuit that corrects the first command value and outputs it as a second command value; a first timing circuit that measures a first period from a first timing to turn on the transistor; and a drive signal output circuit that outputs a drive signal to turn on the transistor when the inductor current reaches a predetermined value and the first period has elapsed since the first timing, and outputs the drive signal to turn off the transistor based on the second command value. When the first period has elapsed since the first timing after the inductor current reaches the predetermined value, the correction circuit corrects the first command value so that the on-period of the transistor is longer.

[0008] Furthermore, in a second aspect of the present invention that solves the above-mentioned problem, a power supply circuit that generates an output voltage of a target level from an AC voltage includes: an inductor to which a voltage corresponding to the AC voltage is applied; a transistor that controls an inductor current flowing through the inductor; and a switching control circuit that controls switching of the transistor, wherein the switching control circuit includes: a first command value output circuit that outputs a first command value corresponding to a difference between a feedback voltage corresponding to the output voltage and a reference voltage; a correction circuit that corrects the first command value and outputs it as a second command value; a first timing circuit that measures a first period from a first timing to turn on the transistor; and a drive signal output circuit that outputs a drive signal to turn on the transistor when the inductor current reaches a predetermined value and the first period has elapsed since the first timing, and outputs the drive signal to turn off the transistor based on the second command value, wherein the correction circuit corrects the first command value so that an on-period during which the transistor is on is lengthened when the first period has elapsed since the first timing after the inductor current reaches the predetermined value. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a switching control circuit that can improve the power factor in a PFC circuit. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram illustrating an example of an AC-DC converter 10. FIG. [Figure 2] FIG. 2 is a diagram illustrating an example of a power factor correction IC 25. [Figure 3] FIG. 2 is a diagram illustrating an example of a digital circuit 43a. [Figure 4] FIG. 4 is a diagram showing main waveforms of a digital circuit 43a. [Figure 5] 2 is a diagram for explaining main waveforms of the AC-DC converter 10. FIG. [Figure 6] FIG. 2 is a diagram for explaining an inductor current IL. [Figure 7]This is a diagram for explaining the inductor current IL. [Figure 8] This is a diagram for explaining the inductor current IL. [Figure 9] This is a diagram showing an example of the digital circuit 45b. [Figure 10] This is a diagram showing an example of the correction circuit 71. [Figure 11] This is a diagram for explaining the inductor current IL. [Figure 12] This is a diagram showing the simulation result. [Figure 13] This is a diagram showing an example of the command value output circuit 81. [Figure 14] This is a diagram showing an example of the correction circuit 75. [Figure 15] This is a diagram showing an example of the command value output circuit 202. [Figure 16] This is a diagram showing an example of the command value output circuit 203.

Embodiments for Carrying Out the Invention

[0011] From the description in this specification and the attached drawings, at least the following matters become clear. Hereinafter, the "circuit" in this embodiment includes not only analog circuits and wired-logic type logic circuits, but also functional blocks (or means) included in a DSP (Digital Signal Processor), a microcomputer, etc. that can execute digital arithmetic processing.

[0012] =====This Embodiment===== <<<Overview of the AC-DC Converter 10>>> FIG. 1 is a diagram showing the configuration of an AC-DC converter 10 according to an embodiment of the present invention. The AC-DC converter 10 is a boost-type PFC circuit that generates an output voltage Vout at a target level from the AC voltage Vac of a commercial power supply.

[0013] The AC-DC converter 10 includes a full-wave rectifier circuit 20, capacitors 21 and 22, an inductor 23, a diode 24, a power factor correction IC 25, an NMOS transistor 26, and resistors 30 to 32. The AC-DC converter 10 corresponds to a "power supply circuit."

[0014] The full-wave rectifier circuit 20 full-wave rectifies the input predetermined AC voltage Vac and outputs it as an input voltage Vrec to the capacitor 21 and the inductor 23. The AC voltage Vac has an effective value of 140 to 240 V and a frequency of 50 to 60 Hz, for example. In the following description of this embodiment, although voltage basically refers to a potential difference with respect to a reference point (GND in the drawing), the AC voltage Vac refers to the voltage between terminals.

[0015] The capacitor 21 smoothes the input voltage Vrec, and the capacitor 22 forms a boost chopper circuit together with the inductor 23, the diode 24, and the NMOS transistor 26. Therefore, the charging voltage of the capacitor 22 becomes the DC output voltage Vout.

[0016] The power factor correction IC 25 is an integrated circuit that controls the switching of the NMOS transistor 26 so that the level of the output voltage Vout becomes a target level (e.g., 400 V) while improving the input power factor of the AC-DC converter 10. Specifically, the power factor correction IC 25 drives the NMOS transistor 26 based on the inductor current IL flowing through the inductor 23 and the output voltage Vout. The power factor correction IC 25 is provided with terminals CS, FB, and OUT, which will be described in detail later. In this embodiment, terminals other than the terminal CS of the power factor correction IC 25 are omitted for convenience. The power factor correction IC 25 corresponds to a "switching control circuit."

[0017] The NMOS transistor 26 is a power transistor for controlling the power to the load 11 of the AC-DC converter 10. In this embodiment, the NMOS transistor 26 is an N-type MOS (Metal Oxide Semiconductor) transistor, but is not limited to this and may be, for example, a P-type MOS transistor, a bipolar transistor, or another switching element. The gate electrode of the NMOS transistor 26 is connected to the terminal OUT.

[0018] The resistors 30 and 31 form a voltage divider circuit that divides the output voltage Vout and generates a feedback voltage Vfb that is used when switching the NMOS transistor 26. The feedback voltage Vfb generated at the node to which the resistors 30 and 31 are connected is applied to the terminal FB.

[0019] The resistor 32 is a resistor for detecting the inductor current IL, and has one end connected to the source electrode of the NMOS transistor 26 and the other end connected to the terminal CS.

[0020] <<<About the Power Factor Correction IC25>>> ==Configuration of Power Factor Correction IC25== 2 is a diagram showing an example of the power factor correction IC 25. The power factor correction IC 25 includes a level shift circuit (LS) 40, analog-to-digital converters (ADCs) 41 and 42, a digital circuit 43, and a buffer circuit 44.

[0021] The level shift circuit 40 is a circuit that shifts the level of the voltage Vcs, which corresponds to the inductor current IL, to an appropriate level. Specifically, the level shift circuit 40 shifts the level of the voltage Vcs, which varies around 0V (zero volts), and outputs the voltage VL. The level shift circuit 40 shifts the voltage Vcs so that the center level of the voltage VL becomes a predetermined level. Here, the "predetermined level" is, for example, half the level (2.5V) of a predetermined power supply voltage (e.g., 5V) generated inside the power factor correction IC 25.

[0022] The level shift circuit 40 includes, for example, a voltage divider circuit or a buffer circuit (or an inverting amplifier circuit) in which a power supply voltage is applied to the high-voltage side and a voltage Vcs is applied to the low-voltage side. The level shift circuit 40 changes the voltage VL with the same polarity as the inductor current IL. Therefore, in this embodiment, when the inductor current IL increases, the voltage VL also increases.

[0023] The AD converter 41 converts the voltage VL into a digital value, and the AD converter 42 converts the feedback voltage Vfb into a digital value. As described above, the voltage VL corresponds to the inductor current IL. For this reason, in the following description of the present embodiment, the voltage VL converted into a digital value may be referred to as the inductor current IL for convenience. The AD converter 41 corresponds to the "second AD converter," and the AD converter 42 corresponds to the "first AD converter."

[0024] The digital circuit 43 is a circuit that outputs a drive signal Vdr for driving the NMOS transistor 26 based on the feedback voltage Vfb and the inductor current IL. The digital circuit 43 is a wired logic circuit that performs various calculations, and is configured to include, for example, logic gates, flip-flops, and memories. However, the digital circuit 43 may also be a DSP (Digital Signal Processor) or a microcomputer. Details of the digital circuit 43 will be described later.

[0025] The buffer circuit 44 is a drive circuit that drives the NMOS transistor 26 based on the drive signal Vdr. Specifically, the buffer circuit 44 turns on the NMOS transistor 26 when the drive signal Vdr goes high (hereinafter referred to as H level), and turns off the NMOS transistor 26 when the drive signal Vdr goes low (hereinafter referred to as L level).

[0026] ==Digital Circuit 43a (Basic Configuration)== 3 shows an example of a digital circuit 43a including a basic circuit for improving the power factor. A digital circuit 43b (described later) of this embodiment includes a circuit for limiting the switching frequency and a circuit for correcting a command value. However, before describing the details of the digital circuit 43b, the basic configuration for improving the power factor will be described using the digital circuit 43a of FIG. 3.

[0027] The digital circuit 43a includes comparison circuits 60 and 64, a subtraction circuit 61, a voltage adjustment circuit (AVR: Automatic Voltage Regulator) 62, a counter 63, an RS flip-flop 65, and a delay circuit 66. In the following description, it is assumed that the inductor current IL as a digital value and the feedback voltage Vfb as a digital value are input to the digital circuit 43a.

[0028] The comparator circuit 60 compares the current value of the inductor current IL with a predetermined current value I0 (for example, several mA) that is slightly greater than zero, and detects whether the inductor current IL is nearly zero (hereinafter, "nearly zero" will be referred to simply as "0" (zero) where appropriate). When the current value of the inductor current IL is smaller than the current value I0 and the inductor current becomes zero, the comparator circuit 60 outputs an H-level signal Vc1. On the other hand, when the current value of the inductor current IL is greater than the current value I0, the comparator circuit 60 outputs an L-level signal Vc1. The current value I0 corresponds to the "predetermined value."

[0029] The subtraction circuit 61 subtracts the feedback voltage Vfb from a reference voltage Vref that serves as a reference for the output voltage Vout at a target level (for example, 400 V), and calculates an error E1 between the reference voltage Vref and the feedback voltage Vfb.

[0030] The voltage adjustment circuit 62 outputs a command value V1 for matching the level of the feedback voltage Vfb with the level of the reference voltage Vref in accordance with the error E1. The command value V1 corresponds to a "first command value," and the voltage adjustment circuit 62 corresponds to a "first command value output circuit." The subtraction circuit 61 and the voltage adjustment circuit 62 in this embodiment correspond to a so-called error amplifier circuit that amplifies and integrates the error E1, for example.

[0031] The counter 63 is a circuit that outputs a signal Vcnt for determining the timing to turn off the NMOS transistor 26, and when the drive signal Vdr goes high, the counter 63 increments its count value from zero in accordance with a clock signal (not shown). In other words, when the drive signal Vdr goes high, the counter 63 outputs a signal equivalent to a ramp wave in which the value of the signal Vcnt increases in proportion to the elapsed time.

[0032] The comparator circuit 64 is a circuit that compares the magnitude of the command value V1 with that of the signal Vcnt. Specifically, when the signal Vcnt is greater than the command value V1, the comparator circuit 64 outputs an H-level signal Vc2, and when the signal Vcnt is greater than the command value V1, the comparator circuit 64 outputs an L-level signal Vc2.

[0033] The signal Vc1 is input to the S input of the RS flip-flop 65, and the signal Vc2 is input to the R input. Therefore, when the signal Vc1 goes to H level, the signal Vq1, which is the Q output of the RS flip-flop 65, goes to H level. On the other hand, when the signal Vc2 goes to H level, the signal Vq1 goes to L level.

[0034] The delay circuit 66 delays the signal Vq1 by a predetermined time and outputs it as the drive signal Vdr. Note that this "predetermined time" is set to be longer than the time from when the NMOS transistor 26 turns off and the inductor current IL decreases to zero until the parasitic capacitance present between the drain and source of the NMOS transistor 26 discharges and the voltage drops. Note that the time when the inductor current IL becomes zero is the theoretical time when the NMOS transistor 26 is next turned on in the critical conduction mode operation.

[0035] For this reason, in this embodiment, it is possible to prevent the NMOS transistor 26 from being turned on when the drain-source voltage of the NMOS transistor 26 is large. This indicates that this embodiment employs a technique for preventing switching loss by utilizing the LC resonance that occurs between the inductor 23 and the parasitic capacitance of the NMOS transistor 26 after the inductor current IL becomes zero.

[0036] ==Operation of digital circuit 43a== With reference to FIG. 4, the operation of the digital circuit 43a when the AC-DC converter 10 generates an output voltage Vout at a target level from a predetermined AC voltage Vac and supplies power to a certain load will be described.

[0037] First, at time t0, the inductor current IL decreases and reaches a current value I0, at which point the comparator circuit 60 changes the signal Vc to an H level. Then, when the signal Vc1 goes to an H level, the RS flip-flop 65 outputs an H-level signal Vq1. As a result, the drive signal Vdr output from the delay circuit 66 also goes to an H level.

[0038] When the drive signal Vdr goes high, the NMOS transistor 26 turns on, causing the inductor current IL to increase. Note that, for convenience, the predetermined time for which the delay circuit 66 delays the signal Vq1 is omitted here because it is short.

[0039] Furthermore, when the drive signal Vdr goes high, the count value of the counter 63 is incremented, and the signal Vcnt also increases. Then, at time t1, when the level of the signal Vcnt becomes higher than the level of the command value V1, the comparator circuit 64 changes the signal Vc2 to high. As a result, the RS flip-flop 65 is reset, and the signal Vq1 goes low.

[0040] When the signal Vq1 goes low, the drive signal Vdr also goes low, turning off the NMOS transistor 26. As a result, the inductor current IL gradually decreases. At time t2, the inductor current IL decreases and becomes zero, and the operation at time t0 is repeated.

[0041] When AC-DC converter 10 generates output voltage Vout at a target level from a predetermined AC voltage Vac, the capacitance of capacitor 22 is sufficiently large, and feedback voltage Vfb remains substantially constant within a period of approximately one cycle of Vac. As a result, command value V1 output from voltage adjustment circuit 62 also remains substantially constant, and the period during which NMOS transistor 26 is on (for example, the period from time t0 to t1) also remains substantially constant.

[0042] Furthermore, when the NMOS transistor 26 is turned on, if the level of the voltage Vrec obtained by rectifying the AC voltage Vac increases, the current value of the inductor current IL also increases. As a result, as shown in FIG. 5, the waveform of the peak value of the inductor current IL has a similar shape to that of the voltage Vrec.

[0043] ==Inductor current IL== <<General waveforms>> Fig. 6 is a diagram for explaining the details of the inductor current IL in Fig. 5. Here, if the peak value of the inductor current IL is Ip1 and the period during which the NMOS transistor 26 is on is period Ton1, the peak value Ip1 of the inductor current IL is expressed by equation (1). Ip1=(Vrec / L)×Ton1 (1) Here, the inductance of the inductor 23 is set to L.

[0044] The period Tf1 during which the NMOS transistor 26 is turned off and the inductor current IL decreases is expressed by equation (2). Tf1=(L×Ip1) / (Vout-Vrec) =(Vrec / (Vout-Vrec))×Ton1···(2)

[0045] In addition, in FIG. 6, the average value Ia1 of the inductor current IL is expressed by equation (3). Ia2=Ip1 / 2=(Vrec×Ton1) / (2×L)···(3)

[0046] 5, the peak value Ip1 is low near a low phase angle (for example, a phase angle of 0° (or 180°)). Furthermore, near a low phase angle, the value of the input voltage Vrec is also small, and the period Tf is therefore short. Therefore, in this region, even if the period Ton1 is constant, the cycle of the drive signal Vdr (period Ton1 + period Tf) is short, and the switching frequency increases.

[0047] When the switching frequency increases, the power consumption of the NMOS transistor 26 and the inductor 23 increases, so it is necessary to limit the increase in the switching frequency so that the switching frequency does not become higher than necessary. In this embodiment, "limiting the switching frequency" means preventing the switching frequency (i.e., the frequency of the drive signal Vdr) from becoming higher than a predetermined value.

[0048] <<When the switching frequency is limited>> FIG. 7 is a diagram illustrating the inductor current IL when the switching frequency is limited. In FIG. 7, the dotted line is an example of the inductor current IL when there is no frequency limit, and the solid line is an example of the inductor current IL when there is a frequency limit. Here, the period of the drive signal Vdr is limited so as not to be shorter than the period Tx. Here, the waveform when the switching frequency is limited will be mainly described, and the details of the circuit configuration for limiting the switching frequency will be described later.

[0049] First, for example, when the NMOS transistor 26 is on from time t10 to t11, the inductor current IL increases. Then, when the NMOS transistor 26 is turned off at time t11, the inductor current IL decreases and becomes zero at time t12.

[0050] When the switching frequency is not limited, the inductor current IL increases again after reaching zero, as shown by the dotted line. However, when the switching frequency is limited, the NMOS transistor 26 does not turn on from time t10 until time t13, when the period Tx has elapsed. Therefore, from time t12 to t13, the inductor current IL is zero, as shown by the solid line. As a result, when the switching frequency is limited, the average value Ia2 (two-dot chain line) of the inductor current IL (solid line) within a switching period is smaller than the average value Ia1 (one-dot chain line) of the inductor current IL (dotted line) within a switching period.

[0051] Therefore, when the switching frequency is limited, the power consumption of the NMOS transistor 26 and the inductor 23 can be reduced, but the average value Ia2 of the inductor current IL within the switching period decreases, causing a deviation from the rectified waveform of the AC voltage, resulting in a deterioration in the power factor.

[0052] <<Methods for increasing the average Ia2>> To increase the average value Ia2 when the switching frequency is limited, for example, the peak value Ip2 of the inductor current IL (solid line) can be made larger than the peak value Ip1 of the inductor current IL (dotted line). Figure 8 is a diagram illustrating the waveform of the inductor current IL with the peak value Ip2 increased. Hereinafter, the inductor current IL (solid line) when the switching frequency is limited will be mainly described.

[0053] The peak value Ip2 of the inductor current IL (solid line) is expressed by equation (4) when the ON period during which the NMOS transistor 26 is ON is Ton2. Ip2=(Vrec / L)×Ton2 (4)

[0054] Furthermore, the period Tf2 from when the NMOS transistor 26 turns off until the inductor current IL (solid line) becomes zero is expressed by equation (5). Tf2=(L×Ip2) / (Vout-Vrec) =(Vrec / (Vout-Vrec))×Ton2···(5)

[0055] Here, the average value Ia2 of the inductor current IL (solid line) is expressed by equation (6). Ia2=(Ip2 / 2)×((Ton2+Tf2) / Tx)···(6) Then, when the peak value Ip2 of the equation (4) and the period Tf2 of the equation (5) are substituted into the equation (6), the equation (7) is obtained. Ia2=(Vrec×Vout×(Ton2) 2 ) / (2×L×Tx×(Vout-Vrec))...(7)

[0056] As is clear from equation (7), the on-period Ton2 can be lengthened to increase the average value Ia2 and improve the power factor. Here, the extent to which the on-period Ton2 should be lengthened is calculated using the average value of the "conduction factor C," which indicates the proportion of the inductor current IL (solid line) flowing during the period Tx. The average value of the conduction factor C is obtained by adding up the conduction factors for each switching period (i.e., each cycle) for several cycles (e.g., 2 to 10 cycles) and dividing the sum by the number of cycles obtained.

[0057] In this embodiment, the average value of the conductivity C is expressed by the following formula (8): Furthermore, hereinafter, unless otherwise specified, the average value of the conductivity C will be simply referred to as "conductivity C." C = (Ton2 + Tf2) / Tx (8)

[0058] 8 is relatively short, the next on-period Ton2 is calculated by multiplying the on-period Ton1 by the reciprocal of the conduction rate C (see equation (9)). Here, the next on-period Ton2 is, for example, the period from time t21. Ton2=Ton1×(1 / C) (9) The conduction ratio C increases as the on-period Ton2 becomes shorter, and decreases as the on-period Ton2 becomes longer. Therefore, when equation (9) is repeatedly calculated and the on-period Ton2 becomes longer, the on-period Ton2 converges to a certain value.

[0059] When the on-period Ton2 converges, the following equation (10) is established. Ton2 = Ton1 × (1 / C) =Ton1×((Ton2+Tf2) / Tx)···(10)

[0060] When the period Tf2 of the formula (5) is substituted into the formula (10) and rearranged, the formula (11) is established. (Ton2) 2 =(Ton1×Tx×(Vout-Vrec)) / Vout...(11)

[0061] Then, by substituting equation (11) into the right side of equation (7) and rearranging, the average value Ia2 is expressed by equation (12). Ia2=(Vrec×Ton1) / (2×L)···(12)

[0062] The right-hand side of equation (12) is the average value Ia1 of the inductor current IL shown in equation (3). Therefore, by repeating equation (9) and varying the on-period Ton2 according to the reciprocal of the conduction ratio C, the on-period Ton2 converges. Furthermore, in this case, the average value Ia2 is equal to the average value Ia1 regardless of the levels of the input voltage Vrec and the output voltage Vout, and therefore the power factor is improved. In this embodiment, the power factor of the AC-DC converter 10 is improved by using a circuit that realizes this principle.

[0063] ==Digital Circuit 43b== 9 is a diagram showing an example of the configuration of a digital circuit 43b capable of realizing the principle for changing the average value Ia2 to the average value Ia1. The digital circuit 43b includes a comparison circuit 60, a subtraction circuit 61, a voltage adjustment circuit (AVR) 62, a counter 70, a correction circuit 71, and a drive signal output circuit 72. Note that blocks with the same reference numerals in FIG. 3 and FIG. 9 are the same. Therefore, the counter 70, the correction circuit 71, and the drive signal output circuit 72 will be mainly described here.

[0064] The counter 70 is a time counter that measures a period Tx corresponding to the upper limit of the switching frequency from the timing (hereinafter referred to as "timing ta") when the drive signal Vdr becomes H level. Specifically, the counter 70 outputs an L-level signal Vt before the period Tx has elapsed since the timing ta, and outputs an H-level signal Vt after the period Tx has elapsed since the timing ta. The timing ta corresponds to the "timing (first timing) when the NMOS transistor 26 turns on," the counter 70 corresponds to the "first timing circuit," and the period Tx corresponds to the "first period."

[0065] The correction circuit 71 is a circuit that corrects the command value V1 and outputs the command value V2 so that the on-period Ton of the NMOS transistor 26 is longer when the switching frequency is limited. The correction circuit 71 will be described in detail later.

[0066] The drive signal output circuit 72 outputs the drive signal Vdr based on the signal Vc1 from the comparator circuit 60, the signal Vt from the counter 70, and the command value V2. Specifically, the drive signal output circuit 72 outputs an H-level drive signal Vdr when the inductor current IL becomes zero and a predetermined period Tx has elapsed since timing ta. Furthermore, the drive signal output circuit 72 outputs an L-level drive signal Vdr when the on-period Ton reaches the period determined by the command value V2.

[0067] The drive signal output circuit 72 includes a counter 63, a comparison circuit 64, an RS flip-flop 65, a delay circuit 66, and an AND circuit 67. As described above, circuits with the same reference numerals are the same in Fig. 3 and Fig. 9. For this reason, the comparison circuit 64 to which the command value V2 is input and the AND circuit 67 will be mainly described here.

[0068] The comparator circuit 64 is a circuit that compares the magnitude of the command value V2 with that of the signal Vcnt. Specifically, if the signal Vcnt is greater than the command value V2, the comparator circuit 64 outputs an H-level signal Vc2, and if the signal Vcnt is greater than the command value V2, the comparator circuit 64 outputs an L-level signal Vc2.

[0069] The AND circuit 67 calculates the logical AND of the signal Vc1 from the comparator circuit 60 and the signal Vt from the counter 70, and outputs the result as a signal Va. Therefore, the AND circuit 67 outputs a high-level signal Va only when the inductor current IL has been determined to be zero (regardless of whether it has remained exactly at zero since then) and a period of time equal to or greater than Tx has elapsed since timing ta. Therefore, the drive signal output circuit 72 will not output a drive signal Vdr whose switching period is shorter than Tx. In other words, the drive signal output circuit 72 limits the frequency of the drive signal Vdr.

[0070] Furthermore, the drive signal output circuit 72 outputs an L-level drive signal Vdr when the signal Vcnt of the counter 63 becomes the command value V2 and the comparator circuit 64 outputs an H-level Vc2. As a result, the on-period Ton of the NMOS transistor 26 changes depending on the level of the command value V2 output from the correction circuit 71. The correction circuit 71 that outputs the command value V2 will be described in detail below.

[0071] <<Configuration of correction circuit 71>> Fig. 10 is a diagram showing an example of the correction circuit 71. The correction circuit 71 is a circuit that corrects the on-period Ton based on the principle described in Fig. 8, and is configured to include an output circuit 80 and a command value output circuit 81.

[0072] ==Configuration of output circuit 80== The output circuit 80 outputs a value Cv indicating a conduction rate C, which indicates the proportion of the inductor current IL flowing during the switching period. Therefore, for example, when the switching period is period Tx, the output circuit 80 outputs a value Cv indicating the calculation result of equation (8). The output circuit 80 includes an RS flip-flop 90 and an averaging circuit 91.

[0073] The RS flip-flop 90 is a circuit that measures the period during which the inductor current IL flows within a switching cycle. Specifically, the RS flip-flop 90 outputs a high-level signal Vq2 based on timing ta when the drive signal Vdr goes high. On the other hand, the RS flip-flop 90 outputs a low-level signal Vq2 based on timing tb when the inductor current IL goes to zero and the signal Vc1 goes high. Therefore, the period during which the signal Vq2 goes high is the period during which the inductor current IL flows (a period greater than or equal to zero).

[0074] The RS flip-flop 90 corresponds to the "signal output circuit," and timing tb corresponds to the "second timing." The H-level signal Vq2 corresponds to the "first level signal," and the L-level signal Vq2 corresponds to the "second level signal." The "period during which the inductor current IL flows" is the period during which the inductor current IL is equal to or greater than zero (the period during which the signal Vq2 is H level), and corresponds to the "second period."

[0075] The averaging circuit 91 is a circuit that calculates the average value of the conduction rate C by performing the calculation of the above-mentioned equation (8). Specifically, the averaging circuit 91 acquires several cycles (e.g., two cycles) of the signal Vq2, which indicates the period during which the inductor current IL flows, and outputs a value Cv that indicates the average value of the conduction rate C. Therefore, as the period during which the inductor current IL flows becomes longer and the conduction rate C becomes higher, the value Cv also increases. Note that the averaging circuit 91 is a circuit that acquires and averages several cycles (e.g., two cycles) of the signal Vq2, but is not limited to this and may also be a so-called low-pass filter. A low-pass filter operates as an averaging circuit because it averages the signal Vq2 over more than several cycles.

[0076] 8, in the critical mode in which the NMOS transistor 26 turns on immediately and the inductor current IL starts to increase when the inductor current IL becomes zero, the conduction rate C is substantially 100%. In this embodiment, when the conduction rate C is 0%, the value Cv is 0 (zero), and when the conduction rate C is 100%, the value Cv is 1. In other words, the value Cv is a value that indicates the conduction rate C, which varies from 0 to 100%, in the range of 0 to 1.

[0077] ==Configuration of command value output circuit 81== The command value output circuit 81 is a circuit that corrects the command value V1 from the voltage adjustment circuit (AVR) 62 in Fig. 9 with a correction amount that decreases as the conduction rate C increases, and outputs the corrected value as a command value V2. Specifically, the command value output circuit 81 is a circuit that calculates the above-mentioned equation (9). Ton2=Ton1×(1 / C) (9)

[0078] However, the value of the conduction rate C for one cycle can vary significantly from cycle to cycle. Therefore, if the conduction rate C for one cycle is used in equation (9), the on-period Ton2 may vary significantly and not converge. However, as described above, C in equation (9) is the average value of the conduction rates for several cycles. Therefore, in this embodiment, the on-period Ton2 can be prevented from varying significantly from cycle to cycle, and can be converged to the period shown in equation (10).

[0079] Here, the on-period Ton1 is a period determined based on the command value V1, and the on-period Ton2 is a period determined based on the command value V2. The command value output circuit 81 is configured to include an arithmetic circuit 100 and a multiplication circuit 101. The command value V2 corresponds to a "second command value," and the command value output circuit 81 corresponds to a "second command value output circuit."

[0080] The arithmetic circuit 100 is a circuit that calculates the reciprocal (1 / Cv) of the value Cv indicating the conduction rate C. Therefore, in this embodiment, as the conduction rate C increases, the reciprocal decreases.

[0081] The multiplication circuit 101 multiplies the calculated reciprocal (1 / Cv) by the command value V1, and outputs a command value V2 (=V1×(1 / Cv)).

[0082] <<<Operation of digital circuit 43b>>> 9, after the NMOS transistor 26 is turned on at timing ta, the inductor current IL may become zero after a period Tx has elapsed, or before the period Tx has elapsed. When the inductor current IL becomes zero after the period Tx has elapsed, the AC-DC converter 10 is operating in a so-called critical mode. On the other hand, when the inductor current IL becomes zero before the period Tx has elapsed, the AC-DC converter 10 is operating in a mode in which the switching frequency of the AC-DC converter 10 is limited.

[0083] In this embodiment, the digital circuit 43b operates in two different modes (critical mode and frequency limit mode) based on the timing when the inductor current IL becomes zero. Therefore, each operation mode will be described here.

[0084] ==When the inductor current IL becomes zero after the period Tx has elapsed== For example, the inductor current IL shown in Fig. 11 becomes zero at time t31, after a period Tx has elapsed since time t30, when the NMOS transistor 26 is turned on. In this critical mode, the AND circuit in Fig. 9 sets the signal Va to H level when the signal Vc1 becomes H level. When the signal Va becomes H level, the signal Vq1 and the drive signal Vdr also become H level.

[0085] As a result, immediately after the signal Vc1 goes to H level, the H-level drive signal Vdr is input to the RS flip-flop 90. Therefore, the RS flip-flop 90 outputs a signal Vq2 that is almost H level, and the value Cv indicating the conduction rate C becomes almost 1.

[0086] In such a case, the command value V2 output from the command value output circuit 81 is approximately equal to the command value V1. Therefore, when operating in the critical mode, the correction circuit 71 in FIG. 9 outputs the command value V1 almost as is, and the AND circuit 67 outputs the signal Vc1 as the signal Va. As a result, the digital circuit 43b operates substantially in the same manner as the digital circuit 43a shown in FIG. 3.

[0087] ==When the inductor current IL becomes zero before the period Tx elapses== For example, the inductor current IL indicated by the solid line in Fig. 8 becomes zero at time t40, before the period Tx has elapsed since time t20 when the NMOS transistor 26 turns on. In such a frequency limit mode, the AND circuit in Fig. 9 sets the signal Va to the H level at the timing when the signal Vt becomes the H level.

[0088] In this case, the correction circuit 71 multiplies the command value V1 by the reciprocal of the value Cv indicating the conduction rate C, and outputs the result as the command value V2 (=V1 / Cv). In this embodiment, the conduction rate C is updated for each switching period. As a result, the digital circuit 43b repeatedly executes equation (9), so the conduction rate C (value Cv) converges, and the average value of the inductor current IL in the frequency limited mode becomes the average value of the inductor current IL in the critical mode. Therefore, in this embodiment, even when the frequency is limited, the average value of the inductor current IL can be prevented from becoming small, thereby improving the power factor.

[0089] <<<Simulation Results>>> FIG. 12 shows the main waveforms of the AC-DC converter 10 when two conditions, namely, frequency limit and command value correction, are changed in the digital circuit 43. Here, the "no frequency limit" in the first column shows the results when the digital circuit 43a of FIG. 3 is used as the digital circuit 43. The diagram in the first row shows the waveform of the inductor current IL, and the diagram in the second row shows the waveform of the input current Iin from the commercial power supply shown in FIG. 1. Furthermore, the diagram in the third row shows the waveform of the command value V1. In the "no frequency limit" case, the total harmonic distortion (THD) of the input current Iin is 13.5%, and the power factor is also relatively good.

[0090] The second column, "with frequency limit," shows the results when a circuit (not shown) is used that includes the configuration of the digital circuit 43b in FIG. 9 except for the correction circuit 71. In this case, the command value V1 from the voltage adjustment circuit 62 is input to the comparison circuit 64. When "with frequency limit," the total harmonic distortion of the input current Iin is 32.1%, and the power factor also deteriorates significantly.

[0091] The third column, "with frequency limit and correction," shows the results when the digital circuit 43b in FIG. 9 is used as the digital circuit 43. In this case, the total harmonic distortion of the input current Iin is 8.8%, and the power factor is very good. Note that with "with frequency limit and correction," the switching frequency is lower than with "without frequency limit" near the low phase angle of the input voltage Vrec. This reduces the influence of the current flowing from the parasitic capacitance of the NMOS transistor 26, resulting in improved total harmonic distortion and power factor compared to the "without frequency limit" case.

[0092] ===Other embodiments=== <<About the command value output circuit>> 13 is a diagram showing another example of a command value output circuit 81 in the correction circuit 71. The command value output circuit 81 may be a division circuit that divides the command value V1 by the value Cb. Even when such a circuit is used, the power factor can be improved in the same way as in this embodiment.

[0093] Furthermore, although a circuit that calculates the reciprocal of the value Cv is used as the arithmetic circuit 100, any circuit that can correct the command value V1 with a correction amount that decreases as the value Cv increases may be used. For example, a subtraction circuit that subtracts Cv from a predetermined constant may be used as the arithmetic circuit 100. Even when such a circuit is used, the power factor can be improved in the same way as in this embodiment.

[0094] <<Other forms of compensation circuit>> Fig. 14 is a diagram showing an example of another embodiment of the correction circuit. Correction circuit 75 is a circuit that is used in place of correction circuit 71 in Fig. 9. As will be described in detail later, correction circuit 75 calculates a value Cv(1) that indicates the conduction rate C for each cycle, rather than the average value of the conduction rates C for several cycles. Thereafter, correction circuit 75 averages the reciprocals of values ​​Cv(1) to determine command value V2.

[0095] In this way, by performing averaging processing on the conduction rate Cv(1) for each cycle, the on-period Ton2 converges, as in the case described above with reference to equations (9) and (10). The correction circuit 75 is configured to include an output circuit 200 and a command value output circuit 201.

[0096] <Output circuit 200> The output circuit 200 is a circuit that outputs a value Cv(1) that indicates the conduction rate C for each cycle (that is, each switching period), and is configured to include an RS flip-flop 300, a counter 301, and an arithmetic circuit 302.

[0097] 10, the RS flip-flop 300 is a circuit that measures the period during which the inductor current IL flows (period greater than or equal to zero) within a switching cycle. Specifically, the RS flip-flop 300 outputs an H-level signal Vq2 during the period during which the inductor current IL flows.

[0098] The counter 301 is a time counter that measures the period during which the inductor current IL flows (a period equal to or greater than zero) based on the H-level signal Vq2. The counter 301 measures the period during which the inductor current IL flows (hereinafter referred to as period Tc) for each cycle. The counter 301 corresponds to a "second timing circuit."

[0099] The calculation circuit 302 calculates a value Cv(1) indicating the conduction rate for each cycle based on a period Tc measured for each cycle and a period Tx corresponding to a switching period. Note that Cv(1) is Tc / Tx, and is calculated by dividing Tc by Tx. The calculation circuit 302 corresponds to a "first calculation circuit."

[0100] <Command value output circuit 201> The command value output circuit 201 is a circuit that corrects the command value V1 using the value Cv(1) for each cycle and outputs the command value V2. The command value output circuit 201 is configured to include an arithmetic circuit 310, a multiplication circuit 311, and an averaging circuit 312.

[0101] The arithmetic circuit 310 is a circuit that calculates the reciprocal of the value Cv(1) for each cycle. The arithmetic circuit 310 corresponds to the "second arithmetic circuit."

[0102] The multiplication circuit 311 multiplies the inverse of the value Cv(1) output from the arithmetic circuit 310 by the command value V1, and outputs the multiplication result (V1 / Cv(1)). The multiplication result of the multiplication circuit 311 is output for each switching period (each cycle).

[0103] The averaging circuit 312 is a circuit that averages the multiplication results over several cycles (at least two cycles or more) and outputs the averaged result as the command value V2. Therefore, as explained in the above equations (9) and (10), even when the correction circuit 75 is used, the on-period Ton2 can be converged to a desired period, as in the case of the correction circuit 71. As a result, even when the correction circuit 75 is used, the power factor in the AC-DC converter 10 can be improved. The averaging circuit 312 is realized by a general digital arithmetic circuit, but may also be, for example, a low-pass filter.

[0104] <<Another embodiment of the command value output circuit in the correction circuit 75>> 15 is a diagram showing an example of another embodiment of a command value output circuit used in the correction circuit 75. The command value output circuit 202 is a circuit used in place of the command value output circuit 201, and is configured to include a division circuit 320 and an averaging circuit 321.

[0105] The division circuit 320 is a circuit that divides the command value V1 by the value Cv(1) output from the arithmetic circuit 310. Therefore, the division circuit 320 outputs the division result (V1 / Cv(1)) for each cycle.

[0106] Similar to the averaging circuit 312, the averaging circuit 321 averages the division results for several cycles (at least two cycles or more) and outputs the averaged result as the command value V2. Even when such a command value output circuit 202 is used in the correction circuit 75, the power factor in the AC-DC converter 10 can be improved.

[0107] <<Another embodiment of the command value output circuit in the correction circuit 75>> 16 is a diagram showing an example of another embodiment of a command value output circuit used in the correction circuit 75. The command value output circuit 203 is a circuit used in place of the command value output circuit 201, and is configured to include an arithmetic circuit 330, an averaging circuit 331, and a multiplication circuit 332.

[0108] The arithmetic circuit 330 is a circuit that calculates the reciprocal of the value Cv(1) for each cycle. The arithmetic circuit 330 corresponds to the "third arithmetic circuit."

[0109] The averaging circuit 321 averages the reciprocals of the values ​​Cv(1) over several cycles (at least two cycles or more), and outputs the average as 1 / Cv.

[0110] Multiplication circuit 332 multiplies the output from averaging circuit 321 by command value V1 and outputs the result as command value V2. Even when such a command value output circuit 203 is used in correction circuit 75, the power factor in AC-DC converter 10 can be improved.

[0111] ===Summary=== The AC-DC converter 10 of this embodiment has been described above. The digital circuit 43b of the power factor correction IC 25 can correct the command value V1 and lengthen the on-period when the switching frequency is limited. Therefore, the power factor correction IC 25 using the digital circuit 43b can improve the power factor of the AC-DC converter 10.

[0112] The correction circuit 71 also includes an output circuit 80 that outputs a value Cv indicating the conduction rate C, and a command value output circuit 81 that corrects the command value V1 by a correction amount (1 / Cv) that decreases as the value Cv increases (see, for example, FIG. 10). As a result, as explained in, for example, equations (9) to (12), the command value V2 converges to a desired value, and the inductor current IL can be increased even when the frequency is limited.

[0113] Furthermore, the averaging circuit 91 integrates the signal Vq2 that is the basis of the conduction ratio C, and outputs a value Cv that indicates the conduction ratio C. As a result, it is possible to obtain a value Cv that accurately reflects the conduction ratio C.

[0114] Furthermore, when determining the conduction ratio C, for example, a counter that counts the switching period and the period during which the inductor current IL flows may be used. However, in this embodiment, an RS flip-flop 90 is used that changes the timing ta when the drive signal Vdr becomes H level, the timing tb when the inductor current IL becomes zero, and the signal Vq2. Therefore, in this embodiment, the conduction ratio C can be detected with a simple configuration.

[0115] Furthermore, the command value output circuit 81 uses, as a circuit for correcting the command value V1, a calculation circuit 100 that calculates the reciprocal of the value Cv and a multiplication circuit 101 that multiplies the command value V1 by the reciprocal. By using such a circuit, it is possible to converge the on-period when the frequency is limited.

[0116] 13, for example, a division circuit can be used as the command value output circuit 81. Even when such a circuit is used, the power factor can be improved.

[0117] Furthermore, for example, even if a correction circuit 75 shown in FIG. 14 is used instead of the correction circuit 71, the power factor can be improved in the same way as in this embodiment.

[0118] Furthermore, the correction circuit 75 calculates a value Cv(1) for each cycle. Then, the averaging circuit 312 averages the results of multiplying the value Cv(1) for each cycle by the command value V1. Even with this configuration, the power factor can be improved in the same way as in this embodiment.

[0119] Furthermore, in the correction circuit 75, the command value output circuit 201 using the multiplication circuit 311 is used, but this is not limited to this, and a command value output circuit 202 including a division circuit 320 may be used as shown in FIG.

[0120] Furthermore, in the command value output circuit 201, the multiplication results are averaged, but this is not limiting. For example, in the command value output circuit 203 shown in Fig. 16, the averaging circuit 331 averages the reciprocal of the value Cv(1) for each cycle. Then, the multiplication circuit 332 multiplies the output from the averaging circuit 331 by the command value V1 and outputs the result as the command value V2. Even with this configuration, the same effects as in this embodiment can be obtained.

[0121] The power factor correction IC 25 also includes an AD converter 41 that converts the voltage VL into a digital value and an AD converter 42 that converts the feedback voltage Vfb into a digital value. While the power factor correction IC 25 is primarily implemented using a digital circuit 43 in this embodiment, it may be implemented using an analog circuit with similar functionality. Even in this case, the power factor can be corrected in the same way as in this embodiment.

[0122] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit thereof, and the present invention includes equivalents thereof. [Explanation of symbols]

[0123] 10 AC-DC converter 11 Load 20 Full wave rectifier circuit 21,22 Capacitor 23 Inductor 24 Diode 25 Power Factor Correction IC 26 NMOS transistors 30~32 Resistance 40 Level shift circuit 41,42 AD converter 43 Digital Circuits 44 Buffer circuit 60,64 Comparison circuit 61 Subtraction Circuit 62 Voltage Regulator Circuit 63 Counter 65, 90, 300 RS Flip-Flops 66 Delay Circuit 67 AND circuit 70,301 counters 71 Correction circuit 72 Drive signal output circuit 80 Output circuit 81 Command value output circuit 91,312,321 Averaging circuit 100,302,310,330 arithmetic circuit 101,311,332 multiplication circuit 320 Division circuit

Claims

1. A switching control circuit for a power supply circuit that generates an output voltage of a target level from an AC voltage, the power supply circuit comprising: an inductor to which a voltage corresponding to an AC voltage is applied; and a transistor that controls an inductor current flowing through the inductor, the power supply circuit controlling switching of the transistor, a first command value output circuit that outputs a first command value corresponding to a difference between a feedback voltage corresponding to the output voltage and a reference voltage; a correction circuit that corrects the first command value and outputs the corrected value as a second command value; a first timing circuit that measures a first period from a first timing at which the transistor is turned on for each switching period; a drive signal output circuit that outputs a drive signal for turning on the transistor when the inductor current reaches a predetermined value indicating zero after the first period has elapsed from the first timing, and outputs the drive signal for turning off the transistor based on the second command value, and outputs the drive signal for turning on the transistor when the inductor current reaches the predetermined value and the first period has elapsed from the first timing, and outputs the drive signal for turning off the transistor based on the second command value; Equipped with The correction circuit when the first period has elapsed since the first timing after the inductor current has reached the predetermined value, the first command value is corrected by a correction amount that decreases as the ratio of a second period during which the inductor current flows increases within the first period, so that an on-period of the transistor becomes longer within the switching cycle; Switching control circuit.

2. 2. The switching control circuit according to claim 1, The correction circuit an output circuit that outputs a first value corresponding to a proportion of the second period in the first period; a second command value output circuit that corrects the first command value with a correction amount that decreases as the ratio increases and outputs the corrected first command value as the second command value; Including, Switching control circuit.

3. 3. The switching control circuit according to claim 2, The output circuit a signal output circuit that outputs a signal that becomes a first logic level from the first timing until a second timing at which the inductor current becomes the predetermined value, and that becomes a second logic level from the second timing until the first timing; an averaging circuit that averages the signal and outputs the averaged signal as the first value; Including, Switching control circuit.

4. 4. The switching control circuit according to claim 3, The signal output circuit a flip-flop that outputs the signal at the first logic level based on the first timing and outputs the signal at the second logic level based on the second timing; Switching control circuit.

5. 5. The switching control circuit according to claim 3 or 4, The second command value output circuit an arithmetic circuit that calculates the reciprocal of the first value; a multiplication circuit that multiplies the calculation result of the calculation circuit by the first command value; Including, Switching control circuit.

6. 5. The switching control circuit according to claim 3 or 4, The second command value output circuit a division circuit that divides the first value from the first command value; Switching control circuit.

7. 3. The switching control circuit according to claim 2, The output circuit a second timing circuit that times the second period; a first calculation circuit that calculates the first value for each switching period based on the second period and the first period measured by the second timing circuit; Including, Switching control circuit.

8. 8. The switching control circuit according to claim 7, The second command value output circuit a second calculation circuit that calculates the reciprocal of the first value; a multiplication circuit that multiplies the calculation result of the second calculation circuit by the first command value; an averaging circuit that averages the outputs of the multiplication circuit; Including, Switching control circuit.

9. 8. The switching control circuit according to claim 7, The second command value output circuit a division circuit that divides the first value from the first command value; an averaging circuit that averages the output of the division circuit; Including, Switching control circuit.

10. 8. The switching control circuit according to claim 7, The second command value output circuit a third calculation circuit that calculates the reciprocal of the first value; an averaging circuit that averages the calculation results of the third calculation circuit; a multiplication circuit that multiplies the output of the averaging circuit by the first command value; Including, Switching control circuit.

11. The switching control circuit according to any one of claims 1 to 10, a first AD converter for converting the feedback voltage into a digital value; a second AD converter that converts a voltage corresponding to the inductor current into a digital value; Including, Switching control circuit.

12. A power supply circuit that generates an output voltage of a target level from an AC voltage, an inductor to which a voltage corresponding to the AC voltage is applied; a transistor for controlling an inductor current flowing through the inductor; a switching control circuit that controls switching of the transistor; The switching control circuit a first command value output circuit that outputs a first command value corresponding to a difference between a feedback voltage corresponding to the output voltage and a reference voltage; a correction circuit that corrects the first command value and outputs the corrected value as a second command value; a first timing circuit that measures a first period from a first timing at which the transistor is turned on for each switching period; a drive signal output circuit that outputs a drive signal for turning on the transistor when the inductor current reaches a predetermined value indicating zero after the first period has elapsed from the first timing, and outputs the drive signal for turning off the transistor based on the second command value, and outputs the drive signal for turning on the transistor when the inductor current reaches the predetermined value and the first period has elapsed from the first timing, and outputs the drive signal for turning off the transistor based on the second command value; Including, The correction circuit when the first period has elapsed since the first timing after the inductor current has reached the predetermined value, the first command value is corrected by a correction amount that decreases as the ratio of a second period during which the inductor current flows increases within the first period, so that an on-period during which the transistor is on becomes longer within the switching cycle; power circuit.

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