Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device with high reliability and reduced switching loss.SOLUTION: A semiconductor device has an insulating circuit board 1, a power semiconductor element mounted on the insulating circuit board 1, a flat first terminal 81 electrically connected to the power semiconductor element and having a first main surface, a second terminal 82 electrically connected to the power semiconductor element and having a second main surface opposite the first main surface of the first terminal 81, an insulating sheet 83 disposed between the first and second main surfaces, and conductive films 84, 85 disposed at least on one of the first and second main surface sides of the insulating sheet 83.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device (power semiconductor module) incorporating a power semiconductor element and a manufacturing method thereof, and more particularly to a wiring structure of terminals connected to an external electrode supply device or DC power wiring of a power semiconductor module. [Background technology]

[0002] In recent years, the global trend toward decarbonization has attracted attention to electrically powered vehicles such as electric cars and electric railway vehicles. Electrically powered vehicles require efficient motor control using power conversion devices such as inverters and converters, and power semiconductor modules are generally used for these power conversion devices. Power semiconductor modules convert DC power to AC power and vice versa. Power semiconductor modules are equipped with multiple power semiconductor elements such as insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, and perform power conversion by switching these power semiconductor elements on and off.

[0003] Power semiconductor elements incur losses during switching. Therefore, switching losses can be reduced by switching as quickly as possible. However, high-speed switching can sometimes result in overvoltage. Overvoltage not only increases losses but can also damage the power semiconductor module. It is known that reducing the parasitic inductance of wiring, or so-called low-inductance, is an effective way to suppress overvoltage during high-speed switching. In a 2-in-1 module in which switching elements such as IGBTs and MOSFETs are connected in series, with positive and negative terminals connected to both ends of the series and an AC output terminal connected between the switching elements, low inductance can be achieved by using a laminated wiring structure in which the positive and negative terminals are laminated so that current flows in opposite directions via an insulator (see Patent Documents 1 to 4). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-137283 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-144377 [Patent Document 3] Japanese Patent Application Laid-Open No. 2006-210500 [Patent Document 4] Patent Publication No. 2021-106235 Summary of the Invention [Problem to be solved by the invention]

[0005] Patent Document 1 discloses a structure in which the positive and negative terminals are laminated inside a power semiconductor module, with an insulator between them. However, the external terminals are not laminated because they are bolted to an external power supply device or DC power wiring, which reduces the inductance reduction effect.

[0006] Patent Document 2 discloses a structure in which the positive and negative terminals outside the power semiconductor module are laminated. However, in order to laminate the wiring to the outside of the power semiconductor module, the terminals are bent. To reduce the wiring inductance of the positive and negative terminals, the distance between the terminals is important and must be controlled to the nearest 0.1 mm. This necessitates highly accurate bending of the terminals, which increases costs.

[0007] Patent Document 2 also discloses a method of bonding a positive electrode terminal and a negative electrode terminal together using an epoxy resin or polyimide adhesive as an insulator between the terminals, and a method of applying an insulating coating to the terminals by electrodeposition coating and then bonding the terminals together with an adhesive. However, air bubbles tend to remain in bent parts, etc., and remain as voids after the adhesive hardens, causing partial discharge. Partial discharge can deteriorate the insulating material and lead to short circuits between the terminals.

[0008] Furthermore, Patent Document 2 discloses a method of filling the space between the positive and negative electrode terminals with an insert resin by insert molding using a mold. However, with insert molding, if the distance between the terminals is too close, the insert resin will not fill properly, and the defective filling will result in voids, so a certain distance must be maintained. To perform insert molding without filling defects, a gap of 1.5 mm or more is generally required, although this depends on the area between the terminals and the type of insert resin, and the inductance reduction effect cannot be fully achieved.

[0009] Patent Document 2 also discloses a method of bonding terminals together using an insulating, flexible adhesive sheet; however, the sheet expands and contracts differently on the inside and outside of the bent portion, expanding on the outside but shrinking on the inside, which can cause the sheet to wrinkle easily on the inside, resulting in the formation of voids.

[0010] In view of the above problems, an object of the present invention is to provide a semiconductor device that is highly reliable and capable of reducing switching loss, and a method for manufacturing the same. [Means for solving the problem]

[0011] One aspect of the present invention is a semiconductor device comprising: (a) an insulating circuit board; (b) a power semiconductor element mounted on the insulating circuit board; (c) a flat first terminal electrically connected to the power semiconductor element and having a first main surface; (d) a second terminal electrically connected to the power semiconductor element and having a second main surface opposite to the first main surface of the first terminal; (e) an insulating sheet disposed between the first main surface and the second main surface; and (f) at least one of the first main surface side and the second main surface side of the insulating sheet. to The present invention also provides a semiconductor device including a conductive film disposed on the semiconductor substrate.

[0012] Another aspect of the present invention is a method for manufacturing a semiconductor device, including: (a) a step of mounting a power semiconductor element on an insulating circuit board; (b) a step of forming a conductive film on at least one of a first main surface side and a second main surface side of an insulating sheet having a first main surface and a second main surface; and (c) a step of sandwiching the first main surface side and the second main surface side of the insulating sheet on which the conductive film has been formed between flat first terminals and flat second terminals, and integrating the insulating sheet with a case. [Effects of the Invention]

[0013] According to the present invention, it is possible to provide a semiconductor device that is highly reliable and capable of reducing switching loss, and a method for manufacturing the same. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a plan view of a semiconductor device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a cross-sectional view taken along the AA direction in FIG. [Figure 3] FIG. 2 is a cross-sectional view seen from the direction BB in FIG. [Figure 4] FIG. 2 is a plan view of a positive electrode terminal of the semiconductor device according to the embodiment. [Figure 5] FIG. 2 is a plan view of an insulating sheet and a positive electrode-side conductive film of the semiconductor device according to the embodiment, as viewed from the positive electrode terminal side. [Figure 6] FIG. 2 is a plan view of a negative electrode terminal of the semiconductor device according to the embodiment. [Figure 7] FIG. 2 is a plan view of an insulating sheet and a negative electrode conductive film of the semiconductor device according to the embodiment, as viewed from the negative electrode terminal side. [Figure 8] 1 is a circuit diagram of a semiconductor device according to an embodiment; [Figure 9] FIG. 10 is a cross-sectional view of a portion of a semiconductor device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, identical or similar parts are designated by identical or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0016] In addition, the definitions of directions such as "up," "down," "up and down," "left," "right," and "left and right" in the following description are merely definitions for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, "up and down" is converted and read as "left and right," and of course, if it is rotated 180 degrees and observed, "up and down" is read inverted. Furthermore, "top surface" and "bottom surface" may be read as "front surface" and "back surface," respectively.

[0017] Furthermore, in this specification, a "first terminal" means either the positive terminal or the negative terminal of a power semiconductor module, and a "second terminal" means the other of the positive terminal and the negative terminal of a power semiconductor module, which is different from the "first terminal." That is, if the "first terminal" is the positive terminal of a power semiconductor module, the "second terminal" becomes the negative terminal of the power semiconductor module, and if the "first terminal" is the negative terminal of a power semiconductor module, the "second terminal" becomes the positive terminal of the power semiconductor module.

[0018] <Structure of semiconductor device> As shown in Fig. 1, the semiconductor device (power semiconductor module) according to the embodiment includes an insulating circuit board 1, power semiconductor elements (semiconductor chips) 3a to 3l mounted on the insulating circuit board 1, and a case 7 arranged to surround the insulating circuit board 1 and the power semiconductor elements 3a to 3l. Fig. 1 does not show the sealing material arranged inside the case 7 to seal the power semiconductor elements 3a to 3l, etc. Also, in Fig. 1, connection points of bonding wires connected to the power semiconductor elements 3a to 3l, etc. are schematically shown by black circles.

[0019] As shown in Fig. 1, in a plan view of the semiconductor device according to the embodiment, the longitudinal direction of the semiconductor device according to the embodiment is defined as the X-axis, and the rightward direction in Fig. 1 is defined as the positive direction of the X-axis. The lateral direction of the semiconductor device according to the embodiment, which is perpendicular to the X-axis, is defined as the Y-axis, and the upward direction in Fig. 1 is defined as the positive direction of the Y-axis. The direction perpendicular to the X-axis and Y-axis is defined as the Z-axis, and the front side of Fig. 1 is defined as the positive direction of the Z-axis. The same applies to Fig. 2 and subsequent figures.

[0020] 1 illustrates a 2-in-1 power semiconductor module in which two pairs of six parallel MOSFETs are connected in series as the power semiconductor elements 3a-3l. The power semiconductor elements 3a-3f form an upper arm for one phase of a three-phase inverter circuit, and the power semiconductor elements 3g-3l form a lower arm. Note that the semiconductor device according to the embodiment is not limited to a 2-in-1 semiconductor module as long as it is a power semiconductor module having a positive terminal 81 and a negative terminal 82, and may be, for example, a 1-in-1 or 6-in-1 semiconductor module.

[0021] The power semiconductor elements 3a to 3l each have a semiconductor substrate, a first main electrode (drain electrode) provided on the lower surface of the semiconductor substrate, and a second main electrode (source electrode) and a control electrode (gate electrode) provided on the upper surface of the semiconductor substrate. The semiconductor substrate is made of, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), or the like. The arrangement positions and number of the power semiconductor elements 3a to 3l are not particularly limited. The power semiconductor elements 3a to 3l may be field effect transistors (FETs) such as MOSFETs, as well as insulated gate bipolar transistors (IGBTs), static induction (SI) thyristors, gate turn-off (GTO) thyristors, or the like.

[0022] The insulating circuit board 1 is formed, for example, of a direct copper bonding (DCB) board or an active matrix solder (AMD) board. The insulating circuit board 1 includes an insulating substrate 10, conductor foils (upper conductor foils) 11a-11j arranged on the upper surface of the insulating substrate 10, and a conductor foil (lower conductor foil) 12 arranged on the lower surface of the insulating substrate 10 (see FIGS. 2 and 3 for the lower conductor foil 12). The insulating substrate 10 can be a ceramic plate mainly made of aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), boron nitride (BN), or the like, or a resin insulating layer made of a polymer material or the like. When a resin insulating layer is used as the insulating substrate 10, the lower conductor foil 12 on the lower surface of the insulating substrate 10 may be omitted. The upper conductor foils 11a-11j and the lower conductor foil 12 are made of, for example, copper (Cu), aluminum (Al), or the like. The upper conductor foils 11a to 11j are formed in an arbitrary pattern and constitute a circuit pattern.

[0023] 1, power semiconductor elements 3a to 3f are bonded to upper conductor foil 11b of insulating circuit board 1 via a bonding material such as solder or a sintered material. Power semiconductor elements 3g to 3l are bonded to upper conductor foil 11h of insulating circuit board 1 via a bonding material such as solder or a sintered material.

[0024] A case 7 is disposed so as to surround the power semiconductor elements 3a to 3f and the insulating circuit board 1. The case 7 can be made of a resin material such as polyphenylene sulfide (PPS), polybutylene terephthalate (PBT), polybutylene succinate (PBS), epoxy, or phenol.

[0025] Control terminals 7a to 7i are provided on the case 7. The control terminal 7c is connected to the upper conductor foil 11f via a bonding wire. The upper conductor foil 11f is electrically connected to the source electrodes of the power semiconductor elements 3a to 3f via bonding wires. The control terminal 7c detects the current flowing through the source electrodes of the power semiconductor elements 3a to 3f.

[0026] The control terminal 7d is connected to the upper conductor foil 11g via a bonding wire. The upper conductor foil 11g is electrically connected to the gate electrodes of the power semiconductor elements 3a to 3f via bonding wires. The control terminal 7d applies a control signal to the gate electrodes of the power semiconductor elements 3a to 3f.

[0027] The control terminal 7g is connected to the upper conductor foil 11i via a bonding wire. The upper conductor foil 11i is connected to the source electrodes of the power semiconductor elements 3g to 3l via bonding wires. The control terminal 7g detects the current flowing through the source electrodes of the power semiconductor elements 3g to 3l.

[0028] The control terminal 7h is connected to the upper conductor foil 11j via a bonding wire. The upper conductor foil 11j is electrically connected to the gate electrodes of the power semiconductor elements 3g to 3l via a bonding wire. A control signal is applied to the gate electrodes of the power semiconductor elements 3g to 3l via the control terminal 7h.

[0029] The case 7 is provided with an output terminal 80, and a positive terminal 81 and a negative terminal 82 that are arranged to face the output terminal 80. The output terminal 80 is connected to an upper conductor foil 11b. The upper conductor foil 11b is electrically connected to the drain electrodes of the power semiconductor elements 3a to 3f. The upper conductor foil 11b is also electrically connected to the source electrodes of the power semiconductor elements 3g to 3l via lead frames 6g to 6l.

[0030] The positive electrode terminal 81 is electrically connected to the upper conductor foil 11h. The upper conductor foil 11h is electrically connected to the drain electrodes of the power semiconductor elements 3e to 3h. The negative electrode terminal 82 is electrically connected to the upper conductor foils 11a and 11e. The upper conductor foil 11a is electrically connected to the source electrodes of the power semiconductor elements 3a to 3c via the lead frames 6a to 6c. The upper conductor foil 11e is electrically connected to the source electrodes of the power semiconductor elements 3d to 3f via the lead frames 6d to 6f.

[0031] FIG. 2 shows a cross section seen from the direction AA passing through the laminated wiring structure of the positive electrode terminal 81 and the negative electrode terminal 82 in FIG. 1, and FIG. 3 shows a cross section seen from the direction BB passing through the laminated wiring structure of the positive electrode terminal 81 and the negative electrode terminal 82 in FIG. 1.

[0032] As shown in Figures 2 and 3, the insulating circuit board 1 and power semiconductor elements 3a-3l inside the case 7 are sealed with a sealing material 9. The sealing material 9 can be an insulating sealing resin such as a thermosetting silicone gel or epoxy resin. A cooling body (base) 2 is arranged on the underside of the insulating circuit board 1. The cooling body 2 can be made of a material with high thermal conductivity, such as copper (Cu), aluminum (Al), a composite material of Al and silicon carbide (AlSiC), or a composite material of magnesium (Mg) and silicon carbide (MgSiC).

[0033] The positive electrode terminal 81 and the negative electrode terminal 82 have a flat plate shape. Materials that can be used for the positive electrode terminal 81 and the negative electrode terminal 82 include copper (Cu), a Cu alloy, aluminum (Al), and an Al alloy. As shown in FIG. 2, the positive electrode terminal 81 is electrically connected to the upper conductor foil 11h via a spacer 5a made of copper (Cu) or the like for height adjustment. Meanwhile, as shown in FIG. 3, the negative electrode terminal 82 is electrically connected to the upper conductor foil 11e via a spacer 5b made of copper (Cu) or the like for height adjustment. Because the distance between the negative electrode terminal 82 and the insulating circuit board 1 is greater than the distance between the positive electrode terminal 81 and the insulating circuit board 1, the height of the spacer 5b connected to the negative electrode terminal 82 is greater than the height of the spacer 5a connected to the positive electrode terminal 81.

[0034] 1 to 3, an insulating sheet 83 is disposed between the upper surface (main surface) of positive electrode terminal 81 and the lower surface (main surface) of negative electrode terminal 82. A conductive film (positive electrode-side conductive film) 84 is disposed between the lower surface of insulating sheet 83 and the upper surface of positive electrode terminal 81. A conductive film (negative electrode-side conductive film) 85 is disposed between the upper surface of insulating sheet 83 and the lower surface of negative electrode terminal 82.

[0035] That is, the positive electrode terminal 81 and the negative electrode terminal 82 are taken out in a laminated state from the inside to the outside of the power semiconductor module via an insulating sheet 83, a positive electrode-side conductive film 84, and a negative electrode-side conductive film 85. The distance between the positive electrode terminal 81 and the negative electrode terminal 82 from the inside to the outside of the power semiconductor module is constant due to the thickness of the insulating sheet 83, the positive electrode-side conductive film 84, and the negative electrode-side conductive film 85. Current flows in the opposite directions in the positive electrode terminal 81 and the negative electrode terminal 82, so that the parasitic inductance of the wiring can be reduced.

[0036] As the insulating sheet 83, a sheet having high insulating and heat-resistant properties, such as insulating paper or polyimide or polyamide, can be used. The thickness of the insulating sheet 83 depends on the rated voltage of the power semiconductor module, but when the rated voltage is 1200 V, it is set to 0.1 mm or more and 1.0 mm or less. More preferably, by setting the thickness to 0.2 mm or more and 0.6 mm or less, the wiring inductance between the positive electrode terminal 81 and the negative electrode terminal 82 can be significantly reduced.

[0037] The thicknesses of the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 can be set, for example, in the range of 0.1 μm or more and 100 μm or less. If the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 are too thin, film formation defects may occur, exposing the insulating sheet 83. On the other hand, if the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 are too thick, warping or the like may occur due to stress in the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85. When the positive electrode terminal 81 and the negative electrode terminal 82 are laminated and returned to a flat state, cracks may occur in the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85. For this reason, the thicknesses of the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 are appropriately adjusted depending on the materials of the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85. The thicknesses of the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 may be the same or different from each other.

[0038] The positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 may be made of any conductive material, preferably a material with higher corrosion resistance than the positive electrode terminal 81 and the negative electrode terminal 82. Examples of materials that can be used for the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 include metals such as gold (Au), platinum (Pt), titanium (Ti), nickel (Ni), and chromium (Cr), conductive diamond-like carbon (DLC), and conductive oxide films such as indium tin oxide (ITO). The positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 may also be made of copper (Cu) or aluminum (Al). The positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 may be made of the same material as the positive electrode terminal 81 and the negative electrode terminal 82, or may be made of different materials.

[0039] FIG. 4 shows a planar pattern of the positive electrode terminal 81. The positions of lines AA and BB in FIG. 4 coincide with the positions of lines AA and BB in FIG. 1. In the planar pattern, the positive electrode terminal 81 has a rectangular main body 81a and protrusions 81b and 81c protruding from the main body 81a. The protrusions 81b and 81c extend inside the case 7 and correspond to portions electrically connected to the upper conductor foil 11h via the spacer 5a. The planar pattern of the positive electrode terminal 81 may have any shape and is not limited to the shape shown in FIG. 4.

[0040] FIG. 5 shows the insulating sheet 83 and the positive electrode conductive film 84 as viewed from the positive electrode terminal 81 side, and the overlapping position of the positive electrode terminal 81 is schematically indicated by a dashed line. The positions of lines AA and BB in FIG. 5 correspond to the positions of lines AA and BB in FIG. 1. The shape of the planar pattern of the insulating sheet 83 corresponds to the shapes of the planar patterns of the positive electrode terminal 81 and the negative electrode terminal 82. The outer edges (ends) of the insulating sheet 83 are larger than the outer edges of the positive electrode terminal 81 and the negative electrode terminal 82 to ensure the necessary insulation creepage distance at the ends of the positive electrode terminal 81 and the negative electrode terminal 82. In the planar pattern, the insulating sheet 83 has a rectangular main body 83a and protrusions 83b and 83c protruding from the main body 83a.

[0041] The positive electrode-side conductive film 84 has, in a planar pattern, a rectangular main body 84a, protrusions 84b and 84c protruding from the main body 84a, and protrusions 84d and 84e protruding from the main body 84a on the side opposite the protrusions 84b and 84c. The protrusions 84b and 84c of the positive electrode-side conductive film 84 overlap with the protrusions 83b and 83c of the insulating sheet 83. The protrusions 84d and 84e of the positive electrode-side conductive film 84 overlap with the protrusions 81b and 81c of the positive electrode terminal 81.

[0042] The outer edge of the positive electrode-side conductive film 84 is smaller than the outer edge of the portion of the insulating sheet 83 facing the positive electrode terminal 81 in plan view, or coincides with the outer edge of the portion of the insulating sheet 83 facing the positive electrode terminal 81. The outer edge of the positive electrode-side conductive film 84 coincides with the outer edge of the insulating sheet 83, or is located more inward than the outer edge of the insulating sheet 83. The outer edge of the positive electrode-side conductive film 84 also coincides with the outer edge of the positive electrode terminal 81, or is located more inward than the outer edge of the positive electrode terminal 81, so as not to protrude outside the positive electrode terminal 81. This prevents electric field concentration on the positive electrode-side conductive film 84 when the positive electrode-side conductive film 84 protrudes outside the positive electrode terminal 81, and prevents deterioration or destruction of the insulating sheet 83.

[0043] FIG. 6 shows a planar pattern of the negative electrode terminal 82. The positions of lines AA and BB in FIG. 6 coincide with the positions of lines AA and BB in FIG. 1. In the planar pattern, the negative electrode terminal 82 has a rectangular main body 82a and protruding portions 82b and 82c protruding from the main body 82a. The protruding portions 82b and 82c extend inside the case 7 and correspond to portions electrically connected to the upper conductor foil 11e via a spacer 5b or the like. The planar pattern of the negative electrode terminal 82 may have any shape and is not limited to the shape shown in FIG. 6.

[0044] 7 shows the insulating sheet 83 and the negative electrode-side conductive film 85 as viewed from the negative electrode terminal 82 side, and also shows the overlapping position of the negative electrode terminal 82 with a dashed line. The positions of lines AA and BB in FIG. 7 coincide with the positions of lines AA and BB in FIG. 1. The negative electrode-side conductive film 85 has, in a planar pattern, a substantially rectangular main body 85a and protruding portions 85b and 85c protruding from the main body 85a. The protruding portions 85b and 85c of the negative electrode-side conductive film 85 overlap with the protruding portions 82b and 82c of the negative electrode terminal 82.

[0045] The outer edge of the negative electrode conductive film 85 is smaller than the opposing outer edges of the insulating sheet 83 and the negative electrode terminal 82 in terms of the planar pattern, or is Negative terminal 82The outer edge of the negative electrode-side conductive film 85 coincides with the outer edge of the portion facing the insulating sheet 83. The outer edge of the negative electrode-side conductive film 85 coincides with the outer edge of the insulating sheet 83 or is located more inward than the insulating sheet 83. The outer edge of the negative electrode-side conductive film 85 also coincides with the outer edge of the negative electrode terminal 82 or is located more inward than the negative electrode terminal 82 so as not to protrude outside the negative electrode terminal 82. This prevents electric field concentration in the negative electrode-side conductive film 85 when the negative electrode-side conductive film 85 protrudes outside the negative electrode terminal 82, and prevents deterioration or destruction of the insulating sheet 83.

[0046] The positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 are not bonded to the positive electrode terminal 81 and the negative electrode terminal 82, respectively, with an adhesive or the like, but are in direct contact with the positive electrode terminal 81 and the negative electrode terminal 82, respectively. This prevents defects caused by expansion of voids remaining in the adhesive or the like during hot molding, which can be a problem when bonding is performed with an adhesive or the like.

[0047] Furthermore, if the positive electrode terminal 81 is in contact with the positive electrode-side conductive film 84 at even one point, the positive electrode terminal 81 and the positive electrode-side conductive film 84 will have the same potential. If the negative electrode terminal 82 is in contact with the negative electrode-side conductive film 85 at even one point, the negative electrode terminal 82 and the negative electrode-side conductive film 85 will have the same potential. Therefore, even if a gap is formed between the positive electrode-side conductive film 84 and the positive electrode terminal 81, or between the negative electrode-side conductive film 85 and the negative electrode terminal 82, partial discharge can be prevented from occurring, and a laminate wiring with high insulation performance can be formed.

[0048] FIG. 8 shows an equivalent circuit of the semiconductor device according to the embodiment shown in FIGS. 1 to 7. As shown in FIG. 8, the semiconductor device according to the embodiment constitutes a part of a three-phase bridge circuit. The drain electrode of the upper arm transistor T1 is connected to the positive terminal P, and the source electrode of the lower arm transistor T2 is connected to the negative terminal N. The source electrode of the transistor T1 and the drain electrode of the transistor T2 are connected to the output terminal U and the auxiliary source terminal S1, respectively. The auxiliary source terminal S2 is connected to the source electrode of the transistor T2. The gate electrodes of the transistors T1 and T2 are connected to gate control terminals G1 and G2. The transistors T1 and T2 have built-in body diodes D1 and D2 connected in anti-parallel and serving as freewheeling diodes (FWD).

[0049] The output terminal U, the positive terminal P, and the negative terminal N shown in Fig. 8 correspond to the output terminal 80, the positive terminal 81, and the negative terminal 82 shown in Fig. 1. The transistor T1 and the body diode D1 shown in Fig. 8 correspond to the power semiconductor elements 3a to 3f shown in Fig. 1. The transistor T2 and the body diode D2 shown in Fig. 8 correspond to the power semiconductor elements 3g to 3l shown in Fig. 1. The gate control terminals G1 and G2 shown in Fig. 8 correspond to the control terminals 7d and 7h shown in Fig. 1, and the auxiliary source terminals S1 and S2 shown in Fig. 8 correspond to the control terminals 7c and 7g shown in Fig. 1.

[0050] According to the semiconductor device of the embodiment, the positive electrode terminal 81 and the negative electrode terminal 82 of the power semiconductor module have a laminate structure with the insulating sheet 83 interposed therebetween, thereby shortening the distance between the positive electrode terminal 81 and the negative electrode terminal 82 and reducing the parasitic inductance of the wiring. Furthermore, since the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 are respectively disposed on the lower and upper surfaces of the insulating sheet 83, it is possible to suppress the occurrence of partial discharge between the positive electrode terminal 81 and the negative electrode terminal 82. This results in high reliability and reduced switching loss.

[0051] <Method of manufacturing a semiconductor device> Next, an example of a manufacturing method of a semiconductor device according to an embodiment will be described with reference to FIGS. 1 to 7. The lower conductor foil 12 of the insulated circuit board 1 shown in FIGS. 2 and 3 is bonded to the cooling body 2 using a bonding material such as solder or a sintered material. Furthermore, the power semiconductor elements 3a to 3l are bonded to the upper conductor foils 11b and 11h of the insulated circuit board 1 shown in FIG. 1 using a bonding material such as solder or a sintered material. The cooling body 2 or the lower conductor foil 12 of the insulated circuit board 1 may be plated with nickel (Ni)-phosphorus (P) or gold (Au) as needed to improve bonding strength. When a resin insulating layer is used as the insulating substrate 10 of the insulated circuit board 1, the resin insulating layer is formed on the surface of the cooling body 2, and the upper conductor foils 11a to 11j are formed on the surface of the resin insulating layer. Direct bonding between the resin insulating layer and the cooling body 2 and between the resin insulating layer and the upper conductor foils 11a to 11j reduces thermal resistance and enables efficient dissipation of heat generated by the power semiconductor elements 3a to 3l.

[0052] Next, the source electrodes on the surfaces of the power semiconductor elements 3a to 3l and the upper conductor foils 11a, 11b, and 11e are electrically connected using lead frames 6a to 6l made of copper (Cu), aluminum (Al), or the like, with a bonding material such as solder or a sintered material. This electrical connection may be achieved by ultrasonic bonding of wire, ribbon, or the like. The control electrodes on the surfaces of the power semiconductor elements 3a to 3l have a small current capacity, so they are electrically connected to the upper conductor foils 11g and 11j by wire bonding of aluminum (Al) or the like.

[0053] Next, an insulating sheet 83 is prepared, and using a mold or the like, the insulating sheet 83 is formed into a shape corresponding to the shapes of the positive electrode terminal 81 and the negative electrode terminal 82. Then, a positive electrode-side conductive film 84 and a negative electrode-side conductive film 85 are formed on the surface of the insulating sheet 83. As a method for forming the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 on the insulating sheet 83, a vacuum process such as vacuum deposition, sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD) can be used, and the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 can be formed in a vacuum. By using a vacuum process, it is possible to prevent the formation of spaces between the insulating sheet 83 and the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85, which can cause partial discharge.

[0054] A metal mask or the like can be used to form the patterns of the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85. The positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 only need to be slightly smaller than the surfaces of the positive electrode terminals 81 and the negative electrode terminals 82 and the insulating sheet 83 facing each other, and dimensional accuracy is not required, so it is preferable to use an inexpensive metal mask. Furthermore, when forming the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 on the insulating sheet 83, heating can be performed to prevent the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 from peeling off from the insulating sheet 83. For this reason, it is preferable to use a highly heat-resistant material for the insulating sheet 83.

[0055] The positive electrode terminal 81 and the negative electrode terminal 82 are formed by punching out a copper (Cu) plate or the like using a die. If necessary, they may be plated with nickel (Ni)-phosphorus (P), gold (Au), or the like. Next, an insulating sheet 83 on which a positive electrode conductive film 84 and a negative electrode conductive film 85 are formed is sandwiched between the positive electrode terminal 81 and the negative electrode terminal 82, and the resulting laminate is attached to a molding die. At the same time, the output terminal 80 and the control terminals 7a-7i are attached to the molding die. Then, a case 7 is molded using a resin material, into which the positive electrode terminal 81, the negative electrode terminal 82, the output terminal 80, and the control terminals 7a-7i are inserted, and the positive electrode terminal 81, the negative electrode terminal 82, the output terminal 80, and the control terminals 7a-7i are integrated with the case 7.

[0056] Because the positive electrode terminal 81, the insulating sheet 83 on which the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 are formed, and the negative electrode terminal 82 are not bonded together with an adhesive or the like, defects due to the expansion of remaining voids during hot molding can be prevented. As long as the positive electrode terminal 81 and the negative electrode terminal 82 are in contact with the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 formed on the insulating sheet 83 at even one point, the positive electrode terminal 81 and the negative electrode terminal 82 will have the same potential as the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85, respectively. Therefore, even if gaps are formed between the positive electrode terminal 81 and the negative electrode terminal 82 and the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85, partial discharge can be prevented, and laminate wiring with high insulation performance can be formed.

[0057] Next, the case 7, into which the positive terminal 81, negative terminal 82, output terminal 80, etc. are insert-molded, and the cooling body 2 are bonded so as to surround the insulated circuit board 1 and the power semiconductor elements 3a-3l. The positive terminal 81, negative terminal 82, and output terminal 80 are joined to the upper conductor foils 11a, 11b, 11e, 11h via spacers 5a, 5b, etc. Although joining can be performed using a joining material such as solder or sintered material, direct joining by laser welding or the like is also possible. The control terminals 7c, 7d, 7g, 7h and the upper conductor foils 11f, 11g, 11i, 11j are electrically connected by wire bonding or the like.

[0058] Next, the area surrounded by the cooling body 2 and the case 7 is sealed (potted) with a sealing material 9 such as a sealing resin so as to protect the insulating circuit board 1 and the power semiconductor elements 3a-3l. It is preferable to degas the sealing resin beforehand. Furthermore, the potting can be performed in a reduced pressure atmosphere to prevent voids from occurring. Here, since epoxy resins and the like can have high viscosity at room temperature, they are heated to a temperature as high as possible below the temperature at which crosslinking begins, to reduce the viscosity, followed by degassing and potting, and then the case 7 is heated to a temperature at or above the temperature at which crosslinking begins, thereby preventing voids from occurring in the sealing material 9.

[0059] According to the manufacturing method of the semiconductor device of the embodiment, it is possible to manufacture a power semiconductor module with reduced wiring inductance and high insulation reliability. Note that the connection between the positive electrode terminal 81 and the negative electrode terminal 82 and an external power supply device or a DC power wiring can be made by laser welding or the like of wiring laminated with an insulating sheet 83.

[0060] <Modification> 9, the semiconductor device according to the modified embodiment differs from the semiconductor device according to the embodiment shown in FIGS. 2 and 3 in the structure of the outer end portions of the laminate wiring structures of the positive electrode terminal 81 and the negative electrode terminal 82. As shown in FIG. 9, an insulating sheet 83 is disposed between the positive electrode terminal 81 and the negative electrode terminal 82. A positive electrode-side conductive film 84 is disposed on the positive electrode terminal 81 side of the insulating sheet 83, and a negative electrode-side conductive film 85 is disposed on the negative electrode terminal 82 side of the insulating sheet 83.

[0061] The positive electrode terminal 81 and the negative electrode terminal 82 are electrically connected to capacitor-side connection terminals 101 and 102, respectively, which are not shown. The end of the positive electrode terminal 81 is bent into an L shape, and a fastening part 104 made up of a bolt and a nut is inserted into a bolt hole formed in the end of the positive electrode terminal 81, thereby fixing the positive electrode terminal 81 to the capacitor-side connection terminal 101. The end of the negative electrode terminal 82 is bent into an L shape, and a fastening part 105 made up of a bolt and a nut is inserted into a hole formed in the end of the negative electrode terminal 82, thereby fixing the negative electrode terminal 82 to the capacitor-side connection terminal 102.

[0062] A capacitor-side insulating sheet 103 is disposed between the capacitor-side connection terminal 101 and the connection terminal 102. An end of the capacitor-side insulating sheet 103 is disposed so as to overlap an end of the insulating sheet 83.

[0063] (Other embodiments) As described above, the present invention has been described by way of the embodiment, but the descriptions and drawings that form part of this disclosure should not be understood as limiting the present invention. From this disclosure, various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art.

[0064] For example, in the embodiment, as shown in Figures 1 to 3, the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 are disposed on both the lower surface and the upper surface of the insulating sheet 83, but at least one of the positive electrode-side conductive film 84 and the negative electrode-side conductive film 85 may be disposed. That is, the positive electrode-side conductive film 84 may be disposed on the lower surface side of the insulating sheet 83, and the negative electrode-side conductive film 85 may not be disposed on the upper surface side of the insulating sheet 83. Alternatively, the negative electrode-side conductive film 85 may be disposed on the upper surface side of the insulating sheet 83, and the positive electrode-side conductive film 84 may not be disposed on the lower surface side of the insulating sheet 83.

[0065] In addition, in the embodiment, as shown in FIGS. 1 to 3, a laminate wiring structure in which the positive electrode terminal 81 is on the lower side and the negative electrode terminal 82 is on the upper side has been exemplified, but the positional relationship between the positive electrode terminal 81 and the negative electrode terminal 82 may be reversed, and a laminate wiring structure in which the positive electrode terminal 81 is on the upper side and the negative electrode terminal 82 is on the lower side may also be adopted.

[0066] As such, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0067] 1...Insulated circuit board 2...Cooling body 3a to 3l: Power semiconductor elements (semiconductor chips) 5a, 5b...Spacer 6a~6l...Lead frame 7. Case 7a~7i...Control terminals 9...Sealing material 10...Insulating substrate 11a to 11j...Upper conductor foil 12...Lower conductor foil 80...Output terminal 81...Positive terminal 81a, 82a, 83a, 84a, 85a...Main body 81b, 81c, 82b, 82c, 83b, 83c, 84b~84e, 85b, 85c...Protruding part 82...Negative terminal 83...Insulation sheet 84...Conductive film (positive electrode side conductive film) 85...Conductive film (negative electrode side conductive film) 101, 102...Connection terminals 103...Insulating sheet 104, 105... Fastening parts D1, D2...Body diode G1, G2...Gate control terminals N...Negative terminal P...Positive terminal S1, S2: Auxiliary source terminals T1, T2...Transistors U: Output terminal

Claims

1. an insulating circuit board; a power semiconductor element mounted on the insulating circuit board; a first terminal having a flat plate shape and a first main surface, the first terminal being electrically connected to the power semiconductor element; a second terminal electrically connected to the power semiconductor element and having a second main surface facing the first main surface of the first terminal; an insulating sheet disposed between the first main surface and the second main surface; a conductive film disposed on at least one of the first main surface side and the second main surface side of the insulating sheet; Equipped with the first terminal and the second terminal each have a main body and protruding portions that protrude from the main body toward the insulating circuit board at different positions, the ends of the protrusions of the first terminal and the second terminal on the insulating circuit board side are located closer to the insulating circuit board than the outer edge of the insulating sheet; and The semiconductor device has an outer edge of the insulating sheet positioned closer to the insulating circuit board than the ends of the main body portions of the first terminals and the second terminals that are on the insulating circuit board side.

2. The semiconductor device according to claim 1 , wherein the conductive film is made of a material having higher corrosion resistance than the first terminal and the second terminal.

3. 3. The semiconductor device according to claim 1, wherein an outer edge of said conductive film coincides with an outer edge of said insulating sheet or is located inside the outer edge of said insulating sheet.

4. the conductive film is disposed between the insulating sheet and the first main surface, A semiconductor device according to any one of claims 1 to 3, wherein the outer edge of the conductive film coincides with the outer edge of the portion of the first main surface facing the insulating sheet, or is positioned more inward than the outer edge of the portion of the first main surface facing the insulating sheet.

5. 5. The semiconductor device according to claim 1, further comprising a case that surrounds said insulating circuit board and said power semiconductor element, and to which said first terminal and said second terminal are attached.

6. the first terminal is a positive terminal, The second terminal is a negative terminal. The semiconductor device according to any one of claims 1 to 5.

7. The conductive film has a main body portion overlapping the main body portion of the first terminal and a protrusion portion overlapping the protrusion portion of the first terminal, an end of the protruding portion of the conductive film on the insulating circuit board side coincides with an outer edge of the insulating sheet; and The outer edge of the insulating sheet is positioned closer to the insulating circuit board than the end of the main body of the conductive film that is on the insulating circuit board side. The semiconductor device according to claim 1 .

8. a step of mounting a power semiconductor element on an insulating circuit board; forming a conductive film on at least one of a first main surface side and a second main surface side of an insulating sheet having a first main surface and a second main surface side; a step of sandwiching the first and second main surfaces of the insulating sheet on which the conductive film is formed between flat first and second terminals and integrating the insulating sheet with a case; Including, the first terminal and the second terminal each have a main body and protruding portions that protrude from the main body toward the insulating circuit board at different positions, the ends of the protrusions of the first terminal and the second terminal on the insulating circuit board side are located closer to the insulating circuit board than the outer edge of the insulating sheet; and A method for manufacturing a semiconductor device, wherein the outer edge of the insulating sheet is located closer to the insulating circuit board than the ends of the main body parts of the first terminals and the second terminals that are on the insulating circuit board side.

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein said step of forming said conductive film comprises forming said conductive film in a vacuum.

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