Model-based fault mitigation for semiconductor processing systems.

Abstract

A method for detecting a cause of a failure in a semiconductor processing system may include receiving an indication of a failure in the semiconductor processing system and providing the indication of the failure as a query to a network representing the semiconductor processing system. The network may include nodes representing on-wafer effects and component functions and relationships between the nodes representing causal dependencies between the component functions and the on-wafer effects. The method may also include calculating a change in probability assigned to the nodes representing the component functions as a result of providing the query and generating an output indicating a probability of at least one of the component functions as a cause of the failure.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Non-Provisional Application No. 17 / 484,888, filed September 24, 2021, and entitled "MODEL-BASED FAILURE MITIGATION FOR SEMICONDUCTOR PROCESSING SYSTEMS," the entire contents of which are incorporated herein by reference for all purposes. [Background technology]

[0002] Complex engineering systems can fail in countless different ways. As engineering systems become more complex, the number of system functions that can have a causal influence on a failure continues to grow. When a failure occurs, it is often difficult to identify the exact function that causes the failure. However, despite this difficulty, accurate identification of causal risk factors for engineering failures can be crucial to preventing such failures from occurring continuously in the future. The current state of the art is to use linguistic scale criteria to rank the risk of each input in a semi-quantitative manner. For example, this ranking can be performed by a team of subject matter experts using a numerical scale (e.g., a 1-5 scale). Although this methodology uses a numerical ranking system, these ranks are often assigned based on user intuition and personal experience, which leaves these rankings open to cognitive bias. Therefore, human ranking systems result in longer times for identifying the root cause of engineering failures in complex systems. Summary of the Invention

[0003] In some embodiments, a method for detecting a cause of a failure in a semiconductor processing system may include receiving an indication of a failure in the semiconductor processing system and providing the indication of the failure as a query to a network representing the semiconductor processing system. The network may include a plurality of nodes representing on-wafer effects and component functions and a plurality of relationships between the plurality of nodes, the relationships representing causal dependencies between the component functions and the on-wafer effects. The method may also include calculating a change in probability assigned to the nodes representing the component functions in the plurality of nodes resulting from providing the query, and generating an output indicating a probability of at least one of the component functions as a cause of the failure in the semiconductor processing system based on the change in probability.

[0004] In some embodiments, a non-transitory computer-readable medium may include instructions that, when executed by one or more processors, may cause the one or more processors to perform operations including receiving an indication of a fault in a semiconductor processing system and providing the indication of the fault as a query to a network representing the semiconductor processing system. The network may include a plurality of nodes representing on-wafer effects and component functions and a plurality of relationships between the plurality of nodes that may represent causal dependencies between the component functions and the on-wafer effects. The operations may also include calculating a change in probability assigned to a node representing the component function in the plurality of nodes as a result of providing the query, and generating an output indicating a probability of at least one of the component functions as a cause of the fault in the semiconductor processing system based on the change in probability.

[0005] In some embodiments, a system may include one or more processors and one or more memory devices containing instructions that, when executed by the one or more processors, cause the one or more processors to perform operations including receiving an indication of a fault in a semiconductor processing system and providing the indication of the fault as a query to a network representing the semiconductor processing system. The network may include a plurality of nodes representing on-wafer effects and component functions and a plurality of relationships between the plurality of nodes that may represent causal dependencies between the component functions and the on-wafer effects. The operations may also include calculating a change in probability assigned to a node representing the component function in the plurality of nodes as a result of providing the query, and generating an output indicating a probability of at least one of the component functions as a cause of the fault in the semiconductor processing system based on the change in probability.

[0006] In any embodiment, any and all of the following features may be implemented in any combination, without limitation: The network may include a Bayesian network; The component functions may include gas flow rates, chamber pressure, and wafer temperature; The on-wafer effects may include deposition rates at multiple locations on the wafer; The probabilities assigned to nodes representing the component functions may include probability distributions discretized into numerical range buckets; The query may include events corresponding to nodes representing on-wafer effects, where the events may indicate that the on-wafer effects are outside of a predetermined range; The semiconductor processing system may include a system for depositing films on semiconductor wafers; The method / operations may also include accessing a system functional map, which may include a data structure relating requirements for the semiconductor processing system to technology components to on-wafer effects to functional requirements for components in the semiconductor processing system, and automatically generating a network from the functional map. The method / operations may also include receiving operational data for the semiconductor processing system and calculating initial probabilities for multiple nodes in the network based on the operational data for the semiconductor processing system. The operational data may be generated by a simulation of the semiconductor processing system. The operational data may represent sensor measurements from operation of the semiconductor processing system when a fault occurs. The operational data may include values ​​in a numerical range, and the method / operations may also include discretizing the operational data into buckets representing subranges within the numerical range. The method / operations may also include using the operational data to statistically verify that multiple relationships between multiple nodes in the network are correct. Generating an output indicating a probability of at least one of the component functions as a cause of the fault in the semiconductor processing system may include comparing a prior probability distribution to a posterior probability distribution for a node representing at least one of the component functions and generating a divergence metric for at least one of the component functions.The output indicating the probability of at least one of the component functions as a cause of the failure may include generating a list of potential causes of the failure ranked by the divergence metric for at least one of the component functions. The nodes representing the on-wafer effects may include a subset of nodes representing one on-wafer effect, each of the subset of nodes representing one on-wafer effect at a different location on the wafer. The system may further include a chemical vapor deposition chamber. The method / operations may also include receiving changes to the operational data as a mitigation of the failure in the semiconductor processing system, using the operational data with the changes to update the probabilities assigned to the nodes representing the component functions, updating the probabilities assigned to the nodes representing the on-wafer effects, and determining whether the changes to the operational data have reduced the probability of at least one of the component functions as a cause of the failure in the semiconductor processing system based at least in part on the probabilities assigned to the nodes representing the on-wafer effects.

[0007] A further understanding of the nature and advantages of various embodiments may be realized by reference to the remaining portions of the specification and the drawings, in which like reference numerals are used throughout the several views to refer to like components. In some instances, a sub-label is associated with a reference numeral to indicate one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a flowchart of a method for identifying a cause of a failure in a semiconductor processing system, according to some embodiments. [Figure 2A] FIG. 1 illustrates a mapping between product requirements and functional requirements, according to some embodiments. [Figure 2B]FIG. 10 illustrates how various mapping data structures can be combined to link possible causes to fault effects, according to some embodiments. [Figure 3] FIG. 1 illustrates a network structure that may be generated based on functional mapping, according to some embodiments. [Figure 4] FIG. 1 illustrates how simulation data may be subdivided into discrete blocks, according to some embodiments. [Figure 5] FIG. 1 illustrates an example of how Bayes' rule can be applied to a chain of relationships, according to some embodiments. [Figure 6] FIG. 10 illustrates the resulting set of probability values ​​assigned to each of the nodes in a network structure, according to some embodiments. [Figure 7] 10 is a graph illustrating how a parent node representing wafer temperature can generate two probabilities based on bad data, according to some embodiments. [Figure 8] 1A-B illustrate how a similarity measure can be used to identify probability distributions that exhibit the greatest variation between prior and posterior distributions, according to some embodiments. [Figure 9] FIG. 10 illustrates the results of a similarity measure for each of the causal nodes that can be tracked through their relationship to the deposition rate node, according to some embodiments. [Figure 10] FIG. 1 illustrates an exemplary computer system in which various embodiments may be implemented. DETAILED DESCRIPTION OF THE INVENTION

[0009] Described herein are embodiments for providing an unbiased, physics-based, and probability-driven approach to identifying defects in semiconductor manufacturing systems. The methodology is primarily based on probabilistic mathematics, physics simulation, physical experimentation, and quantitative analysis, which eliminates the cognitive biases that previously plagued systematic failure analysis. The system combines physics-based cause-and-effect relationships to generate a Bayesian network that links functional causes to failure outputs. The Bayesian network can be generated directly from functional mapping, device requirements, and design / technology requirements. The Bayesian network can then be validated using statistical testing, and probabilities for each node in the network can be established using discrete groupings of sensor data and / or simulated data. The Bayesian network can then represent known causal and probabilistic relationships between operational requirements, technical functions, and design / technology components.

[0010] When a new fault occurs, a query representing the fault can be provided as a query input to the Bayesian network. For example, the query can be used to derive updated probabilities at various nodes throughout the network. The marginal prior probabilities can then be compared to the marginal posterior probabilities in the network using a divergence or difference metric to identify the function most likely to be the cause of the fault. The system can then propose several different input changes that can be applied to the semiconductor manufacturing system, and the network can be iteratively queried and updated until the probability of the fault cause is sufficiently minimized. This provides an objective diagnosis of the fault and allows the system to validate proposed mitigation strategies using an objective, data-driven approach. The system can be applied in diagnosing design, system, functional, or safety faults in semiconductor manufacturing systems.

[0011] The embodiments described herein may be applied to semiconductor processing and manufacturing equipment. For example, engineering failures may occur in equipment such as chemical vapor deposition chambers, sputtering chambers, etching chambers, plasma chambers, polishing chambers, and / or other equipment used in semiconductor manufacturing processes. These embodiments may also be applied generally to any type of engineered system, such as a display processing or manufacturing chamber. Furthermore, the embodiments described herein may be applied to a semiconductor processing system as a whole, or alternatively, to individual components in a semiconductor processing system, such as a heater or a flow control valve. For clarity, the present disclosure may use a chemical vapor deposition chamber configured to deposit a tungsten bulk film with WF and H reactants. However, this particular type of semiconductor processing system is provided by way of example only and is not limiting.

[0012] The term "fault" as used herein may refer to a measured system output that is outside a predetermined tolerance range. For example, a fault may occur when the thickness of a deposition layer exceeds a maximum allowable thickness. In another example, a fault may occur when the deposition rate of a deposition layer is above or below a specified range. In another example, a fault may occur when the ash rate in a plasma ashing process is outside a specified range. The systems described herein may include any of these or other types of faults that may occur in an engineering system as nodes in a network described below. When a fault occurs in one of these nodes, the methods and systems described below may be used to identify the most likely cause of the fault. The term "cause" as used herein may refer to any condition or input in an engineering system that causes the fault to occur. For example, a cause may include a temperature in a deposition chamber that is outside a predetermined range. A cause may also refer to the concentration of a chemical reactant above a predetermined threshold. A cause may be linked to a fault through one or more relationships defined in a structural network described below.

[0013] FIG. 1 shows a flowchart 100 of a method for identifying failure causes in a semiconductor processing system, according to some embodiments. A semiconductor processing system may include an entire semiconductor processing system and / or individual semiconductor processing components that are combined together to form the entire system. As the complexity of these systems continues to increase, the relationship between root causes and resulting failures may become obscured or hidden by layers of intermediate functions and outcomes. To solve these and other technical problems, a system implementing this method may begin by importing a system functional map (102) and / or a component functional map (104). These functional mappings may be maintained in specialized software that tracks these relationships between functions, components, and outcomes, and the software may provide the method with a data structure representing these functional mappings.

[0014] FIG. 2A illustrates a mapping between product requirements and functional requirements, according to some embodiments. A specific example used here may include a thermal chemical vapor deposition (CVD) chamber for depositing a tungsten bulk film with WF and H reactants. Product requirements may also be referred to as customer requirements, and they may represent requirements imposed on a system to function properly. The "product" may be the product of the chamber, such as a semiconductor wafer having a tungsten film deposited thereon. These product requirements may be set by a customer and may specify performance metrics for the chamber or characteristics of the resulting wafer. Product requirements may include measurable outputs, such as deposition rate, film thickness, resistance, layer impurities, throughput, ashing rate, and / or other results of the semiconductor manufacturing process. Product requirements may be expressed at the system level, while component requirements may be expressed at the component level.

[0015] In this example, a data structure may map product requirements to a set of functional requirements. For example, data structure 202 maps product requirements, such as deposition rate or resulting impurities, to a set of functional requirements that may be causally related to the product requirements. Based on the product requirements, a set of functional requirements to be incorporated into the chamber to produce the product requirements may be selected. In this example, deposition rate may be related to functional requirements, such as controlling wafer temperature, controlling partial pressure in the chamber, preventing HO angle deposition, uniform distribution of chucking, and / or other functional requirements. The mapping may imply that implementation of a functional requirement may affect whether the product requirement results in a failure.

[0016] The mapping may be generated in a user interface where a subject matter expert can provide relationships in a matrix between specific product requirements and specific functional requirements, such as that shown in FIG. 2A. For example, known relationships between product requirements and functional requirements may be represented in data structure 202. A user may provide an estimate of the strength of the relationship between the product requirements and the functional requirements, which may be characterized using a numerical requirement (e.g., 5.00) and / or using qualitative requirements (e.g., high (H), medium (M), and low (L)).

[0017] Multiple levels of mapping may be represented by different data structures. For example, some embodiments may also map functional requirements to technology requirements. The technology requirements may represent different operations performed by technologies or components in a system. For example, data structure 204 may map functional requirements to technology requirements. Functional requirements from vertical columns in data structure 202 may now be represented in horizontal rows in data structure 204. For example, a functional requirement for controlling pressure or controlling wafer temperature may be related to technology requirements such as controlling pedestal temperature, controlling the flow of various gases or other reactants (e.g., Ar, WF, H, etc.), controlling chamber pressure, and / or other requirements that may be imposed on different technology components.

[0018] 2A , some embodiments may include a data structure that maps additional layers between product requirements and specific technology components in a semiconductor manufacturing system. For example, a mapping may be represented between product requirements, functional requirements, design goals, and / or technology components added to the system. For example, multiple methods may be available for heating a wafer, and depending on the specific heating technique selected, the set of technology requirements may differ for wafer / temperature functional requirements.

[0019] 2B illustrates how various mapping data structures can be combined to link possible causes to failure effects, according to some embodiments. In this example, technical requirements (e.g., pedestal temperature, chamber pressure, reaction flow rate, etc.) can be identified as possible causes 210 of a failure. Using the mapping from the data structures 202, 204 described above, these possible causes 210 can be linked to functional requirements 212, such as controlling wafer temperature and controlling partial pressure. These functional requirements 212 can then be linked to on-wafer effects 214, such as deposition rate. By linking these data structures together, individual on-wafer effects 214 can be mapped to a specific list of possible causes 210 through a hierarchy of relationships when the effect represents a failure.

[0020] Some embodiments may present a user interface, as shown in FIG. 2A , allowing a user to input functional requirements, product requirements, etc. The user interface may also allow a user to form relationships between entities in horizontal rows and vertical columns, such as between functional requirements and product requirements. In some embodiments, the user may also enter numerical scores, while other embodiments may automatically calculate and enter numerical scores using the process described below to characterize causal relationships between entities.

[0021] Returning to FIG. 1 , importing the system functional map / component functional map (102, 104) may include importing the data structures described above in FIGS. 2A-2B. The method may then include generating a network structure (118). The network structure may include multiple nodes. Each individual node may represent an entry in one of the data structures from FIGS. 2A-2B. Edges between these nodes in the data structure may represent relationships between the nodes. These relationships may be causal relationships between the functions, components, and / or requirements represented by the nodes. For example, a relationship or edge between two nodes in the data structure may indicate a causal relationship between a function in a parent node and an outcome in a child node.

[0022] FIG. 3 illustrates a network structure 300 that may be generated based on functional mapping, according to some embodiments. The system may automatically import the data structure described above in FIG. 2A to establish the nodes and relationships shown in network structure 300. Note that some embodiments need not establish relationships between every node represented in the data structure. For example, the strength (e.g., numerical score) of a relationship may be subject to a threshold. If the strength of a relationship is equal to or less than the threshold, the relationship need not be represented in network structure 300. Other embodiments may represent all relationships. The method may automatically proceed by creating a node for every function, requirement, component, etc. that has at least one relationship with another function, requirement, component, etc. that has a sufficient numerical score or user-assigned qualitative relationship. The method may then generate relationships between nodes based on the relationships specified in the imported data structure.

[0023] In the example of FIG. 3 , the rows / columns in the data structure of FIG. 2A may be mapped to layers of nodes in the network structure 300. For example, node 302 in the top layer may represent a design or technical requirement. Node 304 in the middle layer may represent a functional requirement. Collectively, the nodes 302 (along with any other internal layers not shown in detail in FIG. 3 ) may be referred to as component functions. For example, controlling the flow of hydrogen gas (node ​​302-3) may be a functional requirement, corresponding to a component function, such as a gas valve that controls gas flow. Similarly, the partial pressure of hydrogen gas at a particular location on the wafer may also be included as a component function because it relates to a requirement for a gas control component. Node 306 and the bottom layer represent on-wafer effects that can be measured and may represent product requirements. Thus, the bottom layer of node 306 may be an on-wafer effect, and all nodes on which the on-wafer effect depends may be broadly referred to as a component function. The relationships in the network may represent causal dependencies between various component functions and resulting on-wafer effects.

[0024] As described in more detail below, some of the sensor measurements and on-wafer effects measured for product requirements and other functional requirements may have continuous value ranges. Instead of representing each specific measurement as a separate node, the measurements may be discretized and combined into groups of measurement ranges. This results in more efficient and easier processing of the data and efficiently represents the nonlinear behavior of the data. Thus, different functional nodes 304 and on-wafer effect nodes 306 were generated measurements at different locations on the wafer. In other words, each on-wafer effect may generate a subset of nodes representing its effect at different locations on the wafer. For example, deposition rate may be measured at radii of 0 mm, 75 mm (e.g., midpoint), and / or 147 mm (e.g., outer periphery of the wafer).

[0025] In this example, the output node or product requirement represents the deposition rate of a film on a wafer in a chamber during processing. Note that the network structure 300 shown in FIG. 3 may represent only one of the product requirements as an output. Other embodiments may generate more complex or additional network structures that represent additional product requirements or output influences. In this example, deposition rates at different radii of the wafer may be probabilistically independent of each other because no direct relationship is established between these nodes. However, functional node 304 and / or causal node 302 may contribute to multiple influence nodes 306. For example, wafer temperature may have a causal influence on the deposition rate at each location on the wafer, as indicated by the relationship between the wafer temperature node and influence node 306. Therefore, the chain of physical relationships should match the chain of probabilistic relationships in network structure 300.

[0026] Returning to FIG. 1 , the method may also include generating operational data (120). The operational data may be generated from sensor measurements and / or imported from failure data (106). For example, the operational data may be received from sensor measurements from actual operation of the semiconductor processing system when a failure occurs. The operational data may also be imported from the design / operational domain (108) when using a physics simulation of the semiconductor processing system. Collecting actual data from live operation of a semiconductor processing system may be difficult when developing a failure analysis system. Therefore, some embodiments may import data from a physics simulation, and the simulated data may then be calibrated using actual data measured from the chamber. This ensures that the simulated data matches the actual data that would result in a physical chamber.

[0027] Virtual sensors may be used to collect data from the simulation, or alternatively, sensors from the physical chamber may be monitored and sampled to collect physical data. The simulation may provide minimum / maximum ranges for each of the input parameters representing causal nodes in the network structure 300. For example, these ranges may be set for gas flow rates, including Ar flow rate (e.g., 2500-3500 sccm), WF flow rate (e.g., 350-450 sccm), H flow rate (e.g., 7000-8000 sccm), wafer temperature (e.g., 300-400°C), etc. These ranges may be simulated to generate comprehensive set output data for characterizing the chamber's response over these operating ranges.

[0028] Optionally, some embodiments may analyze and format the data using discrete ranges to reduce data complexity (122). Simulation and / or measured data may include nonlinear data that may be distributed throughout the entire operating range. To make the data easier to handle and minimize the number of probabilities that need to be assigned to nodes in the network structure, the data set from the simulation may be discretized or grouped into subranges. Using discrete numbers rather than continuous ranges of data makes calculations more efficient and data representation simpler. For example, if the operating data occupies a large range of values, the system may first discretize the operating data into multiple "buckets," each of which may represent a value somewhere within the numerical range. Each bucket may thus function as part of a histogram of values ​​within the corresponding subrange.

[0029] FIG. 4 illustrates how simulation data may be subdivided into discrete blocks, according to some embodiments. Graph 402 represents data point density as a function of wafer temperature. Similarly, graph 402 represents data point density as a function of deposition rate at the center of the wafer. Graph 406 represents wafer temperature as a function of deposition rate. Note that the ranges here are continuous across a wide spectrum of possible values. This many values ​​would typically require a node and a calculation for each possible value. Therefore, some embodiments may simplify this distribution by creating a fewer number of discrete groups or buckets for data represented by a single value.

[0030] For example, graph 412 represents the data from graph 402 subdivided into five groups or buckets of data. The frequency of the data points in each bucket is shown for each of five discrete ranges of values. Similarly, graph 414 represents the data from graph 404 subdivided into five groups or buckets of data. Again, the frequency of the data points in each bucket is shown for each of five ranges of deposition rate at the wafer center. Finally, the conditions for each of the effects (e.g., deposition rate) are shown as a function of wafer temperature in five discrete groupings in graph 416. Focusing on graph 416, the highest wafer temperature produces approximately a 95% chance of producing a failing wafer deposition rate that is outside of product requirements.

[0031] Returning to FIG. 1 , some embodiments may verify that the network structure is correct (124). Statistical methods may be used to examine the accuracy of the network structure. As explained above, the network structure may be created based on identified relationships between functions, causes, effects, and other aspects of the relationship between product requirements and technology implementations. However, one of the technical benefits provided by these embodiments is minimizing human bias that may be imprinted in the analysis of identifying the causes of failures. Therefore, the network structure may be independently verified using probability-based and simulation-based methods.

[0032] In particular, the domain knowledge and physical relationships used to form the network can be compared to the simulated or measured data collected above. If a strong statistical or probabilistic correlation is indicated between a parent node and a child node, that relationship can be verified in the network structure. However, if the data indicates an extremely weak correlation between a parent node and a child node, that relationship can be removed from the network structure. Furthermore, nodes that are not related in the network structure but have a strong causal correlation indicated by the simulated / measured data can have their relationship added in the network structure. The mutual information G 2 Several different statistical methods, such as tests, can be used to discover and / or verify causal relationships between nodes. Continuing with the CVD chamber example described above, it can be observed that large temperature variability dominates the deposition rate, which follows Arrhenius kinetics, thereby further validating the network structure.

[0033] The method may further include deriving 126 initial network node probabilities for each node in the network structure. In some embodiments, the network structure may represent a Bayesian network that includes probabilities based on Bayes' rule. FIG. 5 shows an example of how Bayes' rule may be applied to a chain of relationships, according to some embodiments. In this example, an observed on-wafer effect may be a wafer temperature that is outside a predetermined tolerance range. This effect may be observed with a probability of 8.1% (probability P(bad WT)=8.1%). A Bayesian network may be constructed to link this bad effect to multiple possible causes.

[0034] Several possible causes can be identified by the relationships in the network structure. For example, one possible cause can be related to the pressure in the chamber, while another can be related to the pedestal temperature. Other possible causes can include HO deposition, applied power, and wafer position on the pedestal, among others. A sensitivity analysis can be performed in which inputs (e.g., pressure and pedestal temperature) are varied to determine the sensitivity of the output effect (e.g., wafer temperature). When this analysis is performed, it can be observed that pressure accounts for 43% of the change in wafer temperature, and pedestal temperature accounts for 42% of the change in wafer temperature. In other words, if pressure goes bad, there is approximately a 43% chance that wafer temperature will go bad. Other possible causes can have a contribution of less than 10% to the change in wafer temperature. Therefore, the analysis can focus on pedestal temperature and chamber pressure as possible causes.

[0035] Instead of relying solely on the probabilities provided by sensitivity analysis, Bayes' rule can also first consider the probability that the pedestal temperature and pressure will fail. For example, domain knowledge based on previous experiments, simulation results, and / or measured data may reveal that the probability that the pressure will be outside of a specified range is approximately 3%. In comparison, domain knowledge may dictate that the probability that the pedestal temperature will be outside of a desired range is approximately 10%. These percentages may be taken from known failure rates of components used to construct the chamber. Using the Bayes' rule formulation shown in FIG. 5, it may be determined that the probability that pressure is the ultimate cause of wafer temperature failure may be approximately 51.9%, compared to the probability that pedestal temperature is the ultimate cause, which is only 15.9%.

[0036] This shows how Bayes' rule can be used to solve ill-posed inverse problems for which there is no unique solution. In the example of Figure 5, the results do not point to a single specific cause, but rather calculate a probability for one of several different possible causes. Because Bayes' rule generates a probability output based on both the probability under consideration and the prior probability, these relationships can be used to form a network of conditional probabilities called a Bayesian network. The network structure 300 in Figure 3 can be assigned a conditional probability at each node using Bayes' rule.

[0037] For example, the process may assign a probability to node 306-2, which represents the deposition rate at the center of the wafer. That probability may depend on the probabilities of each of its parent nodes 304-4, 304-5, 304-6, and 304-10. Note that each of these parent nodes represents a function at R=0 mm. Thus, a deposition rate may be calculated for each combination of values ​​for the input nodes. However, as explained above, the probabilities for the parent nodes have previously been adjusted so that they can be subdivided into a small number (e.g., five buckets) of representative values ​​across a defined range. Possible probabilities may be assigned by calculating the probability that each combination of possible input values, even using the discrete value ranges described above, may yield an extremely large data set of probabilities for each possible input value. For these discrete ranges, the individual probabilities may be aggregated together. Alternatively, if a continuous range of probabilities is used, the values ​​may be integrated together over the continuous range of values.

[0038] While a single probability value was used in FIG. 5 as an example, most input probabilities would be represented by a probability distribution rather than a singular value. FIG. 6 shows the resulting set of probability values ​​assigned to each of the nodes in a network structure, according to some embodiments. For each node, the process described above can be performed by generating possible probabilities from each of the parent nodes and aggregating / integrating those values ​​together to generate a final probability distribution for the child node based on Bayes' rule. Each node's probability distribution can represent the probability of failure based on a chain of probabilities from each of the preceding nodes in the hierarchy.

[0039] Returning to FIG. 1 , the method may also include processing the fault query through the network and updating the node probabilities (128). Once the network structure node probabilities are set, the network structure may be available to accept queries using subsequent fault data. For example, a network query may be generated to determine the root cause of a deposition rate being outside of an operational range (e.g., query="What if the deposition rate is greater than 7.5 at R=0 mm?"). The query may be entered as a result of an event obtained from sensor data, on-wafer data, or component data, depending on the nature of the problem. For example, a sensor may record an electrical short circuit or a deposition rate that is outside a predetermined range. To find the cause of this fault, a query for the network structure may set a fault mode for the deposition rate node 606-2 and update the probabilities of parent nodes throughout the network until the probability is updated for the causal node 602. Thus, the query may result in calculating changes in the probabilities assigned to nodes representing component functions.

[0040] Similar to the sensitivity analysis described above, two different probabilities can be calculated for each of the possible cause nodes for the deposition rate (R=0 mm) node 606-2. FIG. 7 shows a graph illustrating how a parent node 604-10 representing wafer temperature can generate two probabilities based on bad data, according to some embodiments. First, a "prior" probability distribution represents the network's probability before the bad data is taken into account. Second, a "posterior" probability distribution can be calculated using the bad data. Graph 702 shows a comparison of the prior and posterior probability distributions when the bad data is taken into account. Note that the probability distribution of node 604-10 can change significantly due to the bad data submitted by the query.

[0041] Returning to Figure 1, the method may also include calculating 130 the maximum variation probability change. This step may be used to identify the parent node that has the largest change between the prior probability distribution and the posterior probability distribution when the fault condition is taken into account. Generally, the greater the change between these distributions, the more likely the function represented by that node is related to the root cause of the fault.

[0042] 8A-8B illustrate how a similarity measure can be used to identify probability distributions that exhibit the greatest variation between prior and posterior distributions, according to some embodiments. To measure the magnitude of variation between the prior and posterior distributions, a similarity measure can be used to compare these distributions. For example, FIG. 8A illustrates two distributions that are relatively different from each other, representing a relatively large variation between the prior and posterior distributions. In contrast, FIG. 8B illustrates two distributions that are relatively similar to each other, representing a relatively small variation between the prior and posterior distributions. While any similarity measure can be used, some embodiments may use the Jensen-Shannon (JS) divergence method to measure the similarity between two probability distributions.

[0043] Returning to FIG. 1 , the method may further include outputting (132) the likely causes of the failure from the similarity comparison of the distributions generated by the network structure. FIG. 9 shows the results of a similarity measure (e.g., a JS divergence metric) on a scale of 0.0 to 1.0 for each of the causal nodes 302 that may be tracked through their relationship with the deposition rate node 606-2. In this example, wafer temperature exhibited the most significant change as measured by the similarity measure compared to the other causal nodes 302. Thus, the output may provide a calculated divergence metric from the similarity measure assigned to each of the causal nodes 302. The divergence metric may be used to generate an output indicating the probability of at least one of the component functions as a cause of the failure in the semiconductor processing system. Some embodiments may generate a ranked listing of the probabilities for each of the component functions.

[0044] This output may be used as a starting point for mitigating the fault. Because the metrics assigned to the causes are based on probability, this output does not represent a definitive indication of the cause of the fault, but rather indicates the most likely cause to which a mitigation technique may be applied. Not only may the network structure be used to identify possible causes for the fault, but the network structure may also be used to evaluate possible mitigation techniques for addressing the fault. The divergence metric may be used to output the component function that is most likely to be the cause of the fault (e.g., at least one of the component functions may be output). Some embodiments may also generate a ranked list of multiple component functions, the ranking of which may be determined based on the divergence metric.

[0045] Continuing with the example above, in which wafer temperature is the most likely cause of the deposition rate failure, possible mitigation techniques may attempt to better control wafer temperature to prevent the deposition rate failure from occurring in subsequent processes. These mitigation steps may include reducing the operating range or specifications for heater control (e.g., shifting from ±6°C to ±3°C) and other specific inputs that may be provided to the network structure. These mitigation steps may be implemented in the semiconductor process, and based on these mitigation steps, a new data set may be obtained. The new data set may be collected by simulation or through sensor measurements, and the physical process may be performed. This new data set may then be provided to the network using the same techniques described above, and a query may be generated (e.g., what if the deposition rate is greater than 7.25°C?). The resulting probability that wafer temperature is the root cause of the deposition failure may then be compared to the previous probability that wafer temperature is the root cause, calculated in FIG. 9 . If the probability of capturing the root cause is reduced, the mitigation technique may be assumed to be effective.

[0046] If the root cause, wafer temperature, is fully addressed, this may result in a relative increase in the probability that other inputs are the root cause of the deposition failure. Therefore, this cycle of relaxing and re-querying may be repeated several times until the probability of each cause is reduced below a predetermined threshold. Note that the network structure described above can operate bidirectionally to perform inference about both causes and failures. For example, the network can operate predictively, where the input causes can be used to predict the probability of failure. Furthermore, the network can also set failure modes as described above and reference the probabilities assigned to possible causes. Furthermore, the above example is simplified to use only a single failure. However, the network structure can be used to assign multiple failures and reference the joint contribution of any number of possible causes. For example, a failure may be set for a deposition rate greater than 7.0 when R=0 mm and for a deposition rate less than 6.5 when R=147 mm, eliminating the WF6 flow control as a possible cause. The causal probabilities of the remaining causal nodes can then be calculated to determine their likelihood of causing this type of joint failure.

[0047] It should be appreciated that the specific steps illustrated in FIG. 1 provide a particular method for identifying fault sources in a semiconductor processing system, according to various embodiments. Other sequences of steps may be implemented according to alternative embodiments. For example, alternative embodiments may implement the steps outlined above in a different order. Moreover, individual steps illustrated in FIG. 1 may include multiple sub-steps that may be implemented in various sequences as appropriate for the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are within the scope of the present disclosure.

[0048] Each of the methods described herein may be implemented by a computer system. Each step of these methods may be performed automatically by the computer system and / or may be provided with input / output involving a user. For example, a user may provide inputs for each step in the method, and each of these inputs may be in response to a particular output requesting such input, which is generated by the computer system. Each input may be received in response to a corresponding requested output. Furthermore, inputs may be received from a user, received from another computer system as a data stream, retrieved from a memory location, retrieved over a network, requested from a web service, etc. Similarly, outputs may be provided to a user, provided to another computer system as a data stream, stored in a memory location, sent over a network, provided to a web service, etc. In short, each step of the methods described herein may be performed by a computer system and may involve any number of inputs, outputs, and / or requests to and from the computer system, which may or may not involve a user. Steps that do not involve a user may be said to be performed automatically by the computer system without human intervention. Thus, in light of this disclosure, it will be understood that each step of each method described herein may be modified to include input and output to and from a user, or may be performed automatically by a computer system without human intervention, with any decisions made by a processor. Additionally, some embodiments of each of the methods described herein may be implemented as a set of instructions stored on a tangible, non-transitory storage medium to form a tangible software product.

[0049] 10 illustrates an exemplary computer system 1000 upon which various embodiments may be implemented. System 1000 may be used to implement any of the computer systems described above. As shown in the figure, computer system 1000 includes a processing unit 1004 that communicates with several peripheral subsystems via a bus subsystem 1002. These peripheral subsystems may include a processing acceleration unit 1006, an I / O subsystem 1008, a storage subsystem 1018, and a communication subsystem 1024. Storage subsystem 1018 includes a tangible computer-readable storage medium 1022 and a system memory 1010.

[0050] Bus subsystem 1002 provides a mechanism for allowing the various components and subsystems of computer system 1000 to communicate with each other as intended. While bus subsystem 1002 is shown schematically as a single bus, alternative embodiments of the bus subsystem may utilize multiple buses. Bus subsystem 1002 may be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. For example, such architectures may include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus, which may be implemented as a mezzanine bus manufactured to the IEEE P1386.1 standard.

[0051] Processing unit 1004, which may be implemented as one or more integrated circuits (e.g., conventional microprocessors or microcontrollers), controls the operation of computer system 1000. One or more processors may be included in processing unit 1004. These processors may include single-core or multi-core processors. In some embodiments, processing unit 1004 is implemented as one or more independent processing units 1032 and / or 1034, each of which may include a single or multi-core processor. In other embodiments, processing unit 1004 may be implemented as a quad-core processing unit formed by integrating two dual-core processors into a single chip.

[0052] In various embodiments, processing unit 1004 may execute various programs in response to program code and may maintain multiple simultaneously executing programs or processes. At a given time, some or all of the program code to be executed may reside in processor(s) 1004 and / or in storage subsystem 1018. Through suitable programming, processor(s) 1004 may provide the various functions described above. Computer system 1000 may further include a processing acceleration unit 1006, which may include a digital signal processor (DSP), a special purpose processor, or the like.

[0053] The I / O subsystem 1008 may include user interface input devices and user interface output devices. User interface input devices may include a keyboard, a pointing device such as a mouse or trackball, a touchpad or touchscreen integrated into a display, a scroll wheel, a click wheel, a dial, buttons, switches, a keypad, an audio input device with a voice command recognition system, a microphone, and other types of input devices. User interface input devices may include, for example, a motion-sensing and / or gesture-recognition device such as a Microsoft Kinect® motion sensor that allows a user to control and interact with an input device, such as a Microsoft Xbox® 360 game controller, through a natural user interface using gestures and spoken commands. User interface input devices may also include an eye-gesture recognition device such as a Google Glass® blink detector that detects eye activity from a user (e.g., “blinking” while taking a picture and / or making a menu selection) and translates the eye gesture as input to an input device (e.g., Google Glass®). Additionally, the user interface input devices may include a voice recognition sensing device that allows a user to interact with a voice recognition system (e.g., the Siri® navigator) through voice commands.

[0054] User interface input devices also include, but are not limited to, three-dimensional (3D) mice, joysticks or pointing sticks, gamepads and graphic tablets, audio / visual devices such as speakers, digital cameras, digital camcorders, portable media players, webcams, image scanners, fingerprint scanners, barcode readers, 3D scanners, 3D printers, laser range finders, and eye-tracking devices. Additionally, user interface input devices may include medical imaging input devices, such as, for example, computed tomography, magnetic resonance imaging, position emission tomography, and medical ultrasound devices. User interface input devices may also include audio input devices, such as, for example, MIDI keyboards, digital musical instruments, and the like.

[0055] User interface output devices may include display subsystems, indicator lights, or non-visual displays such as audio output devices, etc. Display subsystems may be flat panel devices such as those using cathode ray tubes (CRTs), liquid crystal displays (LCDs), or plasma displays, projection devices, touch screens, etc. In general, use of the term "output device" is intended to include all conceivable types of devices and mechanisms for outputting information from computer system 1000 to a user or to another computer. For example, user interface output devices may include various display devices that visually convey text, graphics, and audio / video information, such as, but not limited to, monitors, printers, speakers, headphones, automobile navigation systems, plotters, voice output devices, and modems.

[0056] Computer system 1000 may include a storage subsystem 1018 that comprises software elements shown as currently residing in system memory 1010. System memory 1010 may store program instructions that are loadable and executable on processing unit 1004, as well as data generated during the execution of these programs.

[0057] Depending on the configuration and type of computer system 1000, system memory 1010 may be volatile (such as random access memory (RAM)) and / or non-volatile (such as read-only memory (ROM), flash memory, etc.). RAM typically contains data and / or program modules that are immediately accessible to and / or presently being operated on and executed by processing unit 1004. In some implementations, system memory 1010 may include several different types of memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some implementations, a basic input / output system (BIOS), containing the basic routines that help to transfer information between elements within computer system 1000, such as during start-up, may typically be stored in ROM. By way of example and not limitation, system memory 1010 also illustrates application programs 1012, program data 1014, and operating system 1016, which may include client applications, a web browser, a mid-tier application, a relational database management system (RDBMS), etc. By way of example, operating system 1016 may include various versions of Microsoft Windows®, Apple Macintosh®, and / or Linux operating systems, various commercially available UNIX® or UNIX-like operating systems (including, but not limited to, various GNU / Linux operating systems, Google Chrome® OS, etc.), and / or mobile operating systems such as iOS, Windows® Phone, Android® OS, BlackBerry® 10 OS, and Palm® OS operating systems.

[0058] The storage subsystem 1018 may also provide a tangible computer-readable storage medium for storing the basic programming and data constructs that provide the functionality of some embodiments. Software (programs, code modules, instructions) that, when executed by a processor, provide the functionality described above may be stored in the storage subsystem 1018. These software modules or instructions may be executed by the processing unit 1004. The storage subsystem 1018 may also provide a repository for storing data used in accordance with some embodiments.

[0059] Storage subsystem 1000 may also include a computer-readable storage medium reader 1020, which may be further connected to a computer-readable storage medium 1022. Together with, and optionally in combination with, system memory 1010, computer-readable storage medium 1022 may comprehensively represent remote, local, fixed, and / or removable storage devices and media for containing, storing, transmitting, and retrieving computer-readable information on a temporary and / or more permanent basis.

[0060] The computer-readable storage medium 1022 containing the code, or portions of code, can include any suitable medium, including, but not limited to, storage and communication media, such as volatile and nonvolatile, removable and non-removable media, implemented in any method or technology for information storage and / or transmission. This can include tangible computer-readable storage media, such as RAM, ROM, Electronically Erasable Programmable ROM (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disk (DVD), or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage, or other magnetic storage devices, or other tangible computer-readable media. This can also include non-tangible computer-readable media, such as a data signal, data transmission, or any other medium that can be used to transmit desired information and that can be accessed by computing system 1000.

[0061] By way of example, the computer-readable storage medium 1022 may include a hard disk drive that reads from or writes to non-removable, non-volatile magnetic media, a magnetic disk drive that reads from or writes to removable, non-volatile magnetic disks, and an optical disk drive that reads from or writes to removable, non-volatile optical disks, such as CD-ROMs, DVDs, and Blu-Ray® disks or other optical media. The computer-readable storage medium 1022 may include, but is not limited to, Zip® drives, flash memory cards, Universal Serial Bus (USB) flash drives, Secure Digital (SD) cards, DVD disks, digital video tapes, etc. The computer-readable storage media 1022 may also include flash memory-based solid-state drives (SSDs), enterprise flash drives, SSDs based on non-volatile memory such as solid-state ROM, SSDs based on volatile memory such as solid-state RAM, dynamic RAM, static RAM, DRAM-based SSDs, magnetoresistive RAM (MRAM) SSDs, and hybrid SSDs that use a combination of DRAM-based SSDs and flash memory-based SSDs. Disk drives and their associated computer-readable media may provide non-volatile storage of computer-readable instructions, data structures, program modules, and other data for the computer system 1000.

[0062] The communications subsystem 1024 provides an interface to other computer systems and networks. The communications subsystem 1024 serves as an interface for receiving data from other systems from the computer system 1000 and for transmitting data to other systems from the computer system 1000. For example, the communications subsystem 1024 may enable the computer system 1000 to connect to one or more devices via the Internet. In some embodiments, the communications subsystem 1024 may include radio frequency (RF) transceiver components, global positioning system (GPS) receiver components, and / or other components for accessing wireless voice and / or data networks (e.g., using cellular telephone technology, advanced data network technologies such as 3G, 4G, or EDGE (Enhanced Data Rates for Global Evolution), WiFi (IEEE 802.11 family of standards), or other mobile communications technologies, or any combination thereof). In some embodiments, the communications subsystem 1024 may provide wired network connectivity (e.g., Ethernet) in addition to or instead of a wireless interface.

[0063] In some embodiments, the communications subsystem 1024 may also receive incoming communications in the form of structured and / or unstructured data feeds 1026, event streams 1028, event updates 1030, etc., for one or more users who may be using the computer system 1000.

[0064] By way of example, the communications subsystem 1024 may be configured to receive data feeds 1026 in real time from users of social networks and / or other communications services, such as web feeds such as Twitter® feeds, Facebook® updates, Rich Site Summary (RSS) feeds, and / or real-time updates from one or more third-party information sources.

[0065] Additionally, the communications subsystem 1024 may also be configured to receive data in the form of a continuous data stream, which may include an event stream 1028 of real-time events and / or event updates 1030, which may be continuous or infinite in nature without an explicit end. Examples of applications that generate continuous data may include, for example, sensor data applications, financial tickers, network performance measurement tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, automobile traffic monitoring, etc.

[0066] The communications subsystem 1024 may also be configured to output structured and / or unstructured data feeds 1026, event streams 1028, event updates 1030, etc. to one or more databases that may be in communication with one or more streaming data source computers coupled to the computer system 1000.

[0067] The computer system 1000 may be one of a variety of types, including a handheld portable device (e.g., an iPhone® cellular phone, an iPad® computing tablet, a PDA), a wearable device (e.g., a Google Glass® head-mounted display), a PC, a workstation, a mainframe, a kiosk, a server rack, or any other data processing system.

[0068] Due to the ever-changing nature of computers and networks, the description of computer system 1000 shown in the figures is intended as a specific example only. Many other configurations are possible, having more or fewer components than the system shown in the figures. For example, customized hardware could also be used, and / or particular elements could be implemented in hardware, firmware, software (including applets), or a combination. Additionally, connections to other computing devices, such as network input / output devices, could be employed. Based on the disclosure and teachings provided herein, other ways and / or methods for implementing various embodiments should be apparent.

[0069] In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. It will be apparent, however, that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0070] The above description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the above description of various embodiments provides an enabling disclosure for implementing at least one embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the several embodiments as set forth in the appended claims.

[0071] Specific details have been given in the above description to provide a thorough understanding of the embodiments. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form in order to avoid obscuring the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments.

[0072] Also, it should be noted that particular embodiments may be described as a process, which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or concurrently. Moreover, the order of operations may be rearranged. A process terminates when its operations are completed, but may have additional steps not included in the diagram. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination may correspond to a return of the function to the calling function or the main function.

[0073] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying instruction(s) and / or data. A code segment or machine-executable instruction may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[0074] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, program code or code segments to perform the necessary tasks may be stored in a machine-readable medium. Processor(s) may perform the necessary tasks.

[0075] In the foregoing specification, features have been described with reference to specific embodiments thereof, but it should be recognized that not all embodiments are limited thereto. Various features and aspects of the several embodiments may be used individually or together. Moreover, the embodiments may be utilized in any number of environments and applications other than those described herein without departing from the broader spirit and scope of the specification. Accordingly, the specification and drawings should be regarded as illustrative rather than restrictive.

[0076] Furthermore, for purposes of explanation, the methods have been described in a particular order. It should be appreciated that in alternative embodiments, the methods may be performed in an order different from that described. It should also be appreciated that the methods described above may be performed by hardware components or may be embodied in a sequence of machine-executable instructions that can be used to cause a machine, such as a general-purpose or special-purpose processor or logic circuitry programmed with instructions, to perform the method. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, a floppy diskette, ROM, RAM, EPROM, EEPROM, a magnetic or optical card, flash memory, or other type of machine-readable medium suitable for storing electronic instructions. Alternatively, the methods may be performed by a combination of hardware and software.

Claims

1. 1. A method for detecting fault sources in a semiconductor processing system, the method comprising: receiving an indication of a fault in a semiconductor processing system; providing the indication of the fault as a query to a network representing the semiconductor processing system, the network comprising: a plurality of nodes representing on-wafer effects and component functions; a plurality of relationships between the plurality of nodes, the plurality of relationships representing causal dependencies between the component functions and the on-wafer effects; and providing said indication of said fault, including: calculating a change in fault probabilities assigned to nodes representing the component functions in the plurality of nodes resulting from providing the query from before providing the query to after providing the query; outputting a probability of at least one of the component functions causing the failure in the semiconductor processing system based on the change in the probability; and A method comprising:

2. The method of claim 1 , wherein the network comprises a Bayesian network.

3. The method of claim 1 , wherein the component functions include gas flow rates, chamber pressure, and wafer temperature.

4. The method of claim 1 , wherein the on-wafer effects include deposition rates at multiple locations on a wafer.

5. The method of claim 1 , wherein the probabilities assigned to the nodes representing the component functions comprise probability distributions discretized into buckets of numerical ranges.

6. The method of claim 1 , wherein the query includes an event corresponding to a node representing the on-wafer effect, the event indicating that the on-wafer effect is outside a predetermined range.

7. The method of claim 1 , wherein the semiconductor processing system comprises a system for depositing a film on a semiconductor wafer.

8. A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to: receiving an indication of a fault in a semiconductor processing system; providing the indication of the fault as a query to a network representing the semiconductor processing system, the network comprising: a plurality of nodes representing on-wafer effects and component functions; a plurality of relationships between the plurality of nodes, the plurality of relationships representing causal dependencies between the component functions and the on-wafer effects; and providing said indication of said fault, including: calculating a change in fault probabilities assigned to nodes representing the component functions in the plurality of nodes resulting from providing the query from before providing the query to after providing the query; outputting a probability of at least one of the component functions causing the failure in the semiconductor processing system based on the change in the probability; and A non-transitory computer-readable medium for performing operations including:

9. The operation is accessing a system functional map including a data structure relating product requirements, functional requirements, technology components, and the on-wafer impacts in the semiconductor processing system; automatically generating the network from the functional map; The non-transitory computer-readable medium of claim 8 , further comprising:

10. The operation is receiving operational data for the semiconductor processing system; calculating initial probabilities for the plurality of nodes in the network based on the operational data for the semiconductor processing system; The non-transitory computer-readable medium of claim 8 , further comprising:

11. The non-transitory computer-readable medium of claim 10 , wherein the operational data is generated by a simulation of the semiconductor processing system.

12. The non-transitory computer-readable medium of claim 10 , wherein the operational data represents sensor measurements from operation of the semiconductor processing system when the fault occurred.

13. the operational data includes values ​​in a range of values; the operations further comprising discretizing the motion data into a plurality of buckets representing subranges within the numerical range. The non-transitory computer-readable medium of claim 10.

14. The operation is using the operational data to statistically verify that the relationships between the nodes in the network are correct. The non-transitory computer-readable medium of claim 10 further comprising:

15. one or more processors; one or more memory devices comprising instructions; wherein the instructions, when executed by the one or more processors, cause the one or more processors to: receiving an indication of a fault in a semiconductor processing system; providing the indication of the fault as a query to a network representing the semiconductor processing system, the network comprising: a plurality of nodes representing on-wafer effects and component functions; a plurality of relationships between the plurality of nodes, the plurality of relationships representing causal dependencies between the component functions and the on-wafer effects; and providing said indication of said fault, including: calculating a change in fault probabilities assigned to nodes representing the component functions in the plurality of nodes resulting from providing the query from before providing the query to after providing the query; outputting a probability of at least one of the component functions causing the failure in the semiconductor processing system based on the change in the probability; and A system that performs an operation including:

16. generating the output indicating the probability of the at least one of the component functions as the cause of the fault in the semiconductor processing system; comparing a prior probability distribution to a posterior probability distribution for a node representing said at least one of said component functions; generating a divergence metric for the at least one of the component functions; The system of claim 15, comprising:

17. 17. The system of claim 16, wherein the output indicating the probability of the at least one of the component functions as the cause of the fault comprises generating a list of potential causes of the fault ranked by the divergence metric for the at least one of the component functions.

18. The system described in claim 15, wherein the nodes representing the on-wafer effects include a subset of nodes representing one on-wafer effect, each of the subsets of nodes representing the one on-wafer effect at a different location on the wafer.

19. The system of claim 15 , wherein the system further comprises a chemical vapor deposition chamber.

20. The operation is receiving a change to operational data corresponding to a mitigation of the fault in the semiconductor processing system; using the operational data together with the changes to update the probabilities assigned to nodes representing the component functions; updating the probabilities assigned to the nodes representing the on-wafer effects; determining whether the change to the operational data reduced the probability of the at least one of the component functions as the cause of the failure in the semiconductor processing system; The system of claim 15 further comprising:

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