Dynamic reconfiguration of the physical layer interface of the display serial interface

Abstract

1. A method for changing an operating frequency in a serial data link, the method comprising: transmitting a first datagram over the serial data link using a first physical layer interface configured for the first operating frequency; configuring a second physical layer interface for a second operating frequency different from the first operating frequency while the first datagram is being transmitted over the serial data link; transmitting configuration information over the serial data link using the first physical layer interface after the second physical layer interface is configured for the second operating frequency; idling the serial data link by terminating transmission over the first physical layer interface; decoupling the first physical layer interface from the serial data link; coupling the second physical layer interface to the serial data link; and transmitting a second datagram over the serial data link using the second operating frequency using the second physical layer interface.

Description

[Technical Field]

[0001]

[0001] The present disclosure relates generally to serial communication over a serial bus in a wireless communication device, and more particularly to changing the rate of data communication over a display serial interface bus. [Background technology]

[0002]

[0002] Mobile communication devices typically include various components, such as circuit boards, integrated circuit (IC) devices, application specific integrated circuit (ASIC) devices, and / or system-on-chip (SoC) devices. Types of components may include processing circuits, user interface components, storage, and other peripheral components that communicate over a serial bus. The serial bus may operate according to a standard or proprietary protocol. In one example, an Inter-Integrated Circuit (I2C) bus or I2C bus is used. 2 C). The I2C bus was developed to connect low-speed peripherals to a processor, and is configured as a multi-drop bus. A two-wire I2C bus includes a serial data line (SDA) that carries data signals and a serial clock line (SCL) that carries a clock signal.

[0003]

[0003] A serial bus can operate according to a multi-master protocol, where one or more devices can be designated as the bus master or controller for the serial bus in some transmissions and as slaves or responders in other transmissions. In one example, the Improved Inter-Integrated Circuit (I3C) protocol can be used to control operations on the serial bus. The I3C protocol is defined by the Mobile Industry Processor Interface (MIPI) Alliance and derives some implementation aspects from the I2C protocol. In another example, the Radio Frequency Front End (RFFE) interface defined by the MIPI Alliance provides a communications interface for controlling various radio frequency (RF) front-end devices, including power amplifiers (PAs), low-noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, etc. These devices can be co-located on a single IC device or on multiple IC devices. In a mobile communication device, multiple antennas and radio transceivers can support multiple simultaneous RF links.

[0004]

[0004] Several standards have been defined for interconnecting specific types of components of a mobile communication device. For example, there are several types of interfaces defined for communication between an application processor and a display or camera component of a mobile communication device. Some components employ interfaces that conform to one or more standards or protocols defined by the MIPI Alliance, including standards and protocols for Camera Serial Interface (CSI) and Display Serial Interface (DSI).

[0005]

[0005] The MIPI Alliance's CSI-2, DSI, and DSI-2 standards define wired interfaces that can be implemented within or between IC and / or SoC devices to couple a camera and an application processor using the CSI protocol, or an application processor and a display using the DSI protocol. The low-level physical layer (PHY) interface for each of these applications can be a MIPI Alliance-defined C-PHY or D-PHY interface. High-speed and low-power communication modes are defined for the C-PHY and D-PHY interfaces. The C-PHY high-speed mode uses low-voltage multiphase signals transmitted on different phases over a three-wire link. The D-PHY high-speed mode uses multiple two-wire lanes to carry low-voltage differential signals. The low-power modes of the C-PHY and D-PHY interfaces offer lower rates than the high-speed modes and transmit signals at higher voltages. The high-speed signals are undetectable by receivers configured for low-power operation.

[0006]

[0006] As device technology improves, the demand for higher data rates over serial buses and multi-mode display panels has created a greater need for switching clock frequencies on the serial data links used to drive the display panels. Switching clock frequencies requires significant reconfiguration and recalibration that can confuse and destabilize the display subsystem. There is a continuing need to improve serial interfaces to take advantage of technological improvements while maintaining operational stability. Summary of the Invention

[0007]

[0007] Some aspects of the present disclosure relate to systems, apparatus, methods, and techniques that enable wireless communication devices to perform DSI PHY switching in a manner that can provide faster, more stable, and safer DSI clock changes across a wide range of operating frequencies.

[0008]

[0008] In various aspects of the present disclosure, a display subsystem includes a first PHY configured in accordance with the MIPI Alliance DSI specification, a second PHY configured in accordance with the MIPI Alliance DSI specification, and a switch configured to selectively couple a serial data link to the first PHY or the second PHY as directed by a controller. The controller may be configured to: cause a first datagram to be transmitted over the serial data link using a first PHY and a first operating frequency; while the first datagram is being transmitted over the serial data link, configure a second PHY for a second operating frequency different from the first operating frequency; after the second PHY is configured for the second operating frequency, cause the first PHY to transmit configuration information over the serial data link using the first operating frequency; after the configuration information has been transmitted, cause the first PHY to terminate transmission over the serial data link, thereby idling the serial data link; cause the switch to decouple the first PHY from the serial data link; cause the switch to couple the second PHY to the serial data link; and cause a second datagram to be transmitted over the serial data link using the second PHY and the second operating frequency.

[0009]

[0009] In various aspects of the present disclosure, a method for changing an operating frequency in a serial data link includes transmitting a first datagram over the serial data link using a first PHY configured for a first operating frequency; configuring a second PHY for a second operating frequency different from the first operating frequency while the first datagram is being transmitted over the serial data link; transmitting configuration information over the serial data link using the first PHY after the second PHY is configured for the second operating frequency; idling the serial data link by terminating transmission by the first PHY after transmitting the configuration information; decoupling the first PHY from the serial data link; coupling the second PHY to the serial data link; and transmitting a second datagram over the serial data link using the second PHY and the second operating frequency.

[0010] In some aspects, a display driver is coupled to the serial data link, responsive to the configuration information, and configured to reconfigure a PHY of the display driver from a first operating frequency to a second operating frequency after the serial data link is idled. A clock generation circuit can be configured and calibrated to provide one or more clock signals corresponding to the second operating frequency. A switch can be coupled to a wire interface circuit coupled to the serial data link.

[0011] In some aspects, the wire interface circuitry can be reconfigured and calibrated for the second operating frequency after the serial data link is idled. The wire interface circuitry can be calibrated using a bus calibration procedure defined by the C-PHY or D-PHY protocol when transmitting the second datagram.

[0012] In various aspects of the present disclosure, a display driver includes a PHY configured according to the MIPI Alliance DSI specification and a controller. The controller may be configured to: cause data to be extracted from first datagrams received from a serial data link through the PHY when the PHY is configured for a first operating frequency; receive configuration information identifying a second operating frequency from at least one of the first datagrams; reconfigure the PHY for the second operating frequency when the serial data link next enters an idle state; and cause data to be extracted from the second datagrams received from the serial data link when the PHY is configured for the second operating frequency.

[0013]

[0013] In various aspects of the present disclosure, a method for changing an operating frequency in a serial data link includes receiving first datagrams from the serial data link through a PHY when the PHY is configured for a first operating frequency, receiving configuration information identifying a second operating frequency from at least one of the first datagrams, reconfiguring the PHY for the second operating frequency when the serial data link enters a next idle state, and receiving a second datagram from the serial data link when the PHY is configured for the second operating frequency.

[0014] In some aspects, the PHY is configured according to the MIPI Alliance DSI specification. The PHY may be configured by configuring a clock generation circuit to provide one or more clock signals corresponding to a second operating frequency and calibrating the clock generation circuit. After the serial data link is idled, a wire interface circuit may be configured and calibrated for the second operating frequency. The wire interface circuit may be calibrated using a bus calibration procedure defined by the C-PHY or D-PHY protocol upon receiving the second datagram. [Brief explanation of the drawings]

[0015] [Figure 1]

[0015] FIG. 1 illustrates an apparatus employing a data link between IC devices that selectively operates according to a standard or proprietary protocol. [Figure 2]

[0016] FIG. 1 illustrates a system architecture for an apparatus employing data links between IC devices. [Figure 3]

[0017] FIG. 1 illustrates an example of a C-PHY interface. [Figure 4]

[0018] FIG. 1 illustrates an example of a D-PHY interface. [Figure 5]

[0019] FIG. 1 illustrates an example of an apparatus that can be adapted in accordance with some aspects disclosed herein. [Figure 6]

[0020] FIG. 1 illustrates transitions between signaling modes in an example C-PHY interface. [Figure 7]

[0021] FIG. 1 illustrates a transition between signaling modes in a D-PHY interface adapted in accordance with certain aspects disclosed herein. [Figure 8]

[0022] FIG. 1 illustrates a display subsystem configured for MIPI Alliance Dual Ping Pong DSI PHY switching, in accordance with certain aspects of the present disclosure. [Figure 9]

[0023] 9 illustrates an example of messaging over a serial data link when the display subsystem of FIG. 8 is configured for MIPI Alliance Dual Ping Pong DSI PHY switching, in accordance with certain aspects of the present disclosure. [Figure 10]

[0024] FIG. 1 illustrates an example of a device employing processing circuitry that may be adapted in accordance with certain aspects disclosed herein. [Figure 11]

[0025] 1 is a flowchart illustrating a method that may be performed by a host device coupled to a serial bus according to some aspects disclosed herein. [Figure 12]

[0026] FIG. 1 illustrates a first example of a hardware implementation for a communication device adapted in accordance with certain aspects disclosed herein. [Figure 13]

[0027] 1 is a flowchart illustrating a method that may be performed by a display driver device coupled to a serial bus, according to some aspects disclosed herein. [Figure 14]

[0028] FIG. 1 illustrates a second example of a hardware implementation for a communication device adapted in accordance with certain aspects disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0016]

[0029] The detailed description set forth below with reference to the accompanying drawings describes various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The Detailed Description includes specific details intended to provide a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0017]

[0030] Several aspects of the present invention will now be presented with reference to various apparatus and methods. These apparatus and methods will be described in the detailed description that follows and illustrated in the accompanying figures by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

[0018] overview

[0031] Data communication links employed by SoCs and other IC devices to connect processors with modems and other peripherals may operate according to industry or proprietary standards or protocols related to the particular function or type of device. In the example of display panels, display subsystems, and display drivers, communication standards and protocols defined by the MIPI Alliance are frequently used. The Display Serial Interface (DSI®), for example, provides the C-PHY and D-PHY standards and protocols used to define, configure, and control high-speed serial interfaces between host processors and display modules. Other standards and protocols may be provided for ancillary uses, including control and management buses implemented using I2C or I3C protocols.

[0019]

[0032] In mobile communication handsets, user equipment, and other devices, interfaces operating according to the DSI specification or protocol are frequently used for communication between application processors and display drivers. The data rate required to support high-resolution displays can vary based on the display configuration, power budget, and application requirements. Changing the data rate requires reconfiguration and recalibration of the physical interface circuitry coupled to the serial bus to allow for the use of a different frequency for the bit transmission clock. The frequency of the bit transmission clock can also be changed during device operation to mitigate electromagnetic interference (EMI). In one example, high-data-rate DSI signaling may involve transmitting signals over wires at frequencies similar to those of RF signals. Dynamically changing the DSI clock signal frequency, including while the display subsystem is active, can result in display system instability and failure.

[0020]

[0033] The ping-pong DSI PHY switching technique disclosed herein can enable reliable, rapid switching of DSI clock signal frequencies while maintaining system stability. In one example, a display subsystem includes first and second DSI PHYs and a switch configured to selectively couple a serial data link to the first DSI PHY or the second DSI PHY as directed by a controller. The controller is configured to transmit a first datagram over the serial data link using the first DSI PHY and a first operating frequency, configure the second DSI PHY for the second operating frequency while the first datagram is being transmitted over the serial data link, transmit configuration information over the serial data link using the first operating frequency after the second DSI PHY is configured for the second operating frequency, idle the serial data link, and cause the switch to decouple the first DSI PHY from the serial data link and couple the second DSI PHY to the serial data link. A second datagram can then be transmitted over the serial data link using the second DSI PHY and the second operating frequency.

[0021] Examples of devices that use serial data links

[0034] According to some aspects, serial data links may be used to interconnect electronic devices that are sub-components of an apparatus, such as cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, global positioning system (GPS) devices, smart home devices, intelligent lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smart watches, health or fitness trackers, eyewear, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multicopters, or any other similarly functional devices.

[0022]

[0035] 1 illustrates an example of a device 100 employing a data communication bus. The device 100 may include a processing circuit 102 having multiple circuits or devices 104, 106, and / or 108, which may be implemented in an SoC or one or more ASICs. In one example, the device 100 may operate as a communications device, and the processing circuit 102 may include a processing device provided in the ASIC 104, one or more peripheral devices 106, and a transceiver 108, which enables the device to communicate with a radio access network, a core access network, the Internet, and / or another network through an antenna 124.

[0023]

[0036] The ASIC 104 may include one or more processors 112, one or more modems 110, on-board memory 114, bus interface circuitry 116, and / or other logic circuits or functions. The processing circuit 102 may be controlled by an operating system, which may provide an application programming interface (API) layer that enables the one or more processors 112 to execute software modules residing in the on-board memory 114 or other processor-readable storage 122 provided on the processing circuit 102. The software modules may include instructions and data stored in the on-board memory 114 or processor-readable storage 122. The ASIC 104 may access its on-board memory 114, processor-readable storage 122, and / or storage external to the processing circuit 102. The on-board memory 114, processor-readable storage 122 may include read-only memory (ROM) or random-access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that may be used in processing systems and computing platforms. The processing circuit 102 may include, implement, or have access to a local database or other parameter storage capable of maintaining operating parameters and other information used to configure and operate the apparatus 100 and / or the processing circuit 102. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, a soft disk, a hard disk, or the like. The processing circuit 102 may also be operably coupled to external devices such as an antenna 124, a display 126, switches or buttons 128, 130, or operator controls such as an external keypad 132, among other components. The user interface module may be configured to operate with the display 126, external keypad 132, etc., through a dedicated communication link or through one or more serial data interconnections.

[0024]

[0037] The processing circuit 102 may provide one or more buses 118a, 118b, 120 that allow several devices 104, 106, and / or 108 to communicate. In one example, the ASIC 104 may include a bus interface circuit 116 that includes a combination of circuits, counters, timers, control logic, and other configurable circuits or modules. In one example, the bus interface circuit 116 may be configured to operate according to a standard-defined communications specification or protocol. The processing circuit 102 may include or control power management functions that configure and manage the operation of the apparatus 100.

[0025]

[0038] FIG. 2 shows a plurality of devices 202 and 2220-222 coupled to a serial bus 220. N 2 shows several aspects of an apparatus 200 including devices 202 and 2220-222. N may be implemented in one or more semiconductor integrated circuit (IC) devices, such as an application processor, an SoC, or an ASIC. N may include, support, or operate as modems, signal processing devices, display drivers, cameras, user interfaces, sensors, sensor controllers, players, media players, transceivers, and / or other such components or devices. N One or more of the devices 202 and 2220 through 2222 may be used to control, manage, or monitor the sensor device. N Communications between the bus master device 202 and the bus 204 are controlled by a bus master device 202. Some types of buses can support multiple bus master devices 202.

[0026]

[0039] In one example, the master device 202 manages access to the serial bus, and the slave devices 2220-2222 NThe master device 202 may include an interface controller 204 that configures dynamic addresses and / or generates a clock signal 228 that is transmitted on a clock line 218 of the serial bus 220. The master device 202 may include configuration registers 206 or other storage 224 and other control logic 212 configured to handle protocols and / or higher-level functions. The control logic 212 may include processing circuitry having processing devices such as a state machine, a sequencer, a signal processor, or a general-purpose processor. The master device 202 includes a transceiver 210 and line drivers / receivers 214a and 214b. The transceiver 210 may include a receiver, a transmitter, and common circuits, which may include timing, logic, and storage circuits and / or devices. In one example, the transmitter encodes and transmits data based on the timing of the clock signal 228 provided by the clock generation circuit 208. Other timing clock signals 226 may be used by the control logic 212 and other functions, circuits, or modules.

[0027]

[0040] At least one device 2220-222 Nmay be configured to operate as a slave device on serial bus 220 and may include circuits and modules supporting a display, an image sensor, and / or circuits and modules for controlling and communicating with one or more sensors for measuring environmental conditions. In one example, a slave device 2220 configured to operate as a display or imaging interface device may communicate with a display or camera through a DSI interface controller 232, which includes circuits and modules for supporting, controlling, or communicating with the display or camera. Slave device 2220 may include configuration registers 234 or other storage 236, control logic 242, a transceiver 240, and line drivers / receivers 244a and 244b. Control logic 242 may include processing circuitry having processing devices such as a state machine, a sequencer, a signal processor, or a general-purpose processor. Transceiver 240 may include a receiver, a transmitter, and common circuitry, which may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data over data line 216 based on the timing of a clock signal 248 provided by clock generation and / or recovery circuitry 246. Clock signal 248 may be derived from a signal received from clock line 218. Other timing clock signals 238 may be used by control logic 242 and other functions, circuits, or modules.

[0028]

[0041] The serial bus 220 may operate according to RFFE, I2C, I3C, or other protocols. In some cases, two or more devices 202, 2220-222 N may be configured to operate as a bus master device on serial bus 220. In some instances, apparatus 200 may be configured to operate as a bus master device on serial bus 220. N or two or more of the devices 202, 2220 to 222 NThe illustrated example includes several slave devices 2221, 2222, 2223, 2224, 2225, 2226, 2227, 2228, 2229, 2230, 2231, 2232, 2233, 2234, 2235, 2236, 2237, 2238, 2239, 2240, 2241, 2242, 2243, 2244, 2245, 2246, 2247, 2248, 2249, 2250, 2251, 2252, 2253, 2254, 2255, 2256, 2257, 2258, 2259, 2260, 2261, 2 N-1 are coupled to a serial bus 250 that operates according to the RFFE protocol, and two of these slave devices 2221, 2222 are also coupled to a primary serial bus 220 that operates according to another protocol. In the illustrated example, one slave device 2220 is configured to operate as a display controller that communicates with a display device via a serial bus 252 that operates according to the C-PHY protocol (or the D-PHY protocol).

[0029]

[0042] In some aspects of the present disclosure, systems and apparatuses may employ a polyphase data encoding and decoding interface method for communicating between IC devices. A polyphase encoder may drive multiple conductors (i.e., M conductors). The M conductors typically include three or more conductors, each of which may be referred to as a wire, although the M conductors may include conductive traces on a circuit board or within a conductive layer of a semiconductor IC device. In one example, the MIPI Alliance-defined "C-PHY" physical layer interface technology may be used to connect a camera or display to an application processor. The C-PHY interface employs three-phase symbol encoding to transmit data symbols over three wire lanes, or "trios," each of which includes an embedded clock.

[0030]

[0043] The M conductors may be divided into multiple transmission groups, each group encoding a portion of the data block to be transmitted. An N-phase encoding scheme is defined in which bits of data are encoded in the phase transitions and polarity changes of the M conductors. Decoding does not depend on individual conductors or conductor pairs, and timing information can be derived directly from the phase and / or polarity transitions of the M conductors. N-phase polarity data transmission can be applied to any physical signaling interface, including electrical, optical, and radio frequency (RF) interfaces.

[0031]

[0044] In the C-PHY example, a three-phase encoding scheme for a three-wire system may define three phase states and two polarities, resulting in six states and five possible transitions from each state. Deterministic voltage and / or current changes can be detected and decoded to extract data from the three wires.

[0032]

[0045] FIG. 3 illustrates a C-PHY interface 300 that can be used to implement some aspects of the serial bus 252 shown in FIG. 2. The illustrated example may pertain to a three-wire link configured to carry three-phase polarity-encoded data according to the DSI protocol. The use of three-phase polarity encoding provides high-speed data transfer, and an N-phase polarity-encoded data link may consume less than half the power of other interfaces because fewer than three drivers in the C-PHY link are always active. The C-PHY interface uses three-phase polarity encoding to encode multiple bits per symbol transition on the three-wire link. In one example, the combination of three-phase encoding and polarity encoding may be used to support a Wide Video Graphics Array (WVGA) liquid crystal display driver IC at 80 frames per second without a frame buffer, delivering pixel data for display refresh at 810 Mbps over three or more wires.

[0033]

[0046] In the illustrated C-PHY interface 300, three-phase polarity encoding is used to control the signaling state of the connectors, wires, traces, and other interconnects that provide a three-wire bus (trio 320). Each wire of trio 320 can be undriven, driven positively, or driven negatively in any symbol transmission interval. In some cases, the undriven signal wires of trio 320 may be in a high impedance state. In some cases, the undriven signal wires of trio 320 may be driven or pulled to a voltage level that is substantially halfway between the positive and negative voltage levels provided to the driven signal wires. In some cases, no current may flow through the undriven signal wires of trio 320. Drivers 308 coupled to the signal wires of trio 320 are controlled so that only one wire of trio 320 is in each of three states (denoted as +1, −1, or 0) in each symbol interval.

[0034]

[0047] In one example, driver 308 may include a unit-level current-mode driver. In another example, driver 308 may drive voltages of opposite polarity on two signals transmitted on two signal wires of trio 320, with the third signal wire being at high impedance and / or pulled to ground. For each transmit symbol interval, at least one signal is in an undriven (0) state, one signal is driven positive (+1 state), and one signal is driven negative (-1 state), so that the total current flowing to the receiver is always zero. For each symbol, the state of at least one signal wire of trio 320 is changed from the symbol transmitted in the preceding transmit interval.

[0035]

[0048] In the C-PHY interface 300, a mapper 302 may receive a 16-bit input data word 318, which may map the input data word 318 into seven symbols 312 for sequential transmission over the signal wires of a trio 320. An M-wire N-phase encoder 306 configured for 3-wire, 3-phase encoding receives the seven symbols 312 generated by the mapper, one input symbol 314 at a time, and calculates the state of each signal wire of the trio 320 at each symbol interval based on the previous state of the signal wires of the trio 320. The seven symbols 312 may be serialized using, for example, a parallel-to-serial converter 304. The encoder 306 provides a control signal 316 that defines the output of a driver 308. The encoder 306 may select the state of the signal wires of the trio 320 based on the input symbol 314 and the previous state of the signal wires of the trio 320, and provide the control signal 316 to cause the driver 308 to generate the desired signaling state of the trio 320.

[0036]

[0049] Using three-wire, three-phase encoding, some bits are encoded in multiple symbols with a non-integer number of bits per symbol. In the example of a three-wire, three-phase system, there are three available combinations of two wires that can be driven simultaneously, and two possible polarity combinations of pairs of wires that are driven simultaneously, resulting in six possible states. As each transition occurs from the current state, five of the six states are available at any transition. With five states, there are log2(5) per symbol transition.

[0037]

number

[0038] 2.32 bits can be encoded. Thus, the mapper may take a 16-bit word and convert it into seven symbols, since seven symbols carrying 2.32 bits per symbol can encode 16.24 bits. In other words, the seven symbol combinations that encode five states are 5 7There are (78,125) possible permutations. Therefore, the seven symbols are 16-bit binary 16 It can be used to encode (65,536) permutations.

[0039]

[0050] The C-PHY interface 300 includes a receiver including a comparator 322 and a decoder 324 configured to provide a digital representation of the state of each of the three signal wires of the trio 320 and the change in state of the three signal wires compared to the state transmitted in the previous symbol period. Seven successive states are assembled by a serial-to-parallel converter 326 and used to generate a set of seven symbols that are processed by a demapper 328 to obtain 16 bits of data that can be buffered in a first-in-first-out (FIFO) storage device 330, which may be implemented using, for example, a register.

[0040]

[0051] According to some aspects disclosed herein, systems and apparatuses may employ some combination of differential and single-ended encoding to communicate between IC devices. In one example, the MIPI Alliance-defined "D-PHY" physical layer interface technology may be used to connect cameras and display devices to application processors. The D-PHY interface can switch between differential (high-speed) and single-ended low-power (LP) modes in real time as needed to facilitate the transfer of large amounts of data or to conserve power and extend battery life. The D-PHY interface can operate in a single data lane with a unidirectional (master-to-slave) clock lane or in a simplex or duplex configuration with multiple data lanes.

[0041]

[0052] 4 shows a generalized D-PHY configuration 400 including a master device 402 and a slave device 404. The master device 402 generates a clock signal that controls transmission on a wire 410. The clock signal is transmitted on a clock lane 406, and data is transmitted on one or more data lanes 408-408.N The data lanes 4081 to 4088 are provided or active on the device. N The number of can be dynamically configured based on application needs, the amount of data being transferred, and power saving needs.

[0042]

[0053] FIG. 5 illustrates several interface configurations associated with a camera subsystem 500 and a display subsystem 550 that may be included, for example, in a mobile communications device. The camera subsystem 500 may include a CSI-2 defined communication link between an image sensor 502 and an application processor 512. The communication link may include a high-data-rate data transfer link 510 used by the image sensor 502 to transmit image data to the application processor 512 using a transmitter 506. The high-data-rate data transfer link 510 may be configured and operate according to the D-PHY or C-PHY protocol. The application processor 512 may include a crystal oscillator (XO 514) or other clock source to generate a clock signal 522 that controls the operation of the transmitter 506. The clock signal 522 may be processed by a phase-locked loop (PLL) 504 of the image sensor 502. In some instances, the clock signal 522 may also be used by the D-PHY or C-PHY receiver 516 of the application processor 512. The communication link may include a camera control interface (CCI) similar in nature to an I2C (Inter-Integrated Circuit) interface. The CCI bus may include a serial clock (SCL) line that carries a clock signal and a serial data (SDA) line that carries data. The CCI link 520 may be bidirectional and may operate at a lower data rate than the high data rate data transfer link 510. The CCI link 520 may be used by the application processor 512 to send control and data information to and receive control and configuration information from the image sensor 502. The application processor 512 may include a CCI bus master 518, and the image sensor 502 may include a CCI slave 508.

[0043]

[0054] The display subsystem 550 may include a unidirectional data link 558 that may be configured and operated according to the D-PHY or C-PHY protocol. In the application processor 552, a clock source such as a PLL 554 may be used to generate a bit clock signal used by a D-PHY or C-PHY receiver 556 to control transmissions on the data link 558. In the display driver 560, a D-PHY or C-PHY receiver 562 may extract embedded clock information from the sequence of symbols transmitted on the data link or from a clock lane provided in the data link 558.

[0044]

[0055] Some aspects disclosed herein relate to systems, devices, and methods that support a wide range of interface protocols and can operate using different physical media. As shown in FIG. 5 , for example, a camera subsystem 500 and / or a display subsystem 550 may communicate high data rate information using a D-PHY or C-PHY protocol. In some configurations, the camera subsystem 500 and / or the display subsystem 550 may communicate using a reverse channel (e.g., a CCI link 520) for configuration of an image sensor 502 or other device. In some cases, a low-power operating mode may be defined for a link that uses either the D-PHY or C-PHY protocol.

[0045]

[0056] 6 illustrates transitions between communication modes of a C-PHY interface for a conventional mode of operation 600 and transitions between communication modes in an Advanced Low Power (ALP) mode of operation 620. In the conventional mode of operation 600, the C-PHY interface is initially configured for a low-power mode of operation 616. Starting at a first point in time 604, an SoT sequence 610 is transmitted on the link 602 to switch the C-PHY interface to a high-speed mode of operation 612. At a second point in time 606, high-speed transmissions begin. Starting at a third point in time 608, an EoT sequence 614 is transmitted to return the C-PHY interface to the low-power mode of operation 618. The receiver may determine that it is desired to return the C-PHY interface to the low-power mode of operation 618 based on signaling received at the higher voltage level of the low-power mode.

[0046]

[0057] According to some aspects disclosed herein, a C-PHY interface adapted to support the ALP mode of operation 620 transitions between high-speed and low-power modes in response to codewords 634, 636 and a post-sequence 638 defined by the C-PHY protocol. In the ALP mode of operation 620, low-voltage differential signaling is used for the high-speed mode 630 and the low-power modes 628, 632. Therefore, transitions between the high-speed mode 630 and the low-power modes 628, 632 are not detectable using voltage level sensors employed in some conventional C-PHY interfaces. The codewords 634, 636 and the post-sequence 638 used in the ALP mode of operation 620 may be transmitted to signal corresponding mode transitions and / or other events. In an example C-PHY, the post-sequence 638 is already provided at the end of a high-speed data transmission to provide a reliable notification of the end of the high-speed burst to the receiver. In the C-PHY protocol, a post-sequence 638 is provided at the end of the high-speed (HS) forward data 640, and the PHY knows that the high-speed transmission is ending by detecting the post-sequence 638. The post-sequence 638 includes a series of unmapped codewords (e.g., a sequence in which all symbols have a value of "4"). A start-of-transmission (SoT) codeword 634 may be transmitted to initiate the high-speed mode 630. In some cases, the receiver may generate an SOT detection signal 624. The SoT codeword 634 may include a sequence of codewords. In one example, the SoT codeword 634 may be defined as the sequence {LP-111, LP-001, LP-000}. The SoT codeword 634 may be preceded by a first pause 642 and followed by a second pause 644.

[0047]

[0058] In the C-PHY interface, symbol timing is embedded in the waveform, eliminating the need to manage the transmit clock signal during transitions between the high-speed mode 630 and the low-power modes 628, 632. According to some aspects disclosed herein, all of the LP escape mode code words of the C-PHY interface (see Table 1 below) can, in whole or in part, use unique C-PHY sequences of seven or more symbols that are not generated by the C-PHY data mapping function. This allows the C-PHY receiver to reliably detect all of the code words without having to rely too heavily on specific transmission conditions. While in high-speed transmission mode, the C-PHY receiver can always recover to the correct power state.

[0048]

[0059] An untransmitted clock lane 626, which may represent an internal clock generation or clock extraction circuit, initiates a transition from low power mode 628 to high speed mode 630 at time 646 during a pause 644 that occurs after an SoT code word 634 is transmitted on link 622. The transition from low power mode 628 to high speed mode 630 may include toggling a pause low power state and enabling high speed mode exit. A transition from high speed mode 630 to a next low power mode 632 may be initiated at time 648 after an LP-111 code is transmitted on link 622. The transition from high speed mode 630 to a next low power mode 632 may include toggling a pause high speed state and enabling high speed mode exit.

[0049]

[0060] In some cases, the clock signal may be toggled only when code needs to be transmitted when the PHY is in a low power state. In some cases, a continuous clock mode may be implemented in which one lane toggles periodically during a low power state. The continuous clock mode may support some implementations in which some link activity is required or desired, including links involving optical media and / or links operating according to the MIPI Alliance's DSI-2 specification. According to some aspects, the master device may be configured to select the clock rate used in the low power mode and / or other modes.

[0050]

[0061] 7 is a graphical representation 700 of waveforms illustrating transitions between communication modes using an example D-PHY interface. The example shows signaling over two wires 702, 704 operating as data lanes of a communication link operating according to the D-PHY protocol. The D-PHY interface can be configured to operate in a low-power mode 710 and / or a high-speed mode 712. In the illustrated example, the high-speed mode 712 begins at a first time point 706 and ends at a second time point 708.

[0051]

[0062] In low-power mode 710, the first wire carries a data signal at a relatively low data rate with a voltage level swing of approximately 1.2 volts. In high-speed mode 712, the first wire 702 and the second wire 704 carry a low-voltage differential signal that may have a data rate several orders of magnitude faster than the data rate of the low-power mode 710. For example, the low-power mode 710 may support a data rate up to 10 megabits per second (Mbps), and the high-speed mode 712 may support a data rate between 80 Mbps and 4.5 gigabits per second (Gbps). In high-speed mode 712, a positive version 714 of the differential signal may be carried on the first wire 702, and a negative version 716 of the differential signal may be carried on the second wire 704. The differential signal may have a relatively small amplitude voltage swing, which may be approximately 200 millivolts (mV) in one example. Conventional C-PHY and D-PHY interface receivers can use voltage level detectors to switch between high-speed and low-power modes of operation.

[0052]

[0063] The bit clock signal of the DSI interface controls the data rate of the DSI interface and may be switched between frequencies used to support different display resolutions or to mitigate electromagnetic interference (EMI) generated by the DSI interface. Mobile communication handsets and other user equipment and devices that include interfaces operating in accordance with the DSI specification are often among the top sources of RF interference for the RF interfaces of user equipment and devices. The data rates required to support high-resolution displays or imaging devices can result in high-frequency EMI that can affect the RF signals.

[0053]

[0064] Some standards defining DSI interfaces include a mandatory requirement that dynamic changes in clock frequency be supported. In one aspect of the present disclosure, dynamic changes include changes that can be initiated while the device is active without significantly affecting ongoing operations. In some examples, a C-PHY or D-PHY interface may be clocked using a clock signal having a frequency between 100 MHz and 1.8 GHz, where interference with RF signals associated with the RF modem of a mobile communication device can severely impact wireless signal quality, reliability, and mobility. Displays with higher resolutions, greater bit depths, and flexible, increased frames per second (FPS) rates may require the C-PHY or D-PHY interface to be clocked at a frequency that can be dynamically changed to accommodate dynamically switched FPS and display resolutions. In some examples, the C-PHY or D-PHY interface may be clocked using a clock signal having a frequency between 100 MHz and 1.8 GHz.

[0054]

[0065] The level of dynamic change in clock frequency may be determined by the type of change or the reason for the change. For example, a 20 MHz change in DSI bit clock frequency from 800 MHz to 820 MHz may be sufficient for the purpose of reducing interference. Larger dynamic changes in clock frequency may be indicated to reduce power consumption and lower DSI operating voltage. Changes in display resolution or FPS may require larger dynamic changes in DSI bit clock frequency. For example, a 150 MHz DSI bit clock frequency may be used to communicate with a display operating at 30 FPS, and a 600 MHz DSI bit clock frequency may be used to communicate with a display operating at 120 FPS.

[0055]

[0066] Dynamic DSI clock change techniques used in conventional systems generally cannot reliably or safely handle large changes in the DSI bit clock frequency. A change in the DSI bit clock frequency may be considered unsafe during runtime when the change results in instability and / or failure to comply with the MIPI Alliance-defined specification for DSI. Rapid switching of the DSI bit clock frequency, such as from 150 MHz to 600 MHz, can lead to instability in the DSI PHY and can easily cause a loss of lock in the PLL 554 used to generate the bit clock signal for controlling transmission over the data link 558 of FIG. 5. Rapid switching of the DSI bit clock frequency may require the entire DSI PHY to be reconfigured to match the change in DSI bit clock frequency and ensure coherence of the DSI analog signal. For example, a large change in the DSI bit clock frequency requires that parameters defined by the DSI timing rules and specifications be changed to match the new target DSI bit clock frequency.

[0056]

[0067] In display panels, significant reconfiguration of the DSI protocol level is typically performed in the display driver IC (DDIC) after a significant change in the DSI bit clock frequency. For example, the protocol may be modified to allow for NULL packets to be inserted into the data stream and to configure a low-power state, such as an ultra-low power state (ULPS), during idle periods. Traditionally, changing the DSI bit clock frequency involves simultaneously changing the configuration of the DSI PHY and the logic implementing the DSI protocol, with the changes occurring during frame refresh, the same vertical synchronization (Vsync), and / or during DSI idle periods. DSI signaling may enter an invalid intermediate state if the reconfiguration of the DSI PHY and DSI protocol logic is not performed simultaneously. For example, inaccurate DSI signaling may occur when the DSI bit clock is changed in frame N, the DSI PHY timing is changed in frame N+1, and the DSI protocol configuration is changed in frame N+2. In the latter example, the DSI PHY may become unstable or be considered unstable.

[0057]

[0068] Some aspects of the present disclosure provide methods, apparatus, and techniques that can be used to rapidly switch the frequency of a bit clock signal of a DSI interface. In one aspect, an active first DSI PHY of a transmitting device may be managing active communication with a DDIC using an initial DSI bit clock frequency, and a second DSI PHY is configured to operate using a changed DSI bit clock frequency. The second DSI PHY may switch roles with the first DSI PHY when the second DSI PHY achieves operational readiness at the changed DSI bit clock operating frequency. The second DSI PHY then manages active communication with the DDIC, and the first DSI PHY enters an idle state or begins reconfiguration. In one example, operational readiness may be indicated when the clock generator circuit of the second DSI PHY is locked, stable, and calibrated, when protocol configuration is completed in the second DSI PHY, and when timing configuration is configured in the second DSI PHY. At a later point in time, when the first DSI PHY is inactive and ready to operate, a switch from the second DSI PHY to the first DSI PHY may occur. Switching between the active and inactive DSI PHYs is sometimes referred to herein as dual ping-pong DSI PHY switching.

[0058]

[0069] Dual ping-pong DSI PHY switching may involve switching between PHYs and several associated hardware circuits and / or protocol controllers. A hardware switch may be used to connect or disconnect the DSI PHYs involved in the ping-pong switching. Dual ping-pong DSI PHY switching can provide fast, stable, and flexible wide-range DSI clock and PHY reconfiguration without interrupting the operation of the DDIC. In one example, the DSI bit clock frequency may be seamlessly switched from 50 MHz to 1.5 GHz with simultaneous changes in corresponding protocol and timing configurations as defined by the DSI specification.

[0059]

[0070] FIG. 8 illustrates a display subsystem 800 configured for dual ping-pong DSI PHY switching in accordance with some aspects of the present disclosure. The display subsystem 800 may, in some examples, be incorporated within a mobile communication device. In the illustrated example, the display subsystem 800 includes a multi-wire serial data link 820 that may be configured and operated in accordance with the DSI specification and protocol. In one example, data is communicated over the serial data link 820 using the C-PHY protocol. In another example, data is communicated over the serial data link 820 using the D-PHY protocol. A host device (here, an application processor 802) is coupled to a DDIC 822 through the serial data link 820. The application processor 802 may configure and control the DDIC 822 and may be configured to provide image data to the DDIC 822. The DDIC 822 includes a DSI PHY circuit 824 that is coupled to the serial data link 820 and configured to respond to transmissions encoded in accordance with the C-PHY or D-PHY protocol.

[0060]

[0071] The illustrated application processor 802 includes two independently configurable clock generation circuits 804a, 804b and two independently configurable DSI PHY circuits 806a, 806b. In some examples, each of the clock generation circuits 804a, 804b includes a clock source such as a PLL, a delay-locked loop (DLL), or another type of configurable clock generator. The clock generation circuits 804a, 804b output clock signals 814a, 814b to the DSI PHY circuits 806a, 806b, respectively. The clock signals 814a, 814b can be configured to control the timing of transmissions on the serial data link 820. The clock generation circuits 804a, 804b can be configured by the controller or processor 812 to generate the clock signals 814a, 814b at different frequencies when ping-pong DSI PHY switching is performed. For example, one clock generation circuit 804a or 804b may be configured to generate a 50 MHz clock signal 814a, and the other clock generation circuit 804b or 804a may be configured to generate a 1.5 GHz clock signal 814b. Other combinations of clock frequencies may be implemented or configured. The controller or processor 812 may configure the clock generation circuits 804a, 804b to provide required or defined clock signals 814a, 814b for each DSI PHY circuit 806a, 806b according to the demands or requirements of the application. In some implementations, the clock generation circuits 804a and 804b may be included in a set of clock generation circuits capable of providing a wide range of clock signals. In some cases, some clock generation circuits may be suitable for generating high-frequency clock signals (up to 1.5 GHz or higher), while other clock generation circuits may be suitable for generating lower-frequency clock signals, including, for example, 50 MHz clock signals. In some cases, the controller or processor 812 may select the clock generation circuit 804a, 804b for each DSI PHY circuit 806a, 806b based on the demands or requirements of the application.

[0061]

[0072] Controller or processor 812 may configure each of DSI PHY circuits 806a, 806b according to timing and protocol specifications defined by the DSI standard. Controller or processor 812 may select between DSI PHY circuits 806a, 806b to manage communications over serial data link 820. Switching circuit 808, operated by controller or processor 812, may be used to couple signal 818 to wire interface circuit 810. In one example, signal 818 is generated or generated by the selected DSI PHY circuit 806a or 806b. In another example, signal 818 is provided to the selected DSI PHY circuit 806a or 806b by another circuit or by controller or processor 812. Wire interface circuit 810 is configured to couple application processor 802 to serial data link 820 and may include line drivers, amplifiers, equalizers, filters, and other circuitry that can optimize the electrical interface between application processor 802 and the wires of serial data link 820.

[0062]

[0073] The DSI PHY circuit 824 of the DDIC 822 is configured to extract data from signals received from the serial data link 820. The DSI PHY circuit 824 is coupled to a wire interface circuit 826 configured to couple the DDIC 822 to the serial data link 820. The wire interface circuit 826 may include receivers, amplifiers, equalizers, filters, and other circuitry that can optimize the electrical interface between the DDIC 822 and the wires of the serial data link 820. In one example, the DSI PHY circuit 824 may operate according to the C-PHY protocol and extract embedded clock information from transitions in a sequence of symbols transmitted over the serial data link 820. The DSI PHY circuit 824 may extract symbols for decoding based on the extracted embedded clock information. In another example, the DSI PHY circuit 824 may operate according to the D-PHY protocol and extract data from signals received over the serial data link 820 based on explicit timing information provided by a clock signal received from the wires of the serial data link 820.

[0063]

[0074] The display subsystem 800 may be configured to implement or operate dual ping-pong DSI PHY switching in accordance with some aspects of the present disclosure. In one example, a first DSI PHY circuit 806a may actively participate in communications with a DDIC 822 over a serial data link 820. A second DSI PHY circuit 806b may be configured or calibrated for communications over the serial data link 820 at a clock rate different from that used by the first DSI PHY circuit 806a. The controller or processor 812 may be provided with a target DSI configuration that includes a desired clock rate and a corresponding configuration of the DSI PHY and DSI protocol. The configuration of the DSI PHY and DSI protocol may be expressed as a set of parameters, register settings, and / or selected options appropriate to the desired clock rate. Some aspects of the configuration may be applied to or managed by the controller or processor 812 or some combination of hardware and software sequences executed in or by the controller or processor 812. In one example, an element of the protocol configuration and / or DSI PHY configuration may relate to NULL packets that may be inserted into the data stream transmitted through the second DSI PHY circuit 806b.

[0064]

[0075] Configuration of the second DSI PHY circuit 806b may include certain targets, thresholds, or limits that are applied to signaling over the serial data link 820 when the desired clock rate is implemented. During configuration of the second DSI PHY circuit 806b, the corresponding clock generation circuit 804b may be configured to generate one or more clock signals at frequencies calculated to enable or facilitate data transmission at the desired data rate. In one example, the clock signals include phase-shifted versions of the desired clock signal. In another example, the one or more clock signals include half-rate or double-rate versions of the desired clock signal. Calibration of the second DSI PHY circuit 806b may include calibrating the clock signals generated by the associated clock generation circuit 804b.

[0065]

[0076] When the second DSI PHY circuit 806b is configured and calibrated, the controller or processor 812 may send one or more commands to the DDIC 822 to cause the DDIC 822 to reconfigure and / or recalibrate its DSI PHY circuit 824 and wire interface circuit 826. The controller or processor 812 may also send configuration parameters to facilitate the reconfiguration and recalibration. The DDIC 822 may perform the reconfiguration and recalibration during the next period that the serial data link 820 is idle. The controller or processor 812 may initiate a switch between the DSI PHY circuits 806a and 806b during the idle period. The controller or processor 812 may reconfigure the wire interface circuit 810 of the application processor 802 to facilitate the data rate change before switching between the DSI PHY circuits 806a and 806b. The wire interface circuits 810, 826 may be calibrated during idle periods or during the transmission of certain preambles defined by the C-PHY or D-PHY protocols used to control data communications over the serial data link 820.

[0066]

[0077] The controller or processor 812 may cause the switching circuit 808 to register the new selection of the second DSI PHY circuit 806b as the active PHY. The switching circuit 808 may respond to the change in selection during an idle period of the serial data link 820, as indicated by a signal 816 received from the wire interface circuit 810. In some implementations, the controller or processor 812 indicates when the idle period begins. In some examples, the signal 816 clocks a flip-flop or register that captures the PHY selection information. Before the switching circuit 808 registers the new selection of the second DSI PHY circuit 806b as the active PHY, commands may be sent by the application processor 802 to the DDIC 822 to prepare for the data rate change. These commands and associated configuration information enable the DDIC 822 to reconfigure its DSI PHY circuit 824, wire interface circuit 826, and one or more associated display panels to be reconfigured, and to prepare the clock generation circuitry to lock to the new DSI clock value. Deskew calibration of D-PHY or C-PHY can be triggered when the target bit clock is at a certain higher frequency. In one example, the DSI protocol provides deskew training when the clock signal has a frequency of 1.8 GHz, and does not provide deskew training when the clock signal has a frequency of 150 MHz.

[0067]

[0078] 9 is a message flow diagram illustrating an example of messaging 900 over serial data link 820 when display subsystem 800 of FIG. 8 is configured for dual ping-pong DSI PHY switching, in accordance with certain aspects of the present disclosure. In the illustrated example, first DSI PHY circuit 806a is initially in an idle state, and second DSI PHY circuit 806b is initially engaged in communication with DDIC 822 over serial data link 820 according to clock signal 814a having a frequency of 1.8 GHz. For example, second DSI PHY circuit 806b transmits datagrams 9021-9022. nAt a first time point 904, the first DSI PHY circuit 806a is reconfigured for 150 MHz operation. The first DSI PHY circuit 806a may receive commands and / or parameters defining the operating characteristics of the 150 MHz operation under the DSI specification. The first DSI PHY circuit 806a may begin a configuration and calibration procedure. In some examples, the controller or processor 812 may configure an associated clock generation circuit 804a to generate one or more clock signals used for 150 MHz operation. The clock generation circuit 804a may take some time to stabilize, and calibration of the first DSI PHY circuit 806a may continue until a stable 150 MHz configuration is achieved. At a second point in time 906, the configuration and calibration is determined to be complete by the controller or processor 812, and the controller or processor 812 causes the second DSI PHY circuit 806b to schedule, queue, or otherwise transmit one or more datagrams 908 including commands and / or data configured to cause the DDIC 822 to prepare for reconfiguration of its DSI PHY circuit 824, wire interface circuit 826, and protocol handler to support 150 MHz operation. In some examples, the commands and / or data are configured to cause the DDIC 822 to switch from 1.8 GHz operation to 150 MHz operation when the serial data link 820 enters an idle state.

[0068]

[0079] In the illustrated example, serial data link 820 enters an idle state at a third time point 910, and DDIC 822 can begin reconfiguring and recalibrating its DSI PHY circuit 824, wire interface circuit 826, and protocol handlers. In application processor 802, controller or processor 812 causes switching circuit 808 to isolate signals generated or received by second DSI PHY circuit 806b from wire interface circuit 810 and couple signals generated or received by first DSI PHY circuit 806a to wire interface circuit 810. Controller or processor 812 may also enable reconfiguration of the protocol handlers. First DSI PHY circuit 806a may then be used for communications between application processor 802 and DDIC 822. Additional calibration may be performed during preamble transmissions defined by the C-PHY and D-PHY protocols. In the illustrated example, a transmitted preamble 916 is shown in the first datagram 914 transmitted by the first DSI PHY circuit 806a after switching from 1.8 GHz operation to 150 MHz operation.

[0069]

[0080] Protocol-specific preambles are included in all datagrams 9021-902 n, 908, 914, 918. It will be understood that the procedure shown in FIG. 9 may be repeated, with the first DSI PHY circuit 806a and the second DSI PHY circuit 806b alternating between an active state and an idle state with each iteration of the procedure. The procedure shown in FIG. 9 may be applied to any combination of operating frequencies supported by the application processor 802 and the DDIC 822. The operating frequencies may be supported when the application processor 802 and the DDIC 822 may be configured to comply with the DSI PHY timing and DSI protocol configuration defined by the DSI specification or the C-PHY or D-PHY protocol. The DSI PHY timing and DSI protocol configuration may be communicated by the controller or processor 812 prior to the ping-pong DSI PHY switching. The operating frequency may be selected based on the display mode to reduce power or reduce EMI caused by transmission over the serial data link 820. In one example, the first DSI PHY circuit 806a may be configured for 10 FPS (with a refresh rate of 10 Hz), and the second DSI PHY circuit 806b may be configured for 120 FPS (with a refresh rate of 120 Hz). In another example, the procedure shown in Figure 9 may pertain to a switch initiated for power reduction purposes, in which the display subsystem 800 is switched from 1.8 GHz operation to 150 MHz operation.

[0070]

[0081] The time elapsed between the start of configuration at the first point in time 904 and the determination that calibration is complete at the second point in time 906 may be referred to as ping pong warm-up time 920. According to some aspects, ping pong warm-up time 920 may be configured to provide sufficient time for DSI PHY circuits 806a, 806b of application processor 802 to complete configuration and calibration of internal and external circuits. In some examples, ping pong warm-up time 920 provides sufficient time for PLL lock and timing stability of circuits responsive to clock signals 814a, 814b.

[0071]

[0082] The time elapsed between the third point in time 904 at which serial data link 820 enters the idle state and the transmission of the first datagram 914 by first DSI PHY circuit 806a may be referred to as DDIC warm-up time 922. According to some aspects, DDIC warm-up time 922 may be configured to provide sufficient time for DSI PHY circuit 824 of DDIC 822 to complete configuration and calibration of its internal and external circuits. In some examples, DDIC warm-up time 922 provides sufficient time for stability of clock generation circuitry and other circuitry responsive to the clock signal used to sample serial data link 820.

[0072]

[0083] Ping-pong preparation time 920 and DDIC preparation time 922 may be configured to flexibly support a wide range of dynamic DSI clock changes. In some implementations, a pair of DSI PHY circuits 806a, 806b is available for use in ping-pong DSI PHY switching. However, both DSI PHY circuits 806a, 806b need not be provided on the same IC device. Furthermore, ping-pong DSI PHY switching may be used by more than two DSI PHY circuits 806a, 806b. For example, one or more DSI PHY circuits 806a, 806b may be capable of operating in frequency ranges that do not completely overlap, and one or more additional DSI PHY circuits may be provided to enable ping-pong DSI PHY switching over a wider frequency range.

[0073]

[0084] Ping-pong DSI PHY switching can be implemented in an SoC or other IC device with multiple DSI PHY circuits. A hardware switch circuit can be added. The hardware switch typically consumes very low power and occupies a small area of ​​the SoC or IC device, measured as a percentage of the DSI PHY. Ping-pong DSI PHY switching can provide fast, stable, and safe DSI clock changes over a wide range of operating frequencies. The availability of fast, stable, and safe ping-pong DSI PHY switching can enable systems to increase power savings without losing performance and reliability during switching. For example, low-temperature polycrystalline oxide (LTPO) organic light-emitting diode (OLED) display panels can operate at much lower FPS, and dynamic DSI clock changes from 1.7 GHz to 0.2 GHz associated with LTPO can be performed reliably using ping-pong DSI PHY switching, increasing the power savings that can be achieved.

[0074] Examples of Processing Circuits and Methods

[0085] FIG. 10 is a diagram illustrating an example of a hardware implementation of device 1000. In some examples, device 1000 may perform one or more functions disclosed herein. According to various aspects of the present disclosure, elements, or any portion of elements, or any combination of elements as disclosed herein, may be implemented using processing circuitry 1002. Processing circuitry 1002 may include one or more processors 1004 controlled by some combination of hardware and software modules. Examples of processors 1004 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gate logic, discrete hardware circuits, and other suitable hardware configured to perform various functions described throughout this disclosure. One or more processors 1004 may include dedicated processors that perform specific functions and may be configured, augmented, or controlled by one of the software modules 1016. One or more processors 1004 may be configured through the loading of a combination of software modules 1016 during initialization and may be further configured by loading or unloading one or more software modules 1016 during operation.

[0075]

[0086] In the depicted example, the processing circuit 1002 may be implemented using a bus architecture generally represented by a bus 1010. The bus 1010 may include any number of interconnected buses and bridges, depending on the particular application and overall design constraints of the processing circuit 1002. The bus 1010 links various circuits together, including one or more processors 1004 and storage 1006. The storage 1006 may include memory devices and mass storage devices, sometimes referred to herein as computer-readable media and / or processor-readable media. The bus 1010 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A bus interface 1008 may provide an interface between the bus 1010 and one or more transceivers 1012a, 1012b. A transceiver 1012a, 1012b may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in the transceivers 1012a, 1012b. Each transceiver 1012a, 1012b constitutes a means for communicating with various other devices over a transmission medium. In one example, the transceiver 1012a may be used to couple the device 1000 to a multi-wire bus. In another example, the transceiver 1012b may be used to connect the device 1000 to a wireless access network. Depending on the nature of the device 1000, a user interface 1018 (e.g., keypad, display, speaker, microphone, joystick) may also be provided and may be communicatively coupled to the bus 1010 directly or through the bus interface 1008.

[0076]

[0087] The processor 1004 may be responsible for general processing, which may include managing the bus 1010 and executing software stored on a computer-readable medium, which may include storage 1006. In this regard, the processing circuitry 1002, including the processor 1004, may be used to perform any of the methods, functions, and techniques disclosed herein. The storage 1006 may be used to store data that is manipulated by the processor 1004 when executing software, which may be configured to perform some of the methods disclosed herein.

[0077]

[0088] The one or more processors 1004 of the processing circuitry 1002 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in storage 1006 or in an external computer-readable medium. The external computer-readable medium and / or storage 1006 may include non-transitory computer-readable media. Non-transitory computer-readable media include, by way of example, magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips), optical disks (e.g., compact disks (CDs) or digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., “flash drives,” cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM) including EEPROM, registers, removable disks, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. Computer-readable media and / or storage 1006 may also include, by way of example, carrier waves, transmission lines, and any other suitable medium for transmitting software and / or instructions that can be accessed and read by a computer. Computer-readable media and / or storage 1006 may reside within processing circuit 1002, within processor 1004, external to processing circuit 1002, or may be distributed across multiple entities, including processing circuit 1002. The computer-readable medium and / or storage 1006 may be incorporated into a computer program product. By way of example, the computer program product may include the computer-readable medium in packaging materials.Those skilled in the art will recognize how to best implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

[0078]

[0089] Storage 1006 may hold software held and / or organized into loadable code segments, modules, applications, programs, etc., sometimes referred to herein as software modules 1016. Each of the software modules 1016 may include instructions and data that, when installed or loaded onto the processing circuitry 1002 and executed by one or more processors 1004, contribute to a runtime image 1014 that controls the operation of the one or more processors 1004. When executed, some instructions may cause the processing circuitry 1002 to perform functions according to some of the methods, algorithms, and processes described herein.

[0079]

[0090] Some of the software modules 1016 may be loaded during initialization of the processing circuit 1002, and these software modules 1016 may configure the processing circuit 1002 to enable implementation of various functions disclosed herein. For example, some software modules 1016 may configure the internal devices and / or logic 1022 of the processor 1004 and may manage access to external devices such as the transceivers 1012a, 1012b, the bus interface 1008, the user interface 1018, timers, mathematical coprocessors, etc. The software modules 1016 may include a control program and / or operating system that interacts with interrupt handlers and device drivers and controls access to various resources provided by the processing circuit 1002. The resources may include memory, processing time, access to the transceivers 1012a, 1012b, the user interface 1018, etc.

[0080]

[0091] The one or more processors 1004 of the processing circuit 1002 may be multifunctional, whereby some of the software modules 1016 are loaded and configured to perform different functions or different instances of the same function. The one or more processors 1004 may additionally be adapted to manage background tasks initiated in response to input from, for example, the user interface 1018, the transceivers 1012a, 1012b, and device drivers. To support the execution of multiple functions, the one or more processors 1004 may be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks serviced by the one or more processors 1004 as needed or desired. In one example, the multitasking environment may be implemented using a time-sharing program 1020 that passes control of the processor 1004 between different tasks, whereby each task returns control of the one or more processors 1004 to the time-sharing program 1020 upon completion of any outstanding operations and / or in response to inputs such as interrupts. When a task has control of one or more processors 1004, the processing circuitry is effectively specialized for the purpose addressed by the function associated with the controlling task. The time-sharing program 1020 may include an operating system, a main loop that transfers control on a round-robin basis, a function that allocates control of one or more processors 1004 according to a prioritization of the functions, and / or an interrupt-driven main loop that responds to external events by providing control of one or more processors 1004 to processing functions.

[0081]

[0092] 11 is a flowchart 1100 of a method for changing the operating frequency of a serial data link in a host or application processor. The method may be implemented in a display subsystem configured for ping-pong DSI PHY switching according to some aspects of the present disclosure. In one example, a mobile communication device includes a serial data link operating according to a C-PHY or D-PHY protocol. The method may be performed using a controller or other processor of the mobile communication device.

[0082]

[0093] In the illustrated method, at block 1102, a controller may transmit a first datagram over a serial data link using a first PHY configured for a first operating frequency. The PHY may operate according to the specifications of the DSI PHY. At block 1104, the controller may configure a second PHY for a second operating frequency different from the first operating frequency while the first datagram is being transmitted over the serial data link. The method may be delayed at block 1106 until the second PHY is configured. In some examples, the method is delayed at block 1106 until the second PHY is calibrated.

[0083]

[0094] At block 1108, the controller may transmit configuration information over the serial data link using the first PHY after the second PHY is configured for the second operating frequency. In one example, the configuration information is transmitted to the DDIC. After transmitting the configuration information, the controller may idle the serial data link by terminating transmission by the first PHY at block 1110. At block 1112, the controller may decouple the first PHY from the serial data link, and at block 1114, the controller may couple the second PHY to the serial data link. The decoupling of the first PHY from the serial data link and the subsequent coupling of the second PHY to the serial data link may be referred to as a PHY switch. The repeated PHY switching between the two PHYs may be referred to as ping-pong switching. At block 1116, the controller may transmit a second datagram over the serial data link using the second PHY and the second operating frequency.

[0084]

[0095] In some examples, the configuration information is configured to cause a display driver coupled to the serial data link to reconfigure a PHY of the display driver from the first operating frequency to the second operating frequency after the serial data link is idle. The first PHY and the second PHY may be configured according to the MIPI Alliance DSI specification. In some examples, configuring the second PHY includes configuring a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency and calibrating the clock generation circuit.

[0085]

[0096] In some examples, a switch may be used to isolate a first PHY from a serial data link and couple a second PHY to the serial data link. The switch may select between the first PHY and the second PHY to drive or manage the serial data link. The switch is coupled to a wire interface circuit coupled to the serial data link. The controller may reconfigure the wire interface circuit after the serial data link is idled, for example, by calibrating the wire interface circuit for a second operating frequency. The controller may calibrate the wire interface circuit using a bus calibration procedure defined by the C-PHY or D-PHY protocol when transmitting the second datagram.

[0086]

[0097] 12 illustrates a first example of a hardware implementation for an apparatus 1200 employing a processing circuit 1202. The processing circuit typically includes one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines, generally represented by a processor 1216. The processing circuit 1202 may be implemented using a bus architecture, generally represented by a bus 1220. The bus 1220 may include any number of interconnected buses and bridges, depending on the particular application and overall design constraints of the processing circuit 1202. The bus 1220 links together various circuits, including one or more processors 1216, modules or circuits 1204, 1206, and 1208, and a processor-readable storage medium 1218. A bus interface circuit and / or module 1214 may be provided to support communication over a serial data link 1212. Bus 1220 may also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further.

[0087]

[0098] The processor 1216 may be responsible for general processing, including executing software, codes, and / or instructions stored in the processor-readable storage medium 1218. The processor-readable storage medium 1218 may include a non-transitory storage medium. The software, when executed by the processor 1216, causes the processing circuit 1202 to perform the various functions described above for any particular apparatus. The processor-readable storage medium may be used to store data that is manipulated by the processor 1216 when executing the software. The processing circuit 1202 further includes at least one of modules 1204, 1206, and 1208. The modules 1204, 1206, and 1208 may be software modules residing / stored in the processor-readable storage medium 1218 and operating within the processor 1216, one or more hardware modules coupled to the processor 1216, or some combination thereof. Modules 1204, 1206, and 1208 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0088]

[0099] In one configuration, the apparatus 1200 includes a module and / or circuit 1204 adapted to select and switch a PHY for coupling to a serial data link 1212, a module and / or circuit 1206 adapted to configure and calibrate the PHY while the PHY is idle or inactive, and a module and / or circuit 1208 adapted to configure, generate, and calibrate a clock signal used by the PHY.

[0089]

[0100] In one example, apparatus 1200 is configured to operate as a mobile communications device having a wireless transceiver configured to transmit and receive RF signals through one or more antennas, a bus interface circuit and / or module 1214 configured to couple apparatus 1200 to a serial data link, and a controller or other processor. Bus interface circuit and / or module 1214 may include a first PHY and a second PHY each configured for DSI operation, and a switch configured to select between the first PHY and the second PHY and to couple the selected PHY to a wire driver circuit coupled to the serial data link. The controller may be configured to: cause a first datagram to be transmitted over the serial data link using a first PHY and a first operating frequency; while the first datagram is being transmitted over the serial data link, configure a second PHY for a second operating frequency different from the first operating frequency; after the second PHY is configured for the second operating frequency, cause the first PHY to transmit configuration information over the serial data link using the first operating frequency; after the configuration information has been transmitted, cause the first PHY to terminate transmission over the serial data link, thereby idling the serial data link; cause the switch to decouple the first PHY from the serial data link; cause the switch to couple the second PHY to the serial data link; and cause a second datagram to be transmitted over the serial data link using the second PHY and the second operating frequency.

[0090]

[0101] In some examples, the display subsystem includes a display driver coupled to the serial data link, the display driver responsive to the configuration information and configured to reconfigure a PHY of the display driver from the first operating frequency to a second operating frequency after the serial data link is idled. In some examples, the controller is further configured to configure a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency and to calibrate the clock generation circuit.

[0091]

[0102] In some examples, the switch is coupled to a wire interface circuit coupled to a serial data link. The controller may be further configured to reconfigure the wire interface circuit and calibrate the wire interface circuit for a second operating frequency after the serial data link is idled. The controller may be further configured to calibrate the wire interface circuit using a bus calibration procedure defined by the C-PHY or D-PHY protocol when transmitting the second datagram.

[0092]

[0103] The processor-readable storage medium 1218 may include instructions to cause the processing circuit 1202 to transmit a first datagram over the serial data link using a first PHY configured for a first operating frequency, configure a second PHY for a second operating frequency different from the first operating frequency while the first datagram is being transmitted over the serial data link, and transmit configuration information over the serial data link using the first PHY after the second PHY is configured for the second operating frequency. The processor-readable storage medium 1218 may include instructions to cause the processing circuit 1202, after transmitting the configuration information, to idle the serial data link by terminating transmission by the first PHY, decouple the first PHY from the serial data link, couple the second PHY to the serial data link, and transmit a second datagram over the serial data link using the second PHY and the second operating frequency.

[0093]

[0104] In some examples, the configuration information is configured to cause a display driver coupled to the serial data link to reconfigure a PHY of the display driver from the first operating frequency to the second operating frequency after the serial data link is idle. In some examples, the first PHY and the second PHY are configured according to the MIPI Alliance DSI specification. In some examples, configuring the second PHY includes configuring a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency and calibrating the clock generation circuit.

[0094]

[0105] In some examples, the instructions cause the processing circuit 1202 to use a switch to isolate a first PHY from a serial data link and couple a second PHY to the serial data link. The switch may be coupled to a wire interface circuit coupled to the serial data link. The instructions may cause the processing circuit 1202 to reconfigure the wire interface circuit, including calibrating the wire interface circuit for a second operating frequency, after the serial data link is idled. The instructions may cause the processing circuit 1202 to calibrate the wire interface circuit using a bus calibration procedure defined by the C-PHY or D-PHY protocol when transmitting the second datagram.

[0095]

[0106] 13 is a flowchart 1300 of a method for adapting to changes in the operating frequency of a serial data link in a display driver. The method may be implemented in a display subsystem configured for ping-pong DSI PHY switching according to some aspects of the present disclosure. In one example, a mobile communication device includes a serial data link operating according to a C-PHY or D-PHY protocol. The method may be performed using a controller or other processor of the display driver.

[0096]

[0107] In the illustrated method, at block 1302, the controller may receive first datagrams from a serial data link through the PHY when the PHY is configured for a first operating frequency. At block 1304, the controller may receive configuration information from at least one of the first datagrams. The configuration information may identify a second operating frequency. At block 1306, the method may be paused until the serial data link becomes idle. The serial data link becoming idle may serve as a trigger for the controller to update the configuration of the PHY and associated circuits and modules. Other triggers may be used, including, for example, explicit commands and timers.

[0097]

[0108] At block 1308, the controller may reconfigure the PHY for a second operating frequency when the serial data link next enters an idle state. At block 1310, the controller may receive a second datagram from the serial data link when the PHY is configured for the second operating frequency. In one example, the PHY is configured according to the MIPI Alliance's DSI specification.

[0098]

[0109] In some examples, configuring the PHY includes configuring a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency and calibrating the clock generation circuit. The controller may reconfigure the wire interface circuit and calibrate the wire interface circuit for the second operating frequency after the serial data link is idled. The controller may calibrate the wire interface circuit using a bus calibration procedure defined by the C-PHY or D-PHY protocol when receiving the second datagram.

[0099]

[0110] 14 illustrates a second example of a hardware implementation for an apparatus 1400 employing a processing circuit 1402. The processing circuit typically includes one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines, generally represented by a processor 1416. The processing circuit 1402 may be implemented using a bus architecture, generally represented by a bus 1420. The bus 1420 may include any number of interconnected buses and bridges, depending on the particular application and overall design constraints of the processing circuit 1402. The bus 1420 links together various circuits, including one or more processors 1416, modules or circuits 1404, 1406, and 1408, and a processor-readable storage medium 1418. A bus interface circuit and / or module 1414 may be provided to support communication over a serial data link 1412. Bus 1420 may also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further.

[0100]

[0111] The processor 1416 may be responsible for general processing, including executing software, codes, and / or instructions stored in the processor-readable storage medium 1418. The processor-readable storage medium 1418 may include a non-transitory storage medium. The software, when executed by the processor 1416, causes the processing circuit 1402 to perform the various functions described above for any particular apparatus. The processor-readable storage medium may be used to store data that is manipulated by the processor 1416 when executing the software. The processing circuit 1402 further includes at least one of modules 1404, 1406, and 1408. The modules 1404, 1406, and 1408 may be software modules residing / stored in the processor-readable storage medium 1418 and operating within the processor 1416, one or more hardware modules coupled to the processor 1416, or some combination thereof. Modules 1404, 1406, and 1408 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0101]

[0112] In one configuration, apparatus 1400 includes a module and / or circuitry 1404 adapted to detect triggers for implementing configuration changes, a module and / or circuitry 1406 adapted to configure the PHY circuitry for various possible operating frequencies, and a module and / or circuitry 1408 adapted to generate, configure, manage, and calibrate one or more clock signals used by the PHY at the desired operating frequencies.

[0102]

[0113] In one example, apparatus 1400 is configured to operate as a DDIC having bus interface circuitry and / or modules 1414 configured according to the MIPI Alliance DSI specification and a controller. The controller may be configured to: cause data to be extracted from first datagrams received from a serial data link through the PHY when the PHY is configured for a first operating frequency; receive configuration information identifying a second operating frequency from at least one of the first datagrams; reconfigure the PHY for the second operating frequency when the serial data link next enters an idle state; and cause data to be extracted from second datagrams received from the serial data link when the PHY is configured for the second operating frequency.

[0103]

[0114] In one example, the controller is further configured to configure the clock generation circuit to provide one or more clock signals corresponding to the second operating frequency, and to calibrate the clock generation circuit.

[0104]

[0115] In some examples, the PHY is coupled to a wire interface circuit that is coupled to a serial data link. The controller may be further configured to reconfigure the wire interface circuit and calibrate the wire interface circuit for a second operating frequency after the serial data link is idled. The controller may be further configured to calibrate the wire interface circuit using a bus calibration procedure defined by the C-PHY or D-PHY protocol when transmitting the second datagram.

[0105]

[0116] The processor-readable storage medium 1418 may include instructions to cause the processing circuit 1402 to receive a measurement of a reference signal representative of RF signal quality at the mobile communication device, determine whether the measurement of the reference signal indicates that the RF signal quality is below a minimum RF signal quality level, and reduce a signal strength of a transmitter coupled to a serial bus provided in the mobile communication device when the RF signal quality falls below the minimum RF signal quality level.

[0106]

[0117] The processor-readable storage medium 1418 may include instructions to cause the processing circuit 1402 to receive, through the PHY, first datagrams from the serial data link when the PHY is configured for a first operating frequency, receive configuration information identifying a second operating frequency from at least one of the first datagrams, reconfigure the PHY for the second operating frequency when the serial data link next enters an idle state, and receive a second datagram from the serial data link when the PHY is configured for the second operating frequency. In some examples, the PHY is configured according to the MIPI Alliance's DSI specification.

[0107]

[0118] In some examples, the instructions for configuring the PHY include instructions for configuring the clock generation circuit to provide one or more clock signals corresponding to the second operating frequency and for calibrating the clock generation circuit. In some examples, the processor-readable storage medium 1418 includes instructions for causing the processing circuit 1402 to reconfigure the wire interface circuit and calibrate the wire interface circuit for the second operating frequency after the serial data link is idled. In some examples, the processor-readable storage medium 1418 includes instructions for causing the processing circuit 1402 to calibrate the wire interface circuit using a bus calibration procedure defined by the C-PHY or D-PHY protocol upon receiving the second datagram.

[0108]

[0119] Several implementations are described in the following numbered clauses. Clause 1. A display subsystem comprising: a first physical layer interface configured in accordance with the Display Serial Interface (DSI) specification of the Mobile Industry Processor Interface (MIPI) Alliance; a second physical layer interface configured in accordance with the DSI specification of the MIPI Alliance; and a switch configured to selectively couple a serial data link to the first physical layer interface or the second physical layer interface as directed by a controller, wherein the controller causes a first datagram to be transmitted over the serial data link using the first physical layer interface and a first operating frequency; and while the first datagram is being transmitted over the serial data link, causes a second operating frequency different from the first operating frequency. a display subsystem configured to: configure a second physical layer interface for a second operating frequency; cause the first physical layer interface to transmit configuration information over the serial data link using the first operating frequency after the second physical layer interface is configured for the second operating frequency; cause the first physical layer interface to terminate transmission over the serial data link after the configuration information has been transmitted, thereby idling the serial data link; cause the switch to decouple the first physical layer interface from the serial data link; cause the switch to couple the second physical layer interface to the serial data link; and cause a second datagram to be transmitted over the serial data link using the second physical layer interface and the second operating frequency. Clause 2. The display subsystem of clause 1, further comprising: a display driver coupled to the serial data link, the display driver responsive to the configuration information and configured to reconfigure a physical layer interface of the display driver from the first operating frequency to the second operating frequency after the serial data link is idled. Clause 3. The display subsystem of clause 1 or clause 2, wherein the controller is further configured to configure the clock generation circuit to provide one or more clock signals corresponding to a second operating frequency and to calibrate the clock generation circuit. Clause 4. A display subsystem according to any of clauses 1 to 3, wherein the switch is coupled to a wire interface circuit that is coupled to a serial data link. Clause 5. The display subsystem of clause 4, wherein the controller is further configured to reconfigure the wire interface circuit and calibrate the wire interface circuit for the second operating frequency after the serial data link is idled. Clause 6. The display subsystem of clause 5, wherein the controller is further configured to calibrate the wire interface circuitry using a bus calibration procedure defined by the C-PHY or D-PHY protocol when transmitting the second datagram. Clause 7. A method for changing an operating frequency in a serial data link, the method comprising: transmitting a first datagram over the serial data link using a first physical layer interface configured for a first operating frequency; configuring a second physical layer interface for a second operating frequency different from the first operating frequency while the first datagram is being transmitted over the serial data link; transmitting configuration information over the serial data link using the first physical layer interface after the second physical layer interface is configured for the second operating frequency; idling the serial data link by terminating transmission over the first physical layer interface after transmitting the configuration information; decoupling the first physical layer interface from the serial data link; coupling the second physical layer interface to the serial data link; and transmitting a second datagram over the serial data link using the second physical layer interface and the second operating frequency. Clause 8. The method of clause 7, wherein the configuration information is configured to cause a display driver coupled to the serial data link to reconfigure a physical layer interface of the display driver from a first operating frequency to a second operating frequency after the serial data link is idled. Clause 9. The method of clause 7 or clause 8, wherein the first physical layer interface and the second physical layer interface are configured in accordance with the Display Serial Interface (DSI) specification of the Mobile Industry Processor Interface (MIPI) Alliance. Clause 10. The method of any of clauses 7 to 9, wherein configuring the second physical layer interface includes configuring a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency, and calibrating the clock generation circuit. Clause 11. The method of any of clauses 7 to 10, further comprising using a switch to isolate the first physical layer interface from the serial data link and couple the second physical layer interface to the serial data link. Clause 12. The method of clause 11, wherein the switch is coupled to a wire interface circuit that is coupled to a serial data link. Clause 13. The method of clause 12, further comprising reconfiguring the wire interface circuitry, including calibrating the wire interface circuitry for the second operating frequency, after the serial data link is idled. Clause 14. The method of clause 13, further comprising calibrating the wire interface circuitry using a bus calibration procedure defined by the C-PHY or D-PHY protocol when transmitting the second datagram. Clause 15. A display driver comprising: a physical layer interface configured in accordance with the Display Serial Interface (DSI) specification of the Mobile Industry Processor Interface (MIPI) Alliance; and a controller, wherein the controller is configured to: cause data to be extracted from first datagrams received from a serial data link through the physical layer interface when the physical layer interface is configured for a first operating frequency; receive configuration information identifying a second operating frequency from at least one of the first datagrams; reconfigure the physical layer interface for the second operating frequency when the serial data link next enters an idle state; and cause data to be extracted from second datagrams received from the serial data link when the physical layer interface is configured for the second operating frequency. Clause 16. A display driver as described in clause 15, wherein the controller is further configured to configure the clock generation circuit to provide one or more clock signals corresponding to a second operating frequency and to calibrate the clock generation circuit. Clause 17. A display driver according to clause 15 or clause 16, wherein the physical layer interface is coupled to a wire interface circuit which is coupled to a serial data link. Clause 18. The display driver of clause 17, wherein the controller is further configured to reconfigure the wire interface circuit and calibrate the wire interface circuit for the second operating frequency after the serial data link is idled. Clause 19. The display driver of clause 18, wherein the controller is further configured to calibrate the wire interface circuitry using a bus calibration procedure defined by the C-PHY or D-PHY protocol upon receiving the second datagram. Clause 20. A method for changing an operating frequency in a serial data link, the method comprising: receiving first datagrams from the serial data link through a physical layer interface when the physical layer interface is configured for a first operating frequency; receiving configuration information from at least one of the first datagrams that identifies a second operating frequency; reconfiguring the physical layer interface for the second operating frequency when the serial data link next enters an idle state; and receiving a second datagram from the serial data link when the physical layer interface is configured for the second operating frequency. Clause 21. The method of clause 20, wherein the physical layer interface is configured in accordance with the Display Serial Interface (DSI) specification of the Mobile Industry Processor Interface (MIPI) Alliance. Clause 22. The method of clause 20 or clause 21, wherein reconfiguring the physical layer interface includes configuring a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency and calibrating the clock generation circuit. Clause 23. The method of any of clauses 20 to 22, further comprising reconfiguring the wire interface circuitry after the serial data link is idled and calibrating the wire interface circuitry for the second operating frequency. Clause 24. The method of clause 23, further comprising calibrating the wire interface circuitry using a bus calibration procedure defined by the C-PHY or D-PHY protocol upon receiving the second datagram.

[0109]

[0120] It is understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of sample approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged. Further, some steps may be combined or omitted. The accompanying method claims present elements of the various steps in a sample order, and are not intended to be limited to the specific order or hierarchy presented.

[0110]

[0121] The foregoing description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Accordingly, the claims are not intended to be limited to the aspects set forth herein but are to be accorded the widest scope consistent with the language of the claims, and references to elements in the singular shall mean "one or more," not "one and only," unless expressly stated otherwise. The term "some" refers to one or more, unless expressly stated otherwise. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later become known to those skilled in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Additionally, nothing disclosed herein is intended to be publicly disclosed, regardless of whether such disclosure is expressly recited in the claims. No element of a claim should be construed as a means-plus-function unless the element is expressly recited using the phrase "means for." The inventions described in the claims of the present application as originally filed are set forth below. [C1] a first physical layer interface configured in accordance with the Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) specification; a second physical layer interface configured in accordance with the MIPI Alliance DSI specification; a switch configured to selectively couple a serial data link to the first physical layer interface or the second physical layer interface as directed by a controller; The controller: causing a first datagram to be transmitted over the serial data link using the first physical layer interface and a first operating frequency; configuring the second physical layer interface for a second operating frequency different from the first operating frequency while the first datagram is being transmitted over the serial data link; causing the first physical layer interface to transmit configuration information over the serial data link using the first operating frequency after the second physical layer interface is configured for the second operating frequency; After the configuration information is transmitted, causing the first physical layer interface to terminate transmission over the serial data link, thereby idling the serial data link; causing the switch to isolate the first physical layer interface from the serial data link; causing the switch to couple the second physical layer interface to the serial data link; a display subsystem configured to cause a second datagram to be transmitted over the serial data link using the second physical layer interface and using the second operating frequency. [C2] The display subsystem of C1, further comprising: a display driver coupled to the serial data link, the display driver configured to be responsive to the configuration information and to reconfigure a physical layer interface of the display driver from the first operating frequency to the second operating frequency after the serial data link is idled. [C3] The controller: configuring a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency; The display subsystem of C1, further configured to calibrate the clock generation circuit. [C4] The display subsystem of C1, wherein the switch is coupled to a wire interface circuit that is coupled to the serial data link. [C5] The controller: reconfiguring the wire interface circuit after the serial data link is idled; The display subsystem of C4, further configured to calibrate the wire interface circuitry for the second operating frequency. [C6] The controller: The display subsystem of C5, further configured to calibrate the wire interface circuitry using a bus calibration procedure defined by a C-PHY or D-PHY protocol when transmitting the second datagram. [C7] 1. A method for changing an operating frequency in a serial data link, comprising: transmitting a first datagram over the serial data link using a first physical layer interface configured for a first operating frequency; configuring a second physical layer interface for a second operating frequency different from the first operating frequency while the first datagram is being transmitted over the serial data link; transmitting configuration information over the serial data link using the first physical layer interface after the second physical layer interface is configured for the second operating frequency; After transmitting the configuration information, terminating transmission over the first physical layer interface, thereby idling the serial data link; decoupling the first physical layer interface from the serial data link; coupling the second physical layer interface to the serial data link; and transmitting a second datagram over the serial data link using the second physical layer interface and the second operating frequency. A method comprising: [C8] The method of C7, wherein the configuration information is configured to cause a display driver coupled to the serial data link to reconfigure a physical layer interface of the display driver from the first operating frequency to the second operating frequency after the serial data link is idled. [C9] The method of C7, wherein the first physical layer interface and the second physical layer interface are configured according to the Display Serial Interface (DSI) specification of the Mobile Industry Processor Interface (MIPI) Alliance. [C10] configuring the second physical layer interface; configuring a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency; calibrating the clock generation circuit; The method according to C7, comprising: [C11] using a switch to isolate the first physical layer interface from the serial data link and to couple the second physical layer interface to the serial data link; The method of C7, further comprising: [C12] The method of C11, wherein the switch is coupled to a wire interface circuit that is coupled to the serial data link. [C13] reconfiguring the wire interface circuit, including calibrating the wire interface circuit for the second operating frequency, after the serial data link is idled. The method of C12, further comprising: [C14] calibrating the wire interface circuitry using a bus calibration procedure defined by a C-PHY or D-PHY protocol when transmitting the second datagram; The method of C13, further comprising: [C15] a physical layer interface configured in accordance with the Mobile Industry Processor Interface (MIPI) Alliance's Display Serial Interface (DSI) specification; a display driver comprising: extracting data from a first datagram received from a serial data link through the physical layer interface when the physical layer interface is configured for a first operating frequency; receiving configuration information from at least one of the first datagrams, the configuration information identifying a second operating frequency; reconfiguring the physical layer interface for the second operating frequency when the serial data link next enters an idle state; and causing data to be extracted from a second datagram received from the serial data link when the physical layer interface is configured for the second operating frequency. Display driver. [C16] The controller: configuring a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency; The display driver of C15, further configured to calibrate the clock generation circuit. [C17] The display driver of C15, wherein the physical layer interface is coupled to a wire interface circuit that is coupled to the serial data link. [C18] The controller: reconfiguring the wire interface circuit after the serial data link is idled; The display driver of C17, further configured to calibrate the wire interface circuitry for the second operating frequency. [C19] The controller: 19. The display driver of claim 18, further configured to calibrate the wire interface circuitry using a bus calibration procedure defined by a C-PHY or D-PHY protocol upon receiving the second datagram. [C20] 1. A method for changing an operating frequency in a serial data link, comprising: receiving a first datagram from the serial data link through a physical layer interface when the physical layer interface is configured for a first operating frequency; receiving configuration information from at least one of the first datagrams, the configuration information identifying a second operating frequency; reconfiguring the physical layer interface for the second operating frequency when the serial data link next enters an idle state; receiving a second datagram from the serial data link when the physical layer interface is configured for the second operating frequency; A method comprising: [C21] The method of C20, wherein the physical layer interface is configured according to the Display Serial Interface (DSI) specification of the Mobile Industry Processor Interface (MIPI) Alliance. [C22] reconfiguring the physical layer interface; configuring a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency; calibrating the clock generation circuit; The method according to C20, comprising: [C23] reconfiguring a wire interface circuit after the serial data link is idled; The method of C20, further comprising: calibrating the wire interface circuit for the second operating frequency. [C24] calibrating the wire interface circuitry using a bus calibration procedure defined by a C-PHY or D-PHY protocol upon receiving the second datagram. The method of C23, further comprising:

Claims

1. a first physical layer interface configured in accordance with the Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) specification; a second physical layer interface configured in accordance with the MIPI Alliance DSI specification; a switch configured to selectively couple a serial data link to the first physical layer interface or the second physical layer interface as directed by a controller; The controller: causing a first datagram to be transmitted over the serial data link using the first physical layer interface and using a first operating frequency; configuring the second physical layer interface for a second operating frequency different from the first operating frequency while the first datagram is being transmitted over the serial data link; causing the first physical layer interface to transmit configuration information over the serial data link using the first operating frequency after the second physical layer interface is configured for the second operating frequency; After the configuration information is transmitted, causing the first physical layer interface to terminate transmission over the serial data link, thereby idling the serial data link; causing the switch to isolate the first physical layer interface from the serial data link; causing the switch to couple the second physical layer interface to the serial data link; a display subsystem configured to cause a second datagram to be transmitted over the serial data link using the second physical layer interface and using the second operating frequency.

2. 2. The display subsystem of claim 1, further comprising: a display driver coupled to the serial data link, the display driver responsive to the configuration information and configured to reconfigure a physical layer interface of the display driver from the first operating frequency to the second operating frequency after the serial data link is idled.

3. The controller: configuring a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency; The display subsystem of claim 1 further configured to calibrate the clock generation circuitry.

4. 2. The display subsystem of claim 1, wherein the switch is coupled to a wire interface circuit that is coupled to the serial data link.

5. The controller: reconfiguring the wire interface circuit after the serial data link is idled; The display subsystem of claim 4 , further configured to calibrate the wire interface circuitry for the second operating frequency.

6. The controller:

6. The display subsystem of claim 5, further configured to calibrate the wire interface circuitry using a bus calibration procedure defined by a C-PHY or D-PHY protocol when transmitting the second datagram.

7. 1. A method for changing an operating frequency in a serial data link, comprising: transmitting a first datagram over the serial data link using a first physical layer interface configured for a first operating frequency; configuring a second physical layer interface for a second operating frequency different from the first operating frequency while the first datagram is being transmitted over the serial data link; transmitting configuration information over the serial data link using the first physical layer interface after the second physical layer interface is configured for the second operating frequency; After transmitting the configuration information, terminating transmission over the first physical layer interface, thereby idling the serial data link; isolating the first physical layer interface from the serial data link; coupling the second physical layer interface to the serial data link; transmitting a second datagram over the serial data link using the second physical layer interface and using the second operating frequency; A method comprising:

8. 8. The method of claim 7, wherein the configuration information is configured to cause a display driver coupled to the serial data link to reconfigure a physical layer interface of the display driver from the first operating frequency to the second operating frequency after the serial data link is idled.

9. 8. The method of claim 7, wherein the first physical layer interface and the second physical layer interface are configured according to the Display Serial Interface (DSI) specification of the Mobile Industry Processor Interface (MIPI) Alliance.

10. Configuring the second physical layer interface comprises: configuring a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency; calibrating the clock generation circuit; The method of claim 7, comprising:

11. using a switch to isolate the first physical layer interface from the serial data link and to couple the second physical layer interface to the serial data link; The method of claim 7 further comprising:

12. The method of claim 11 , wherein the switch is coupled to a wire interface circuit that is coupled to the serial data link.

13. reconfiguring the wire interface circuit, including calibrating the wire interface circuit for the second operating frequency, after the serial data link is idled. The method of claim 12 further comprising:

14. calibrating the wire interface circuitry using a bus calibration procedure defined by a C-PHY or D-PHY protocol when transmitting the second datagram; The method of claim 13 further comprising:

15. a physical layer interface configured in accordance with the Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) specification; a display driver comprising: extracting data from a first datagram received from a serial data link through the physical layer interface when the physical layer interface is configured for a first operating frequency; receiving configuration information from at least one of the first datagrams, the configuration information identifying a second operating frequency; reconfiguring the physical layer interface for the second operating frequency when the serial data link next enters an idle state; and causing data to be extracted from a second datagram received from the serial data link when the physical layer interface is configured for the second operating frequency. Display driver.

16. The controller: configuring a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency; 16. The display driver of claim 15, further configured to calibrate the clock generation circuit.

17. 16. The display driver of claim 15, wherein the physical layer interface is coupled to a wire interface circuit that is coupled to the serial data link.

18. The controller: reconfiguring the wire interface circuit after the serial data link is idled; 20. The display driver of claim 17, further configured to calibrate the wire interface circuitry for the second operating frequency.

19. The controller:

20. The display driver of claim 18, further configured to calibrate the wire interface circuitry using a bus calibration procedure defined by a C-PHY or D-PHY protocol upon receiving the second datagram.

20. 1. A method for changing an operating frequency in a serial data link, comprising: receiving a first datagram from the serial data link through a physical layer interface when the physical layer interface is configured for a first operating frequency; receiving configuration information from at least one of the first datagrams, the configuration information identifying a second operating frequency; reconfiguring the physical layer interface for the second operating frequency when the serial data link next enters an idle state; receiving a second datagram from the serial data link when the physical layer interface is configured for the second operating frequency; wherein the physical layer interface is configured in accordance with the Display Serial Interface (DSI) specification of the Mobile Industry Processor Interface (MIPI) Alliance.

21. reconfiguring the physical layer interface; configuring a clock generation circuit to provide one or more clock signals corresponding to the second operating frequency; calibrating the clock generation circuit; 21. The method of claim 20, comprising:

22. reconfiguring a wire interface circuit after the serial data link is idled; calibrating the wire interface circuit for the second operating frequency; 21. The method of claim 20, further comprising:

23. calibrating the wire interface circuitry using a bus calibration procedure defined by the C-PHY or D-PHY protocol upon receiving the second datagram.

23. The method of claim 22, further comprising:

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