Analog-to-digital converter and interstage gain calibration method

Abstract

The present application provides an analog-to-digital converter including a sample-and-hold circuit configured to periodically sample and hold an analog input signal; a first level sub-analog-to-digital converter configured to convert the analog input signal into a first digital signal, convert the first digital signal into a first voltage signal, and perform differential processing between the analog input signal and the first voltage signal to obtain a second voltage signal; a first processing circuit configured to clock-synchronize and periodically delay the first digital signal to obtain a second digital signal; an inter-stage amplifier realized using an open-loop structure and configured to amplify and process the second voltage signal to obtain a third voltage signal; a second level sub-analog-to-digital converter configured to convert the third voltage signal into a third digital signal; a second processing circuit configured to clock-synchronize the third digital signal to obtain a fourth digital signal; and an adder configured to merge and add the second digital signal, which is a higher-order codeword, and the fourth digital signal, which is a lower-order codeword, to obtain a digital output signal, and a method for calibrating the inter-stage gain.

Description

[Technical Field]

[0001] This application claims priority from Chinese Patent Application No. 202111189751.9 filed on October 12, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] The present application relates to the field of analog-to-digital conversion technology, and more particularly to an analog-to-digital converter and a method for calibrating interstage gain. [Background technology]

[0003] As the manufacturing process of integrated circuits advances to the nanoscale, the operating speed of analog-to-digital converters is becoming increasingly faster. The interstage amplifiers in pipelined analog-to-digital converters or hybrid pipelined-successive approximation analog-to-digital converters are generally implemented using switched-capacitor closed-loop amplifier structures, and the interstage gains are calibrated according to corresponding calibration circuits. However, at high operating speeds, the design requirements for the bandwidth of the operational amplifiers in the closed-loop amplifier structures are very high, and the power consumption is large, making it difficult to implement the closed-loop amplifier structures at high operating speeds. Summary of the Invention [Means for solving the problem]

[0004] In a first aspect, an embodiment of the present application provides an analog-to-digital converter including: a sample-and-hold circuit configured to periodically sample and hold an analog input signal; a first-level sub-analog-to-digital converter configured to perform a first analog-to-digital conversion of the held analog input signal to obtain a first digital signal, perform digital-to-analog conversion of the first digital signal to obtain a first voltage signal, and perform differential processing between the held analog input signal and the first voltage signal to obtain a second voltage signal; a first processing circuit configured to perform clock synchronization and cyclic delay on the first digital signal to obtain a second digital signal; an interstage amplifier realized using an open-loop structure and configured to amplify and process the second voltage signal to obtain a third voltage signal; a second-level sub-analog-to-digital converter configured to perform a second analog-to-digital conversion of the third voltage signal to obtain a third digital signal; a second processing circuit configured to clock synchronize the third digital signal to obtain a fourth digital signal; and an adder configured to merge and add the second digital signal, which is a most significant codeword, and the fourth digital signal, which is a least significant codeword, to obtain a digital output signal.

[0005] In a second aspect, the present embodiment is applied to the foreground calibration stage of the analog-to-digital converter, and the gain setting circuit adjusts the inter-stage gain of the inter-stage amplifier based on the current gain control code, and the current gain control code is between 0 and 2. qan output detection circuit determining to continue inter-stage gain calibration based on a digital output signal corresponding to the current gain control code and a digital output signal corresponding to a previous gain control code, and adding 1 to the current gain control code to obtain a next gain control code, and the gain setting circuit adjusting the inter-stage gain of the inter-stage amplifier based on the next gain control code; the output detection circuit determining to stop inter-stage gain calibration based on a digital output signal corresponding to the current gain control code and a digital output signal corresponding to a previous gain control code, and setting an optimal gain control code and outputting it to the gain setting circuit, and the gain setting circuit adjusting the inter-stage gain of the inter-stage amplifier based on the optimal gain control code, and the optimal gain control code is one of the current gain control code and the previous gain control code. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a circuit schematic diagram of an analog-to-digital converter according to an embodiment of the present invention; [Figure 2] 1 is a circuit schematic diagram of an analog-to-digital converter according to an embodiment of the present invention when an analog input signal is a differential signal. [Figure 3] 1 is a circuit schematic diagram of an interstage amplifier according to an embodiment of the present invention; [Figure 4] 1 is a circuit schematic diagram of an interstage amplifier according to an embodiment of the present invention when an analog input signal is a differential signal. [Figure 5] 10 is a schematic diagram illustrating a digital output signal obtained by merging and adding a second digital signal, which is a higher-order codeword, and a fourth digital signal, which is a lower-order codeword, according to an embodiment of the present invention. FIG. [Figure 6] 1 is a flowchart of a method for calibrating interstage gain according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0007] In order to enable those skilled in the art to better understand the technical solution of the present application, the analog-to-digital converter and the inter-stage gain calibration method provided by the present application will be described in detail below in conjunction with the accompanying drawings.

[0008]

[0023] The present disclosure will be described in detail below with reference to the accompanying drawings, in which:

[0024] The present disclosure will be described in detail with reference to the accompanying drawings, in which:

[0025] The present disclosure will be described in detail with reference to the accompanying drawings, in which:

[0026] The present disclosure will be described in detail with reference to the accompanying drawings, in which:

[0027] The present disclosure will be described in detail with reference to the accompanying drawings, in which:

[0028] The present disclosure will be described in detail with reference to the accompanying drawings, in which:

[0029] The present disclosure will be described in detail with reference to the accompanying drawings, in which:

[0030] The present disclosure will be described in detail with reference to the accompanying drawings, in which:

[0031] The present disclosure will be described in detail with reference to the accompanying drawings, in which:

[0009] Unless contradictory, each embodiment and each feature in each embodiment in the present application can be combined with each other.

[0010] As used herein, the term "and / or" includes any and all combinations of at least one of the associated listed items.

[0011] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to limit the scope of the present application. In this specification, the singular forms "a," "an," and "the" are intended to include the plural, unless the context clearly dictates otherwise. Furthermore, when the terms "comprising" and / or "consisting of" are used in this specification, they indicate the presence of certain features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or possible addition of at least one other feature, whole, step, operation, element, component, and / or group thereof.

[0012] Unless otherwise specified, all terms used in this specification (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art. Furthermore, terms defined in commonly used dictionaries should be understood to have the same meaning as in the relevant art and the context of this application, and should not be construed as having an idealized meaning or an overly formal meaning unless expressly limited in this specification.

[0013] FIG. 1 is a circuit diagram of an analog-to-digital converter according to an embodiment of the present invention.

[0014] In a first aspect, referring to FIG. 1 , the present embodiment includes a sample-and-hold circuit 101 configured to periodically sample and hold an analog input signal; a first level sub-analog-to-digital converter 102 configured to perform a first analog-to-digital conversion of the held analog input signal to obtain a first digital signal, perform digital-to-analog conversion of the first digital signal to obtain a first voltage signal, and perform differential processing between the held analog input signal and the first voltage signal to obtain a second voltage signal; and a first processing circuit configured to perform clock synchronization and periodic delay on the first digital signal to obtain a second digital signal. an inter-stage amplifier 104 realized using an open-loop structure and configured to amplify and process the second voltage signal to obtain a third voltage signal; a second level sub-analog-to-digital converter 105 configured to perform a second analog-to-digital conversion of the third voltage signal to obtain a third digital signal; a second processing circuit 106 configured to clock synchronize the third digital signal to obtain a fourth digital signal; and an adder 107 configured to merge and add the second digital signal, which is a high-order code word, and the fourth digital signal, which is a low-order code word, to obtain a digital output signal.

[0015] In the present embodiment, the analog input signal, the first voltage signal, the second voltage signal, and the third voltage signal may be differential signals or non-differential signals. For example, as shown in FIG. 2, the analog input signal is a differential signal V inp1 and V inn1 and the first voltage signal is the differential signal V DACp and V DACn (V DACp and V DACn belongs to the internal signal of the first-level sub-analog-to-digital converter 102 (not shown in FIG. 2), and the second voltage signal is the differential signal V resp and V resn and the third voltage signal is the differential signal Vinp2 and V inn2 and V inp1 and V DACp Taking the difference with V resp and V inn1 and V DACn Take the difference and V resn and the interstage amplifier 104 outputs a residual voltage signal (the residual voltage signal is V resp and V resn The difference signal V inp2 and V inn2 and get the difference.

[0016] In some embodiments, sampling and holding the analog input signal means that after the sample and hold circuit 101 samples the analog input signal, the signal input to the first level sub analog to digital converter 102 remains as the sampled analog input signal.

[0017] In some embodiments, the first-level sub-analog-digital converter 102 digital-to-analog converting the first digital signal to obtain the first voltage signal means that the first-level sub-analog-digital converter 102 controls the digital-to-analog converter inside the first-level sub-analog-digital converter 102 based on the first digital signal to digital-to-analog convert the first digital signal to obtain the first voltage signal.

[0018] In some embodiments, as shown in FIG. 3, the inter-stage amplifier 104 includes a transconductance unit and a resistor string, the input terminal of the transconductance unit is connected to the output terminal of the first-level sub-analog-to-digital converter 102 that outputs a second voltage signal, the output terminal of the transconductance unit is connected to the input terminal of the second-level sub-analog-to-digital converter 105, and the output terminal of the transconductance unit is connected to ground via the resistor string, or to a power supply or a common-mode DC level.

[0019] In some embodiments, a transconductance unit refers to a circuit capable of converting an input voltage signal into a current signal, and the transconductance unit may include transistors and other passive elements. For example, the transconductance unit may include a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and a current source, where the gates of the first MOS transistor and the second MOS transistor are input terminals of the transconductance unit, the drains of the first MOS transistor and the second MOS transistor are output terminals of the transconductance unit, and the sources of the first MOS transistor and the second MOS transistor are connected to ground via the current source; or the transconductance unit may include a first transistor, a second transistor, and a current source, where the bases of the first transistor and the second transistor are input terminals of the transconductance unit, the collectors of the first transistor and the second transistor are output terminals of the transconductance unit, and the emitters of the first transistor and the second transistor are connected to ground via the current source.

[0020] In some embodiments, the resistor string may be two or more resistors connected in series, two or more resistors connected in parallel, or two or more resistors mixed (including series and parallel). The resistors in the resistor string may be variable resistors, resistors connected in series with switches, or a configuration in which the resistance value of the resistor string can be arbitrarily changed.

[0021] In some embodiments, when the analog input signal, the first voltage signal, the second voltage signal, and the third voltage signal are all differential signals, the inter-stage amplifier 104 includes two input terminals, two output terminals, two resistor strings, and a transconductance unit, and as shown in FIG. 4, each output terminal of the inter-stage amplifier 104 is grounded by a resistor string, specifically, the first output terminal is grounded by the first resistor string, and the second output terminal is grounded by the second resistor string.

[0022] The interstage amplifier 104 in this embodiment is implemented using an open-loop structure, and the interstage gain is adjusted by adjusting the transconductance unit and the resistor string. Therefore, the load on the circuit preceding the interstage amplifier 104 is only the input capacitance of the interstage amplifier 104 itself, which is advantageous for low power consumption design and is more suitable for use in analog-to-digital converters with higher operating speeds.

[0023] In this embodiment, the purpose of performing clock synchronization and period delay on the first digital signal and clock synchronization on the third digital signal is to ensure that the second digital signal and the fourth digital signal can be output at the same clock tact, so that the adder 107 can merge and add the second digital signal, which is the upper code word, and the fourth digital signal, which is the lower code word, to obtain a digital output signal.

[0024] In some embodiments, the adder 107 is specifically configured to add n-1 zeros to the end of the second digital signal, and add the zero-paused second digital signal to the fourth digital signal to obtain the digital output signal, where n is the number of bits of the fourth digital signal. For example, as shown in FIG. 5, o1 <m:1>where m is an integer equal to or greater than 2, m is the number of bits of the second digital signal, and the fourth digital signal is D o2 <n:1>Assuming that n is an integer equal to or greater than 3, the final digital output signal D is obtained by adding the last bit of the second digital signal to the first bit of the fourth digital signal, which may generate a carry. out <m+n:1> is m+n bits, not m+n-1 bits, so there is one redundant bit.

[0025] In some embodiments, the analog-to-digital converter generates a gain control code GAIN <q:1>to a gain setting circuit 109; and a gain control code GAIN <q:1>and a gain setting circuit 109 configured to adjust the inter-stage gain of the inter-stage amplifier 104 based on

[0026] In some embodiments, the gain setting circuit 109 is configured to receive a gain control code GAIN <q:1>The interstage gain is adjusted by adjusting the equivalent transconductance of the transconductance unit and the resistance value of the resistor string based on the above equation. Specifically, G=g m R out , g m is the equivalent transconductance of the transconductance unit, and R out is the resistance of the resistor string, and G is the interstage gain.

[0027] In the present embodiment, the interstage gain G may be set to correspond to the gain control code, for example, set so that the interstage gain G increases as the gain control code increases. The analog-to-digital converter of the present embodiment may be an analog-to-digital converter with a high-speed pipeline structure, or may be an analog-to-digital converter with a mixed pipeline-successive approximation structure.

[0028] In some embodiments, the output detection circuit 108 and the gain setting circuit 109 can employ the inter-stage gain calibration method described in the embodiments of the present application to realize foreground calibration of the inter-stage gain of the analog-to-digital converter.

[0029] The analog-to-digital converter according to the present embodiment uses an open-loop structure to easily realize the interstage amplifier. Compared with a switched-capacitor closed-loop amplification structure, the structure of the interstage amplifier in the analog-to-digital converter of the present application is relatively simple, resulting in low circuit complexity and power consumption, and enabling a relatively high operating speed to be achieved under conditions of low power consumption.

[0030] FIG. 6 is a flowchart of a method for calibrating interstage gain according to an embodiment of the present invention.

[0031] In a second aspect, referring to FIG. 6, an embodiment of the present application provides an inter-stage gain calibration method applied to the foreground calibration stage of the analog-to-digital converter, where the foreground calibration stage refers to a gain calibration stage performed before the analog-to-digital converter operates normally, and the inter-stage gain calibration method includes steps 601 to 603.

[0032] In step 601, the gain setting circuit adjusts the interstage gain of the interstage amplifier based on the current gain control code, and the current gain control code is set to 0 to 2. q -1, and q is an integer greater than or equal to 2.

[0033] In some embodiments, the gain setting circuitry includes a gain control code GAIN <q:1>The interstage gain is adjusted by adjusting the equivalent transconductance of the transconductance unit and the resistance value of the resistor string based on the above equation. Specifically, G=g m R out , g m is the equivalent transconductance of the transconductance unit, and R out is the resistance of the resistor string, and G is the interstage gain.

[0034] In the present embodiment, the interstage gain G may be set to correspond to the gain control code. For example, the interstage gain G may be set to increase as the gain control code increases. Specifically, the interstage gain G may be set to increase by a fixed value ΔG every time the gain control code increases by 1.

[0035] In the present embodiment, in order to obtain a good calibration effect, the q value can be set large and the interstage gain can be distributed more densely. In the present embodiment, the ideal value of the interstage gain is set to the gain control code 0 to 2. q It is necessary to set the ideal value of the interstage gain within the gain range corresponding to the gain control code of -1, and it is necessary to set the ideal value of the interstage gain to correspond to the gain control code of the intermediate position as much as possible, and the ideal value of the interstage gain is set within the gain control code of 0 to 2. q If it is set outside the gain interval corresponding to -1, calibration cannot be performed.

[0036] The reference voltage of the first level sub-analog-to-digital converter is V ref1 and the reference voltage of the second-level sub-analog-to-digital converter is V ref2 Assuming that, ideally, the ratio of the voltage range of the first level sub-analog-to-digital converter to the voltage range of the second level sub-analog-to-digital converter is V ref1 / V ref2 The ideal interstage gain of the interstage amplifier is G0=2 m-1 (V ref2 / V ref1 ) and G0 is the ideal value of the interstage gain.

[0037] In step 602, the output detection circuit determines to continue calibrating the inter-stage gain based on the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code, adds 1 to the current gain control code to obtain the next gain control code, and the gain setting circuit adjusts the inter-stage gain of the inter-stage amplifier based on the next gain control code.

[0038] In some embodiments, the digital output signal corresponding to the current gain control code is the digital output signal output from the analog-to-digital converter after the gain setting circuit adjusts the inter-stage gain of the inter-stage amplifier based on the current gain control code, and the digital output signal corresponding to the previous gain control code is the digital output signal output from the analog-to-digital converter after the gain setting circuit adjusts the inter-stage gain of the inter-stage amplifier based on the previous gain control code.

[0039] In some embodiments, the output detection circuit determining to continue the inter-stage gain calibration based on the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code includes: the output detection circuit comparing the digital output signal corresponding to the current gain control code with the digital output signal corresponding to the previous gain control code; the output detection circuit determining that no hopping has occurred between the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code; or the output detection circuit determining that the hopping between the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code is not a hop from a fifth digital signal to a sixth digital signal; wherein the (m+n-1)th bit and the (n-1)th bit in the fifth digital signal are 1, and the remainder are 0; and the (m+n-1)th bit and the (n-2)th to (1)th bits in the sixth digital signal are 1, and the remainder are 0,

[0040] In step 603, the output detection circuit determines to stop the inter-stage gain calibration based on the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code, sets an optimal gain control code, and outputs it to the gain setting circuit, which adjusts the inter-stage gain of the inter-stage amplifier based on the optimal gain control code, where the optimal gain control code is one of the current gain control code or the previous gain control code.

[0041] In some embodiments, the output detection circuit determining to stop the inter-stage gain calibration based on the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code includes: the output detection circuit comparing the digital output signal corresponding to the current gain control code with the digital output signal corresponding to the previous gain control code; the output detection circuit determining that the hopping between the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code is from a fifth digital signal to a sixth digital signal; the (m+n-1)th bit and the (n-1)th bit in the fifth digital signal are 1, and the rest are 0; the (m+n-1)th bit and the (n-2)th bit to the first bit in the sixth digital signal are 1, and the rest are 0, wherein m is the number of bits in the second digital signal, and n is the number of bits in the fourth digital signal.

[0042] In some embodiments, the output detection circuit hardening the optimal gain control code and outputting it to the gain setting circuit means that after the output detection circuit outputs the optimal gain control code to the gain setting circuit, the output detection circuit no longer adjusts the gain control code output to the gain setting circuit based on the digital output signal.

[0043] In some embodiments, the analog input signal is V CM +V small / 2 and V CM -V small / 2, and V CM is the input common-mode voltage of the analog-to-digital converter, and V small is a small positive voltage, 0 <V small < <V ref1 / 2 m If , the optimal gain control code is the previous gain control code, -V ref1 / 2 m < <V small <0, the optimal gain control code is the current gain control code, and V ref1 / 2 m is the voltage corresponding to the least significant bit of the first-level sub-analog-to-digital converter.

[0044] The reason why the optimum gain control code is located at the hopping point between the fifth and sixth digital signals will be explained below.

[0045] The reference voltage of the first level sub-analog-to-digital converter is V ref1 and the reference voltage of the second-level sub-analog-to-digital converter is V ref2 Then, the voltage corresponding to the least significant bit (LSB) of the first level sub-analog-to-digital converter is V ref1 / 2 m and the voltage corresponding to the LSB of the second level sub-analog-to-digital converter is V ref2 / 2 n is.

[0046] The input common mode voltage of the analog-to-digital converter is V CM and the output common-mode voltage of the first-level sub-analog-to-digital converter is V CM1O and the output common-mode voltage of the second-level sub-analog-to-digital converter is V CM2I Assume that:

[0047] The analog input signal is the differential signal V inp1 and V inn1 The specific values ​​are V CM +V small / 2 and V CM -V small / 2, and V CM is the input common-mode voltage of the analog-to-digital converter, and V small The second voltage signal is V resp and V resn and is shown as equations (1) and (2).

[0048] V resp =V CM1O +V small / 2-V ref1 / 2 m+1 (1) V resn =V CM1O -V small / 2+V ref1 / 2 m+1 (2)

[0049] The corresponding residual voltage is given by equation (3). V resp -V resn =V small -V ref1 / 2 m (3)

[0050] When the gain control code corresponds to the ideal interstage gain value G0, the third voltage signal is expressed as in equations (4) and (5).

[0051] V inp2 =V CM2I +G0(V small / 2-V ref1 / 2 m+1 ) (4) V inn2 =V CM2I -G0(V small / 2-V ref1 / 2 m+1 ) (5)

[0052] The first digital signal output from the first level sub-analog-to-digital converter is processed by the first processing circuit, and then the second digital signal output is D stg 1=(100...00)₂ (with m - 1 zeros), and after the third digital signal output by the second - level sub - analog - to - digital converter is processed by the second processing circuit, the fourth digital signal output is D stg2 =(01...00)₂ (the (n - 1) - th bit is 1 and the remaining bits are 0), when the digital output signal of the analog - to - digital converter is D out =(010...010...0)₂ (the (m + n - 1) - th bit and the (n - 1) - th bit are 1 and the remaining bits are 0), which is the correct value.

[0053] If the inter - stage gain varies, errors may occur in the digital output signal of the analog - to - digital converter. When it is not ideal, the formula for the inter - stage gain G is given by equation (6).

[0054] G = G₀(1 + a)=2 m-1 (V ref2 / V ref1 )(1 + a) (6) a is the range of change of the gain error.

[0055] The corresponding third - voltage signal is shown in equations (7) and (8).

[0056] V inp2 =V CM2I +G₀(1 + a)(V small / 2 - V ref1 / 2 m+1 ) (7) V inn2 =V CM2I -G₀(1 + a)(V small / 2 - V ref1 / 2 m+1 ) (8)

[0057] As can be seen from analyzing the conversion process of the second - level sub - analog - to - digital converter, when - 1 / 2 n-2 [[ID=**56**]]<a < 0, the digital output signal of the analog - to - digital converter is D out =(010...010...0)₂ (the (m + n - 1) - th bit and the (n - 1) - th bit are 1 and the remaining bits are 0), and when 0 < a < 1 / 2 n-2 It should be noted that there seems to be a formatting issue in the original text where the symbol "**56**" in line is likely a mistake. It should probably be a normal tag or text. If this is a special symbol in the original language that has a specific meaning, more context would be needed for accurate translation.In this case, the digital output signal of the analog-to-digital converter is D out =(010...111...1)₂ (the (m + n - 1)-th bit, the (n - 2)-th to the 1st bits are 1, and the remaining bits are 0).

[0058] Taking specific numerical values as an example, assuming m = n = 4, when -1 / 4 < a < 0, the digital output signal of the analog-to-digital converter is D out =(01000100)₂, and when 0 < a < 1 / 4, the digital output signal of the analog-to-digital converter is D out =(01000011)₂. That is, when a takes 0, that is, when the optimal value of the inter-stage gain appears, it is exactly at the hopping position of the digital output signals corresponding to the above two adjacent gain control codes. As can be seen from this phenomenon, when a = 0, the actual value G of the inter-stage gain is closest to the ideal value G₀, and the values of these two gain control codes are respectively the integer k and k + 1, and 0 < V small << V ref1 / 2 m For the value range of, when the value of the gain control code is k, the corresponding digital output signal is the correct output value D out =(010...010...0)₂ (the (m + n - 1)-th and the (n - 1)-th bits are 1, and the other bits are 0), so the optimal gain control code GAIN is selected as k, and -V ref1 / 2 m << V small <0, for the value range of, when the value of the gain control code is k + 1, the corresponding digital output signal is the correct output value D out =(010...010...0)₂ (the (m + n - 1)-th and the (n - 1)-th bits are 1, and the other bits are 0), so the optimal gain control code GAIN is selected as k + 1.

[0059] The method for calibrating the inter-stage gain according to the embodiments of the present application can obtain the optimal inter-stage gain based on the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code. The algorithm is simple and the complexity is low.

[0060] Those skilled in the art will understand that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above can be implemented as software, firmware, hardware, or any suitable combination thereof. In hardware embodiments, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components. For example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor (e.g., a central processing unit, a digital signal processor, or a microprocessor), as hardware, or as an integrated circuit, such as a dedicated integrated circuit. Such software may be located on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable commands, data structures, program modules, or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and that can be accessed by a computer. Additionally, those skilled in the art will know that communication media typically include computer-readable commands, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism and can include any information delivery media.

[0061] Although exemplary embodiments are disclosed and specific terms are used herein, they are used for general descriptive purposes only and should be construed as such and not for purposes of limitation. It will be apparent to those skilled in the art that, unless expressly indicated otherwise, in some embodiments, features, characteristics, and / or elements described in connection with a particular embodiment can be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will recognize that changes in form and detail may be made without departing from the scope of the present application, as defined by the appended claims.

Claims

1. a sample and hold circuit configured to periodically sample and hold the analog input signal; a first level sub-analog-to-digital converter configured to perform a first analog-to-digital conversion on the held analog input signal to obtain a first digital signal, perform digital-to-analog conversion on the first digital signal to obtain a first voltage signal, and perform differential processing between the held analog input signal and the first voltage signal to obtain a second voltage signal; a first processing circuit configured to perform clock synchronization and period delay on the first digital signal to obtain a second digital signal; an interstage amplifier implemented using an open loop architecture and configured to amplify and process the second voltage signal to obtain a third voltage signal; a second level sub-analog-to-digital converter configured to perform a second analog-to-digital conversion of the third voltage signal to obtain a third digital signal; a second processing circuit configured to clock the third digital signal to obtain a fourth digital signal; an adder configured to merge and add the second digital signal, which is a most significant codeword, and the fourth digital signal, which is a least significant codeword, to obtain a digital output signal; an output detection circuit configured to output a gain control code based on the digital output signal; a gain setting circuit configured to adjust the interstage gain of the interstage amplifier based on the gain control code output from the output detection circuit; the output detection circuit determines whether to continue or stop the interstage gain calibration based on the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code; if it is determined that the interstage gain calibration should be continued, it determines and outputs a next gain control code; if it is determined that the interstage gain calibration should be stopped, it determines and outputs an optimal gain control code; the optimal gain control code is one of the current gain control code or the previous gain control code; Analog-to-digital converter.

2. the analog input signal, the first voltage signal, the second voltage signal, and the third voltage signal are all differential signals; 2. The analog-to-digital converter according to claim 1.

3. the interstage amplifier includes a transconductance unit and a resistor string; The input end of the transconductance unit is connected to the output end of the first level sub-analog-to-digital converter for outputting the second voltage signal, the output end of the transconductance unit is connected to the input end of the second level sub-analog-to-digital converter, and the output end of the transconductance unit is grounded by the resistor string, or connected to a power supply or a common-mode DC level; 2. The analog-to-digital converter according to claim 1.

4. The adder further comprises: padding the second digital signal with n-1 zeros, and adding the zero-padded second digital signal to the fourth digital signal to obtain the digital output signal, where n is the number of bits of the fourth digital signal; 2. The analog-to-digital converter according to claim 1.

5. Applied to a foreground calibration stage of an analog-to-digital converter according to any one of claims 1 to 4, The gain setting circuit adjusts the interstage gain of the interstage amplifier based on the current gain control code, where the current gain control code is between 0 and 2. ｑ -1, and q is an integer of 2 or greater; an output detection circuit determines to continue inter-stage gain calibration according to the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code, and adds 1 to the current gain control code to obtain a next gain control code; and the gain setting circuit adjusts the inter-stage gain of the inter-stage amplifier according to the next gain control code; the output detection circuit determines to stop the inter-stage gain calibration according to the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code, sets an optimal gain control code, and outputs it to the gain setting circuit, the gain setting circuit adjusts the inter-stage gain of the inter-stage amplifier according to the optimal gain control code, and the optimal gain control code is one of the current gain control code or the previous gain control code. Interstage gain calibration method.

6. the output detection circuit determines whether to continue the inter-stage gain calibration based on the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code; the output detection circuit compares the digital output signal corresponding to the current gain control code with the digital output signal corresponding to the previous gain control code; the output detection circuit determines that no hopping occurs between the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code, or the output detection circuit determines that the hopping between the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code is not hopping from a fifth digital signal to a sixth digital signal, wherein the (m+n-1)th bit and the (n-1)th bit in the fifth digital signal are 1 and the rest are 0, and the (m+n-1)th bit and the (n-2)th bit to the first bit in the sixth digital signal are 1 and the rest are 0, where m is the number of bits of the second digital signal and n is the number of bits of the fourth digital signal.

6. The method for calibrating interstage gain according to claim 5.

7. the output detection circuit determines whether to stop the inter-stage gain calibration based on the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code; the output detection circuit compares the digital output signal corresponding to the current gain control code with the digital output signal corresponding to the previous gain control code; the output detection circuit determines that the hopping between the digital output signal corresponding to the current gain control code and the digital output signal corresponding to the previous gain control code is hopping from a fifth digital signal to a sixth digital signal, wherein the (m+n-1)th bit and the (n-1)th bit in the fifth digital signal are 1 and the rest are 0, and the (m+n-1)th bit and the (n-2)th bit to the first bit in the sixth digital signal are 1 and the rest are 0, where m is the number of bits of the second digital signal and n is the number of bits of the fourth digital signal.

6. The method for calibrating interstage gain according to claim 5.

8. The analog input signal is V ＣＭ +V ｓｍａｌｌ / 2 and V ＣＭ -V ｓｍａｌｌ / 2, where V ＣＭ is the input common-mode voltage of the analog-to-digital converter, and V ｓｍａｌｌ is a small positive voltage, 0<V ｓｍａｌｌ <<V ｒｅｆ１ / 2 ｍ the optimal gain control code is the previous gain control code, Here, V ｒｅｆ１ / 2 ｍ is the voltage corresponding to the least significant bit of the first-level sub-analog-to-digital converter; The method for calibrating interstage gain according to any one of claims 5 to 7.

9. The analog input signal is V ＣＭ +V ｓｍａｌｌ / 2 and V ＣＭ -V ｓｍａｌｌ / 2, where V ＣＭ is the input common-mode voltage of the analog-to-digital converter, and V ｓｍａｌｌ is a small positive voltage, -V ｒｅｆ１ / 2 ｍ <<V ｓｍａｌｌ <0, the optimal gain control code is the current gain control code, Here, V ｒｅｆ１ / 2 ｍ is the voltage corresponding to the least significant bit of the first-level sub-analog-to-digital converter; The method for calibrating interstage gain according to any one of claims 6 to 8.

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