METHOD FOR OPERATING A MEMORY SYSTEM AND MEMORY SYSTEM - Patent application

Abstract

The present disclosure provides: METHOD FOR OPERATING A MEMORY SYSTEM, A MEMORY SYSTEM, AND A STORAGE MEDIUM This method providing a logical block management table, the logical block management table including a first sequence corresponding to identities of M first logical blocks, the identities of the M first logical blocks being structured as a ring queue, and the allocation status of the M first logical blocks being managed via the logical block management table; Toto Allocating one first logical block whose allocation state is a first state representing an unallocated state to one second logical block among the N second logical blocks according to the order of the identities of the M first logical blocks in the ring queue, where N is an integer greater than M, and updating the allocation state of the first logical block from the first state to a second state representing an allocated state. Toto , including.

Description

[Technical Field]

[0001] The present disclosure relates to the field of storage technology, including, but not limited to, methods of operating memory systems, memory systems, and storage media. [Background technology]

[0002] The memory system may perform mapping from logical addresses associated with data and recognizable by a host to physical addresses for storing the data in a storage space, and the mapping between the logical addresses and the physical addresses (L2P mapping) may constitute a logical-to-physical (L2P) mapping table. A memory controller of the memory system may manage and allocate logical block resources formed by dividing the storage space, recommend appropriate logical block resources to the host, and cache L2P mapping relationships corresponding to the appropriate logical block resources on the host side, thereby improving performance of the memory system. Please note that the information disclosed in the Background section above is intended merely to enhance understanding of the background of the present disclosure and may therefore include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0003] An object of the present disclosure is to provide a method for operating a memory system, a memory system, and a storage medium.

[0004] Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0005] An embodiment of the present disclosure provides a method for operating a memory system, the method including: providing a logical block management table, the logical block management table including a first sequence corresponding to identities of M first logical blocks, the identities of the M first logical blocks being structured as a ring queue, and allocation states of the M first logical blocks being managed via the logical block management table, where M is an integer greater than or equal to 2; allocating one first logical block, whose allocation state is a first state representing an unallocated state, to one second logical block among N second logical blocks according to the order of the identities of the M first logical blocks in the ring queue, where N is an integer greater than M; and updating the allocation state of the first logical block in the logical block management table from the first state to a second state representing an allocated state.

[0006] In some implementations of the present disclosure, M represents the number of logical blocks supported by the memory controller of the memory system in HPB mode, and the N second logical blocks cover all physical addresses of the memory devices of the memory system.

[0007] In some embodiments of the present disclosure, the method further includes, if a first logical block whose corresponding allocation status is the first state is not present in the ring queue, deallocating a second logical block corresponding to the first logical block initially updated to the second state, and updating the allocation status corresponding to the first logical block initially identified as being in the second state to the first state.

[0008] In some implementations, the ring queue includes a pointer configured to sequentially point to one of the M first logical blocks according to an order of the identities of the M first logical blocks in the ring queue, and the method further includes, in response to the allocation state of the first logical block pointed to by the pointer being the second state, deallocating a second logical block corresponding to the first logical block initially updated to the second state and updating the allocation state corresponding to the first logical block initially identified as being in the second state to the first state.

[0009] In some embodiments, the method further includes assigning the first logical block pointed to by the pointer to one second logical block among the N second logical blocks, and pointing the pointer to the next first logical block according to the order of identities of the M first logical blocks in the ring queue.

[0010] In some embodiments, the method further includes allocating Y first logical blocks having an allocation state in a first state to Y second logical blocks among the N second logical blocks, where Y is an integer greater than 1 and less than M, and updating the allocation states of the Y first logical blocks in the logical block management table from the first state to a third state representing an allocated and pinned state.

[0011] In some embodiments, allocating Y first logical blocks having an allocation state in a first state to Y second logical blocks of the N second logical blocks includes allocating Y consecutive first logical blocks having an allocation state in the ring queue to the Y second logical blocks.

[0012] In some embodiments, the first logical blocks whose allocation status is in the third state are skipped according to the order of the identities of the M first logical blocks in the ring queue.

[0013] In some embodiments, the logical block management table further includes a second sequence corresponding to the identities of the N second logical blocks, and the method further includes updating the identity of the one first logical block or the identity of the one second logical block in the logical block management table.

[0014] In some implementations, the number of elements in the ring queue is the same as the number of first logical blocks, and each element stores the identity and allocation state of the corresponding first logical block.

[0015] In some implementations, the size of the first logical block is the same as the size of the second logical block.

[0016] In some embodiments, the method further includes sending the updated logical block management table to the host.

[0017] In some embodiments, the method further includes transmitting an L2P mapping table corresponding to the one second logical block to the host.

[0018] Some embodiments of the present disclosure provide a memory system including a memory device and a memory controller coupled to the memory device and configured to control the memory device to perform data storage operations. The memory controller includes an interface communicatively coupled to a host, the interface configured to sequentially transmit at least a portion of mapping information of a first logical block management table and a second logical block management table to the host, the first logical block management table and the second logical block management table respectively representing mapping relationships between the first logical blocks and the second logical blocks at different times. Each of the first logical block management table and the second logical block management table includes a first sequence corresponding to identities of M first logical blocks, the identities of the M first logical blocks being organized as a ring queue, and allocation states of the M first logical blocks being managed via the first and second logical block management tables, where M is an integer greater than or equal to 2. The first logical block management table and the second logical block management table respectively include, at different times, identities of K first logical blocks whose allocation states are second states representing allocated states, and identities of K second logical blocks among the N second logical blocks to which the K first logical blocks are allocated, where K is an integer greater than 1 and less than or equal to M, and N is an integer greater than M. To represent an update of the mapping relationship of the second logical block management table to the mapping relationship of the first logical block management table, an initially allocated one first logical block among the K first logical blocks corresponding to the first logical block management table can be updated and allocated to one second logical block among the K second logical blocks of the second logical block management table.

[0019] In some implementations, M represents the number of logical blocks supported by the memory controller of the memory system in HPB mode, and the N second logical blocks cover all physical addresses of the memory devices of the memory system.

[0020] In some embodiments, both the first logical block management table and the second logical block management table include identities of Y first logical blocks whose allocation state is a third state representing an allocated and pinned state, and identities of Y second logical blocks to which the Y first logical blocks are allocated, where Y is an integer greater than 1 and the sum of Y and K is less than or equal to M. The interface is configured to sequentially transmit to the host the K pieces of mapping information of the first logical block management table and the K pieces of mapping information of the second logical block management table to be updated relative to the first logical block management table.

[0021] In some embodiments, the interface is further configured to transmit an L2P mapping table corresponding to the one second logical block to the host.

[0022] Some embodiments of the present disclosure provide a memory system including a memory device and a memory controller coupled to the memory device and configured to control the memory device to perform a data storage operation, the memory controller including an interface communicatively coupled to a host, the interface configured to sequentially transmit a first mapping relationship and a second mapping relationship to the host upon triggering two adjacent updates of a logical block management table, the first mapping relationship being a mapping relationship between the first logical block and the second logical block. P including pieces of mapping information, P The mapping information is included in a first logical block management table, and the second mapping relationship is a relationship between the first logical block and the second logical block. Q including pieces of mapping information, Qthe mapping information is included in a second logical block management table, each of the first logical block management table and the second logical block management table includes a first sequence corresponding to identities of the M first logical blocks, the identities of the M first logical blocks are structured as a ring queue, and allocation states of the M first logical blocks are managed via the logical block management table, M is an integer equal to or greater than 2; P and Q are both integers between 1 and M. To indicate an update of the mapping relationship of the second logical block management table to the mapping relationship of the first logical block management table, one first logical block that is allocated first among the M first logical blocks corresponding to the first logical block management table is updated to the first logical block of the second logical block management table. Q One of the second logical blocks is assigned to be updated.

[0023] In some embodiments, M represents the number of logical blocks supported by the memory controller of the memory system in the HPB mode, the number of second logical blocks is N, where N is an integer greater than M, and the N second logical blocks cover all physical addresses of the memory devices of the memory system.

[0024] In some embodiments, the interface is further configured to transmit an L2P mapping table corresponding to the one second logical block to the host.

[0025] Embodiments of the present disclosure provide a non-transitory computer-readable storage medium having stored thereon computer instructions that, when executed, perform any of the methods for operating a memory system as described above.

[0026] It should be noted that the above general description and the following detailed description are exemplary and explanatory only and are not to be construed as limiting the present disclosure. [Brief explanation of the drawings]

[0027] The drawings herein are incorporated in and constitute a part of this specification, illustrate examples according to the present disclosure, and are used together with this specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some examples of the present disclosure. Other drawings can be obtained based on these drawings without creative efforts. [Figure 1] 1 shows a block diagram of an exemplary system having a memory device, according to some examples of the present disclosure. [Figure 2a] 1 shows a schematic diagram of a memory card integrated with a memory controller and a memory device according to some examples of the present disclosure. [Figure 2b] 1 shows a schematic diagram of an SSD integrated with a memory controller and memory devices, according to some examples of the present disclosure. [Figure 3] 1 shows a schematic diagram of a system including a host and a memory system according to some examples of the present disclosure. [Figure 4] 1 shows a schematic diagram of management performed by a memory system in selectively providing portions of an L2P mapping table to a host. [Figure 5] 1 illustrates a schematic flowchart of a method for operating a memory system according to some examples of the present disclosure. [Figure 6] 1 shows a schematic diagram of a ring queue, according to some examples of the present disclosure. [Figure 7] 1 shows a schematic diagram of a ring queue, according to some examples of the present disclosure. [Figure 8] 1 shows a schematic diagram of a ring queue, according to some examples of the present disclosure. [Figure 9] 1 shows a schematic diagram of a ring queue, according to some examples of the present disclosure. [Figure 10] 1 shows a schematic diagram of a ring queue, according to some examples of the present disclosure. [Figure 11] 1 illustrates a schematic diagram of a logical block management table, according to some examples of the present disclosure. [Figure 12]1 illustrates a schematic diagram of a logical block management table, according to some examples of the present disclosure. [Figure 13] 1 illustrates a schematic diagram of a logical block management table, according to some examples of the present disclosure. [Figure 14] 1 illustrates a schematic diagram of a logical block management table, according to some examples of the present disclosure. [Figure 15] 1 illustrates a schematic diagram of a logical block management table, according to some examples of the present disclosure. [Figure 16] 10 shows a schematic diagram of another logical block management table according to some examples of the present disclosure. [Figure 17] 10 shows a schematic diagram of another logical block management table according to some examples of the present disclosure. [Figure 18] 10 shows a schematic diagram of another logical block management table according to some examples of the present disclosure. [Figure 19] 10 shows a schematic diagram of another logical block management table according to some examples of the present disclosure. [Figure 20] 10 shows a schematic diagram of another logical block management table according to some examples of the present disclosure. [Figure 21] 10 illustrates a schematic flowchart of another method for operating a memory system according to some examples of the present disclosure. [Figure 22] 10 illustrates a schematic flowchart of another method for operating a memory system according to some examples of the present disclosure. [Figure 23] 1 illustrates a schematic diagram of interaction between a host and a memory system, according to some examples of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0028] Examples will now be more fully described with reference to the accompanying drawings. However, examples may be implemented in various forms and should not be construed as limited to the examples set forth herein. Rather, these examples are provided so that this disclosure may be more complete and comprehensive to convey the concepts of the examples. The described features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0029] Furthermore, the drawings are merely schematic diagrams of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings indicate the same or similar parts, and redundant descriptions are omitted. Some of the block diagrams shown in the figures are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different network and / or processor and / or microcontroller devices.

[0030] Furthermore, in the description of this disclosure, "plurality" means at least two, e.g., two, three, etc., unless otherwise specified. The terms "first" and "second" are used for descriptive purposes only and cannot be construed to indicate or imply relative importance or the number of technical features indicated. Thus, a feature defined as "first" or "second" can explicitly or implicitly include one or more of the features.

[0031] FIG. 1 shows a block diagram of an exemplary system 100 having a memory device, according to some examples of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein. As shown in FIG. 1, the system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a system-on-chip (SoC) (e.g., an application processor (AP)) or a processor (e.g., a central processing unit (CPU)) of the electronic device. The host 108 may be configured to transmit data to or receive data from the memory device 104.

[0032] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 106 is designed to operate in a high-duty-cycle environment, such as a solid-state disk (SSD) or embedded multimedia card (eMMC) used as data storage in mobile devices such as smartphones, tablet computers, laptop computers, and enterprise storage arrays.

[0033] The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can be further configured to manage various functions related to data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 106 is further configured to process error correcting codes (ECC) on data read from and written to the memory device 104. The memory controller 106 can further perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., a host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of a variety of interface protocols, such as a USB protocol, a Multimedia Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0034] The memory controller 106 and one or more memory devices 104 may be integrated into various types of storage devices, for example, contained in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged in different types of end electronic products. In the example shown in FIG. 2a, the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association (PCMCIA) card), a CF card, a SmartMedia (SM) card, a Memory Stick, a MultiMediaCard (MMC, Reduced Size (RS)-MMC, MMCmicro), a Secure Digital (SD) card (SD, miniSD, microSD, SD High Capacity (SDHC)), UFS, etc. The memory card 202 may further include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 of FIG. 1). 2b, the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may further include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 of FIG. 1). In some implementations, the storage capacity and / or operating speed of the SSD 206 exceeds the storage capacity and / or operating speed of the memory card 202.

[0035] Figure 3 shows a schematic diagram of a system 300 including a host 310 and a memory system 320, according to some examples. The system 300 of Figure 3 may correspond to the system 100 described above with reference to Figure 1, the host 310 of Figure 3 may correspond to the host 108 described above with reference to Figure 1, and the memory system 320 of Figure 3 may correspond to the memory system 102 described above with reference to Figure 1.

[0036] The memory system 320 may include a memory controller 330 and a memory device 340. The memory controller 330 may include a host interface 332, a processor 334, a cache 336, and a memory device interface 338. The memory controller 330 may receive commands from the host 310 via the host interface 332 and control the operation of the memory device 340 via the processor 334 based on the received commands. The memory controller 330 may communicate with the memory device 340 via the memory device interface 338 to control the operation of the memory device 340. Commands and data included in the commands received by the memory controller 330 via the host interface 332 may be temporarily stored in the cache 336, which may be further configured to temporarily store data read by the memory device 340 for transmission to the host 310. In some examples, the cache 336 may be further configured to cache related information included elsewhere in the memory system 320.

[0037] In some examples, the memory controller 330 can receive data write commands, read commands, etc. from the host 310 via the host interface 332, generate commands for controlling the operation of the memory device 340 using the processor 334 based on the received commands, and send the commands to the memory device 340 via the memory device interface 338. The memory device 340 is configured to receive commands and addresses from the memory controller 330 and access a region of the memory cell array of the memory controller 330 selected by the address. That is, the memory device 340 performs an internal operation on the region selected by the address in response to the command. For example, the memory device 340 can perform program operations, read operations, and erase operations. During a program operation, the memory device 340 can program data into the region selected by the address. During a read operation, the memory device 340 can read data from the region selected by the address. During an erase operation, the memory device 340 can erase data stored in the region selected by the address. In some examples, the memory device 340 can include one or more memory arrays of any type of memory cell, such as non-volatile memory cells, volatile memory cells, or any combination thereof. The memory device 340 may perform write and read operations on a page-by-page basis, and may perform erase operations on a block-by-block basis.

[0038] In some examples, memory system 320 may have a flash translation layer (FTL) in memory controller 330, which may execute one or more command operations, internal operations, etc. For example, memory controller 330 may control memory device 340 in response to a request from host 310. Memory controller 330 may also perform internal operations (e.g., garbage collection operations, read reclamation operations, and wear leveling operations) regardless of a request from host 310. For example, memory controller 330 may execute the above operations by using software to execute the FTL. The FTL may be executed by processor 334 of memory controller 330. Thus, various operations of the FTL may be executed by processor 334.

[0039] An important operation of the FTL includes completing a mapping from the logical address space of the host 310 to the physical address space of the memory device 340, and every time the memory system 320 writes user data to the memory device 340, it records the mapping from the logical address of the user data to the physical address of the user data in the memory device 340. When the host 310 reads user data, the memory system 320 reads the user data from the memory device 340 according to the mapping and then feeds it back to the host 310.

[0040] In some examples, the operations performed by the commands and internal operations may be performed by an FTL, which may perform address mapping operations that convert logical addresses (LA) provided by the host 310 into physical addresses (PA) of the memory device 340. The L2P mapping information may be provided in a logical-to-physical mapping table (i.e., L2P mapping table) that contains logical-to-physical address mapping data. As the memory system 320 expands, the size of the L2P mapping table necessarily increases. Therefore, it takes longer for the memory system 320 to search the L2P mapping table, which may slow down the operating speed of the memory system 320, especially for memory systems 320 not configured with DRAM.

[0041] In some examples, a system 300 including a host 310 and a memory system 320 may have a host memory 312 in the host 310, and at least a portion of the L2P mapping table of the memory system 320 may be synchronized to the host memory 312 so that address mapping operations may be preferentially performed in the host 310 to improve performance of the memory system 320. For example, the host 310 may send L2P mapping information retrieved from the host memory 312 along with a read command to the memory system 320, the host interface 332 may receive the read command and the L2P mapping information, and the processor 334 may send a read command to the memory device 340 to read user data along with a physical address corresponding to the read command. The memory device 340 may read the user data corresponding to the received read command. The read user data may be transferred to the memory controller 330 and from the memory controller 330 to the host 310.

[0042] To synchronize at least a portion of the L2P mapping information of memory system 320 to host memory 312, host 310 and memory system 320 are configured to facilitate this operation, which may be a host performance booster (HPB) operation or a host memory buffer (HMB) operation. If memory system 320 provides all of the L2P mapping tables stored in memory system 320 to host 310, the ability of memory system 320 to facilitate the corresponding operation may be limited, or it may be difficult for host 310 to allocate storage space in host memory 312 to store all of the L2P mapping information, or memory system 320 is limited by other functions. Therefore, instead of providing all of the L2P mapping tables to host 310, memory system 320 may selectively provide a portion of the L2P mapping tables to host 310.

[0043] 4 shows a schematic diagram of the management performed by the memory system 320 when selectively providing a portion of the L2P mapping table to the host 310. The memory controller 330 can perform corresponding coverage representation of the physical address space of the memory device 340 by correspondingly using a logical address space divided into multiple logical blocks. Referring to FIG. 4, the logical address space can cover all physical addresses of the memory device 340, and the logical address space can be evenly divided into multiple second logical blocks 121 such that each logical block has the same size, and the multiple second logical blocks 121 are compiled into a second logical block table 120 (region table). The size of each second logical block 121 can be configured according to actual needs, and the number of second logical blocks 121 is determined according to the size of the memory device 340 and the size of each second logical block 121. For example, referring to FIG. 4, the size of the memory device 340 is 512G, the size of the second logical block 121 is 16M, then the number of the second logical blocks 121 is 32K, and the length of the second logical block table 120 is 32K.

[0044] When selectively providing a portion of the L2P mapping table to the host 310, the memory system 320 selects a portion of the second logical blocks 121 from among the plurality of second logical blocks 121, transfers the L2P mapping table corresponding to the selected portion of the second logical blocks 121 to the host 310, and stores the L2P mapping table in the host memory 312 for the host 310 to access upon a read request. The memory system 320 configures a logical space to support the above-mentioned operation and may divide the logical space into a plurality of first logical blocks, the number of which is less than the number of second logical blocks. Referring to FIG. 4 , the plurality of first logical blocks 111 may be compiled into a first logical block table (subregion table). The size of the first logical block 111 may be set according to actual requirements; for example, the size of the first logical block 111 may be the same as the size of the second logical block 121. For example, referring to FIG. 4, the size of the first logical block 111 may be 16M, and the memory system 320 may configure a logical space of 128G to support the aforementioned operations, where the number of first logical blocks 111 is 8K, the length of the first logical block table 110 is 8K, and the memory system 320 may be configured such that the logical space to support the aforementioned operations is available only to recommend to the host 310 an L2P mapping table corresponding to the 128G physical address space of the memory device 340.

[0045] When selectively providing a portion of the L2P mapping table to the host 310, the memory system 320 can select at least one second logical block 121 that meets the recommended standard from the second logical block table 120, map it with at least one first logical block 111 in the first logical block table 110, and recommend a mapping relationship between the first logical block 111 and the second logical block 121 to the host 310. Upon receiving the mapping relationship between the first logical block 111 and the second logical block 121, the host 310 requests the memory system 320 for an L2P mapping table corresponding to the second logical block 121. In response to this request, the memory system 320 sends the L2P mapping table corresponding to the second logical block 121 to the host 310 and stores it in the host memory 312.

[0046] 4 , when updating a portion of the L2P mapping table selectively provided to the host 310 by the memory system 320, before the update, the first through eighth logical blocks 121 are selected as 8K second logical blocks 121 that meet the recommended standard and are mapped one-to-one with the 8K first logical blocks 111 in the first logical block table 110 to form an 8K mapping relationship 110A between the first logical blocks 111 and the second logical blocks 121. The mapping relationship 110A between the first logical blocks 111 and the second logical blocks 121 is recommended to the host 310, and the L2P mapping tables corresponding to the first through eighth logical blocks 121, respectively, are stored in the host memory 312. 4, a search is made for a first logical block in the first logical block table 110 to be mapped to the new second logical block 121 that conforms to the recommended standard. For example, referring to FIG. 4, a first one of the first logical blocks 111 is mapped to the (8K+1) second logical block 121, and a second one of the first logical blocks 111 is mapped to the (8K+2) second logical block 121, forming a new 8K mapping relationship 110B between the first logical block 111 and the second logical block 121. The mapping relationship 110B between the first logical block 111 and the second logical block 121 is recommended to the host 310, and the L2P mapping table stored in the host memory 312 is updated.

[0047] When the memory system 320 selectively provides a portion of the L2P mapping table to the host 310, management of the mapping relationship becomes relatively complicated when the memory system 320 searches for a first logical block 111 in the first logical block table 110 that maps to a second logical block 121 that meets the recommended standard. Some examples of the present disclosure provide a method for quickly updating the mapping relationship between the first logical block 111 and the second logical block 121 to improve resource management efficiency.

[0048] In the example of the present disclosure, the memory controller 330 of the memory system 320 stores a logical block management table of first logical blocks (e.g., sub-regions) and second logical blocks (e.g., regions), and the memory controller 330 can manage and allocate multiple first logical blocks using the logical block management table. In some examples, if one of the multiple second logical blocks meets a recommended standard, one of the multiple first logical blocks is allocated to this second logical block, and the correspondence is sent to the host 310. In response to this correspondence, the host 310 can obtain the L2P mapping table corresponding to the one second logical block stored in the memory system 320, thereby achieving updating of a portion of the L2P mapping table to the host 310. In this way, data read efficiency and system performance can be improved.

[0049] 5 shows a schematic flowchart of a method for operating a memory system in some examples of the present disclosure. The method may be performed by the memory controller 330 of the memory system 320. As shown in FIG. 5, the method for operating a memory system provided in some examples of the present disclosure may include the following operations S502 and S504.

[0050] In S502, a logical block management table is provided, the logical block management table includes a first sequence corresponding to identities of M first logical blocks, the identities of the M first logical blocks are structured as a ring queue, and the allocation status of the M first logical blocks is managed via the logical block management table, where M is an integer greater than or equal to 2.

[0051] In some examples of the present disclosure, the logical block management table includes a mapping relationship between first logical blocks and second logical blocks, and there may be M first logical blocks. M may represent the number of logical blocks supported by the memory controller 330 of the memory system 320 in the HPB mode, and M may also represent the number of logical blocks supported by the memory controller 330 of the memory system 320 in the HMB mode. The M first logical blocks may cover a portion of the physical address space of the memory devices 340 of the memory system 320. There may be N second logical blocks, and the N second logical blocks may cover some or all of the physical addresses of the memory devices 340 of the memory system 320. It should be noted that M is an integer greater than or equal to 1 and can be specifically configured in the memory controller 330, N is an integer greater than M, and the physical address space of the memory devices 340 of the memory system 320 covered by the M first logical blocks is smaller than the physical address space of the memory devices 340 of the memory system 320 covered by the N second logical blocks.

[0052] For example, in the case of a 512G memory system 320, the physical address space of the memory device 340 is 512G, the storage space corresponding to the entire physical address space of the memory device 340 that can be covered by N second logical blocks may be 512G, and the storage space corresponding to the portion of the physical address space of the memory device 340 that can be covered by M first logical blocks may be, for example, 128G.

[0053] In some examples of the present disclosure, the size of the first logical block is the same as the size of the second logical block, for example, the size of the first logical block and the size of the second logical block are both 16 M. In some examples, the size of the first logical block may also be different from the size of the second logical block.

[0054] In an example of the present disclosure, the logical block management table may include a first sequence corresponding to the identities of M first logical blocks. The identities of the first logical blocks may be identification (ID) of the first logical blocks, and each first logical block has its corresponding identity. The first sequence may be a column of the logical block management table, for example, the first column of logical block management table A as shown in FIGS. 11-15, or the second column of logical block management table B as shown in FIGS. 16-20. The logical block management table may also include a second sequence for representing the identities of second logical blocks, and the identities of the second logical blocks may be IDs of second logical blocks, and each second logical block has its corresponding identity. The second sequence includes the identities of the second logical blocks assigned to each first logical block (if a first logical block is not assigned, the identity of the corresponding second logical block in the second sequence may be an initial value or a preset value, for example, 0). The logical block management table may further include a third sequence including the allocation status of each first logical block.

[0055] Specifically, the allocation state of a first logical block may include, but is not limited to, a first state, a second state, and a third state. The first state may represent an "unassigned" state, the second state may represent an "allocated" state, and the third state may represent an "allocated and pinned" state. The "allocated" state may refer to a state in which the first logical block is assigned to an available second logical block (e.g., a second logical block that meets a recommended standard), and the "allocated and pinned" state may refer to an allocation state in which the first logical block is pinned to the second logical block, and the second logical block to which the first logical block is assigned remains substantially unchanged.

[0056] In some examples of the present disclosure, a ring queue may be constructed according to the number of first logical blocks, and the number of elements in the ring queue is the same as the number of first logical blocks. For example, as shown in FIGS. 6 to 10 , a first-in, first-out (FIFO) ring queue 600 with a depth of M may be initialized to manage resources of the first logical blocks. Each element of the ring queue 600 may store the identity of a corresponding first logical block and the allocation state of the first logical block. For example, the first element of the ring queue 600 may store the identity (ID=1) of a first one of the first logical blocks, the second element of the ring queue 600 may store the identity (ID=2) of a second one of the first logical blocks, ..., the Mth element of the ring queue 600 may store the identity (ID=M) of an Mth one of the first logical blocks, and the initial allocation state of each first logical block may be configured as an "unassigned" first state.

[0057] In some examples, ring queue 600 may include a pointer 601. In the initial state, pointer 601 points to a first one of the first logical blocks of ring queue 600; for example, in the case shown in FIG. 6, pointer 601 points to the first logical block corresponding to identity 1 in the initial state.

[0058] In step S504, according to the order of the identities of the M first logical blocks in the ring queue, one first logical block having an allocation state of a first state representing an unallocated state is allocated to one second logical block among the N second logical blocks, where N is an integer greater than M, and in the logical block management table, the allocation state of the first logical block is updated from the first state to a second state representing an allocated state.

[0059] In some examples of the present disclosure, according to the order of the identities of the M first logical blocks in the ring queue, i.e., according to the order of the M elements in the ring queue (e.g., identity 1 is placed in the first element (corresponding to the first of the first logical blocks), identity 2 is placed in the second element (corresponding to the second of the first logical blocks), ... identity M is placed in the Mth element (corresponding to the Mth of the first logical blocks)), one of the first logical blocks whose allocation state is a first state representing an unallocated state is subsequently allocated to one of the N second logical blocks, and the allocation state of this first logical block is updated from the first state to the second state in the logical block management table.

[0060] In some examples, if one of the N second logical blocks meets the recommended standard, the first logical block pointed to by the pointer in the ring queue whose allocation state is in the first state may be allocated to the second logical block that meets the recommended standard (the L2P mapping table corresponding to this second logical block is activated after being stored in the host memory 312, and this second logical block may also be referred to as an active second logical block). The pointer in the ring queue may point to the first logical block whose allocation state is in the first state according to the order of the identities of the M first logical blocks in the ring queue.

[0061] In some examples, the M first logical blocks may establish mapping relationships with the M corresponding second logical blocks, i.e., all of the first logical blocks in the logical block management table are already allocated. In this case, no first logical blocks in the ring queue have a corresponding allocation status of the first state. Here, the method may include deallocating the second logical blocks in the ring queue that correspond to the first logical blocks that were initially updated to the second state, and updating the allocation status of the first logical blocks that were initially identified as having the second state to the first state.

[0062] In some examples, there may be no first logical blocks whose corresponding allocation status is the first state in the ring queue, i.e., all corresponding first logical blocks in the ring queue are in the second state or the third state. In other words, all first logical blocks have already been assigned to second logical blocks that meet the recommended standard or pinned second logical blocks. In this case, a first logical block to be updated to the second state (i.e., a first logical block that is first assigned to a second logical block that meets the recommended standard) is first determined, and the second logical block corresponding to this first logical block is deallocated (also referred to as deactivated), i.e., the mapping relationship between the first logical block and its corresponding second logical block is released, and the allocation status of the first logical block in the logical block management table is updated from the second state to the first state, and the first logical block is reassigned to another second logical block that meets the recommended standard.

[0063] In some examples, if there is no first logical block in the ring queue whose corresponding allocation state is the first state, the first logical block to be allocated first may be determined according to the order of the identities of the M first logical blocks in the ring queue. For example, referring to FIG. 9 , the ring queue 600 includes M identities, and none of the allocation states of the M first logical blocks corresponding to the M identities are in the first state. The first of the identities is identity 1, and the first logical block corresponding to identity 1 is the first of the first logical blocks. Therefore, the first of the first logical blocks is the first logical block to be allocated first.

[0064] 21 is a schematic flowchart of another method for operating a memory system according to some examples of the present disclosure. As shown in FIG. 21, the method for operating a memory system provided according to some examples of the present disclosure may include the following operations S2102 to S2110.

[0065] In S2102, a second logical block that satisfies the recommended standard is determined.

[0066] In some examples, if it is determined that there is a second logic block that meets the recommended standard, operation S2104 may be performed.

[0067] In S2104, it is determined whether or not a first logical block whose corresponding allocation status is the first status exists in the ring queue.

[0068] In some examples, if a first logical block whose corresponding allocation state is the first state is in the ring queue, operation S2106 is performed. If a first logical block whose corresponding allocation state is the first state is not present in the ring queue logical block, operation S2108 is performed.

[0069] In S2106, according to the order of the identities of the M first logical blocks in the ring queue, the first logical blocks whose allocation status is initially in the first state are allocated to the second logical blocks that meet the recommended standard.

[0070] In S2108, the second logical block corresponding to the first logical block that was initially updated to the second state is deallocated, the allocation state corresponding to the first logical block that was initially identified as being in the second state is updated to the first state, and the first logical block is allocated to a second logical block that meets the recommended standard.

[0071] In S2110, the allocation state of the first logical block allocated to the second logical block that meets the recommended standard is updated from the first state to the second state.

[0072] For other details of the example of FIG. 21, please refer to the description of the example method above, and the description will not be repeated.

[0073] In some examples, the ring queue includes a pointer configured to sequentially point to one of the M first logical blocks in order of the identities of the M first logical blocks in the ring queue.

[0074] For example, initially, referring to Figure 6, pointer 601 points to a first one of the first logical blocks in ring queue 600 (i.e., the first logical block corresponding to identity 1). Referring to Figure 7, after the first one of the first logical blocks is allocated, pointer 601 points to a second one of the first logical blocks in ring queue 600 (i.e., the first logical block corresponding to identity 2), and so on. After the first logical block currently pointed to by pointer 601 is allocated, the pointer sequentially points to the first logical block following the current first logical block.

[0075] In some examples, in response to the allocation state corresponding to the first logical block pointed to by the pointer being in a first state, the first logical block pointed to by the pointer is allocated to a second logical block, and the sequential pointer is made to point to the next first logical block.

[0076] In some examples, when the allocation status corresponding to the first logical block pointed to by the pointer is a first state, it means that the first logical block is allocatable, and this first logical block can be directly allocated to a second logical block that currently meets the recommended standard, and the pointer is made to point to the next first logical block in sequence.

[0077] In some examples, the method may include, in response to the allocation state of the first logical block pointed to by the pointer being the second state, deallocating a second logical block corresponding to the first logical block initially updated to the second state and updating the allocation state corresponding to the first logical block initially identified as being in the second state to the first state.

[0078] In some examples, when the allocation status of the first logical block pointed to by the pointer is the second state, the first logical block pointed to by the pointer is the first logical block to be updated to the second state first. The second logical block corresponding to the first logical block pointed to by the pointer can be deallocated. Therefore, the first logical block to be allocated can be quickly located through the pointer.

[0079] In some examples, the method may further include assigning the first logical block pointed to by the pointer to a second logical block among the N second logical blocks, and pointing the pointer to the next first logical block.

[0080] For example, if the first logical block pointed to by the pointer is a first one of the first logical blocks corresponding to identity 1, and the allocation state of the first one of the first logical blocks is a second state, the method may include first deallocating a second logical block to which the first one of the first logical blocks was allocated, updating the allocation state of the first one of the first logical blocks to the first state, reassigning the first one of the first logical blocks to a second logical block that currently meets the recommended standard (not the same second logical block as the second logical block to which the first one of the first logical blocks was previously allocated), updating the allocation state of the first one of the first logical blocks to the second state, and pointing the pointer to a second one of the first logical blocks corresponding to identity 2.

[0081] 22 is a schematic flowchart of another method for operating a memory system according to an example of the present disclosure. As shown in FIG. 22, the method for operating a memory system according to an example of the present disclosure may include the following operations S2202 to S2212.

[0082] In S2202, a second logical block that satisfies the recommended standard is determined.

[0083] In some examples, if it is determined that there is a second logic block that meets the recommended standard, operation S2204 may be performed.

[0084] In S2204, it is determined whether the allocation state of the first logical block currently pointed to by the pointer is the first state.

[0085] In some examples, if the allocation state of the first logical block currently pointed to by the pointer is the first state, operation S2206 is performed. If the allocation state of the first logical block currently pointed to by the pointer is not the first state, operation S2208 is performed.

[0086] In S2206, the first logical block currently pointed to by the pointer is assigned to a second logical block that meets the recommended standard.

[0087] In S2208, the second logical block corresponding to the first logical block currently pointed to by the pointer is deallocated, and the allocation status corresponding to the first logical block currently pointed to by the pointer is updated to the first status. The first logical block currently pointed to by the pointer is allocated to the second logical block that meets the recommended standard.

[0088] In S2210, the allocation state of the first logical block currently pointed to by the pointer is updated from the first state to the second state.

[0089] In S2212, the pointer points to the next first logical block according to the order of the identities of the M first logical blocks in the ring queue.

[0090] For other details of the example in FIG. 22, please refer to the description of the example method above, and the description will not be repeated.

[0091] In some examples, the method may further include allocating Y first logical blocks whose allocation status is a first state to Y second logical blocks among the N second logical blocks, where Y is an integer greater than 1 and less than M, and updating the allocation status of the Y first logical blocks from the first state to a third state representing an “allocated and pinned” state in the logical block management table.

[0092] In some examples, when the system is initialized, Y second logical blocks out of the N second logical blocks are used to store relevant configuration information, i.e., these Y second logical blocks are logical blocks (also referred to as pinned areas) for storing configuration information, and the information stored in the Y second logical blocks (pinned areas) does not substantially change after initialization.

[0093] In some examples, the Y first logical blocks in the first state are allocated to the Y second logical blocks (pinned areas), and the allocation status of the Y first logical blocks in the logical block management table is updated to a third state. After the Y first logical blocks are allocated to the Y second logical blocks (pinned areas), the allocation status corresponding to the Y first logical blocks remains substantially unchanged. The mapping relationship between the Y first logical blocks and the Y second logical blocks (pinned areas) is sent to the host 310, and the host 310 requests L2P mapping tables corresponding to the Y second logical blocks (pinned areas) according to the mapping relationship between the Y first logical blocks and the Y second logical blocks (pinned areas). The memory system 320 sends the L2P mapping tables corresponding to the Y second logical blocks (pinned areas) to the host 310 and stores them in the host memory 312. Because the mapping relationship between the Y first logical blocks and the Y second logical blocks (pinned areas) does not substantially change after initialization, if the mapping relationship between the first logical blocks and the second logical blocks is subsequently updated, the mapping relationship between the Y first logical blocks and the Y second logical blocks (pinned areas) is not repeatedly sent to the host 310.

[0094] In some examples, Y consecutive first logical blocks of a ring queue whose allocation state is in a first state may be pinned and allocated to Y second logical blocks (the pinned region).

[0095] In some examples, Y consecutive first logical blocks at the head of a ring queue whose allocation state is in the first state may be pinned and allocated to Y second logical blocks (pinned region). Y consecutive first logical blocks at the tail of a ring queue whose allocation state is in the first state may also be pinned and allocated to Y second logical blocks (pinned region). Y consecutive first logical blocks at the middle of a ring queue whose allocation state is in the first state may also be pinned and allocated to Y second logical blocks (pinned region).

[0096] 7, Y consecutive first logical blocks 602 corresponding to the identities of the (M-Y+1)th through Mth first logical blocks in the ring queue are assigned to Y second logical blocks (pinned regions). In another example, Y first logical blocks corresponding to the identities of the 1st through Yth first logical blocks in the ring queue are assigned to Y second logical blocks (pinned regions). In another alternative example, the Y first logical blocks pinned and assigned to the Y second logical blocks (pinned regions) may be randomly determined in advance in the ring queue.

[0097] In some examples, when a first logical block is allocated to a second logical block that meets the recommended standard, the first logical block whose allocation status is in the third state may be skipped according to the order of the identities of the M first logical blocks in the ring queue.

[0098] In some examples, after determining the Y first logical blocks whose allocation state is the third state, the identities of the Y first logical blocks may be recorded. When the allocation is performed, the Y first logical blocks are skipped with respect to the first logical blocks corresponding to the identities of the Y first logical blocks according to the order of the identities of the M first logical blocks in the ring queue.

[0099] 7, the (M-Y+1) through M first logical blocks 602 in the ring queue 600 are first logical blocks in the third state. After the (M-Y) first logical block is assigned to the corresponding second logical block, the (M-Y+1) through M first logical blocks are skipped, and the first of the first logical blocks is assigned to the corresponding second logical block.

[0100] In some examples, the ring queue includes a pointer that can be used to skip the first logical block whose allocation state is in the third state.

[0101] For example, after Y consecutive first logical blocks corresponding to the identities of the first logical blocks from (M-Y+1) to M in the ring queue are assigned to Y second logical blocks, if one first logical block belongs to the first to (MY-1) first logical blocks, the pointer points to the first logical block next to this first logical block.

[0102] For example, referring to Figure 7, if the first logical block pointed to by pointer 601 is a first one of the first logical blocks, and the allocation status of the first one of the logical blocks is a first state, then the first one of the first logical blocks may be directly allocated to a second logical block that currently complies with the recommended standard, the allocation status of the first one of the first logical blocks is updated to a second state, and pointer 601 points to the second one of the first logical blocks, as shown in Figure 8. As another example, if the first logical block pointed to by pointer 601 is a second one of the first logical blocks, then the second one of the first logical blocks may be directly allocated to a second logical block that currently complies with the recommended standard, the allocation status of the second one of the first logical blocks is updated to a second state, and pointer 601 points to a third one of the first logical blocks, etc.

[0103] In some examples, if one first logical block is the MYth first logical block, the pointer points to the first of the first logical blocks.

[0104] 9, if the first logical block pointed to by pointer 601 is the (MY)-th first logical block and the allocation status of the (MY)-th first logical block is in the first state, then the (MY)-th first logical block can be directly allocated to a second logical block that currently complies with the recommended standard, the allocation status of the (MY)-th first logical block is updated to the second state, and pointer 601 points to the first of the first logical blocks. In this case, the (MY-Y+1)-th through M-th first logical blocks 602 in the ring queue, whose allocation status is in the third state, are skipped by the pointer.

[0105] 9 and 10, if the first logical block pointed to by pointer 601 is the first of the first logical blocks and the allocation state of the first of the first logical blocks is the second state, in this case, it is necessary to first deallocate the second logical block to which the first of the first logical blocks was allocated, update the allocation state of the first of the first logical blocks to the first state, then re-allocate the first of the first logical blocks to a second logical block (not the same second logical block as the second logical block to which the first of the first logical blocks was previously allocated) that currently meets the recommended standard, update the allocation state of the first of the first logical blocks to the second state, and point pointer 601 to the second of the first logical blocks. This allows for rapid management and allocation of logical block resources via the ring queue.

[0106] In some examples, the method may further include updating the identity of the first logical block or the identity of the second logical block in a logical block management table.

[0107] The logical block management table in some examples of the present disclosure may be logical block management table A as shown in Figures 11 to 15, or may be logical block management table B as shown in Figures 16 to 20. In some examples, M may be 8K and N may be 32K.

[0108] Hereinafter, updating of the identity of the second logical block in the logical block management table will be described using the logical block management table A shown in FIGS. 11 to 15 as an example.

[0109] 6 and 11, the first column of Logical Block Management Table A is the identity of the first logical block, the second column is the identities of the second logical blocks assigned to the first logical block, and the third column is the allocation status of the first logical block. In the initial stage, the first column contains the identities 1 to M of the first logical blocks. At this time, since none of the first logical blocks are assigned, the identities of the second logical blocks in the second column are initial values, for example, all identities of the second logical blocks are 0, and the allocation statuses in the third column are all in the first state, i.e., unassigned.

[0110] 7 and 12 in combination, Y first logical blocks 602 corresponding to the identities of the (M-Y+1)th through Mth first logical blocks in the ring queue 600 are allocated to Y second logical blocks (pinned areas). The identities of the second logical blocks corresponding to the identities of the (M-Y+1)th through Mth first logical blocks in the logical block management table A are updated to X to Z, and the allocation states corresponding to the identities of the (M-Y+1)th through Mth first logical blocks in the logical block management table A are updated to a third state.

[0111] 7, 8, and 13 in combination, for example, the second logical block currently meeting the recommended standard is the second logical block with an identity of 1. If the first logical block pointed to by pointer 601 is the first of the first logical blocks, and the allocation status of the first of the first logical blocks is the first state, the first of the first logical blocks can be directly allocated to the second logical block with an identity of 1. The identity of the second logical block corresponding to the identity of the first of the first logical blocks in logical block management table A is updated to 1, the allocation status corresponding to the identity of the first of the first logical blocks in logical block management table A is updated to the second state, pointer 601 points to the second of the first logical blocks, and so on. With combined reference to FIGS. 9, 10, and 15, for example, the second logical block currently meeting the recommended standard is the second logical block with an identity of (M-Y+1). When the first logical block pointed to by the pointer 601 is the first one of the first logical blocks, and the allocation state of the first one of the first logical blocks is the second state, in this case, it is necessary to first deallocate the second logical block (e.g., the second logical block with an identity of 1) to which the first one of the first logical blocks was allocated, then re-allocate the first one of the first logical blocks to the second logical block with an identity of (M-Y+1), update the identity of the second logical block corresponding to the identity of the first one of the first logical blocks from 1 to (M-Y+1) in the logical block management table A, and point the pointer to the second one of the first logical blocks.

[0112] Hereinafter, updating of the identity of the first logical block in the logical block management table will be described using the logical block management table B shown in FIGS. 16 to 20 as an example.

[0113] 6 and 16, the first column of Logical Block Management Table B is the identities of second logical blocks, the second column is the identities of first logical blocks to which the second logical blocks are allocated, and the third column is the allocation status of the first logical blocks. In the initial stage, the first column contains the identities 1 to N of the second logical blocks. At this time, since none of the second logical blocks are allocated, the identities of the second logical blocks in the second column are initial values, for example, all the identities of the first logical blocks are 0, and the allocation statuses in the third column are all in the first state, i.e., unallocated.

[0114] 7 and 17 in combination, Y first logical blocks corresponding to the identities of the (M-Y+1)th to Mth first logical blocks in the ring queue 600 are allocated to Y second logical blocks Block (pinned area). The identities of the first logical blocks corresponding to the identities of the Xth to Zth second logical blocks in the logical block management table B are updated from (M-Y+1) to M, and the allocation states corresponding to the identities of the (M-Y+1)th to Mth first logical blocks in the logical block management table B are updated to a third state.

[0115] 7, 8, and 18 in combination, for example, the second logical block currently meeting the recommended standard is the second logical block with an identity of 1. If the first logical block pointed to by pointer 601 is the first of the first logical blocks, and the allocation status of the first of the first logical blocks is a first state, the first of the first logical blocks can be directly allocated to the second logical block with an identity of 1. The identity of the first logical block corresponding to the identity of the second logical block in logical block management table B is updated to 1, the allocation status corresponding to the first logical block with an identity of 1 in logical block management table B is updated to a second state, pointer 601 points to the second of the first logical blocks, and so on. With combined reference to FIGS. 9 and 19, for example, the second logical block currently meeting the recommended standard is the second logical block with an identity of 0X5999. If the first logical block pointed to by pointer 601 is the (MY) first logical block and the allocation status of the (MY) first logical block is the first state, then the (MY) first logical block may be directly allocated to a second logical block having an identity of 0X5999. The identity of the first logical block corresponding to the second logical block having an identity of 0X5999 in logical block management table B is updated to (MY), the allocation status of the (MY) first logical block is updated to the second state, and pointer 601 points to the first of the first logical blocks. Referring to Figures 9, 10, and 20 in combination, for example, the second logical block currently conforming to the recommended standard is the second logical block with an identity of 0X6E2D.When the first logical block pointed to by the pointer 601 is the first of the first logical blocks, and the allocation state of the first of the first logical blocks is the second state, in this case, it is necessary to first deallocate the second logical block (e.g., the second logical block having an identity of 1) to which the first of the first logical blocks was allocated, update the identity of the first logical block corresponding to the second logical block having an identity of 1 in the logical block management table B to an invalid value (e.g., 0X7FFF), update the state corresponding to the first logical block having an identity of the invalid value to the first state, and then reassign the first of the first logical blocks to the second logical block having an identity of 0X6E2D, update the identity of the first logical block corresponding to the second logical block having an identity of 0X6E2D to 1, and point the pointer to the second of the first logical blocks.

[0116] In some examples, the method may further include transmitting the updated logical block management table to the host, and transmitting a logical address-to-physical address mapping table (L2P mapping table) corresponding to the particular second logical block in the logical block management table to the host.

[0117] In some examples of the present disclosure, the memory controller 330 may transmit the logical block management table to the host 310 at preset time intervals. Alternatively, the memory controller 330 may also assign the first logical block to the new second logical block that conforms to the recommended standard every time a new second logical block that conforms to the recommended standard appears, obtain an updated logical block management table, and transmit the updated logical block management table to the host 310. After receiving the recommended second logical block and the mapping relationship between the first logical block and the second logical block, the host 310 may obtain a logical address-physical address mapping table (i.e., an L2P mapping table) corresponding to the recommended second logical block from the memory system 320 and store the L2P mapping table in the host memory 312.

[0118] In some examples of the method for operating a memory system provided by the present disclosure, the allocation status of first logical blocks and the allocation relationship between the first logical blocks and second logical blocks can be dynamically managed via a logical block management table, and fast and efficient search for first logical blocks can be realized via a ring queue constructed according to the identities of the M first logical blocks, thereby quickly allocating a first logical block corresponding to a second logical block among the N second logical blocks that meet the recommended standard, improving resource allocation efficiency, random read performance, and system performance.

[0119] In some examples, if there is no first logical block whose allocation status is the first state, the earliest allocated first logical block can be quickly and efficiently placed through the ring queue, which enables the corresponding first logical block to be quickly allocated to a second logical block among the N second logical blocks that meet the recommended standard.

[0120] 3 , some examples of the present disclosure provide a memory system 320 including a memory device 340 and a memory controller 330 coupled to the memory device 340. The memory controller 330 can control the memory device 340 to perform data storage operations. The memory controller 330 includes an interface (e.g., a host interface 332) communicatively coupled to a host 310, the host interface 332 being configured to sequentially transmit at least a portion of the mapping information of the first logical block management table and the second logical block management table to the host 310.

[0121] The first logical block management table and the second logical block management table each represent a mapping relationship between first logical blocks and second logical blocks at different times. Identities of M first logical blocks are configured as a ring queue, and allocation states of the M first logical blocks are managed by a logical block management table, where M is an integer greater than or equal to 2. The first logical block management table and the second logical block management table each include identities of K first logical blocks whose allocation states are second states representing allocation states at different times, and identities of K second logical blocks among the N second logical blocks to which the K first logical blocks are allocated, where K is an integer greater than 1 and not greater than M, and N is an integer greater than M. To represent an update of the mapping relationship of the second logical block management table to the mapping relationship of the first logical block management table, one first logical block that is initially allocated among the K first logical blocks corresponding to the first logical block management table is updated and allocated to one second logical block among the K second logical blocks in the second logical block management table.

[0122] In some examples of the present disclosure, the host interface 332 may sequentially send all of the mapping information of the first logical block management table and the second logical block management table to the host 310, and may send a portion of the mapping information of the first logical block management table and the second logical block management table (e.g., updated mapping information of the second logical block management table relative to the first logical block management table).

[0123] In some examples, the first logical block management table may be the logical block management table shown in Figure 11 (i.e., the initial state of the logical block management table, where all allocation states corresponding to the first logical blocks are in a first state representing an unallocated state). The second logical block management table may be the logical block management table shown in Figure 12, and may include the bolded entries in the logical block management table shown in Figure 12 (i.e., Y first logical blocks are in a pinned allocation to Y second logical blocks (pinned area)).

[0124] 11 as the first logical block management table and the logical block management table shown in FIG. 12 as an example of the second logical block management table, when the host interface 332 sends the first logical block management table to the host 310, the logical block management table shown in FIG. 11 is the initial state of the logical block management table, so in this case the host interface 332 sends all of the mapping entries of the logical block management table shown in FIG. 11 to the host 310. Next, the host interface 332 sends a second logical block management table to the host 310, and in this case the host interface 332 may send all of the mapping entries of the logical block management table shown in FIG. 12 to the host 310, and may send updated mapping entries of the logical block management table shown in FIG. 12 (i.e., the bolded entries of the logical block management table shown in FIG. 12 (i.e., the corresponding mapping entries of the Y pinned first logical blocks and the Y second logical blocks (pinned areas) to which the Y first logical blocks are assigned by pinning)) to the logical block management table shown in FIG. The allocation status corresponding to the Y first logical blocks remains substantially unchanged. After the mapping relationship between the Y first logical blocks and the Y second logical blocks (pinned areas) is transmitted to the host 310, if the mapping relationship between the first logical blocks and the second logical blocks is subsequently updated, the mapping relationship between the Y first logical blocks and the Y second logical blocks (pinned areas) does not need to be repeatedly transmitted to the host 310.

[0125] In some examples, the first logical block management table may be the logical block management table shown in FIG. 12 or may include the bolded portion of the logical block management table shown in FIG. 12, and the second logical block management table may be the logical block management table shown in FIG. 13 or may include the bolded entries of the logical block management table shown in FIG. 13 (i.e., the first of the first logical blocks is assigned to the first second logical block).

[0126] 12 as the first logical block management table and the logical block management table shown in FIG. 13 as the second logical block management table, when the host interface 332 sends the first logical block management table to the host 310, the host interface 332 may send all mapping entries of the logical block management table shown in FIG. 12 to the host 310, and may send updated mapping entries of the logical block management table shown in FIG. 12 for the logical block management table shown in FIG. 11 (i.e., the bolded entries of the logical block management table shown in FIG. 12 (i.e., the corresponding mapping entries of the Y pinned first logical blocks and the Y second logical blocks (pinned areas) to which the Y first logical blocks are assigned by pinning)). Next, the host interface 332 sends the second logical block management table to the host 310, in which case the host interface 332 may send all mapping entries of the logical block management table shown in FIG. 13 to the host 310, or may send updated entries of the logical block management table shown in FIG. 13 for the logical block management table shown in FIG. 12 (i.e., the bolded entries of the logical block management table shown in FIG. 13 (i.e., the mapping entries corresponding to the first logical block identity 1 and the second logical block identity 1)).

[0127] In some examples, the first logical block management table may be the logical block management table shown in FIG. 13 or may include the bolded portion of the logical block management table shown in FIG. 13, and the second logical block management table may be the logical block management table shown in FIG. 14 or may include mapping entries corresponding to first logical block identities 1 to MY of the logical block management table shown in FIG. 14 (i.e., first logical blocks 1 through MY are assigned to second logical blocks 1 through MY, respectively).

[0128] 13 as the first logical block management table and the logical block management table shown in FIG. 14 as an example as the second logical block management table, when sending the first logical block management table to the host 310, the host interface 332 may send all mapping entries of the logical block management table shown in FIG. 13 to the host 310, or may also send updated mapping entries of the logical block management table shown in FIG. 13 (i.e., the bolded entries of the logical block management table shown in FIG. 13) for the logical block management table shown in FIG. 12. Next, the host interface 332 sends the second logical block management table to the host 310. In this case, the host interface 332 may send all mapping entries of the logical block management table shown in FIG. 14 to the host 310, or may also send updated mapping entries of the logical block management table shown in FIG. 14 (i.e., the mapping entries corresponding to the first logical block identities 1 to MY in the logical block management table shown in FIG. 14) for the logical block management table shown in FIG. 13.

[0129] In some examples, the first logical block management table may be the logical block management table shown in FIG. 14 or may include the bolded portions of the logical block management table shown in FIG. 14, and the second logical block management table may be the logical block management table shown in FIG. 15 or may include the bolded entries in the logical block management table shown in FIG. 15.

[0130] 14 as the first logical block management table and the logical block management table shown in FIG. 15 as an example as the second logical block management table, when sending the first logical block management table to the host 310, the host interface 332 may send all mapping entries of the logical block management table shown in FIG. 14 to the host 310, or may also send updated mapping entries of the logical block management table shown in FIG. 14 for the logical block management table shown in FIG. 13 (i.e., mapping entries corresponding to the first logical block identities 1 to MY in the logical block management table shown in FIG. 14). Next, the host interface 332 sends the second logical block management table to the host 310. In this case, the host interface 332 may send all mapping entries of the logical block management table shown in FIG. 15 to the host 310, or may also send updated mapping entries of the logical block management table shown in FIG. 15 for the logical block management table shown in FIG. 14 (i.e., the bolded entries in the logical block management table shown in FIG. 15).

[0131] If the first logical block management table is the logical block management table shown in Figure 14 and the second logical block management table is the logical block management table shown in Figure 15 as an example, among the K first logical blocks corresponding to the first logical block management table shown in Figure 14, in the first assigned first logical block (i.e., the first logical block corresponding to identity 1), the first logical block corresponding to identity 1 is updated and assigned to the second logical block (i.e., the second logical block corresponding to identity (M-Y+1)) among the K second logical blocks.

[0132] In some examples, the first logical block management table may be the logical block management table shown in FIG. 16, and the second logical block management table may be the logical block management table shown in FIG. 17, or may include the bolded entries in the logical block management table shown in FIG. 17.

[0133] In some examples, the first logical block management table may be the logical block management table shown in FIG. 17 or may include the bolded portions of the logical block management table shown in FIG. 17, and the second logical block management table may be the logical block management table shown in FIG. 18 or may include the bolded entries of the logical block management table shown in FIG.

[0134] In some examples, the first logical block management table may be the logical block management table shown in FIG. 18 or may include the bolded portions of the logical block management table shown in FIG. 18, and the second logical block management table may be the logical block management table shown in FIG. 19 or may include the bolded entries of the logical block management table shown in FIG.

[0135] In some examples, the first logical block management table may be the logical block management table shown in FIG. 19 or may include the bolded portions of the logical block management table shown in FIG. 19, and the second logical block management table may be the logical block management table shown in FIG. 20 or may include the bolded entries in the logical block management table shown in FIG. 20.

[0136] In some examples, the first logical block management table and the second logical block management table may be two adjacent updates of the logical block management table between the first logical block and the second logical block sent by the host interface 332 to the host 310. The memory controller 330 may use the host interface 332 to update the logical block management table and send the updated logical block management table to the host at every preset time interval. In this case, the first logical block management table is the logical block management table that the host interface 332 sends to the host 310 at time T1 to update the L2P mapping table stored in the host memory 312, and the second logical block management table is the logical block management table that the host interface 332 sends to the host 310 at time T2. The time difference between time T1 and time T2 is the preset time interval. The memory controller 330 may also send the updated logical block management table to the host 310 via the host interface 332 every time the logical block management table is updated to update the L2P mapping table stored in the host memory 312. The memory controller 330 may also send the updated logical block management table to the host 310 via the host interface 332 after the updated mapping relationship between the first logical block and the second logical block reaches a certain quantity, in order to update the L2P mapping table stored in the host memory 312.

[0137] In some examples, the first logical block management table includes a first sequence corresponding to identities of M first logical blocks, the identities of the M first logical blocks being organized as a ring queue, and allocation states of the M first logical blocks being managed via the logical block management table. The first logical block management table may include identities of K first logical blocks whose initial allocation state is a second state representing an allocated state, and identities of K second logical blocks among the N second logical blocks to which the K first logical blocks were initially allocated. The second logical block management table may include identities of K first logical blocks whose allocation state at a second time is a second state representing an allocated state (the identities of the K first logical blocks in the second logical block management table are different from the identities of the K first logical blocks in the first logical block management table), and identities of K second logical blocks among the N second logical blocks to which the K first logical blocks are allocated at the second time. To represent the update of the mapping relationship of the second logical block management table to the mapping relationship of the first logical block management table, one first logical block among the K first logical blocks corresponding to the initially allocated first logical block management table is updated and allocated to one second logical block among the K second logical blocks in the second logical block management table.

[0138] In some examples of the present disclosure, M represents the number of logical blocks supported by the memory controller of the memory system in HPB mode, and the N second logical blocks cover all physical addresses of the memory devices of the memory system.

[0139] In some examples of the present disclosure, both the first logical block management table and the second logical block management table include identities of Y first logical blocks whose allocation state is a third state representing an allocated and pinned state, and identities of Y second logical blocks to which the Y first logical blocks are allocated, where Y is an integer greater than 1, and the sum of Y and K is less than or equal to M. The host interface 332 is configured to send, to the host 310, mapping information of the K pieces of the second logical block management table to the first logical block management table.

[0140] In some examples of the present disclosure, if Y first logical blocks are pinned and allocated to Y second logical blocks (pinned areas), the allocation status of the Y first logical blocks in the logical block management table is updated to a third state. After the logical block management table is updated, the host interface 332 transmits the updated logical block management table to the host 310 (e.g., including the logical block management table shown in FIG. 12 or the bolded entries of the logical block management table shown in FIG. 12). When the logical block management table is subsequently updated and transmitted, only the updated entries (e.g., the updated K mapping information) may be transmitted without repeatedly transmitting the Y mapping information corresponding to the Y first logical blocks or other entries that have not been updated in the logical block management table.

[0141] In some examples of the present disclosure, the host interface 332 is further configured to send to the host 310 a logical address-physical address mapping table corresponding to one second logical block.

[0142] FIG. 23 shows a schematic diagram of interaction between a host and a memory system according to some examples of the present disclosure.

[0143] In some examples of the present disclosure, referring to FIG. 23, the process of interaction between the host 310 and the memory system 320 may include the following operations S2301-S2306.

[0144] In S2301, the host interface 332 of the memory controller 330 sends the first logical block management table to the host 310.

[0145] In some examples of the present disclosure, the host interface 332 may send the first logical block management table to the host 310, or may also send part of the mapping information of the first logical block management table to the host 310. The first logical block management table (or part of the mapping information of the first logical block management table) that the host interface 332 sends to the host 310 includes at least one mapping relationship between the first logical block and the second logical block.

[0146] In S2302, the host 310 requests the memory system 320 for an L2P mapping table corresponding to the second logical block included in the first logical block management table.

[0147] In some examples of the present disclosure, after receiving the first logical block management table (or a portion of the mapping information of the first logical block management table), the host 310 requests from the memory system 320 an L2P mapping table corresponding to the second logical block included in the received first logical block management table (or a portion of the mapping information of the first logical block management table).

[0148] In S2303, the host interface 332 of the memory controller 330 sends the L2P mapping table corresponding to the second logical block included in the first logical block management table to the host 310, and the L2P mapping table corresponding to the second logical block included in the first logical block management table is stored in the host memory 312 of the host 310.

[0149] In some examples of the present disclosure, in response to a request for an L2P mapping table sent by host 310, memory system 320 sends to host 310 an L2P mapping table corresponding to the second logical block included in the first logical block management table (or part of the mapping information of the first logical block management table) for storage in host memory 312.

[0150] In S2304, the host interface 332 of the memory controller 330 sends the second logical block management table to the host 310.

[0151] In some examples of the present disclosure, the memory controller 330 may transmit a logical block management table to the host 310 at every preset time interval. The logical block management tables transmitted sequentially at one preset time interval are a first logical block management table and a second logical block management table.

[0152] In some examples of the present disclosure, the memory controller 330 can also allocate a first logical block to a new second logical block that conforms to the recommended standard each time the new second logical block that conforms to the recommended standard appears, obtain an updated logical block management table, and send the updated logical block management table to the host 310. The logical block management table before each update is the first logical block management table, and the logical block management table after the update is the second logical block management table.

[0153] In some examples of the present disclosure, the host interface 332 may send the second logical block management table to the host 310, or may also send part of the mapping information of the second logical block management table to the host 310. The second logical block management table (or part of the mapping information of the second logical block management table) that the host interface 332 sends to the host 310 includes at least one mapping relationship between a first logical block and a second logical block.

[0154] In S2305, the host 310 requests the memory system 320 for an L2P mapping table corresponding to the second logical block included in the second logical block management table.

[0155] In some examples of the present disclosure, after receiving the second logical block management table (or a portion of the mapping information of the second logical block management table), the host 310 requests from the memory system 320 an L2P mapping table corresponding to the second logical block included in the received second logical block management table (or a portion of the mapping information of the second logical block management table).

[0156] In S2306, the host interface 332 of the memory controller 330 sends the L2P mapping table corresponding to the second logical block included in the second logical block management table to the host 310, and the L2P mapping table corresponding to the second logical block included in the second logical block management table is stored in the host memory 312 of the host 310.

[0157] In some examples of the present disclosure, in response to a request for an L2P mapping table sent by host 310, memory system 320 sends to host 310 an L2P mapping table corresponding to the second logical blocks included in the second logical block management table for storage in host memory 312.

[0158] 3 , some examples of the present disclosure provide a memory system 320 including a memory device 340 and a memory controller 330 coupled to the memory device 340 and controlling the memory device 340 to perform data storage operations. The memory controller 330 includes an interface (i.e., a host interface 332) communicatively coupled to the host 310, where the host interface 332 is configured to sequentially transmit a first mapping relationship and a second mapping relationship to the host 310 after two adjacent logical block management table updates are triggered.

[0159] The first mapping relationship includes P pieces of mapping information between the first logical block and the second logical block, and the P pieces of mapping information are included in a first logical block management table. The second mapping relationship includes Q pieces of mapping information between the first logical block and the second logical block, and the Q pieces of mapping information are included in a second logical block management table. Both the first logical block management table and the second logical block management table include a first sequence corresponding to identities of M first logical blocks, and the identities of the M first logical blocks are structured as a ring queue, and the allocation status of the M first logical blocks is managed via the logical block management table. M is an integer equal to or greater than 2, and both P and Q are integers equal to or greater than 1 and equal to or less than M. To represent the update of the mapping relationship of the second logical block management table to the mapping relationship of the first logical block management table, one first logical block that is initially assigned among the M first logical blocks corresponding to the first logical block management table is updated and assigned to one second logical block among the Q second logical blocks of the second logical block management table.

[0160] In some examples of the present disclosure, after a specific update of the logical block management table (the updated logical block management table is referred to as the first logical block management table), the host interface 332 sends the updated mapping information (e.g., P pieces of mapping information) in the first logical block management table to the host 310. After the next update after the specific update (the updated logical block management table is referred to as the second logical block management table), the host interface 332 sends the updated mapping information (e.g., Q pieces of mapping information) in the second logical block management table to the host 310.

[0161] In some examples, the first logical block management table obtained in a particular update may be the logical block management table shown in FIG. 12, and the updated mapping information may be the mapping information in bold in FIG. 12. The host interface 332 may send the mapping information in bold in FIG. 12 to the host 310. The second logical block management table obtained in the update following the particular update may be the logical block management table shown in FIG. 13, and the updated mapping information may be the mapping information in bold in FIG. 13. The host interface 332 may send the mapping information in bold in FIG. 13 to the host 310.

[0162] In some examples of the present disclosure, when host interface 332 sends updated mapping information to host 310, host interface 332 may send the updated mapping information to host 310 one by one in the form of mapping entries, and each mapping entry may include at least an identity of a first logical block and an identity of a second logical block.

[0163] Taking the updated mapping information in bold in FIG. 12 as an example, host interface 332 may send to host 310 the mapping entry in FIG. 12 in which the identity of the first logical block is M-Y+1 and the identity of the second logical block is X, then host interface 332 sends to host 310 the mapping entry in FIG. 12 in which the identity of the first logical block is M-Y+2, the identity of the second logical block is X+1, ..., and then host interface 332 sends to host 310 the mapping entry in FIG. 12 in which the identity of the first logical block is M and the identity of the second logical block is Z.

[0164] 14, the host interface 332 may send the mapping entry in FIG. 14 in which the identity of the first logical block is 1 and the identity of the second logical block is 1 to the host 310, then the host interface 332 may send the mapping entry in FIG. 14 in which the identity of the first logical block is 2, the identity of the second logical block is 2, ... to the host 310, then the host interface 332 may send the mapping entry in FIG. 14 in which the identity of the first logical block is MY and the identity of the second logical block is MY to the host 310. That is, the host interface may send the updated mapping information in the form of mapping entries one by one to the host 310.

[0165] In some examples, the first logical block management table obtained in a particular update may be the logical block management table shown in FIG. 14, and the updated mapping information may be the mapping information in bold in FIG. 14. The host interface 332 may send the mapping information in bold in FIG. 14 to the host 310. The second logical block management table obtained in the update following the particular update may be the logical block management table shown in FIG. 15, and the updated mapping information may be the mapping information in bold in FIG. 15. The host interface 332 may send the mapping information in bold in FIG. 15 to the host 310.

[0166] If the first logical block management table is the logical block management table shown in Figure 14 and the second logical block management table is the logical block management table shown in Figure 15 as an example, among the M first logical blocks corresponding to the first logical block management table shown in Figure 14, in the first assigned first logical block (i.e., the first logical block corresponding to identity 1), the first logical block corresponding to identity 1 is updated and assigned to one second logical block (i.e., the second logical block corresponding to identity (M-Y+1)) among the Q second logical blocks.

[0167] In some examples, the first logical block management table obtained in a particular update may be the logical block management table shown in FIG. 17, and the updated mapping information may be the mapping information in bold in FIG. 17. The host interface 332 may send the mapping information in bold in FIG. 17 to the host 310. The second logical block management table obtained in the update following the particular update may be the logical block management table shown in FIG. 18, and the updated mapping information may be the mapping information in bold in FIG. 18. The host interface 332 may send the mapping information in bold in FIG. 18 to the host 310.

[0168] The principle of the example system for solving the problem is similar to that of the above-mentioned example method, so the implementation of the example system can refer to the implementation of the above-mentioned example method, and a repeated description will not be given.

[0169] Some examples of the present disclosure provide a non-transitory computer-readable storage medium having stored thereon computer instructions that, when executed, perform any of the methods for operating a memory system as described above. The computer instructions are adapted to be loaded by a processor and to execute the method for operating a memory system according to each step of any of the above examples. For details, please refer to the implementation according to each step of any of the above examples, and a description of the beneficial effects of adopting the same method will not be repeated here. For technical details not disclosed in the examples of the computer-readable storage medium included in the present disclosure, please refer to the description of the examples of the method of the present disclosure. For example, the computer program may be deployed to be executed on a computer device, on multiple computer devices at one site, or on multiple computer devices distributed across multiple sites and interconnected by a communication network.

[0170] Some examples of the present disclosure further provide a computer program product or computer program that includes computer instructions stored on a computer-readable storage medium, where a processor in a computer device memory reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, causing the computer device to perform the method provided in various optional implementations of any of the foregoing examples.

[0171] Those skilled in the art will understand that the schematic units and algorithmic operations described according to the examples disclosed herein can be implemented by electronic hardware, computer software, or a combination thereof. To clearly illustrate the compatibility of hardware and software, the configurations and steps of each example are generally described herein in terms of functions. Whether a function is implemented by hardware or software depends on the specific application and design constraints of the technical solution. For each specific application, those skilled in the art may use different methods to implement the described functions, but such implementations should not be considered beyond the scope of the present disclosure.

[0172] The methods and related devices provided in the examples of this disclosure are described with reference to flowcharts and / or structural diagrams of the methods presented in the examples of this disclosure, and each flow block and / or structural diagram block of the flowcharts and / or block diagrams can be embodied in computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable application display device to produce a machine, such that the instructions executed by the processor of the computer or other programmable application display device produce a device configured to perform the functions specified in one or more blocks of the flowcharts and / or structural diagrams. These computer program instructions can also be stored in a computer-readable memory that can instruct the computer or other programmable application display device to operate in a particular manner, such that the instructions stored in the computer-readable memory produce a product including the device of instructions, and the device of instructions performs the functions specified in one or more blocks of the flowcharts and / or structural diagrams. These computer program instructions may also be loaded into a computer or other programmable application display device, causing the computer or other programmable device to execute a series of operational steps to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more flows of the flowcharts and / or one or more blocks of the structural schematics.

[0173] Other examples of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure which follow the general principles of the present disclosure and which include common general knowledge or conventional technical means in the art that are not disclosed in the present disclosure. The specification and examples are exemplary, with the actual scope and spirit of the present disclosure being defined by the appended claims.

Claims

1. 1. A method of operating a memory system, comprising: providing a logical block management table, the logical block management table including a first sequence corresponding to identities of M first logical blocks, the identities of the M first logical blocks being structured as a ring queue, and an allocation status of the M first logical blocks being managed via the logical block management table, where M is an integer greater than or equal to 2; allocating one first logical block whose allocation state is a first state representing an unallocated state to one second logical block among N second logical blocks according to the order of the identities of the M first logical blocks in the ring queue, where N is an integer greater than M, and updating the allocation state of the one first logical block in the logical block management table from the first state to a second state representing an allocated state.

2. 2. The method of claim 1, wherein M represents a number of logical blocks supported by a memory controller of the memory system in HPB mode, and the N second logical blocks cover all physical addresses of memory devices of the memory system.

3. 2. The method of claim 1, further comprising: if there is no first logical block in the ring queue whose corresponding allocation state is the first state, deallocating the second logical block corresponding to the first logical block that was first updated to the second state, and updating the allocation state corresponding to the first logical block that was first identified as the second state to the first state.

4. the ring queue includes a pointer configured to sequentially point to one of the M first logical blocks according to the order of the identities of the M first logical blocks in the ring queue; The method comprises:

2. The method of claim 1, further comprising: in response to the allocation status of the first logical block pointed to by the pointer being the second state, deallocating the second logical block corresponding to the first logical block that was initially updated to the second state, and updating the allocation status corresponding to the first logical block that was initially identified as being in the second state to the first state.

5. 5. The method of claim 4, further comprising: assigning the first logical block pointed to by the pointer to one second logical block among the N second logical blocks; and pointing the pointer to a next first logical block according to the order of the identities of the M first logical blocks in the ring queue.

6. 6. The method of claim 1, further comprising: allocating Y first logical blocks whose allocation states are the first state to Y second logical blocks among the N second logical blocks, where Y is an integer greater than 1 and less than M; and updating the allocation states of the Y first logical blocks in the logical block management table from the first state to a third state representing an allocated and pinned state.

7. The allocation of the Y first logical blocks whose allocation state is the first state to the Y second logical blocks among the N second logical blocks includes:

7. The method of claim 6, further comprising allocating Y consecutive first logical blocks in the ring queue whose allocation state is in the first state to the Y second logical blocks.

8. 7. The method of claim 6, wherein the first logical blocks whose allocation state is the third state are skipped according to the order of the identities of the M first logical blocks in the ring queue.

9. the logical block management table further includes a second sequence corresponding to the identities of the N second logical blocks; The method comprises:

2. The method of claim 1, further comprising: updating the identity of the one first logical block or the identity of the one second logical block in the logical block management table.

10. 2. The method of claim 1, wherein the number of elements in the ring queue is the same as the number of first logical blocks, and each element stores the identity and the allocation state of a corresponding first logical block.

11. The method of claim 1 , wherein the size of the first logical block is the same as the size of the second logical block.

12. The method of claim 1, further comprising sending the logical block management table to a host after updating the logical block management table.

13. 13. The method of claim 12, further comprising transmitting an L2P mapping table corresponding to the one second logical block to the host.

14. 1. A memory system comprising: a memory device; and a memory controller coupled to the memory device and configured to control the memory device to perform data storage operations; the memory controller comprises an interface communicatively coupled to a host and configured to sequentially transmit at least a portion of mapping information of a first logical block management table and a second logical block management table to the host; the first logical block management table and the second logical block management table respectively represent mapping relationships between first logical blocks and second logical blocks at different times, each of the first logical block management table and the second logical block management table includes a first sequence corresponding to identities of M first logical blocks, the identities of the M first logical blocks are configured as a ring queue, and allocation states of the M first logical blocks are managed by the first logical block management table and the second logical block management table, where M is an integer equal to or greater than 2; the first logical block management table and the second logical block management table each include, when different from one another, identities of K first logical blocks that have a second state representing an allocated state as their allocated state, and identities of K second logical blocks among N second logical blocks to which the K first logical blocks are allocated, where K is an integer greater than 1 and equal to or less than M, and N is an integer greater than M; a first logical block that is initially allocated among the K first logical blocks corresponding to the first logical block management table is updated and allocated to one second logical block among the K second logical blocks of the second logical block management table to represent an update of the mapping relationship of the second logical block management table to the mapping relationship of the first logical block management table.

15. 15. The system of claim 14, wherein M represents a number of logical blocks supported by the memory controller of the memory system in HPB mode, and the N second logical blocks cover all physical addresses of the memory devices of the memory system.

16. both the first logical block management table and the second logical block management table include identities of Y first logical blocks whose allocation states are in a third state representing an allocated and pinned state, and identities of Y second logical blocks to which the Y first logical blocks are allocated, Y being an integer greater than 1, and the sum of Y and K being less than or equal to M; 16. The system according to claim 14, wherein the interface is configured to transmit, to the host, K pieces of mapping information of the second logical block management table to be updated relative to the first logical block management table.

17. 16. The system of claim 14, wherein the interface is further configured to transmit an L2P mapping table corresponding to the one second logical block to the host.

18. 1. A memory system comprising: a memory device; and a memory controller coupled to the memory device and configured to control the memory device to perform data storage operations; the memory controller comprising an interface communicatively coupled to a host; the interface is configured to sequentially transmit a first mapping relationship and a second mapping relationship to the host when two adjacent updates of the logical block management table are triggered; the first mapping relationship includes P pieces of mapping information of a first logical block and a second logical block, the P pieces of mapping information being included in a first logical block management table; the second mapping relationship includes Q pieces of mapping information of the first logical block and the second logical block, the Q pieces of mapping information being included in a second logical block management table; each of the first logical block management table and the second logical block management table includes a first sequence corresponding to identities of M first logical blocks, the identities of the M first logical blocks being structured as a ring queue; allocation states of the M first logical blocks are managed via the logical block management table, M is an integer equal to or greater than 2, and both P and Q are integers equal to or greater than 1 and equal to or less than M; a first logical block that is initially allocated among the M first logical blocks corresponding to the first logical block management table is updated and allocated to one second logical block among the Q second logical blocks of the second logical block management table, representing an update of the mapping relationship of the second logical block management table to the mapping relationship of the first logical block management table.

19. 20. The system of claim 18, wherein M represents a number of logical blocks assisted by the memory controller of the memory system in HPB mode, the number of second logical blocks is N, N is an integer greater than M, and the N second logical blocks cover all physical addresses of the memory devices of the memory system.

20. 20. The system of claim 18 or 19, wherein the interface is further configured to transmit an L2P mapping table corresponding to the one second logical block to the host.

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