Semiconductor structure integrating logic and memory elements

Abstract

A semiconductor structure is provided that includes a substrate, a logic element, and a memory element, and integrates the logic element and the memory element. In a semiconductor structure (100), a substrate (110) has a first region (110A) and a second region (110B) laterally adjacent to the first region. A logic element (120) is disposed in the first region of the substrate, and a memory element (130) is disposed in the second region of the substrate. The logic element includes a plurality of transistors. The memory element includes an upper electrode (133), a lower electrode (132), and dielectric layers (134, 135) disposed between the upper and lower electrodes. The lower electrode includes a metal layer (1321) and a copper-phosphorus alloy layer (1322) extending along the contour of and surrounding the metal layer (1321). The upper electrode includes a metal layer (1331) and a copper-phosphorus alloy layer (1332) extending along the contour of and surrounding the metal layer (1331).

Description

[Technical Field]

[0001] cross reference This application claims the benefit of prior application U.S. Patent No. 18 / 931,868, filed October 30, 2024, which is incorporated by reference in its entirety.

[0002] Field of the Disclosure The present disclosure relates to semiconductor structures, and more particularly to semiconductor structures that integrate logic and memory elements. [Background technology]

[0003] With the advancement of technology, artificial intelligence and the high-performance computing (HPC) required for it have become indispensable in the fields of science and technology. While the computational speed of processors continues to improve, the memory access speed cannot keep up with that speed, resulting in the "memory wall" problem. In other words, when the processor's computational speed exceeds the memory access speed, the overall output speed is limited, and the expected performance cannot be achieved.

[0004] Additionally, certain memories require higher operating voltages and cannot be manufactured using the same manufacturing process as logic circuits, so these memories and logic circuits must be placed on different chips. This complicates communication between the memory and the processor, which is detrimental to improving memory access speeds. Therefore, the field is seeking a fully integrated solution by redesigning the logic circuit and memory cell structures to promote the development of HPC. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a semiconductor structure integrating logic and memory elements is provided. The semiconductor structure includes a substrate, a logic element, and a memory element. The substrate has a first region and a second region laterally adjacent to the first region. The logic element is disposed in the first region of the substrate and includes a plurality of transistors. The logic element is operable as a bit line and word line decode circuit. The memory element is disposed in the second region of the substrate and is fabricated using a manufacturing process compatible with that of the logic element in the first region. Thus, both the logic circuit and the memory circuit can be fabricated on the same chip substrate (e.g., forming a computing-in-memory (CIM) structure within a memory chip), thereby alleviating the memory wall problem in the prior art. The memory element includes an upper electrode, a lower electrode, and a dielectric layer disposed between the upper and lower electrodes. The lower electrode is disposed above the substrate and includes a first metal layer and a first copper-phosphorus alloy layer extending along the contour of the first metal layer and surrounding the first metal layer. The top electrode is disposed above the substrate and the bottom electrode and includes a second metal layer and a second copper-phosphorus alloy layer extending along the contour of the second metal layer and surrounding the second metal layer.

[0006] According to another aspect of the present disclosure, an electronic device is provided. The electronic device includes a circuit board, an electronic component, and an organic solderability preservative (OSP). The circuit board includes a plurality of conductive trace layers, and a surface conductive trace layer of the plurality of conductive trace layers includes a plurality of solder contacts. The electronic component includes a semiconductor structure and a plurality of pins, the plurality of pins being soldered to a plurality of corresponding solder contacts. The OSP coats the surface conductive trace layer. The circuit board operates in a cooling gas or is immersed in a cooling fluid. The OSP does not cover all or at least some of the plurality of solder contacts of the surface conductive trace layer, such that at least some of the other wires operate in the cooling gas or are in direct contact with the cooling fluid.

[0007] According to another aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a substrate, a logic element, and a memory element. The substrate has a first region and a second region laterally adjacent to the first region. The logic element is disposed in the first region of the substrate and includes a plurality of transistors. The memory element is disposed in the second region of the substrate. The memory element includes a source, a drain, a first oxide layer, a control gate, and a first copper-phosphorus alloy layer. The source and drain are located in the substrate. The first oxide layer is disposed in the substrate between the source and drain. The control gate is disposed in the first oxide layer. The first copper-phosphorus alloy layer is disposed between the first oxide layer and the control gate. [Brief explanation of the drawings]

[0008] For a more comprehensive understanding of the present disclosure, reference may be made to the following embodiments, claims, and accompanying drawings. In accordance with standard practice in the art, various features in the drawings may not be drawn to scale. In fact, the dimensions of certain features may be intentionally increased or decreased for ease of illustration.

[0009] [Figure 1] 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. [Figure 2] 2 is a partially enlarged schematic view of a barrier layer, a copper-phosphorus alloy layer, and a dielectric layer in FIG. 1. [Figure 3] FIG. 2 is a cross-sectional view of the semiconductor structure in FIG. [Figure 4] FIG. 2 is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure. [Figure 5] 5 is a top view of the copper-phosphorus alloy layer of the semiconductor structure in FIG. 4. [Figure 6] FIG. 2 is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure. [Figure 7] 1 is a schematic diagram of a memory element according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a cross-sectional view of the memory element in FIG. [Figure 9] FIG. 2 is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure. [Figure 10]FIG. 2 is a top view of a ferroelectric material layer. [Figure 11] FIG. 2 is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure. [Figure 12] FIG. 1 is a schematic diagram of a circuit board according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] The following disclosure provides numerous different embodiments or examples for implementing different features of the subject matter described herein. To simplify the disclosure, the following description provides specific examples of elements, arrangements, and configurations. Note that this description is merely illustrative and does not limit the disclosure. For example, in the following description, "forming a first feature on / on or above a second feature" may include an embodiment in which the first feature and the second feature are formed so that they are in direct contact with each other, or an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact with each other. Furthermore, numerals and / or symbols may be repeated to refer to elements in various embodiments of the disclosure. Such repetition is for the purpose of brevity and clarity and does not determine or represent a relationship between the embodiments and / or configurations described herein.

[0011] Also, for ease of explanation, relative spatial terms such as "below," "below," "lower," "above," and "top" may be used to describe the relationship between one element or feature and another element or feature shown in the figures. In addition to the orientation depicted in the figures, these relative spatial terms are intended to encompass different orientations of the device in use or operation. The device may be configured in other orientations (e.g., rotated 90 degrees or otherwise oriented) and the relative spatial terms may be similarly interpreted accordingly.

[0012] Although the broader ranges and parameters defined in this disclosure are all approximations, the relevant values ​​in certain embodiments are reported herein as precisely as possible. However, any value necessarily contains standard deviations as a result of the respective testing methods. Thus, unless otherwise specified, the numerical parameters set forth in this disclosure and the appended claims may be approximations that vary depending on requirements. These numerical parameters should be understood as values ​​obtained using at least the specified number of significant digits and applying ordinary rounding techniques. Herein, numerical ranges are expressed as from one endpoint to another endpoint or between two endpoints. Unless otherwise specified, all numerical ranges disclosed herein include the endpoints.

[0013] 1 shows a schematic diagram of a semiconductor structure 100 according to one embodiment of the present disclosure. The semiconductor structure 100 may include a substrate 110, a logic element 120, and a memory element 130. The substrate 110 has a first region 110A and a second region 110B, with the first region 110A laterally adjacent to the second region 110B. The logic element 120 may be disposed in the first region 110A of the substrate 110, and the memory element 130 may be disposed in the second region 110B of the substrate 110. In this embodiment, the logic element 120 located in the first region 110A may include, for example, multiple transistors and is operable to perform data write or data read operations on memory cells of the memory element 130 located in the second region 110B.

[0014] In some embodiments, the substrate 110 may comprise a semiconductor material, such as silicon (Si), germanium (Ge), gallium (Ga), any combination thereof, semiconductor on diamond (SOD), silicon on insulator (SOI), or silicon on sapphire (SOS).

[0015] In this embodiment, each transistor of logic element 120 may include, for example, a complementary metal-oxide-semiconductor field-effect transistor (MOSFET), although the present disclosure is not limited to the above example. In some other embodiments, logic element 120 may also include a multi-bridge channel FET (MBCFET), a stacked nanosheet FET, a finFET (FINFET), a gate-all-around FET (GAAFET), or other types of FETs. Also, each transistor of logic element 120 may be an enhancement-mode transistor or a depletion-mode transistor. In some embodiments, by effectively using enhancement-mode and depletion-mode transistors, a basic logic gate (e.g., a NAND gate or a NOR gate) can be implemented with fewer transistors, thereby reducing the components required for the overall circuit.

[0016] In this embodiment, memory device 130 may include dynamic random access memory (DRAM) memory cells, although the disclosure is not limited to the above example. In some embodiments, memory device 130 may include electrically erasable programmable read-only memory (EEPROM) memory cells, ferroelectric memory, or other types of memory.

[0017] In the semiconductor structure 100, the manufacturing processes for the logic elements 120 and the memory elements 130 are compatible, allowing them to be fabricated on the same substrate 110, thereby enabling the logic elements 120 to access nearby memory elements 130 for improved memory access speed. Furthermore, in some embodiments of the present disclosure, each memory element 130 can be controlled and accessed by a single adjacent transistor, thereby reducing the number of transistors required and further improving computational speed. Compared to conventional techniques in which memory elements and logic elements are fabricated separately on different dies and then packaged via an interposer (e.g., silicon) using 2.5D or 3D techniques, the logic elements 120 and memory elements 130 of the semiconductor structure 100 of the present disclosure can be fabricated on the same wafer substrate, thereby achieving better heat dissipation efficiency and operational performance. The semiconductor structure 100 provided by the embodiments of the present disclosure can be applied to attach memory cells to logic circuits or logic units to memory circuits, thereby improving the performance of various circuits.

[0018] In some embodiments, memory device 130 may include a decoding circuit having bit lines and word lines, although the present disclosure is not limited to the above examples. In some embodiments, memory device 130 may further include a logic circuit for performing calculations. In other words, both the logic circuit and the memory circuit can be fabricated on the substrate of the same chip (e.g., forming a computing-in-memory (CIM) structure within a memory chip), thereby mitigating the "memory wall" problem in the prior art.

[0019] In semiconductor structure 100, logic element 120 may include multiple transistors, and memory element 130 may include multiple capacitors. However, in this embodiment, only one FET of logic element 120 and one capacitor of memory element 130 adjacent to the FET are shown in FIG. 1 to better understand the details of the present disclosure.

[0020] As shown in FIG. 1 , the substrate 110 may include a wafer layer 112, an epitaxial layer 114, and a P-well PW1 and an N-well NW1 formed in the epitaxial layer 114. In this embodiment, the logic element 120 may include an NMOSFET disposed in the P-well PW1, and the memory element 130 may include a capacitor disposed in the N-well NW1. The P-well PW1 of the logic element 120 includes N-type heavily doped regions 121A and 121B, which can be used as the source and drain of the transistor, respectively. In this embodiment, in the P-well PW1, N-type lightly doped regions 122A and 122B may be disposed between and adjacent to the N-type heavily doped regions 121A and 121B to improve the thermal conduction efficiency and reliability of the transistor. In this embodiment, in the P well PW1, an indium gallium zinc oxide (IGZO) channel 123 may be disposed between the N-type low concentration regions 122A and 122B, and may be doped with a trivalent element, calcium (Ca), magnesium (Mg), or copper (Cu), to adjust the threshold voltage of the transistor, although the present disclosure is not limited to the above examples. In some embodiments, the channel 123 is made of a silicon germanium material, for example, Si (1-x) Ge x (0≦x≦0.5).

[0021] Additionally, logic element 120 may further include a gate structure 124 disposed in channel 123. In some embodiments, gate structure 124 may include a high-k dielectric layer 1241 and a polycrystalline silicon layer 1242, where high-k dielectric layer 1241 is fabricated from a material such as, but not limited to, hafnium oxide (HfO). Also, as shown in FIG. 1 , semiconductor structure 100 may further include a dielectric layer 126 disposed on substrate 110, where dielectric layer 126 may cover logic element 120. In some embodiments, dielectric layer 126 may include, for example, a silicate glass, including, but not limited to, phosphosilicate glass or borophosphosilicate glass.

[0022] In this embodiment, logic element 120 may further include conductive plugs 125A, 125B, and 125C that penetrate dielectric layer 126. Conductive plugs 125A, 125B, and 125C respectively contact N-type heavily doped region 121A (i.e., the source of the transistor), N-type heavily doped region 121B (i.e., the drain of the transistor), and gate structure 124. In some embodiments, multiple metal line layers (not shown in FIG. 1 ) may be disposed in logic element 120, and the sources, drains, and gates of the transistors of logic element 120 are electrically connected to lines in the metal line layers via conductive plugs 125A, 125B, and 125C.

[0023] In this embodiment, the conductive plugs 125A, 125B, and 125C may have a multi-layer structure. For example, the conductive plug 125A may include a barrier layer 1251, a copper-phosphorus alloy layer 1252, and an electrode metal layer 1253. The barrier layer 1251 and the copper-phosphorus alloy layer 1252 may be formed along the contours of a recess in the dielectric layer 126, and the electrode metal layer 1253 may fill the recess in the copper-phosphorus alloy layer 1252, such that the copper-phosphorus alloy layer 1252 is sandwiched between the electrode metal layer 1253 and the barrier layer 1251. In some embodiments, for example, the barrier layer 1251 may include titanium nitride (TiN), and the electrode metal layer 1253 may include Cu, tungsten (W), cobalt (Co), or ruthenium (Rh).

[0024] 1 , memory element 130 may include a bottom electrode 132, a top electrode 133, and dielectric layers 134 and 135 disposed between bottom electrode 132 and top electrode 133. Bottom electrode 132 may be disposed above substrate 110, and top electrode 133 may be disposed above substrate 110 and bottom electrode 132. In this embodiment, memory element 130 may include, for example, a DRAM memory cell, and top electrode 133, bottom electrode 132, and the dielectric material therein (including dielectric layers 134 and 135) may form a capacitor for storing charge. In some embodiments, dielectric layers 134 and 135 have a high dielectric constant (k) and may be fabricated from a material such as hafnium oxide (HfO2).

[0025] 1, the memory element 130 may be disposed in the second region 110B of the substrate 110 at the drain of the transistor of the logic element 120, and the top electrode 133 of the memory element 130 may cover the conductive plug 125B along the vertical direction (e.g., the Z direction). In other words, the top electrode 133 of the memory element 130 may be electrically connected to the drain of the transistor of the logic element 120 (i.e., the N-type heavily doped region 121B).

[0026] In this embodiment, the lower electrode 132 may include a metal layer 1321, a copper-phosphorus alloy layer 1322, and a barrier layer 1323. The copper-phosphorus alloy layer 1322 may extend along the contour of the metal layer 1321 and surround it, and the barrier layer 1323 may also surround the copper-phosphorus alloy layer 1322 along the contour of the copper-phosphorus alloy layer 1322. FIG. 2 is a partially enlarged schematic view of the barrier layer 1323, the copper-phosphorus alloy layer 1322, and the metal layer 1321 located in region 110B in FIG. 1 according to one embodiment of the present disclosure. As shown in FIG. 2, due to the properties of the copper-phosphorus alloy, the surface of the copper-phosphorus alloy layer 1322 has a needle-like structure, which can increase the surface area of ​​the lower electrode 132 and increase the capacitance of the capacitor formed by the upper electrode 133 and the lower electrode 132. Similarly, the upper electrode 133 may include a metal layer 1331, a copper-phosphorus alloy layer 1332, and a barrier layer 1333. The copper-phosphorus alloy layer 1332 may extend along the contour of the metal layer 1331 and surround the metal layer 1331, and the barrier layer 1333 may also extend along the contour of the copper-phosphorus alloy layer 1332 and surround the copper-phosphorus alloy layer 1332.

[0027] In this embodiment, a shallow trench isolation structure 138 made of a material including undoped silicate glass (USG) may further be formed in the N-well NW1 in the second region 110B of the substrate 110. In this manner, the bottom electrode 132 can be isolated from the N-well NW1 of the substrate 110 by the shallow trench isolation structure 138.

[0028] As shown in FIG. 1 , the metal layer 1321 may have a comb-like structure including multiple protrusions 1321A, and the metal layer 1331 may also have a comb-like structure including multiple protrusions 1331A. The protrusions 1321A extend toward the upper electrode 133, and the protrusions 1331A extend toward the lower electrode 132. The multiple protrusions 1321A and the multiple protrusions 1331A may be interlaced. This interlacing comb-like structure design can increase the effective overlap surface area between the metal layer 1321 and the metal layer 1331, thereby increasing the capacitance value of the memory element 130. In some embodiments, the multiple protrusions 1321A may be arranged in an array, and the multiple protrusions 1331A may also be arranged in an array, but the present disclosure is not limited to the above examples.

[0029] 1, substrate 110 may include a first region 110A in which logic elements 120 are formed and a second region 110B in which memory elements 130 are formed. As shown in FIG. 1, N-type heavily doped regions 121A and 121B may be disposed in a P well PW1 of first region 110A, N-type lightly doped regions 122A and 122B may be disposed between and adjacent to N-type heavily doped regions 121A and 121B, and an IGZO channel 123 may be disposed between N-type lightly doped regions 122A and 122B. In some embodiments, channel 123 may be a silicon germanium channel comprising a silicon germanium material.

[0030] Also, in the semiconductor structure 100, the memory element 130 may be formed in the second region 110B where a P-type transistor is usually formed. More specifically, the shallow trench isolation structure 138 may be formed in the N-well NW1, and the bottom electrode 132 may be formed in the shallow trench isolation structure 138. In this embodiment, the shallow trench isolation structure 138 may be, for example, a USG.

[0031] In FIG. 1 , a gate structure 124 may be formed in the channel 123. After the gate structure 124 is formed, at least one dielectric layer 126 may be further formed. The dielectric layer 126 may include, for example, silicate glass. The gate structure 124 may also include a high-k dielectric layer 1241 and a polycrystalline silicon layer 1242. In some embodiments, the high-k dielectric layer 1241 may include HfO2 and be fabricated by atomic layer deposition (ALD) to improve its reliability. The high-k dielectric layer 1241 may have a thickness of, for example, 5 nm to 10 nm, although the present disclosure is not limited to this example. In some embodiments, the high-k dielectric layer 1241 may include a two-layer stacked structure of zirconium dioxide (ZrO2) and HfO2.

[0032] 1, the dielectric layer 126 on the N-type heavily doped regions 121A and 121B and on the gate structure 124 (i.e., the source, drain, and gate of the transistor) may be formed with openings, and the dielectric layer 126 in the second region 110B may be formed with a deep trench structure (larger openings). In such a case, by a lift-off process, the barrier layer 1251 and the copper-phosphorus alloy layer 1252 are sequentially deposited in the openings of the dielectric layer 126 in the first region 110A, and the barrier layer 1323 and the copper-phosphorus alloy layer 1322 are sequentially deposited in the deep trenches of the dielectric layer 126 in the second region 110B.

[0033] Next, the electrode metal layer 1253 may be continuously filled in the openings of the dielectric layer 126 in the first region 110A to form electrodes connected to the source, drain, and gate of the transistor. In this embodiment, the electrode metal layer 1253 may include, for example, Cu, W, Co, or Rh. Also, the metal layer 1321 may be formed on the barrier layer 1323 and the copper-phosphorus alloy layer 1322 in the second region 110B, and the metal layer 1321 may be partially removed by lithography and lift-off processes, thereby forming a plurality of protrusions 1321A in the metal layer 1321. In some embodiments, the metal layer 1321 may be made of a material such as Cu, W, Co, or Rh and may be manufactured using the same manufacturing process as the electrode metal layer 1253. Therefore, the manufacturing process for the capacitor of the memory element 130 is compatible with the manufacturing process for the transistor of the logic element 120. In this embodiment, the copper-phosphorus alloy layer 1322 and the barrier layer 1323 may be sequentially formed on the metal layer 1321, so that the copper-phosphorus alloy layer 1322 and the barrier layer 1323 can extend along the contour of the metal layer 1321 and completely protect the metal layer 1321. In some embodiments, a copper-phosphorus alloy layer and a barrier layer (not shown) may further be formed above the electrode metal layer 1253.

[0034] FIG. 3 shows a cross-sectional view of the semiconductor structure 100 in FIG. 1 taken along section line A1-A1' in FIG.

[0035] In the embodiment in FIG. 3, the plurality of protrusions 1321A may be arranged in an array to increase the surface area of ​​the lower electrode 132, but the present disclosure is not limited to the above example.

[0036] In FIG. 1, a dielectric layer 134 may be formed in the recesses between the protrusions 1321A to fill the recesses. In some embodiments, the dielectric layer 134 may be formed by depositing HfO2 by ALD. Because HfO2 has a high dielectric constant of 26-30, the memory device 130 can achieve higher capacitance values ​​in the same area compared to memory devices using conventional materials. Additionally, the high dielectric constant dielectric layer 134 formed by ALD can improve reliability and help reduce capacitance leakage, further improving the performance of the memory device 130.

[0037] The dielectric layer 135 may be formed on the protrusions 1321A by a lithography process and may be made of the same material as that of the dielectric layer 134. Then, the upper electrode 133 (including the barrier layer 1333, the copper-phosphorus alloy layer 1332 and the metal layer 1331) may be formed on the dielectric layers 134 and 135. In this way, the protrusions 1331A of the metal layer 1331 are staggered with the protrusions 1321A of the lower electrode 132.

[0038] The presence of alternating protrusions 1321A and 1331A on the metal layer 1321 of the bottom electrode 132 and the metal layer 1331 of the top electrode 133 increases the effective overlapping surface area between the bottom electrode 132 and the top electrode 133. In this way, compared to conventional structures, the memory element 130 of the present disclosure can increase the capacitance value of the capacitor within the same bottom area, thereby increasing the memory density and capacity within a unit bottom area of ​​the semiconductor structure 100. In addition, because the transistors of the logic element 120 may be electrically connected to the capacitors of adjacent memory elements 130, the parasitic capacitance of the bit line can be more easily reduced, thereby reducing heat and power losses generated when charging / discharging the capacitor.

[0039] FIG. 4 illustrates a schematic diagram of a semiconductor structure 300 according to one embodiment of the present disclosure. Compared to the semiconductor structure 100, the semiconductor structure 300 differs in that the memory element 330 of the semiconductor structure 300 may include an EEPROM memory cell. However, the memory cell structure differs from the silicon-oxide-nitride-oxide-silicon (SONOS) floating gate used in typical EEPROMs. In this embodiment, a copper-phosphorus alloy layer having multiple protruding structures may be added to the floating gate of the memory cell of the memory element 330 to enhance the electric field for write and erase operations, thereby making the operation of the memory element 330 more efficient. Also, similar to the semiconductor structure 100, the logic element 320 and the memory element 330 in the semiconductor structure 300 are fabricated using compatible fabrication processes, allowing them to be fabricated on the same wafer substrate using the same fabrication process.

[0040] The semiconductor structure 300 includes a substrate 310, a logic element 320, and a memory element 330. The substrate 310 has a first region 310A and a second region 310B laterally adjacent to the first region 310A. The logic element 320 may be disposed in the first region 310A of the substrate 310, and the memory element 330 may be disposed in the second region 310B of the substrate 310.

[0041] In this embodiment, the substrate 310 may include a wafer layer 312, an epitaxial layer 314, and P-wells PW1 and PW2 and an N-well NW1 formed in the epitaxial layer 314. The logic element 320 may include multiple transistors. For example, as shown in FIG. 4 , the logic element 320 may include an N-type transistor M1N and a P-type transistor M1P. The N-type transistor M1N may include a P-well PW1, N-type heavily doped regions 321A and 321B, a gate structure 324A, and conductive plugs 325A and 325B. The P-type transistor M1P may include an N-well NW1, P-type heavily doped regions 321C and 321D, a gate structure 324B, and conductive plugs 325C and 325D.

[0042] The N-type heavily doped regions 321A and 321B may be disposed on two opposite sides of the P-well PW1 and function as the source and drain of the transistor M1N, respectively. In this embodiment, to improve the reliability of the N-type transistor M1N, the transistor M1N may further include N-type lightly doped regions 322A and 322B disposed between the N-type heavily doped regions 321A and 321B and adjacent to the N-type heavily doped regions 321A and 321B. The gate structure 324A of the transistor M1N may be disposed in the P-well PW1 and between the N-type heavily doped regions 321A and 321B. The gate structure 324A includes an oxide layer 3244 (e.g., a silicon dioxide (SiO) layer formed by ALD), a polycrystalline silicon layer 3245, a barrier layer 3241 (e.g., including TiN), a copper-phosphorus alloy layer 3242, and an electrode metal layer 3243 (e.g., including Cu, W, Co, or Rh). Conductive plugs 325A and 325B may penetrate the SiO layer 342 and a silicate glass layer 344 (e.g., phosphosilicate glass or borophosphosilicate glass) formed on the substrate 310 and be electrically connected to the source and drain (i.e., N-type heavily doped regions 321A and 321B) of the transistor M1N. In this embodiment, the conductive plugs 325A and 325B may also have a multi-layer structure. For example, the conductive plug 325A may include a barrier layer 3251 (eg, TiN), a copper-phosphorus alloy layer 3252, and an electrode metal layer 3253 (eg, including Cu, W, Co, or Rh).

[0043] The P-type transistor M1P may include an N-well NW1, P-type heavily doped regions 321C and 321D, a gate structure 324B, and conductive plugs 325C and 325D. The P-type heavily doped regions 321C and 321D may be disposed on two opposite sides of the N-well NW1 and function as the source and drain of the transistor M1P, respectively. In this embodiment, to improve the reliability of the P-type transistor M1P, the transistor M1P may further include P-type lightly doped regions 322C and 322D disposed between the P-type heavily doped regions 321C and 321D and adjacent to the P-type heavily doped regions 321C and 321D. The gate structure 324B of the transistor M1P may be disposed in the N-well NW1 and between the P-type heavily doped region 321C and the P-type heavily doped region 321D. The gate structure 324B may have the same multi-layer structure as the gate structure 324A, and the conductive plugs 325C and 325D may also have the same multi-layer structure as the gate structures of the conductive plugs 325A and 325B. Furthermore, the conductive plugs 325C and 325D may penetrate the SiO layer 342 and the silicate glass layer 344 on the substrate 310 and be electrically connected to the source and drain (i.e., the P-type heavily doped regions 321C and 321D) of the transistor M1P.

[0044] The memory element 330 may include a source 334A, a drain 334B, an oxide layer 331, copper-phosphorus alloy layers 333 and 337 (having needle-like structures arranged in an array) capable of rapidly absorbing or releasing electrons, a charge storage layer 338, an oxide layer 336, a control gate 332, and conductive plugs 339A and 339B. In this embodiment, the memory element 330 may be disposed in a P-well PW2, and the source 334A and the drain 334B may be disposed in N-type heavily doped regions of the P-well PW2. Also, as shown in FIG. 4 , the memory element 330 may further include N-type lightly doped regions 335A and 335B disposed between the source 334A and the drain 334B and adjacent to the source 334A and the drain 334B.

[0045] An oxide layer 331 may be disposed on the substrate 310 between the source 334A and the drain 334B. In some embodiments, the oxide layer 331 may comprise SiO and be formed by ALD. In such cases, the oxide layer 331 may have higher reliability and therefore help prevent charge from escaping from the charge storage layer 338. Additionally, the oxide layer 331 formed by ALD may have a smaller thickness, which may further reduce the operating voltage required for read and write operations performed by the memory element 330.

[0046] 4 , the copper-phosphorus alloy layer 333 may be disposed on the oxide layer 331, the charge storage layer 338 may be disposed on the copper-phosphorus alloy layer 333 and the oxide layer 331, and the copper-phosphorus alloy layer 337 may be disposed on the charge storage layer 338. In other words, the copper-phosphorus alloy layers 333 and 337 (having needle-like structures arranged in an array) that can quickly absorb or release electrons may be disposed above and below the charge storage layer 338, respectively. Also, the oxide layer 336 may be disposed on the charge storage layer 338 and the copper-phosphorus alloy layer 337. In such a case, the copper-phosphorus alloy layer 333 is sandwiched between the oxide layer 331 and the charge storage layer 338, and the copper-phosphorus alloy layer 337 is sandwiched between the oxide layer 336 and the charge storage layer 338. In some embodiments, oxide layer 331 may be referred to as a first oxide layer, oxide layer 336 may be referred to as a second oxide layer, copper-phosphorus alloy layer 333 may be referred to as a first copper-phosphorus alloy layer, and copper-phosphorus alloy layer 337 may be referred to as a second copper-phosphorus alloy layer, although the present disclosure is not limited to the above examples.

[0047] In this embodiment, the copper-phosphorus alloy layer 333 has a plurality of protruding structures facing the copper-phosphorus alloy layer 337, and the copper-phosphorus alloy layer 337 has a plurality of protruding structures facing the copper-phosphorus alloy layer 333. Figure 5 shows a top view of the copper-phosphorus alloy layer 333 obtained by cutting along the cutting line A2-A2' in Figure 4.

[0048] In this embodiment, after an oxide layer 331 (e.g., SiO2 with a thickness of 1 nm to 2 nm) is formed between the source 334A and the drain 334B on the substrate 310 by ALD, a SiN layer may be deposited on the oxide layer 331 as the charge storage layer 338. An array of needle-like holes may then be formed in the SiN layer by a lithography process, and a copper-phosphorus alloy layer 333 may be formed in the holes in the SiN layer by a lift-off process. In some embodiments, before the copper-phosphorus alloy layer 333 is formed, a barrier layer (not shown) may first be filled in the holes to prevent metal diffusion and contamination. In some embodiments, the barrier layer may be made of a material such as TiN.

[0049] After the copper-phosphorus alloy layer 333 is formed, another SiN layer is deposited on the copper-phosphorus alloy layer 333 and the original SiN layer, and the two sequentially formed upper and lower SiN layers become the charge storage layer 338. Then, multiple holes are formed in the newly formed SiN layer, and then the copper-phosphorus alloy layer 337 is formed in the holes of the SiN layer by a lift-off process. In this embodiment, the protruding structures of the copper-phosphorus alloy layer 333 and the copper-phosphorus alloy layer 337 may be alternately arranged. For example, the protruding structures of the copper-phosphorus alloy layer 333 and the copper-phosphorus alloy layer 337 may not overlap in the X-axis direction. In this embodiment, the protruding structures of the copper-phosphorus alloy layer 333 and the copper-phosphorus alloy layer 337 have a small radius of curvature, which helps to strengthen the electric field for capturing or releasing electrons, thereby improving the efficiency of the write operation and the erase operation of the EEPROM (i.e., the memory element 330).

[0050] In the above embodiment, the charge storage layer 338 may include, for example, SiN, but the present disclosure is not limited to the above example. In some embodiments, the charge storage layer 338 may include SiN, hafnium aluminum oxide (HaAlO), HfO, aluminum oxide (AlO), or a combination thereof. For example, the charge storage layer 338 may include HaAlO. Because the energy band difference between the conduction bands of HaAlO and Si is only 1.63 eV, electrons moving within the channel 329 of the memory element 330 can tunnel more easily into the conduction band of the charge storage layer 338 under the same gate voltage.

[0051] The charge storage layer 338 may also contain HfO. The HfO structure helps trap electrons, helping to solve the problem of excessive erasure, thereby improving the performance of the memory element 330. Furthermore, a copper-phosphorus alloy is used as an oxygen scavenger, creating two positively charged oxygen vacancies at the lattice sites of HfO. Therefore, the copper-phosphorus alloy layers 333 and 337 disposed on the upper and lower sides of the charge storage layer 338 can improve the charge storage capability of HfO. Meanwhile, the copper-phosphorus alloy layers 333 and 337 can also prevent oxygen atoms from escaping from HfO and diffusing into the substrate 310, thereby preventing an increase in the thickness of silicon dioxide (SiO) and mitigating the rate of performance degradation of the memory element 330. In other words, the copper-phosphorus alloy layers 333 and 337 containing HfO and the charge storage layer 338 enable the memory element 330 to achieve better performance and reliability.

[0052] In this embodiment, the control gate 332 may also include a multilayer structure. For example, the control gate 332 may include a barrier layer 3321, a copper-phosphorus alloy layer 3322 (e.g., a third copper-phosphorus alloy layer), and a gate electrode layer 3323, which are sequentially formed on the oxide layer 336. The barrier layer 3321 may prevent the metal of the gate electrode layer 3323 from diffusing into the oxide layer 336, and the copper-phosphorus alloy layer 3322 may function as a wetting layer for plating the gate electrode layer 3323. In some embodiments, for example, the barrier layer 3321 may include TiN, and the gate electrode layer 3323 may include Cu, W, Co, or Rh. Also, in this embodiment, the conductive plugs 339A and 339B may also include a multilayer structure. For example, the conductive plug 339A may include a barrier layer 3391, a copper-phosphorus alloy layer 3392, and an electrode metal layer 3393.

[0053] The operations of the memory device 330, including the write operation, the erase operation (including two types), and the read operation, are described in detail below.

[0054] When a write operation is performed, the control gate 332 and the drain 334B receive a positive voltage (e.g., a power supply voltage), and the source 334A receives a ground voltage. In this case, a vertically downward (e.g., negative Z-axis) electric field is generated between the control gate 332 and the substrate 310. When electrons are accelerated along the channel 329 from the source 334A toward the drain 334B and collide with the junction region of the drain 334B, a hot electron injection effect is induced, whereby some electrons are attracted by the vertically downward electric field in the channel 329, pass through the oxide layer 331, and enter the charge storage layer 338. Because the electrons entering the charge storage layer 338 do not have excess energy, these electrons are stored in the charge storage layer 338 after the write operation, thereby placing the memory element 330 in a written state. In this embodiment, the copper-phosphorus alloy layers 333 and 337 have an array of needle-like protrusion structures, which can increase both the charge density at the tips and the vertical downward electric field in the channel 329, so that electrons passing through the channel 329 can be captured and quickly pass through the oxide layer 331 into the charge storage layer 338. This can shorten the time for a write operation and improve the performance of the memory element 330.

[0055] When a first type of erase operation is performed, the control gate 332 receives a ground voltage or a negative voltage, and the source 334A and the drain 334B receive a positive voltage (e.g., a power supply voltage). In this case, a vertically upward (e.g., positive Z-axis) electric field is generated between the control gate 332 and the substrate 310, and electrons present in the charge storage layer 338 are attracted to the copper-phosphorus alloy layer 333 (which can cause a tip effect that can strengthen and concentrate the vertically upward electric field) and quickly return to the channel 329 between the source 334A and the drain 334B, erasing the written state of the memory element 330.

[0056] In some other embodiments, when a second type of erase operation is performed, the control gate 332 receives a positive voltage, and simultaneously, the source 334A and the drain 334B receive a negative voltage. In such a case, the strong vertical downward electric field can further attract electrons present in the charge storage layer 338 to the copper-phosphorus alloy layer 337 (which can cause a tip effect that can strengthen and concentrate the vertical downward electric field), thereby allowing the trapped electrons to quickly pass through the control gate 332 and erase the written state of the memory element 330. In other words, in the second type of erase operation, the memory element 330 of the present disclosure can attract electrons present in the charge storage layer 338 to the control gate 332, thereby allowing the electrons to pass through another oxide layer 336, reducing the number of times the electrons pass through the oxide layer 331, and prolonging the endurance of the memory element 330.

[0057] When a read operation is performed, the control gate 332 receives a ground voltage, the drain 334B receives a second positive voltage (e.g., a threshold voltage), and the source 334A receives a ground voltage. The current flowing in the channel from the drain 334B to the source 334A is measured under the above conditions. If the measured current is less than a predetermined threshold, it means that electrons are accumulated in the charge storage layer 338, and the memory element 330 is determined to be in a written state (e.g., represented by a value of "1"). Conversely, if the measured current is greater than another predetermined threshold, it means that not enough electrons have accumulated in the charge storage layer 338, and the memory element 330 is determined to be in an erased or unwritten state (e.g., represented by a value of "0").

[0058] In some embodiments, the memory element 330 may have two or more memory states. That is, the memory element 330 may be a multi-level cell (MLC) capable of storing multiple bits. For example, the memory element 330 may be determined to be in one of multiple memory states depending on the number of electrons in the charge storage layer 338. In such a case, the state of the number of electrons stored in the memory element 330 may be determined depending on the magnitude of the current rating read on the channel. In some embodiments, there may be four (or eight) states depending on the number of electrons stored in the memory element 330, and the memory element 330 may be used to store two (or three) bits of data.

[0059] 6 shows a schematic diagram of a semiconductor structure 400 according to one embodiment of the present disclosure. The semiconductor structure 400 further includes IGZO or silicon germanium (e.g., Si) in the channel between the source and drain of the transistors of the logic and memory elements. (1-x) Ge x , where 0≦x≦0.5) may be added. For example, transistor M1N′ of logic element 420 may further include channel 421A between source 321A and drain 321B, transistor M1P′ of logic element 420 may further include channel 421B between source 321C and drain 321D, and memory element 430 may further include channel 431 between source 334A and drain 334B. In this embodiment, channels 421A, 421B, and 431 may be IGZO channels or silicon germanium channels.

[0060] Compared to enhancement-mode elements made of single-crystal silicon, IGZO is a depletion-mode element, offering increased carrier concentration and electron mobility, which not only increases the speed of read and write operations but also improves conductivity and reduces the operating voltage and size of transistors. Generally, the surface of IGZO absorbs oxygen from the environment, allowing electrons (i.e., carriers) therein to bind, thereby enabling transistors to have higher threshold voltages. Therefore, in some embodiments, channels 421A, 421B, and 431 may be IGZO channels, which may be further doped with Ca, Mg, or Cu to adjust the threshold voltages of logic element 320 and memory element 330. In this manner, the transistors therein may also be configured as enhancement-mode transistors, thereby achieving better power savings.

[0061] In some embodiments, the logic elements and memory elements may include FINFETs. In this embodiment, the memory elements may be formed as EEPROM units based on the structure of FINFETs. FIG. 7 shows a schematic diagram of a memory element 530 according to one embodiment of the present disclosure. The memory element 530 includes N memory cells 530_1 through 530_N connected in parallel, where N is an integer greater than 1. Each of the memory cells 530_1 through 530_N includes a fin structure 532 in a substrate 510 and a control gate 539 that controls a fin structure channel.

[0062] 7, each of the memory cells 530_1 to 530_N may further include a source 52 and a drain 53 disposed at two opposite ends of the fin structure 532. In this embodiment, the fin structure 532 between the source 52 and the drain 53 may be designed as a narrow nanoscale transistor channel. In this case, the narrow width of the channel between the source 52 and the drain 53 and the use of a copper-phosphorus alloy array structure (not shown) in the charge storage region can increase the probability of collision between electrons and crystal lattices in the channel or junction region, thereby increasing the incidence of hot electron injection, reducing the operating voltage and operating time required for the memory element 530, and improving the overall performance of the memory element 530.

[0063] Additionally, to enable the memory device 530 to generate sufficient current to facilitate a read operation, the memory cells 530_1-530_N within the memory device 530 may be connected in parallel. For example, as shown in FIG. 7 , the sources 52 of the memory cells 530_1-530_N may be connected to each other by a conductive line 51A, and the drains 53 of the memory cells 530_1-530_N may be connected to each other by a conductive line 51B. In other words, the memory cells 530_1-530_N receive the same voltage, allowing write, erase, and read operations to be performed simultaneously. In some embodiments, the conductive lines 51A and 51B may be fabricated from a material such as a multilayer structure including a TiN layer, a copper-phosphorus alloy layer, and a metal layer (Cu, W, Co, or Rh), and the copper-phosphorus alloy layer may be disposed between the TiN layer and the metal layer, although the present disclosure is not limited thereto.

[0064] In this embodiment, the channels of the logic and memory elements (e.g., the channels between the source 52 and the drain 53) are made of silicon germanium material (e.g., Si (1-x) Ge x, 0≦x≦0.5). Compared to silicon-based channels, channels made using silicon germanium materials can provide increased mobility (e.g., 40% increase), increased operating frequency (e.g., 10% increase), and reduced threshold voltage. Additionally, using silicon germanium as a channel material can improve negative-bias temperature instability (NBTI) of the threshold voltage of P-type transistors.

[0065] 8 shows a cross-sectional view of the memory element 530 taken along the line A3-A3′ in FIG. 7. In this embodiment, the memory cells 530_1 to 530_N may have the same structure and can operate synchronously. For example, the memory cell 530_1 may include an oxide layer 533 (e.g., including SiO), a copper-phosphorus alloy layer 534, a charge storage layer 535 (e.g., including SiN, HaAlO, HfO, AlO, or a combination thereof), a copper-phosphorus alloy layer 536, an oxide layer 537, and a control gate 539 (e.g., including Cu, W, Co, or Rh), which are sequentially stacked on the fin structure 532 and surround the top and sidewalls of the fin structure 532. In some embodiments, oxide layer 533 may be a first oxide layer, copper-phosphorus alloy layer 534 may be a first copper-phosphorus alloy layer, oxide layer 537 may be a second oxide layer, and copper-phosphorus alloy layer 536 may be a second copper-phosphorus alloy layer, although the present disclosure is not limited thereto.

[0066] In this embodiment, the details of the operation of the memory device 530 are the same as those of the memory device 330 described above, so a duplicated description will be omitted here.

[0067] In addition to the DRAM units of memory device 130 and the EEPROM units of memory devices 330, 430 and 530 described above, the memory devices may also be implemented by ferroelectric memory cells whose manufacturing process is compatible with that of the transistors of the logic devices.

[0068] 9 shows a schematic diagram of a semiconductor structure 600 according to one embodiment of the present disclosure. The memory element 630 of the semiconductor structure 600 is a ferroelectric memory cell.

[0069] The semiconductor structure 600 includes a substrate 610, a logic element 620, and a memory element 630. The logic element 620 may be disposed in a first region 610A of the substrate 610, and the memory element 630 may be disposed in a second region 610B of the substrate 610. The substrate 610 may include a wafer layer 612, an epitaxial layer 614, and P-wells PW1, PW2, and an N-well NW1 formed in the epitaxial layer 614. The logic element 620 may include an N-type transistor M1N and a P-type transistor M1P formed in the P-well PW1 and the N-well NW1, respectively. The N-type transistor M1N and the P-type transistor M1P have the same structures as the transistors of the logic element 320 of the semiconductor structure 300, and therefore will not be described again here.

[0070] The memory element 630 may include a source 634A and a drain 634B disposed in a P well PW2, an oxide layer 631, a ferroelectric material layer 636 (having a thickness of 5 nm to 15 nm) having an array structure, a copper-phosphorus alloy layer 633, and a control gate 632. The source 634A and the drain 634B are N-type heavily doped regions in the P well PW2. In this embodiment, to improve the reliability of the memory element 630, N-type lightly doped regions 635A and 635B may be disposed between the source 634A and the drain 634B and adjacent to the source 634A and the drain 634B.

[0071] An oxide layer 631 is disposed on the substrate 610 between the source 634A and the drain 634B. FIG. 10 shows a cross-sectional view of the ferroelectric material layer 636 taken along the line A4-A4′ in FIG. 9 . In this embodiment, the ferroelectric material layer 636 may be disposed on the oxide layer 631 (having a thickness of 1 nm to 5 nm) and may include an array formed by a plurality of protrusion structures, as shown in FIG. 10 . A copper-phosphorus alloy layer 633 may be formed on the oxide layer 631 and fill the gaps around the ferroelectric material layer 636 in the array structure. A control gate 632 may include an electrode metal (e.g., Cu, W, Co, or Rh) and may be disposed on the copper-phosphorus alloy layer 633 and fill the recesses in the copper-phosphorus alloy layer 633. In this case, the copper-phosphorus alloy layer 633 is disposed between the oxide layer 631 and the control gate 632, and the ferroelectric material layer 636 of the array structure is disposed between the copper-phosphorus alloy layer 633 and the oxide layer 631. In another embodiment, the ferroelectric material layer 636 and the copper-phosphorus alloy layer 633 may be a planar structure (not shown) that has uniform thickness and is stacked sequentially.

[0072] In this embodiment, the ferroelectric material layer 636 may include HfO. Compared to conventional perovskite-type ferroelectric materials, HfO is more compatible with CMOS fabrication processes. Furthermore, HfO can maintain efficient and high-speed ferroelectricity even at a thickness of 5 nm to 15 nm. In some embodiments, Si, Zr, Al, N, La (lanthanum), or Ti may be added to the HfO during deposition to bond with the HfO to form an electric dipole. However, due to the low crystallization temperature of HfO, the oxide layer 631 may crystallize during the fabrication process of the semiconductor structure 600, which may allow electrons to easily tunnel, resulting in a large leakage current. In this embodiment, to avoid this problem, when forming the oxide layer 631, finer SiO is formed by ALD, thereby reducing the generation of leakage current.

[0073] Because the copper-phosphorus alloy layer 633 of the memory element 630 can extend into the holes of the ferroelectric material layer 636, the ferroelectric material layer 636 having an array of protrusion structures can be induced with an enhanced electric field in multiple directions during a write operation, thereby accelerating the rate of electric dipole polarization. Furthermore, because the copper-phosphorus alloy layer 633 can function as an oxygen scavenger, the number of lattice sites for HfO2 can be increased, strengthening the electric dipole effect and thereby reducing the operating voltage required for the memory element 630. Meanwhile, the oxygen scavenging ability of the copper-phosphorus alloy layer 633 can prevent oxygen atoms of HfO2 from diffusing into the substrate 610, thereby preventing an increase in the thickness of SiO2 and mitigating the rate of performance degradation of the ferroelectric memory cell.

[0074] Details of the operation of memory device 630, including write and read operations, are described below.

[0075] In this embodiment, the memory element 630 can support two write operation modes corresponding to different memory states. For example, a first type of write operation provides the ferroelectric material layer 636 with a first dipole polarization direction (e.g., a negative Z-axis direction), and a second type of write operation provides the ferroelectric material layer 636 with a second dipole polarization direction (e.g., a positive Z-axis direction). In some embodiments, when the ferroelectric material layer 636 has the first dipole polarization direction, the memory element 630 is in a first memory state (e.g., a logic "0"); conversely, when the ferroelectric material layer 636 has the second dipole polarization direction, the memory element 630 is in a second memory state (e.g., a logic "1").

[0076] When a first type of write operation is performed, the source 634A and the drain 634B receive a ground voltage or a negative voltage, and the control gate 632 receives a positive voltage (e.g., a threshold voltage). In this manner, the ferroelectric material layer 636, surrounded on three sides by the copper-phosphorus alloy layer 633, receives downward (i.e., negative Z-axis) electric fields from multiple directions, such as from above (positive Z-axis), left (negative X-axis), and right (positive X-axis), thereby allowing the HfO2 to quickly generate a downward electric dipole. At this point, the memory element 630 is written to have a first memory state (e.g., logic "0").

[0077] When a second type of write operation is performed, the source 634A and the drain 634B receive a positive voltage (e.g., a threshold voltage), and the control gate 632 receives a ground voltage or a negative voltage. In this manner, the ferroelectric material layer 636, surrounded on three sides by the copper-phosphorus alloy layer 633, receives upward electric fields (i.e., in the direction of the Z-axis) from multiple directions, which allows the HfO2 to quickly generate upward electric dipoles. At this point, the memory element 630 is written to have a second memory state (e.g., logic "1").

[0078] When a read operation is performed, the control gate 632 receives a ground voltage, the drain 634B receives a positive voltage (e.g., a threshold voltage), and the source 634A receives a ground voltage. When the memory element 630 is written to have a first memory state (i.e., the electric dipole of the ferroelectric material layer 636 is oriented downward), only a very small current (close to zero current) is generated in the channel. However, when the memory element 630 is written to have a second memory state (i.e., the electric dipole of the ferroelectric material layer 636 is oriented upward), a large current is generated in the channel. Therefore, the memory state of the memory element 630 can be determined by reading the magnitude of the read channel current.

[0079] 11 shows a schematic diagram of a semiconductor structure 700 according to one embodiment of the present disclosure. The semiconductor structure 700 may further include IGZO (or silicon germanium) doping in the channels between the source and drain of the transistor structures of the logic elements and between the source and drain of the memory elements. For example, the transistor M1N′ of the logic element 720 may further include a channel 721A disposed in the substrate 610 between the source 621A and the drain 621B, the transistor M1P′ may further include a channel 721B disposed in the substrate 610 between the source 621C and the drain 621D, and the memory element 730 may further include a channel 731 disposed in the substrate 610 between the source 634A and the drain 634B. In some embodiments, the channels 721A, 721B, and 731 are IGZO or silicon germanium, e.g., Si (1-x) Ge x (where 0≦x≦0.5) may be added.

[0080] Compared to amorphous silicon, IGZO has an increased carrier concentration and electron mobility, which improves conductivity and thereby reduces the operating voltage and size of the transistor. The IGZO channel 731 can also prevent leakage current and improve response speed of the ferroelectric nonvolatile memory cell. In some embodiments, the IGZO channel 731 can be doped with a trivalent or pentavalent element to adjust the threshold voltage according to requirements. In some embodiments, the transistors M1N′ and M1P′ can be designed to be enhancement-mode or depletion-mode transistors, as needed. Effective use of enhancement-mode or depletion-mode transistors can reduce the number of transistors required for a logic gate (e.g., a NAND gate or a NOR gate), thereby reducing the total required circuit area.

[0081] The IGZO channel 731 also supports the operation of the memory element 730. For example, when a first type of write operation is performed, the source 634A and the drain 634B receive a ground voltage or a negative voltage, and the control gate 632 receives a positive voltage. In this manner, the ferroelectric material layer 636, surrounded on three sides by the copper-phosphorus alloy layer 633, receives downward (i.e., opposite to the Z-axis) electric fields from multiple directions, such as from above (the Z-axis direction), from the left (the opposite to the X-axis direction), and from the right (the X-axis direction). This allows the HfO2 to rapidly generate a downward electric dipole, thereby writing the memory element 730 to a first memory state (e.g., logic "0"). Furthermore, due to the influence of the downward electric dipole, electron holes are generated on the upper surface of the IGZO channel 731 near the oxide layer 631 as a result of the induction of the electric field, forming an NPN transistor. When a first type of write operation is performed, the voltages of the source 634A and the drain 634B are at ground voltage (or a negative voltage), so the junction of the P well PW2 to the source 634A and the drain 634B is not forward biased, thereby preventing the holes in the channel from moving, indicating an off state. In this embodiment, such an off state may serve as a basis for determining the data state when a subsequent read operation is performed.

[0082] In contrast, when a second-type write operation is performed, the source 634A and the drain 634B receive a positive voltage, and the control gate 632 receives a negative voltage. In this manner, the ferroelectric material layer 636, surrounded on three sides by the copper-phosphorus alloy layer 633, receives an upward electric field (i.e., in the Z-axis direction) from multiple directions, which allows the HfO2 to rapidly generate an upward electric dipole, and the memory element 630 is rapidly written to the second memory state (e.g., logic "1"). Furthermore, due to the influence of the upward electric dipole in the ferroelectric material layer 636 and the induction of the electric field therein, more electrons are generated at the top surface of the IGZO channel 731 close to the oxide layer 631 as a result of the induction of the electric field, thereby causing the IGZO channel 731 to exhibit a more ON state. In this embodiment, such an ON state may serve as a basis for determining the data state when a subsequent read operation is performed.

[0083] When a read operation is performed, the source 634A receives a ground voltage, the drain 634B receives a positive voltage, and the control gate 632 receives a ground voltage. In this case, when the memory element 730 is written to have a first memory state, the current flowing between the source 634A and the drain 634B is close to zero due to the off state indicated by the IGZO channel 731. In contrast, when the memory element 730 is written to have a second memory state, the current flowing between the source 634A and the drain 634B becomes more significant due to the on state indicated by the IGZO channel 731. In this manner, the memory state to be written into the memory element 730 can be determined depending on the magnitude of the current flowing between the source 634A and the drain 634B. In addition, in this embodiment, because a large electric field is not generated between the control gate 632, the source 634A, and the drain 634B during the read operation, the direction of the electric dipole of the ferroelectric material layer 636 does not change. That is, during a read operation, whether memory element 730 is in the first or second storage state, its storage state is not changed.

[0084] In some embodiments, with proper design (e.g., by applying electric fields of different magnitudes), the memory element 730 can support more memory states, and the memory state of the memory element 730 can be further determined according to the magnitude of the read channel current during a read operation. In other words, the memory element 730 may be an MLC that can store multiple bits. For example, when the memory element 730 is written into four memory states according to the direction and level of the electric dipole polarization of the ferroelectric material layer 636, the memory element 730 can be used to store two bits of data.

[0085] In high-performance computing, computational operations often involve many memory access operations, generating large amounts of heat energy. In this case, heat dissipation is essential to maintain normal system operation. For example, high-bandwidth memory (HBM), which is often used in high-performance computing, urgently requires heat dissipation solutions. In addition, DRAM, which requires frequent charging and discharging, also has high heat dissipation requirements.

[0086] In such cases, the circuit board for mounting the memory may be placed in a cooling gas or a cooling liquid to improve heat dissipation efficiency. In some embodiments of the present disclosure, the organic solderability preservative (OSP) of the circuit board is partially removed to allow the conductive lines to directly contact the cooling gas or the cooling liquid, thereby achieving a better heat dissipation effect.

[0087] FIG. 12 shows a schematic diagram of a circuit board B1 according to one embodiment of the present disclosure. The circuit board B1 may include multiple conductive trace layers, but only the surface conductive trace layer C1 (e.g., copper foil formed by electroplating) of the circuit board B1 is shown in FIG. 12. The traces in the surface conductive trace layer C1 may be used to connect various electronic components. The surface conductive trace layer C1 is typically coated with OSP P1, i.e., a so-called green paint. The OSP P1 can reduce oxidation of the conductive traces in the surface conductive trace layer C1 and prevent the conductive traces in the surface conductive trace layer C1 from being damaged or short-circuited during test operation.

[0088] The surface conductive trace layer C1 may include multiple solder contacts S1 for soldering to an electronic component (e.g., a chip). The solder contacts S1 (e.g., SMT pads) may be exposed from the OSP P1 to facilitate subsequent solder printing for soldering to the electronic component. For example, an electronic component including the semiconductor structure 100 may have multiple pins, and the multiple pins of the electronic component may be soldered to corresponding solder contacts S1. In this embodiment, in addition to exposing the solder contacts S1 from the OSP P1, the OSP P1 on some of the conductive traces of the surface liner layer C1 may be removed. In this way, when the circuit board B1 operates in a cooling gas or is immersed in a cooling liquid, at least some of the conductive traces of the surface conductive trace layer C1 can be in direct contact with the cooling gas or liquid, thereby improving heat dissipation. In some embodiments, some of the conductive traces exposed from the OSP P1 may include, for example, a ground line G1 for analog signals, a ground line G2 for digital signals, and a ground line G3 for power. In some embodiments, the three ground wires G1, G2, and G3 may be connected to each other within a ground plane (not shown). These ground wires are generally thick, wide, and long, which can further improve heat dissipation. Furthermore, these ground wires G1, G2, and G3 have zero voltage, which minimizes the impact on the safety of the entire system.

[0089] In addition, in the semiconductor structures 100-700 according to the embodiments of the present disclosure, the conductive lines connecting the logic elements and the memory elements are coated with a copper-phosphorus alloy, which reduces the occurrence of oxidation and corrosion of the conductive lines under high temperature conditions. Similarly, the conductive lines of the circuit board B1 may also be coated with a copper-phosphorus alloy to reduce the occurrence of oxidation and corrosion of the conductive lines under high temperature conditions and in an air or liquid operating environment.

[0090] In summary, the semiconductor structure provided by the embodiments of the present disclosure can integrate logic and memory elements on the same chip using the same manufacturing process, thereby reducing manufacturing time and cost, shortening the time required to access memory, and incorporating a method to improve the overall thermal performance of the PCB, thereby facilitating the development of high performance computing.

[0091] Features of the various embodiments have been described above to enable those skilled in the art to better understand the aspects of the present disclosure. Those skilled in the art can readily use the details of the disclosure as a basis for designing or modifying other operations and structures to carry out the same purpose or achieve the same advantages as the embodiments. Those skilled in the art will understand that these equivalent solutions do not depart from the spirit or scope of the present disclosure, and that various changes, substitutions, substitutions, and alterations can be made without departing from the spirit or scope of the present disclosure.

[0092] Moreover, the scope of the present disclosure is not limited to the particular embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the detailed description. Those skilled in the art will appreciate from this disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that perform the same function or achieve substantially the same results as the corresponding embodiments described herein. Accordingly, it is intended that the appended claims encompass all such processes, machines, manufactures, compositions of matter, devices, methods, or steps.

Claims

1. a substrate having a first region and a second region laterally adjacent to the first region; a logic element disposed in the first region of the substrate and including a plurality of transistors; a memory element disposed in the second region of the substrate, a bottom electrode disposed above the substrate, the bottom electrode including a first metal layer and a first copper-phosphorus alloy layer extending along the contour of the first metal layer and surrounding the first metal layer; an upper electrode including a second metal layer and a second copper-phosphorus alloy layer extending along the contour of the second metal layer and surrounding the second metal layer, the upper electrode being disposed above the substrate and the lower electrode; a dielectric layer disposed between the top electrode and the bottom electrode; and 1. A semiconductor structure integrating logic and memory elements, comprising:

2. 10. The semiconductor structure of claim 1, wherein said memory element is a dynamic random access memory (DRAM) memory cell.

3. The semiconductor structure of claim 1 , wherein the first metal layer has a comb-like structure including a plurality of first protrusions, and the second metal layer has a comb-like structure including a plurality of second protrusions.

4. 4. The semiconductor structure of claim 3, wherein the first projections extend toward the top electrode and the second projections extend toward the bottom electrode, and the first projections and the second projections alternate.

5. 2. The semiconductor structure of claim 1, wherein said bottom electrode further comprises a first barrier layer surrounding said first copper-phosphorus alloy layer along the contour of said first copper-phosphorus alloy layer.

6. 2. The semiconductor structure of claim 1, wherein said top electrode further comprises a second barrier layer surrounding said second copper-phosphorus alloy layer along the contour of said second copper-phosphorus alloy layer.

7. 2. The semiconductor structure of claim 1, wherein a first transistor of the plurality of transistors is adjacent to the second region, and the top electrode is electrically connected to a drain of the first transistor.

8. 8. The semiconductor structure of claim 7, further comprising a first conductive plug located in the substrate and contacting the drain of the first transistor, wherein a top electrode of the memory element covers the first conductive plug along a vertical direction.

9. 10. The semiconductor structure of claim 1, wherein said dielectric layer is made of a material including photoresist material, hafnium oxide (HfO2), or other high dielectric constant material.

10. 10. The semiconductor structure of claim 1, wherein the plurality of transistors comprises at least one of a gate-all-around field-effect transistor (GAAFET), a multi-bridge channel FET, a stacked nanosheet FET, a finFET, or a complementary FET (CFET).

11. 10. The semiconductor structure of claim 1, wherein the logic element channel comprises indium gallium zinc oxide (IGZO) or silicon germanium.

12. a circuit board including a plurality of conductive trace layers, wherein a surface conductive trace layer of the plurality of conductive trace layers includes a plurality of solder contacts; 10. An electronic component comprising: the semiconductor structure of claim 1; and a plurality of pins, wherein the plurality of pins are soldered to a plurality of corresponding solder contacts among the plurality of solder contacts; an organic solderability preservative (OSP) film coating the surface conductive line layer; An electronic device, wherein the circuit board is immersed in a cooling fluid or operates in a cooling gas, and the OSP film does not cover the plurality of solder contacts or at least some of the conductive lines of the surface conductive line layer so that at least some of the conductive lines are in direct contact with the cooling fluid or the cooling gas.

13. The electronic device of claim 12 , wherein at least some of the conductive lines include a ground line.

14. a substrate having a first region and a second region laterally adjacent to the first region; a logic element disposed in the first region of the substrate and including a plurality of transistors; a memory element disposed in the second region of the substrate; The memory element comprises: an electrically erasable programmable read-only memory (EEPROM) memory cell; The memory element comprises: a source and a drain located in the substrate; a first oxide layer disposed on the substrate between the source and the drain; a control gate disposed in the first oxide layer; a first copper-phosphorus alloy layer disposed between the first oxide layer and the control gate; a charge storage layer disposed on the first oxide layer and the first copper-phosphorus alloy layer; a second copper-phosphorus alloy layer disposed on the charge storage layer; a second oxide layer disposed on the second copper-phosphorus alloy layer, the second oxide layer being disposed between the control gate and the charge storage layer, the first copper-phosphorus alloy layer being disposed between the first oxide layer and the charge storage layer, and the second copper-phosphorus alloy layer being disposed between the second oxide layer and the charge storage layer; 2. A semiconductor structure integrating logic and memory elements, comprising:

15. 15. The semiconductor structure of claim 14, wherein the first copper-phosphorus alloy layer has a plurality of first protrusion structures facing the second copper-phosphorus alloy layer, and the second copper-phosphorus alloy layer has a plurality of second protrusion structures facing the first copper-phosphorus alloy layer.

16. 16. The semiconductor structure of claim 15, wherein the plurality of first protruding structures and the plurality of second protruding structures are staggered.

17. 15. The semiconductor structure of claim 14, wherein the charge storage layer is fabricated from a material comprising silicon nitride (SiN), hafnium aluminum oxide (HaAlO), hafnium oxide (HfO2), aluminum oxide (Al2O3), or a combination thereof.

18. The control gate is a gate electrode layer; a barrier layer disposed between the gate electrode layer and the first oxide layer and surrounding a bottom and sidewalls of the gate electrode layer; a third copper-phosphorous alloy layer disposed between said gate electrode layer and said barrier layer.

19. 15. The semiconductor structure of claim 14, wherein the substrate has a plurality of fin structures, and the source and the drain of the memory element are located at two opposite ends of a first fin structure of the plurality of fin structures.

20. 20. The semiconductor structure of claim 19, wherein the first oxide layer, the first copper-phosphorus alloy layer, the charge storage layer, the second copper-phosphorus alloy layer, the second oxide layer, and the control gate are sequentially stacked on the first fin structure and surround a top and sidewalls of the first fin structure.

21. A substrate having a first region and a second region laterally adjacent to the first region; a logic element disposed in the first region of the substrate and including a plurality of transistors; a memory element disposed in the second region of the substrate; the memory element is a memory cell of a ferroelectric memory, The memory element comprises: a source and a drain located in the substrate; a first oxide layer disposed on the substrate between the source and the drain; a control gate disposed in the first oxide layer; a first copper-phosphorus alloy layer disposed between the first oxide layer and the control gate; a ferroelectric material layer disposed between the first copper-phosphorus alloy layer and the first oxide layer; the ferroelectric material layer includes an array formed by a plurality of protrusion structures, and the first copper-phosphorus alloy layer fills gaps around the ferroelectric material layer; or The ferroelectric material layer and the first copper-phosphorus alloy layer have uniform thicknesses and are two sequentially stacked planar structures.

22. 22. The semiconductor structure of claim 21, wherein the ferroelectric material layer is made of a material comprising hafnium oxide (HfO2).

23. 22. The semiconductor structure of claim 21, wherein the first oxide layer has a thickness between 1 nm and 5 nm and the ferroelectric material layer has a thickness between 5 nm and 15 nm.

24. 22. The semiconductor structure of claim 21, wherein the logic elements and the channels of the memory elements comprise indium gallium zinc oxide (IGZO) or silicon germanium.

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