Semiconductor Devices

Abstract

To suppress the variation in the switching time due to the temperature change.SOLUTION: A resistor component 20 having the reverse characteristics to the temperature dependence of a gate current of a power transistor 100 subjected to switching control by a switching control unit 200 is provided in the switching control unit 200, and the change in the gate current following the temperature change is suppressed by the change in the resistor component 20 following the temperature change.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device including, for example, a complementary MOS (Metal Oxide Semiconductor) transistor (hereinafter referred to as a CMOS transistor) that uses a semiconductor material with a band gap larger than that of silicon. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2009-89544 (Patent Document 1) describes a technology that links the temperature change of a switching power module and a gate resistor that supplies output to a gate drive circuit, so that even if the temperature of the switching power module rises from, for example, 20 to 100 degrees Celsius due to heat generation, the surge voltage remains within the withstand voltage of the switching power module.

[0003] Non-Patent Document 1 describes a technology in which a first semiconductor chip on which a gate driver including a CMOS transistor using silicon carbide is formed, a second semiconductor chip on which a power transistor using silicon carbide is formed, and a third semiconductor chip on which a diode using silicon carbide is formed are multi-chip mounted on a single PCB wiring board.

[0004] Non-Patent Document 2 describes a technology relating to a semiconductor device in which a CMOS transistor using silicon carbide and a power transistor using silicon carbide are monolithically integrated on a silicon carbide substrate. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-89544 [Non-patent literature]

[0006] [Non-Patent Document 1] M. Barlow et. al., IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 11, NOVEMBER 2019 [Non-patent document 2] M. Okamoto, A. Yao, H. Sato, and S. Harada, 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, 2021, pp. 71-74. Summary of the Invention [Problem to be solved by the invention]

[0007] The switching time of a power transistor used in a power semiconductor device varies with temperature. In this case, even if a control parameter such as the switching time is adjusted to an optimal value at room temperature, the control parameter may deviate from the optimal value as the temperature changes, which may lead to fluctuations in the characteristics of the power transistor and reduced controllability. Furthermore, for example, if the switching time becomes shorter than the optimal value as the temperature increases, the voltage change rate or current change rate increases, which may lead to unexpected failures due to surges or ringing. Furthermore, for example, if the switching time becomes longer than the optimal value as the temperature decreases, the voltage change rate or current change rate decreases, which may lead to increased switching losses and unexpected failures. Therefore, there is a need for a method for suppressing fluctuations in switching time due to temperature changes. [Means for solving the problem]

[0008] In one embodiment, a semiconductor device includes a power transistor using a semiconductor material with a bandgap larger than that of silicon, and a switching control unit that controls switching of the power transistor. Here, the switching control unit includes a CMOS transistor using a semiconductor material with a bandgap larger than that of silicon, and a resistance component electrically connected to the CMOS transistor. In this case, changes in the switching time of the power transistor due to temperature changes are suppressed by changes in the resistance value of the resistance component due to temperature changes. [Effects of the Invention]

[0009] According to one embodiment, fluctuations in switching time due to temperature changes can be suppressed. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an example of a circuit configuration using a silicon carbide power semiconductor device. [Figure 2] FIG. 10 is a diagram illustrating room for improvement that the present inventors have focused on. [Figure 3] FIG. 1 is a diagram illustrating the basic concept of suppressing the temperature dependency of the “turn-on time.” [Figure 4] FIG. 1 is a diagram illustrating the basic concept of suppressing the temperature dependency of the “turn-off time.” [Figure 5] FIG. 1(a) is a photograph showing the actual layout of a silicon carbide power semiconductor device, and FIG. 1(b) is a diagram showing a schematic layout of the silicon carbide power semiconductor device. [Figure 6] FIG. 10 is a diagram showing the layout of a semiconductor chip on which CMOS transistors that configure a switching control section are formed. [Figure 7] FIG. 7 is an enlarged view showing a partial area of ​​FIG. 6. [Figure 8] 8(a) is a cross-sectional view taken along line AA in FIG. 7, and FIG. 8(b) is a cross-sectional view taken along line BB in FIG. [Figure 9] 1 is a graph showing the temperature dependency of "turn-on time." [Figure 10]FIG. 10 is a diagram showing a device structure in Modification 1. [Figure 11] FIG. 10 is a diagram showing a device structure in Modification 2. [Figure 12] FIG. 10 is a diagram showing a device structure in embodiment 2. [Figure 13] FIG. 10 is a diagram showing the layout of a semiconductor chip in embodiment 3. [Figure 14] 14 is a diagram showing cross-sectional views taken along lines AA, BB, and CC in FIG. 13. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] In all the drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. In addition, hatching may be used even in plan views to make the drawings easier to understand.

[0012] <Advantages of wide bandgap semiconductors> Power semiconductor devices are required to have, for example, low on-resistance and low switching loss in addition to high breakdown voltage. Currently, the mainstream of power semiconductor devices is a field effect transistor formed on a semiconductor substrate whose main component is silicon, but these power semiconductor devices are approaching their theoretical performance limits.

[0013] In this regard, semiconductor devices including field effect transistors formed on a semiconductor substrate whose main component is a semiconductor material with a band gap larger than that of silicon (hereinafter referred to as wide band gap power semiconductor devices) have attracted attention.

[0014] This is because a large band gap means that the material has high dielectric breakdown strength, making it easier to achieve high breakdown voltage.

[0015] Furthermore, if the semiconductor material itself has high dielectric breakdown strength, the withstand voltage can be ensured even if the drift layer that maintains the withstand voltage is made thin. Therefore, for example, by making the drift layer thinner and increasing the impurity concentration, the on-resistance of the power semiconductor device can be reduced.

[0016] That is, wide bandgap power semiconductor devices are superior in that they can achieve both improved breakdown voltage and reduced on-resistance, which are in a trade-off relationship with each other. Wide bandgap power semiconductor devices with these advantages also have the advantage of being able to operate at high temperatures and with high-speed switching due to their large bandgap.

[0017] The technical idea of ​​this embodiment is a technical idea related to a wide bandgap power semiconductor device using a semiconductor material with a bandgap larger than that of silicon. Examples of semiconductor materials with a bandgap larger than that of silicon include compound semiconductors such as silicon carbide (SiC) and gallium nitride (GaN). However, the technical idea of ​​this embodiment is not limited to these and can be widely applied to wide bandgap power semiconductor devices using semiconductor materials with a bandgap larger than that of silicon.

[0018] In the following, a wide bandgap power semiconductor device using silicon carbide will be described as an example of a wide bandgap power semiconductor device.

[0019] Silicon carbide has a dielectric breakdown field strength approximately one order of magnitude greater than that of silicon, and so by thinning the drift layer to approximately one-tenth the thickness required to ensure the breakdown voltage and increasing the impurity concentration by approximately 100 times, it is theoretically possible to reduce the on-resistance (device resistance) by three orders of magnitude or more. Furthermore, because silicon carbide has a band gap approximately three times larger than that of silicon, it is also capable of high-temperature operation, and wide-bandgap power semiconductor devices using silicon carbide (hereinafter referred to as silicon carbide power semiconductor devices) are expected to achieve performance that exceeds that of silicon power semiconductor devices.

[0020] <Circuit configuration of silicon carbide power semiconductor device> First, an example of a circuit configuration of a silicon carbide power semiconductor device will be described below.

[0021] FIG. 1 is a diagram showing an example of a circuit configuration using a silicon carbide power semiconductor device 1. As shown in FIG.

[0022] 1, silicon carbide power semiconductor device 1 has a power transistor 100, a Schottky barrier diode 110, and a switching control unit 200. Examples of power transistor 100 include a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor). Note that power transistor 100, Schottky barrier diode 110, and switching control unit 200 are formed using silicon carbide. Silicon carbide power semiconductor device 1 is connected to a load 120 and an external power supply 130.

[0023] Specifically, an external power supply 130 is connected between a power supply potential Vd and a reference potential Vs, and a power transistor 100 and a Schottky barrier diode 110 are connected in series with the external power supply 130. A load 120 is connected in parallel with the Schottky barrier diode 110. The load 120 is, for example, a motor and includes an inductance.

[0024] A switching control unit 200 is connected to the gate of the power transistor 100, and the switching of the power transistor is controlled by this switching control unit 200. The switching control unit 200 includes a CMOS transistor, which is composed of a p-channel field-effect transistor 10A and an n-channel field-effect transistor 10B connected in series between a power supply potential Vdd and a reference potential Vss. In the following description, the p-channel field-effect transistor will be abbreviated to pFET and the n-channel field-effect transistor will be abbreviated to nFET. In this case, the gate of pFET 10A and the gate of nFET 10B are electrically connected.

[0025] Here, the inputs of switching control unit 200 are the gates of pFET 10A and nFET 10B, which are electrically connected to each other. On the other hand, the output of switching control unit 200 is the connection node between the drain of pFET 10A and the drain of nFET 10B, and this connection node is electrically connected to the gate of power transistor 100. In the circuit configured as above, the switching of power transistor 100 is controlled based on a control signal input to the input of switching control unit 200, thereby controlling the current flowing through load 120.

[0026] Next, an operation of controlling the switching of the power transistor 100 by the switching control unit 200 will be described. In Fig. 1, it is assumed that a low-level signal (for example, Vss) is input to the input of the switching control unit 200. In this case, "Vss" is applied to the gate of the pFET 10A that constitutes the switching control unit 200 and the gate of the nFET 10B that constitutes the switching control unit 200. As a result, the pFET 10A is turned on, while the nFET 10B is turned off. Therefore, a high-level signal (for example, Vdd) is output from the output of the switching control unit 200.

[0027] Specifically, when pFET 10A is turned on, a current flows from the power supply potential Vdd to the source of pFET 10A, then to the drain of pFET 10A, then to the output of switching control unit 200, and finally to the gate of power transistor 100. This current causes charge to accumulate in the gate-drain capacitance of power transistor 100, and ultimately the gate voltage of the power transistor becomes "Vdd," turning the power transistor on. This causes a current to flow through load 120, enabling the load to be driven.

[0028] 1, assume that a high-level signal (e.g., Vdd) is input to the input of the switching control unit 200. In this case, "Vdd" is applied to the gate of the pFET 10A constituting the switching control unit 200 and the gate of the nFET 10B constituting the switching control unit 200. As a result, the pFET 10A is turned off, while the nFET 10B is turned on. Therefore, a low-level signal (e.g., Vss) is output from the output of the switching control unit 200. Therefore, when the nFET 10B is turned on, the charge accumulated in the gate-drain capacitance of the power transistor 100 is discharged, and a current flows through the path of the gate of the power transistor 100 → the output of the switching control unit 200 → the drain of the nFET 10B → the source of the nFET 10B → the reference potential Vss. As a result, the gate voltage of the power transistor 100 finally becomes "Vss," and the power transistor 100 is turned off. This blocks the current flowing through the load 120. At this time, since the load 120 includes an inductance, when the current flowing through the load 120 is interrupted, a counter electromotive force that tries to keep the current flowing is generated in the inductance. A current based on this counter electromotive force flows through the Schottky barrier diode 110. In other words, a return current flows through a closed loop formed by the load 120 and the Schottky barrier diode 110.

[0029] As described above, the switching operation of the power transistor 100 is controlled by the switching control section 200, whereby the load 120 can be driven.

[0030] <Consideration of improvements> Next, the room for improvement that the present inventors have focused on will be described.

[0031] FIG. 2 is a diagram for explaining room for improvement that the present inventors have focused on.

[0032] In FIG. 2, according to previous research, it is known that the switching time can be approximated by the following (Equation 1).

[0033] t sw ≒ 0.8 × Q gd / I g (Equation 1) t sw : Switching time Q gd : Amount of charge stored in the gate-drain capacitance of a power transistor I g : Gate current

[0034] Here, during the "turn-on time", the gate current I g is equal to the drain current of pFET10A that flows through path "A". On the other hand, during the "turn-off time", the gate current I g is equivalent to the drain current of nFET 10B flowing through path "B".

[0035] In this specification, the term "switching time" is used as a concept that includes both the "turn-on time" when a power transistor transitions from an off state to an on state, and the "turn-off time" when a power transistor transitions from an on state to an off state.

[0036] "Turn-on time" refers to the drain-source voltage (V ds ) is 100%, it is defined as the time required for the drain-source voltage to change from 90% to 10% of the drain-source voltage. For example, when the drain-source voltage (V ds ) is 600V, the time it takes to transition from 540V to 60V is defined as the "turn-on time."

[0037] "Turn-off time" is defined as the time required for the drain-source voltage to change from 10% to 90% of the drain-source voltage, assuming that the drain-source voltage (Vds) when the power transistor is off is 100%. For example, if the drain-source voltage (Vds) when off is 600V, the time it takes to transition from 60V to 540V is defined as the "turn-off time."

[0038] Here, in the pFET 10A and nFET 10B constituting the switching control section 200, the drain current when conducting changes with temperature. In this regard, taking into consideration the above-mentioned (Equation 1), the drain current of the pFET 10A or nFET 10B (the gate current I g ) changes with temperature change, which means that the switching time t sw Here, in order to suppress the fluctuation of the characteristics of the power transistor and the deterioration of the controllability due to the temperature change, the switching time t sw It is desirable that the switching time t of the power transistor 100 is constant even when the temperature changes. sw It can be seen that there is room for improvement in terms of keeping the temperature constant.

[0039] Therefore, in this embodiment, a device is implemented to overcome the above-mentioned room for improvement. The technical concept of this embodiment that implements this device will be described below.

[0040] <Basic Concept of the Embodiment> The basic idea of ​​this embodiment is, for example, to compensate for the temperature dependency of the drain current of a CMOS transistor constituting the switching control unit by the temperature dependency of a resistance component included in the switching control unit. In other words, the basic idea can be said to be to provide a resistance component in the switching control unit that has a characteristic inverse to the temperature dependency of the gate current of a power transistor whose switching is controlled by the switching control unit, and to suppress changes in the gate current caused by temperature changes by the change in the above-mentioned resistance component caused by temperature changes.

[0041] According to this basic concept, the change in the gate current can be compensated for by the change in the resistance component, and as a result, the temperature dependency of the gate current can be reduced. Considering the above-mentioned (Equation 1), this means that the temperature dependency of the switching time can be reduced. Therefore, according to this basic concept, the temperature dependency of the switching time can be reduced, and as a result, the performance of the silicon carbide power semiconductor device can be improved.

[0042] <<Basic Concept of "Turn-on Time">> FIG. 3 is a diagram illustrating the basic concept of suppressing the temperature dependency of the "turn-on time."

[0043] 3, during the "turn-on time," the drain current flowing through pFET 10A corresponds to the gate current flowing into the gate of power transistor 100. Since the drain current flowing through pFET 10A changes with temperature changes, the gate current also changes with temperature changes.

[0044] In particular, the drain current flowing through pFET 10A is treated as increasing with increasing temperature, and in this case, the gate current flowing into the gate of power transistor 100 increases with increasing temperature.

[0045] 3, the basic idea is to provide a resistance component 20 included in the switching control unit 200 between the drain of the pFET 10A constituting the switching control unit 200 and the gate of the power transistor 100. In particular, this resistance component 20 is composed of a resistance component having a characteristic inverse to the temperature dependency of the drain current of the pFET 10A. As a result, changes in the drain current of the pFET 10A are suppressed by changes in the resistance component 20. For example, because the drain current of the pFET 10A increases with increasing temperature, the resistance component 20 is composed of a resistance component whose resistance value increases with increasing temperature. As a result, increases in the drain current of the pFET 10A are suppressed by the increase in the resistance value of the resistance component 20.

[0046] This will be specifically explained using mathematical expressions.

[0047] The inventors are considering expressing the gate current by (Equation 2).

[0048] I g =(V dd -V g (T)) / (Rpf(T)+Rpw(T))...(Formula 2) I g : Gate current V dd : Power supply potential of switching control section V g (T): Gate voltage (= Miller plateau voltage) Rpf(T): Equivalent resistance excluding wiring resistance of pFET10A Rpw(T): Resistance component (wiring resistance) T: Temperature

[0049] Here, (Equation 2) is the gate current I of the power transistor 100 during the "turn-on time". g This is the formula for the gate current I g can also be said to be the drain current of pFET 10A.

[0050] V g(T) is the Miller plateau voltage, which decreases as the temperature increases. Here, the Miller plateau voltage V g (T) is the gate voltage value at which charging and discharging of the Miller capacitance begins during switching. The Miller plateau voltage V g (T) decreases as the temperature increases.

[0051] Rpf(T) is the equivalent resistance of the pFET 10A excluding the wiring resistance, and is typically the channel resistance, and its resistance value decreases as the temperature rises. In other words, it represents the characteristic that the drain current of the pFET 10A increases with increasing temperature.

[0052] Rpw(T) is typically the wiring resistance of pFET 10A, but may also be a resistor connected to the drain terminal and / or source terminal of pFET 10A. Rpw(T) corresponds to resistance component 20 in FIG.

[0053] In (Equation 1), Q gd Since the gate current I g If the fluctuation of Rpf(T) can be suppressed, the temperature fluctuation of the "turn-on time" can be suppressed. g (T) decreases as its value decreases. g As Rpw(T) increases, the value of I g When the temperature T rises, Rpf(T) decreases, and V g (T) also decreases, so in (Equation 2) the gate current I g To cancel the fluctuation of I g It can be seen that Rpw(T) should be increased to compensate for the fluctuation of

[0054] From the above, the basic idea of ​​the "turn-on time" is that if the temperature dependency of the resistance component Rpw(T) (resistance component 20) of the switching control unit 200 is a temperature dependency in which the resistance value increases with the temperature rise, the gate current I of the power transistor 100 with the temperature rise g In this case, based on (Equation 1), it is possible to reduce the change in "turn-on time" that accompanies a temperature change.

[0055] Although Figure 3 illustrates an example in which resistance component 20 is provided on the drain side of pFET 10A, the basic concept of the "turn-on time" is not limited to this. For example, resistance component 20 may be provided on the source side of pFET 10A, or resistance component 20 may be provided on both the drain side and the source side.

[0056] <<Basic Concept of "Turn-off Time">> FIG. 4 is a diagram illustrating the basic idea of ​​suppressing the temperature dependency of the "turn-off time."

[0057] In FIG. 4, during the "turn-off time," the drain current flowing through nFET 10B corresponds to the gate current flowing out from the gate of power transistor 100. Since the drain current flowing through nFET 10B changes with temperature changes, the gate current also changes with temperature changes. In particular, the drain current flowing through nFET 10B is treated as increasing with temperature rise. In this case, the gate current of power transistor 100 increases with temperature rise.

[0058] In this regard, in FIG. 4, the basic idea is to provide a resistance component 30 included in the switching control unit 200 between the drain of the nFET 10B constituting the switching control unit 200 and the gate of the power transistor 100. In particular, this resistance component 30 is composed of a resistance component having a characteristic inverse to the temperature dependency of the drain current of the nFET 10B. As a result, changes in the drain current of the nFET 10B are suppressed by changes in the resistance component 30. For example, because the drain current of the nFET 10B increases with increasing temperature, the resistance component 30 is composed of a resistance component having a characteristic that its resistance value increases with increasing temperature. As a result, an increase in the drain current of the nFET 10B is suppressed by an increase in the resistance value of the resistance component 30.

[0059] However, detailed distinction is required between cases, and this will be explained using mathematical expressions.

[0060] The inventors are considering expressing the gate current by (Equation 3).

[0061] I g =(V g (T)-V ss ) / (Rnf(T)+Rnw(T)) (Equation 3) I g : Gate current V ss : Reference potential of the switching control section V g (T): Gate voltage (= Miller plateau voltage) Rnf(T): Equivalent resistance excluding the wiring resistance of nFET10A Rnw(T): Resistance component (wiring resistance) T: Temperature

[0062] V g (T) is the Miller plateau voltage, whose value decreases with increasing temperature.

[0063] Rnf(T) is the equivalent resistance of nFET 10B excluding the wiring resistance, and is typically the channel resistance, and its resistance value decreases as the temperature increases. In other words, it represents the characteristic that the drain current of nFET 10B increases with increasing temperature.

[0064] Rnw(T) is typically the wiring resistance of nFET 10B, but may be a resistance connected to the drain terminal and / or source terminal of nFET 10B. Rnw(T) corresponds to resistance component 30 in FIG.

[0065] In (Equation 1), Q gd Since the gate current I g If the fluctuation of I can be suppressed, the temperature fluctuation of "turn-off time" can be suppressed. In (Equation 3), when the value of Rnf(T) decreases, the g Rnw(T) increases as its value increases. g In addition, in (Equation 3), V g (T) is the value of I g This is the inverse relationship to (Equation 2). When the temperature T increases, Rnf(T) decreases and I g increases, but V g (T) decreases, so I g and both are I g Therefore, the following three cases are possible:

[0066] (1) I due to Rnf(T) as the temperature rises g The increase in V g (T) by I g In this case, according to (Equation 3), the I that could not be canceled out due to the relationship between Rnf(T) and Vg(T) g Increase Rnw(T) to cancel the increase of I g Reduces.

[0067] (2) I due to Rnf(T) as the temperature rises g The increase in V g(T) by I g In this case, according to (Equation 3), Rnf(T) and V g I arising from the relationship (T) g Decrease Rnw(T) to cancel the decrease of I g Increase.

[0068] (3) I due to Rnf(T) as the temperature rises g The increase in V g (T) by I g In this case, Rnw(T) is set to not vary with temperature according to (Equation 3).

[0069] From the above, the basic idea of ​​"turn-off time" is that the temperature dependency of the drain current flowing through nFET 10B is greater than the gate voltage V g When the influence of the temperature dependency of the power transistor 100 is larger than that of the gate voltage V g It is necessary to distinguish between cases where the temperature dependency of the drain current through the nFET 10B has a larger effect than the temperature dependency of the drain current through the nFET 10C.

[0070] The temperature dependence of the drain current flowing through the nFET 10B is greater than the gate voltage V g In the case where the influence of the temperature dependency is greater than the temperature dependency of the resistance component Rnw(T) (resistance component 30) of the switching control unit 200, the basic idea of ​​the "turn-off time" is that if the temperature dependency of the resistance component Rnw(T) (resistance component 30) of the switching control unit 200 is a temperature dependency in which the resistance value increases with the temperature rise, the gate current I g In this case, based on (Equation 1), it is possible to reduce the change in "turn-off time" that accompanies a temperature change.

[0071] On the other hand, the gate voltage V of the power transistor 100 gIn the case where the temperature dependency of the drain current flowing through nFET 10B has a larger effect than the temperature dependency of the drain current flowing through nFET 10B, the basic idea of ​​the "turn-off time" is that if the temperature dependency of the resistance component Rnw(T) (resistance component 30) of switching control section 200 is a temperature dependency in which the resistance value decreases with increasing temperature, then the gate current I g In this case, based on (Equation 1), it is possible to reduce the change in "turn-off time" that accompanies a temperature change.

[0072] Although Figure 4 illustrates an example in which the resistance component 30 is provided on the drain side of the nFET 10B, the basic concept of the "turn-off time" is not limited to this. For example, the resistance component 30 may be provided on the source side of the nFET 10B, or the resistance component 30 may be provided on both the drain side and the source side.

[0073] The following describes embodiments that embody the basic concept described above.

[0074] <Realization mode 1> <<Layout of Silicon Carbide Power Semiconductor Devices>> FIG. 5 is a diagram showing the layout of the silicon carbide power semiconductor device 1. In particular, FIG. 5(a) shows the layout of the silicon carbide power semiconductor device 1. 5(b) is a diagram showing a schematic layout of the silicon carbide power semiconductor device 1. FIG.

[0075] 5(b), silicon carbide power semiconductor device 1 has a wiring substrate WB. Terminals TE1 to TE6, which serve as conductive regions, are formed on this wiring substrate WB. Although there are no particular limitations on the wiring substrate WB, it is preferable to use, for example, a base substrate made of a SiN-AMC (silicon nitride-active metal copper circuit) substrate and a Cu-Mo-Cu (CMC) composite material bonded to the underside thereof in order to improve heat dissipation and match the thermal expansion coefficient with the semiconductor chip.

[0076] When viewed as a whole, silicon carbide power semiconductor device 1 has terminal TE6 as a signal input node (IN in FIG. 1), terminal TE2 as an output node (drain of the power transistor), and other terminals TE1, TE3 to TE5 as power supply nodes.

[0077] The terminal TE1 is applied with the reference potential Vs shown in Fig. 1, and the terminal TE3 is applied with the power supply potential Vd shown in Fig. 1. The terminal TE4 is applied with the reference potential Vss shown in Fig. 1, and the terminal TE5 is applied with the power supply potential Vdd shown in Fig. 1.

[0078] A semiconductor chip CHP1 having a power transistor formed thereon is mounted on the terminal TE2, a semiconductor chip CHP3 having a Schottky barrier diode formed thereon is mounted on the terminal TE3, and a semiconductor chip CHP2 having a CMOS transistor forming a switching control unit formed thereon is mounted on the terminal TE4.

[0079] The terminal TE1 is connected by a wire to the source of the power transistor formed on the semiconductor chip CHP1, and the terminal TE2 is connected by a wire to the anode of the Schottky barrier diode formed on the semiconductor chip CHP3.

[0080] The terminal TE4 is connected by a wire to the source of the nFET that constitutes the CMOS transistor formed on the semiconductor chip CHP2. Furthermore, the terminal TE5 is connected by a wire to the source of the pFET that constitutes the CMOS transistor. Furthermore, the terminal TE6 is connected by a wire to the gate of the pFET and the gate of the nFET, which are electrically connected to each other. In other words, the terminal TE6 is connected by a wire to the input of the CMOS transistor that constitutes the switching control unit. Meanwhile, the semiconductor chips CHP1 and CHP2 are connected by a wire. Specifically, the gate of the power transistor formed on the semiconductor chip CHP1 is connected by a wire to the output of the CMOS transistor formed on the semiconductor chip CHP2.

[0081] In the silicon carbide power semiconductor device 1 having such a layout, the semiconductor chips CHP1 and CHP2 are arranged close to each other. This means that the output of the CMOS transistor formed in the semiconductor chip CHP2 and the gate of the power transistor formed in the semiconductor chip CHP1 are connected by a short wire. As a result, the parasitic inductance of the wire can be reduced, enabling high-speed switching operation. For example, the silicon carbide power semiconductor device 1 having the layout shown in FIG. 5 can achieve switching times of several nanoseconds. In other words, it can achieve "turn-on times" and "turn-off times" of several nanoseconds or less.

[0082] Furthermore, the power transistor chip (semiconductor chip CHP1) and the CMOS transistor chip (semiconductor chip CHP2) are arranged close to each other on the wiring board WB, which has high thermal conductivity as mentioned above. As a result, the heat generated by the power transistor chip is linked to the temperature of the CMOS transistor chip. To strengthen the thermal coupling between the chips, the experiment was conducted with the shortest distance between the two chips set to 0.8 mm, but it is desirable for the distance to be in the range of 0 to 5 mm.

[0083] <<Semiconductor chip layout>> Next, the layout of the semiconductor chip CHP2 on which the CMOS transistors constituting the switching control section are formed will be described.

[0084] Fig. 6 is a diagram showing the layout of a semiconductor chip CHP2 on which CMOS transistors constituting a switching control section are formed. In Fig. 6, a plurality of pads are formed on the surface of the semiconductor chip CHP2. Specifically, the semiconductor chip CHP2 is formed with an input pad (In) of the CMOS transistor, a power supply potential pad (Vdd), a reference potential pad (Vss), and an output pad (Out) of the CMOS transistor.

[0085] Fig. 7 is an enlarged view of region RA in Fig. 6. As shown in Fig. 7, metal wirings WL1 to WL5 are arranged side by side in the y direction, and each of the metal wirings WL1 to WL5 extends in the x direction. Each of these metal wirings WL1 to WL5 is made of, for example, aluminum wiring containing aluminum as a main component.

[0086] Here, the term "main component" refers to the component that is contained in the largest amount, and is used to indicate that it does not exclude the presence of other components. For example, "containing aluminum as the main component" means that aluminum is contained in the largest amount.

[0087] The metal wiring WL1 is the input wiring (In) of the CMOS transistor, and the metal wiring WL2 is a reference wiring to which a reference potential (Vss) is applied. The metal wiring WL3 is the output wiring (Out) of the CMOS transistor, and the metal wiring WL4 is a power supply wiring to which a power supply potential (Vdd) is applied. The metal wiring WL5 is the input wiring (In) of the CMOS transistor. In the metal wirings WL1 to WL5 configured as described above, a plurality of nFETs 10B constituting the CMOS transistor are formed between the metal wiring WL2 and the metal wiring WL3, and the plurality of nFETs 10B are arranged side by side in the x direction. Each of the plurality of nFETs 10B has a source electrode SE1 and a drain electrode DE1, and a gate electrode GN arranged between the source electrode SE1 and the drain electrode DE1. The source electrode SE1 is electrically connected to the metal wiring WL2, while the drain electrode DE1 is electrically connected to the metal wiring WL3. The gate electrode GN is also electrically connected to the metal wiring WL1.

[0088] On one side, a plurality of pFET10A that form a CMOS transistor are formed between the metal wiring WL3 and the metal wiring WL4, and the plurality of pFET10A are arranged side by side in the x direction. Each of these plurality of pFET10A has a source electrode SE2 and a drain electrode DE2, and also has a gate electrode GP disposed between the source electrode SE2 and the drain electrode DE2. The source electrode SE2 is electrically connected to the metal wiring WL4, while the drain electrode DE2 is electrically connected to the metal wiring WL3. Further, the gate electrode GP is electrically connected to the metal wiring WL5.

[0089] The source electrode SE1 and the source electrode SE2, the drain electrode DE1 and the drain electrode DE2, the metal wiring WL2, the metal wiring WL3, and the metal wiring WL4 are formed of aluminum wiring in the same layer and are patterned by photolithography technology.

[0090] In the above manner, the semiconductor chip CHP2 is laid out.

[0091] <<Device Structure of CMOS Transistor>> Subsequently, after describing the device structure of the nFET that forms a CMOS transistor, the device structure of the pFET that forms a CMOS transistor will be described.

[0092] FIG. 8(a) is a cross-sectional view taken along the line A-A of FIG. 7 and shows the device structure of the nFET10B that forms a CMOS transistor.

[0093] 8(a), for example, a drain region DRN made of an n-type diffusion layer and a source region SRN made of an n-type diffusion layer are formed apart from each other in a p-type silicon carbide substrate SUB. A p-type body contact region BCP is formed so as to contact the source region SRN. Meanwhile, the region sandwiched between the source region SRN and the drain region DRN is a channel formation region, and a gate insulating film GOX1 is formed on this channel formation region. A gate electrode GN is formed on the gate insulating film GOX1.

[0094] Next, an insulating layer IL is formed on the surface of the p-type silicon carbide substrate SUB covering the gate electrode GN, and a drain electrode DE1 and a source electrode SE1 are formed to penetrate this insulating layer IL. The drain electrode DE1 is formed to penetrate the insulating layer IL and reach the drain region DRN, and is electrically connected to the drain region DRN. On the other hand, the source electrode SE1 is formed to penetrate the insulating layer IL and reach both the source region SRN and the p-type body contact region BCP, and is electrically connected to the source region SRN and the p-type body contact region BCP.

[0095] Next, the drain electrode DE1 is electrically connected to a metal wiring WL3 in a planar direction (not shown) (see FIG. 7), while the source electrode SE1 is electrically connected to a metal wiring WL2 in a planar direction (not shown) (see FIG. 7).

[0096] In this way, nFET 10B is configured.

[0097] Next, FIG. 8(b) is a cross-sectional view taken along line BB in FIG. 7, showing the device structure of a pFET 10A that constitutes a CMOS transistor.

[0098] 8(b), for example, an n-type well NWL is formed in a p-type silicon carbide substrate SUB, and a drain region DRP made of a p-type diffusion layer and a source region SRP made of a p-type diffusion layer are formed in this n-type well NWL and spaced apart from each other. An n-type body contact region BCN is formed so as to contact the source region SRP. Meanwhile, a depleted p-type buried region PL is formed in a region sandwiched between the source region SRP and the drain region DRP, and a gate insulating film GOX2 is formed on this p-type buried region PL. A gate electrode GP is formed on the gate insulating film GOX2.

[0099] Subsequently, an insulating layer IL is formed on the surface of the p-type silicon carbide substrate SUB covering the gate electrode GP, and a drain electrode DE2 and a source electrode SE2 are formed to penetrate this insulating layer IL. The drain electrode DE2 is formed to penetrate the insulating layer IL and reach the drain region DRP, and is electrically connected to the drain region DRP. On the other hand, the source electrode SE2 is formed to penetrate the insulating layer IL and reach both the source region SRP and the n-type body contact region BCN, and is electrically connected to the source region SRP and the n-type body contact region BCN.

[0100] Next, the drain electrode DE2 is electrically connected to a metal wiring WL3 in a planar direction (not shown) (see FIG. 7), while the source electrode SE2 is electrically connected to a metal wiring WL4 in a planar direction (not shown) (see FIG. 7).

[0101] In this way, pFET 10A is configured.

[0102] In the pFET 10A, a depleted p-type buried region PL is formed in the channel formation region. As a result, the pFET 10A employs a so-called "buried channel structure" in which a channel is formed below the p-type buried region PL. The reason for this is as follows.

[0103] It is known that field-effect transistors formed on silicon carbide substrates have a high density of interface states at the MOS interface, which reduces channel mobility and increases on-resistance. These interface states are generated, for example, during the heat treatment process when forming the gate insulating film, and are particularly noticeable in that the threshold voltage of pFETs increases.

[0104] Regarding this point, our research has shown that donor-like traps (hole traps) exist near the center of the bandgap. Once holes are trapped, they cannot be detrapped by thermal energy due to the large bandgap of silicon carbide. The trapped holes act as effective positive fixed charges, shifting the threshold voltage of pFET 10A negatively. In other words, the threshold voltage of pFET 10A increases. Here, the same hole traps exist in nFET 10B, and applying a negative gate bias generates an effective positive fixed charge. However, when a positive gate bias is applied to induce an inversion layer in the channel, the electrons constituting the inversion layer recombine with the holes in the hole traps, returning the device to an electrically neutral state and not affecting the electrical characteristics. Thus, the effects of hole traps are less noticeable in nFET 10B, but are evident in pFET 10A.

[0105] Therefore, in the pFET 10A, a "buried channel structure" is adopted instead of a "surface channel structure" in order to avoid the influence of the interface state.

[0106] Here, it is conceivable to form a "buried channel structure" using ion implantation. However, ion implantation of p-type impurities such as aluminum into a silicon carbide substrate generates implantation defects, resulting in a side effect of reduced channel mobility. For this reason, in embodiment 1, the "buried channel structure" is formed using an epitaxial layer. This allows for a reduction in the on-resistance of pFET 10A and a reduction in the threshold voltage, since no impurities are implanted by ion implantation.

[0107] 8 shows a structure in which pFET 10A and nFET 10B are formed on a p-type silicon carbide substrate SUB, but if a p-type silicon carbide substrate SUB is difficult to use, a similar structure can be formed by epitaxially growing a p-type silicon carbide layer on an n-type silicon carbide substrate or a semi-insulating silicon carbide substrate. The structure of CMOS region AR1, which will be described later in FIG. 14, can also be used as is. The same applies to the substitution of the p-type silicon carbide substrate SUB in FIGS. 10, 11, and 12, which will be described later.

[0108] <<Features of Embodiment 1>> Next, the features of embodiment 1 will be described.

[0109] The basic idea is that the change in the switching time of a power transistor due to a change in temperature is suppressed by the change in the resistance value of a resistance component electrically connected to a CMOS transistor due to a change in temperature. Here, a feature of the first embodiment is that, for example, as shown in Fig. 7, metal wirings WL2 to WL4 are used as the resistance component electrically connected to the CMOS transistor. Specifically, a feature of the first embodiment is that the metal wirings WL2 to WL4 are intentionally extended in the x-direction, thereby utilizing the wiring resistance of the metal wirings WL2 to WL4 as the above-mentioned resistance component.

[0110] For example, focusing on the "turn-on time" of the switching time, the change in the "turn-on time" due to a rise in temperature can be reduced if the temperature dependency of the resistance component Rpw(T) of the switching control unit is such that the resistance value increases with a rise in temperature. In particular, by using a resistance component electrically connected to pFET 10A that has temperature dependency that increases the resistance value with a rise in temperature, the change in the "turn-on time" can be suppressed.

[0111] In this regard, in the first embodiment, for example, as shown in FIG. 7, the resistance components electrically connected to pFET 10A include the wiring resistance of metal wiring WL3 electrically connected to drain electrode DE2 of pFET 10A and metal wiring WL4 electrically connected to source electrode SE2 of pFET 10A. Here, metal wiring WL3 and metal wiring WL4 are composed mainly of aluminum and have the characteristic that their resistance value increases with increasing temperature. Therefore, according to the first embodiment, changes in the "turn-on time" are suppressed by changes in the wiring resistance of metal wiring WL3 and metal wiring WL4, and as a result, the "turn-on time" can be maintained approximately constant regardless of increases in temperature.

[0112] On the other hand, when focusing on the "turn-off time" of the switching time, the change in the "turn-off time" due to the temperature rise varies depending on the conditions. That is, the temperature dependency of the drain current flowing through the nFET 10B is more strongly related to the gate voltage V g When the influence of the temperature dependency of the power transistor 100 is larger than that of the gate voltage V g It is necessary to distinguish between cases where the temperature dependency of the drain current through the nFET 10B has a larger effect than the temperature dependency of the drain current through the nFET 10C.

[0113] The temperature dependence of the drain current flowing through the nFET 10B is greater than the gate voltage V g When the influence of temperature on the resistance component Rnw(T) is greater than that of temperature on the resistance component Rnw(T), the change in the "turn-off time" can be reduced if the temperature dependency of the resistance component Rnw(T) of the switching control unit is such that the resistance value increases with increasing temperature. In particular, by using a resistance component electrically connected to nFET 10B that has a characteristic that the resistance value increases with increasing temperature, the change in the "turn-off time" can be suppressed.

[0114] In this regard, in the first embodiment, for example, as shown in FIG. 7, the resistance components electrically connected to the nFET 10B are the wiring resistance of the metal wiring WL3 electrically connected to the drain electrode DE1 of the nFET 10B and the metal wiring WL2 electrically connected to the source electrode SE1 of the nFET 10B. In this case, the metal wiring WL2 and the metal wiring WL3 are made of wiring mainly composed of aluminum, and have the characteristic that their resistance value increases with increasing temperature. Therefore, according to the first embodiment, the temperature dependency of the drain current flowing through the nFET 10B is stronger than that of the gate voltage V of the power transistor 100. g When the influence of the temperature dependency is greater than that of the metal wiring WL2, the change in the "turn-off time" is suppressed by the change in the wiring resistance of the metal wiring WL3, and as a result, the "turn-off time" can be kept almost constant regardless of the temperature rise.

[0115] Next, the verification results will be described.

[0116] Figure 9 is a graph showing the temperature dependence of "turn-on time." In Figure 9, the horizontal axis is temperature (°C) and the vertical axis is "turn-on time" (ns). The plots of black circles are experimental data, while the plots of white circles are calculated data.

[0117] Focusing on the experimental data in FIG. 9 , the “turn-on time” is 8.5 ns near room temperature (25°C), and when the temperature rises to around 200°C, the “turn-on time” temporarily decreases to 7 ns. Then, when the temperature rises from around 200°C to around 300°C, the “turn-on time” increases. This behavior can be qualitatively explained, for example, as follows. First, at temperatures below 200°C, as the temperature rises, the gate voltage (Miller plateau voltage) decreases and the drain current of pFET 10A increases. As a result, for example, based on Equation 2, the gate current of power transistor 100 increases, and therefore the “turn-on time” decreases according to Equation 1. This means that the experimental data can explain the decrease in the “turn-on time” from 8.5 ns to 7 ns. Next, when the temperature rises above 200°C, in the first embodiment, the increase in the drain current of pFET 10A is suppressed by the increase in the wiring resistance of metal wiring WL3 and the increase in the wiring resistance of metal wiring WL4. As a result, the gate current of power transistor 100 decreases, which increases the "turn-on time" according to Equation 1. In other words, the increase in the wiring resistance of metal wiring WL3 and the increase in the wiring resistance of metal wiring WL4 suppresses the decrease in the "turn-off time."

[0118] The behavior of the experimental data is explained as above. Based on this experimental data, the above behavior suppresses the fluctuation of the "turn-on time" within 18% when the temperature of silicon carbide power semiconductor device 1 is in the range of 25°C to 300°C.

[0119] Therefore, according to the first embodiment, it is confirmed that the decrease in the "turn-on time" of the power transistor 100 due to temperature changes is suppressed by the increase in the resistance value of the resistance components electrically connected to the CMOS transistor (the wiring resistance of the metal wiring WL3 and the wiring resistance of the metal wiring WL4) due to temperature changes.

[0120] It should be noted that the "turn-off time" hardly changes even when the temperature changes in a high-speed switching operation with a switching time of several nanoseconds. This is because the switching time is faster than the charging time required to accumulate charge in the output capacitance of the power transistor 100 and the Schottky barrier diode 110, and the "turn-off time" is rate-determined by the charging time. That is, for example, as shown in FIG. 5 , in the silicon carbide power semiconductor device 1 in the first embodiment, a semiconductor chip CHP1 on which the power transistor 100 is formed and a semiconductor chip CHP2 on which a CMOS transistor is formed are closely arranged, thereby enabling high-speed switching operation (several nanoseconds). In this case, the "turn-off time" has almost no temperature dependency, so it can be said that it is not necessary to adopt the basic idea that changes in the "turn-off time" are suppressed by changes in the wiring resistance of the metal wiring WL2 and the wiring resistance of the metal wiring WL3.

[0121] Here, "high-speed switching operation" is defined as a switching operation with a switching time of a few nanoseconds (e.g., 9 nanoseconds or less). For example, a switching time of 7 nanoseconds or more and 8 nanoseconds or less can be cited. On the other hand, "low-speed switching operation" can be defined as a switching operation with a switching time slower than "high-speed switching operation." For example, a switching operation with a switching time on the order of several tens of nanoseconds (e.g., 10 nanoseconds or more and 99 nanoseconds or less) can be cited.

[0122] In addition, when the switching time is several tens of nanoseconds, the "turn-off time" is also slower than the discharge time of the charge, and therefore it is considered that the temperature dependence is not determined by the discharge time. Here, the temperature dependence of the drain current flowing through the nFET 10B is particularly greater than the gate voltage V gConsider a case where a condition is realized in which the influence of the temperature dependency of nFET 10B is greater than the temperature dependency of nFET 10B. In this case, the configuration of Embodiment 1, which uses the wiring resistance of metal wiring WL3 electrically connected to drain electrode DE1 of nFET 10B and metal wiring WL2 electrically connected to source electrode SE1 of nFET 10B as resistance components electrically connected to nFET 10B, is useful in that it can maintain the "turn-off time" approximately constant regardless of temperature rise.

[0123] <<Variation 1>> Fig. 10 is a diagram showing a device structure in Modification 1. In Fig. 10, a p-type silicon carbide substrate SUB is provided with an n-type resistor element RD together with a pFET 10A. In this case, the n-type resistor element RD has an n-type semiconductor region RN formed in the p-type silicon carbide substrate SUB and a pair of electrodes EA and EB electrically connected to the n-type semiconductor region RN. A drain electrode DE2 of the pFET 10A and the electrode EA of the n-type resistor element RD are electrically connected by a wiring.

[0124] In this manner, in the present modification 1, for example, the resistance of the n-type semiconductor region RN constituting the n-type resistor element RD is used as the resistance component electrically connected to the pFET 10 A. In this regard, in a silicon carbide semiconductor, the n-type semiconductor region RN has a characteristic that the resistance value increases with an increase in temperature.

[0125] Therefore, according to this modification 1, the increase in the resistance value of the n-type semiconductor region RN constituting the n-type resistor element RD due to the increase in temperature can suppress the decrease in the "turn-on time" of the power transistor 100 due to the increase in temperature.

[0126] In the first modification, an example has been described in which the n-type resistor element RD is provided so as to be electrically connected to the drain electrode DE2 of the pFET 10A. However, the configuration of the first modification is not limited to this, and the n-type resistor element RD may be provided so as to be electrically connected to the source electrode SE2 of the pFET 10A. Furthermore, a configuration may be provided in which an n-type resistor element RD electrically connected to the drain electrode DE2 and an n-type resistor element RD electrically connected to the source electrode SE2 are provided.

[0127] Although not shown, the resistance of the n-type semiconductor region RN constituting the n-type resistor element RD can also be used as a resistance component electrically connected to the nFET 10B. In this case, the temperature dependency of the drain current flowing through the nFET 10B is higher than that of the gate voltage V g When the condition that has a larger influence than the temperature dependence of the n-type resistance element RD is satisfied, the increase in the resistance value of the n-type semiconductor region RN that constitutes the n-type resistance element RD due to the increase in temperature suppresses the decrease in the "turn-off time" of the power transistor 100 due to the increase in temperature.

[0128] <<Variation 2>> The temperature dependence of the drain current flowing through nFET 10B is greater than the gate voltage V g The basic idea behind the "turn-off time" is to use, as a resistance component electrically connected to nFET 10B, a resistance component whose resistance value increases with increasing temperature, under conditions where the influence of the temperature dependency of nFET 10B is greater than that of nFET 10B. In this regard, for example, as in the above-described first modification, an n-type resistance element RD can be used as the resistance component electrically connected to nFET 10B.

[0129] However, in nFET 10B, source region SRN and drain region DRN are composed of n-type semiconductor regions. Therefore, by adjusting the sizes of source region SRN and drain region DRN to have a resistance component, the basic idea of ​​using a resistance component (n-type semiconductor region) whose resistance value increases with increasing temperature as a resistance component electrically connected to nFET 10B can be realized.

[0130] Specifically, FIG. 11 is a diagram showing a device structure in the second modification.

[0131] As shown in FIG. 11 , in the nFET 10B of the present second modification, the size of the source region SRN is increased, and the size of the drain region DRN is also increased. In other words, the width of the source region SRN in the x-direction and the width of the drain region DRN in the x-direction are increased. This allows the parasitic resistance components of the source region SRN and the drain region DRN, which are n-type semiconductor regions, to be adjusted. Therefore, according to the present second modification, it is possible to provide the source region SRN and the drain region DRN with resistance components made of n-type semiconductor regions, thereby providing resistance components whose resistance value increases with increasing temperature. As a result, it is possible to suppress the decrease in the "turn-off time" of the power transistor 100 caused by increasing temperature.

[0132] <Realization mode 2> When focusing on the "turn-off time," in the above-described first embodiment, the temperature dependency of the drain current flowing through the nFET 10B is greater than the temperature dependency of the gate voltage V g It is assumed that the influence of the temperature dependence of the

[0133] In this case, by using a resistance component electrically connected to nFET 10B whose resistance value increases with increasing temperature, it is possible to suppress the decrease in the "turn-off time" of power transistor 100 that occurs with increasing temperature. In contrast, in the configuration of embodiment 1, the gate voltage V g If the temperature dependency of the drain current through nFET 10B has a larger effect than the temperature dependency of the drain current through nFET 10B, it becomes difficult to suppress the increase in "turn-off time" that accompanies a rise in temperature.

[0134] Therefore, in the second embodiment, the gate voltage V of the power transistor 100 g Assuming that the temperature dependency of the drain current through nFET 10B has a larger effect than the temperature dependency of the drain current through nFET 10B, we will explain some ideas for suppressing the increase in the "turn-off time" that accompanies a rise in temperature.

[0135] In this regard, the gate voltage V of the power transistor 100 g When the temperature dependency of the drain current through nFET 10B has a greater effect than the temperature dependency of the drain current through nFET 10B, the increase in the "turn-off time" of power transistor 100 due to an increase in temperature can be suppressed by using a resistance component electrically connected to nFET 10B that has a characteristic that its resistance value decreases with an increase in temperature (basic idea).

[0136] Below, an example that embodies this basic idea will be described.

[0137] Fig. 12 is a diagram showing a device structure in Embodiment 2. In Fig. 12, a p-type resistor element RD2 is provided together with an nFET 10B on a p-type silicon carbide substrate SUB. In this case, the p-type resistor element RD2 has a p-type semiconductor region RP included in an n-type well NWL formed in the p-type silicon carbide substrate SUB, and a pair of electrodes EA2 and EB2 electrically connected to the p-type semiconductor region RP. A drain electrode DE1 of the nFET 10B and the electrode EA2 of the p-type resistor element RD2 are electrically connected by a wiring.

[0138] In this way, in the second embodiment, for example, the resistance of the p-type semiconductor region RP constituting the p-type resistor element RD2 is used as the resistance component electrically connected to the nFET 10B. In this regard, in a silicon carbide semiconductor, the p-type semiconductor region RP has a characteristic that the resistance value decreases with an increase in temperature.

[0139] In silicon carbide semiconductors, aluminum (Al) is used as a p-type dopant, but while Al has a low ionization rate at low temperatures around room temperature, as the temperature rises, the ionization rate increases, the number of hole carriers increases, and the resistance value decreases.However, nitrogen (N) and phosphorus (P), which are n-type dopants in silicon carbide semiconductors, do not behave like Al dopants because they are sufficiently ionized and emit electrons even at room temperature.

[0140] Therefore, according to the second embodiment, the decrease in the resistance value of the p-type semiconductor region RP constituting the p-type resistor element RD2 with an increase in temperature can suppress the increase in the "turn-on time" of the power transistor 100 with an increase in temperature.

[0141] In the second embodiment, the p-type resistor element RD2 is provided so as to be electrically connected to the drain electrode DE1 of the nFET 10B. However, the configuration of the second embodiment is not limited to this, and the p-type resistor element RD2 may be provided so as to be electrically connected to the source electrode SE1 of the nFET 10B. Furthermore, the configuration may be such that a p-type resistor element RD2 electrically connected to the drain electrode DE1 and a p-type resistor element RD2 electrically connected to the source electrode SE1 are provided.

[0142] <Realization mode 3> In the third embodiment, an example will be described in which the basic idea of ​​the embodiment is applied to a semiconductor device in which a power transistor 100 and a switching control section 200 (CMOS transistor) are formed on one semiconductor chip.

[0143] FIG. 13 is a diagram showing the layout of a semiconductor chip CHP in the third embodiment.

[0144] In FIG. 13, the semiconductor chip CHP includes an input signal terminal TVin, a CMOS reference potential terminal TVSS, a CMOS power supply potential terminal TVDD, a power source terminal TVs, a CMOS area AR1 (switching control section area), and a power transistor area BR1.

[0145] 13, a CMOS region AR1 is arranged in the center of the semiconductor chip CHP, and an input signal terminal TVin, a CMOS reference potential terminal TVSS, and a CMOS power supply potential terminal TVDD are arranged on one side (left side) of the CMOS region AR1. Meanwhile, a power transistor region BR1 is arranged on the other side (right side) of the CMOS region AR1. Note that a power source terminal TVs is arranged within the power transistor region BR1 and above the power transistor.

[0146] Fig. 14 is a diagram showing cross sections taken along lines AA, BB, and CC in Fig. 13, illustrating the device structure of unit transistors in each region. In particular, in Fig. 14, region NAR is the region where nFET 10B constituting the switching control section (CMOS transistor) is formed, and corresponds to the AA cross section. Meanwhile, region PAR is the region where pFET 10A constituting the switching control section (CMOS transistor) is formed, and corresponds to the BB cross section. Furthermore, region BR1 is the region where power transistor 100 is formed, and corresponds to the CC cross section.

[0147] <<Device structure of power transistor 100>> 14, the semiconductor chip CHP includes a power transistor region BR1 and a CMOS region AR1. A power transistor 100 is formed in the power transistor region BR1, while an nFET 10B is formed in a region NAR of the CMOS region AR1. A pFET 10A is formed in a region PAR of the CMOS region AR1.

[0148] The power transistor 100 is composed of a trench-gate power MOSFET having a gate, a source, and a drain, whereas the nFET 10B is composed of a surface-channel MOSFET having a gate, a source, and a drain, and the pFET 10A is composed of a buried-channel MOSFET having a gate, a source, and a drain.

[0149] The power transistor 100, the nFET 10B, and the pFET 10A are formed on a laminated semiconductor substrate SB.

[0150] The laminated semiconductor substrate SB has a drift layer (n-type semiconductor layer) DL formed on the semiconductor substrate SUB1, a buried base layer (p-type semiconductor layer) BBL formed on the drift layer DL, and a base layer (p-type semiconductor layer) BL formed on the buried base layer BBL.

[0151] The semiconductor substrate SUB1 is an n-type silicon carbide substrate, and its polytype is, for example, 4H. That is, the semiconductor substrate SUB1 is made of an n-type 4H—SiC substrate.

[0152] The drift layer DL is an n-type semiconductor layer and is composed of an epitaxial layer formed on the semiconductor substrate SUB1 by epitaxial growth.

[0153] The buried base layer BBL is a p-type semiconductor layer formed on the drift layer DL using epitaxial growth and ion implantation. The buried base layer BBL has a thickness of approximately 1 μm. The buried base layer BBL has a layered structure of buried base layers BBL1 and BBL2, and the thicknesses of the buried base layers BBL1 and BBL2 are each approximately 0.5 μm.

[0154] The base layer BL is a p-type semiconductor layer, for example, an epitaxial layer formed on the buried base layer BBL by epitaxial growth. The base layer BL has a thickness greater than that of the buried base layer BBL. The base layer BL has a lower p-type impurity concentration than that of the buried base layer BBL. In the base layer BL, a channel formation region of the power transistor 100 is formed in the power transistor region BR1, while an nFET 10B and a pFET 10A are formed in the CMOS region AR1.

[0155] By forming the base layer BL as an epitaxial layer by epitaxial growth, it is possible to form a base layer BL having a relatively large thickness without using a special ion implantation device capable of outputting MeV-level ion implantation energy, thereby improving the degree of freedom in designing the breakdown voltage in the CMOS region AR1.

[0156] The semiconductor substrate SUB1, drift layer DL, and base layer BL are provided throughout the power transistor region BR1 and CMOS region AR1. The buried base layer BBL is provided throughout the CMOS region AR1, but is selectively provided in the power transistor region BR1. A trench protection region (p-type semiconductor region) TPR is provided at the bottom of the trench groove TG, and a JFET layer (n-type semiconductor layer) DLS1 and a JFET layer (n-type semiconductor layer) DLS2 are provided around the trench groove TG and trench protection region TPR.

[0157] In the power transistor region BR1, the buried base layer BBL is disposed in a region other than the regions where the trench protection region TPR, the JFET layer DLS1, and the JFET layer DLS2 are provided. In addition, a drain electrode ED is formed on the back surface of the semiconductor substrate SUB1 over the entire power transistor region BR1 and the CMOS region AR1.

[0158] In the power transistor region BR1, a trench groove TG is formed which penetrates from the surface of the laminated semiconductor substrate SB through the source region RSU and the base layer BL, and a gate insulating film GIU and a gate electrode EGU are formed in the trench groove TG.

[0159] The gate insulating film GIU is, for example, a silicon oxide film formed by using a CVD method. The gate electrode EGU is formed from a polysilicon film containing n-type impurities.

[0160] A source region (n-type semiconductor region) RSU and a p-type region (p-type semiconductor region) RPU are formed in the base layer BL. The source regions RSU are arranged on both sides of the trench groove TG, sandwiching the trench groove TG. The p-type region (p-type semiconductor region) RPU is arranged on the opposite side of the source region RSU from the trench groove TG or the gate electrode EGU. In other words, it can be said that the p-type region RPU is arranged between the source regions RSU of adjacent unit transistors. The source region RSU and the p-type region RPU are electrically connected to the source electrode ESU.

[0161] The p-type impurity concentration of the trench protection region (p-type semiconductor region) TPR provided at the bottom of the trench groove TG is equal to the p-type impurity concentration of the buried base layer BBL and higher than the p-type impurity concentration of the base layer BL. The trench protection region (p-type semiconductor region) TPR is an electric field relaxation layer. This trench protection region TPR has a structure in which the trench groove TG is embedded into the trench protection region TPR at the bottom of the trench groove TG to relax the electric field concentration in the gate insulating film GIU at the bottom of the trench groove TG. In other words, the depth of the trench groove TG is greater than the total film thickness of the base layer BL and the buried base layer BBL2, but less than the total film thickness of the base layer BL and the buried base layer BBL.

[0162] In the region between the drift layer DL and the base layer BL, the trench protection region TPR is sandwiched between JFET layers (n-type semiconductor layers) DLS1, and the trench groove TG is sandwiched between JFET layers (n-type semiconductor layers) DLS2. At the bottom of the trench groove TG, the gate insulating film GIU is covered with the trench protection region TPR, so that dielectric breakdown of the gate insulating film GIU can be prevented. Furthermore, by optimizing the n-type impurity concentrations of the JFET layers DLS1 and DLS2, dielectric breakdown of the gate insulating film GIU can be prevented without increasing the JFET resistance.

[0163] Furthermore, by providing a buried base layer BBL between the drift layer DL and the base layer BL, which has a p-type impurity concentration higher than the p-type impurity concentration of the base layer BL, the drain-source breakdown voltage of the power transistor 100 can be improved.

[0164] In addition, since the base layer BL in which the channel of the power transistor 100 is formed is formed of an epitaxial layer with a low impurity concentration, high channel mobility can be ensured, and thereby, the on-resistance of the power transistor 100 can be reduced. That is, by providing the embedded base layer BBL and the base layer BL with different p-type impurity concentrations, it is possible to improve the breakdown voltage between the drain and the source and reduce the on-resistance without being affected by each other.

[0165] The power transistor 100 is configured as described above.

[0166] <<Device Structure of CMOS Transistor>> The nFET 10B has a source region (n-type semiconductor region) RSN and a drain region (n-type semiconductor region) RDN formed in the base layer BL, a channel region RCN provided between the source region RSN and the drain region RDN, and a gate electrode EGN formed on the channel region RCN via a gate insulating film GIN.

[0167] The nFET 10B is a surface channel type MOSFET. When a desired gate voltage is applied to the gate electrode EGN, a channel is formed in the channel region RCN immediately below the interface between the base layer BL and the gate insulating film GIN. The channel region RCN provided between the source region RSN and the drain region RDN of the nFET 10B is a part of the p-type base layer BL, and since no impurity ions are implanted into the channel region RCN for threshold voltage adjustment, the p-type impurity concentration of the channel region RCN is equal to the p-type impurity concentration of the base layer BL.

[0168] The pFET 10A is formed in an n-type well region (n-type semiconductor region) NW formed in the base layer BL. The pFET 10A has a source region (p-type semiconductor region) RSP and a drain region (p-type semiconductor region) RDP formed in the n-type well region NW, and a gate electrode EGP formed on the surface of the stacked semiconductor substrate SB via a gate insulating film GIP.

[0169] The pFET 10A is a buried channel MOSFET having a buried channel region EBC approximately 0.2 μm thick from the surface of the laminated semiconductor substrate SB. The buried channel region EBC is a p-type semiconductor region within the n-type well NW, but is a region into which n-type impurities are not substantially ion-implanted. When a desired voltage is applied to the gate electrode EGP, a channel is formed not directly below the interface between the buried channel region EBC and the gate insulating film GIP, but at a position deeper than the interface.

[0170] The n-type well region NW is composed of an n-type well layer (n-type semiconductor layer) NW1, an n-type well layer (n-type semiconductor layer) NW2, and an n-type well layer (n-type semiconductor layer) NW3.

[0171] The n-type well layer NW1 is provided at a relatively deep position from the surface of the laminated semiconductor substrate SB, and an n-type well layer 2NW2 is provided on the n-type well layer NW1. The n-type well layer NW1 and the n-type well layer NW2 are formed, for example, by implanting nitrogen ions into the base layer BL. The p-type impurity concentration of the buried channel region EBC is equal to the p-type impurity concentration of the base layer BL. The p-type impurity concentration of the base layer BL means, for example, the p-type impurity concentration in the channel formation region of the power transistor 100.

[0172] In this manner, a CMOS transistor is configured.

[0173] <<Application of basic concepts>> The basic concept can also be applied to the semiconductor device of the third embodiment having the above-described configuration. For example, metal wiring can be used as a resistance component electrically connected to a CMOS transistor. Specifically, by intentionally extending the metal wiring and using the wiring resistance of the metal wiring as a resistance component electrically connected to the CMOS transistor, the temperature dependence of the drain current of the CMOS transistor constituting the switching control unit can be compensated for by the temperature dependence of the resistance component included in the switching control unit, and as a result, the temperature dependence of the switching time can be reduced.

[0174] Furthermore, in the third embodiment, it is also possible to utilize the resistance of an n-type semiconductor region or a p-type semiconductor region of a silicon carbide semiconductor, instead of the wiring resistance of a metal wiring, as in the above-described first and second modifications. For example, as a configuration that embodies the basic idea of ​​the third embodiment, it is also possible to provide an n-type resistor element or a p-type resistor element connected to a CMOS transistor.

[0175] <Expansion of the basic idea> In the above-described embodiment, the basic idea and an embodiment that embodies the basic idea are described on the assumption that the temperature dependency of the drain current in pFET 10A and nFET 10B that constitute the CMOS transistor is such that the drain current increases with increasing temperature.

[0176] However, depending on the manufacturing conditions of a CMOS transistor, it is possible that the temperature dependence of the drain current decreases with increasing temperature, rather than increasing with increasing temperature. Even in this case, the basic concept can be extended and applied.

[0177] For example, let us focus on the "turn-on time" among the switching times.

[0178] During the "turn-on time" of the power transistor 100, the gate current of the power transistor 100 is expressed by the above-mentioned (Equation 2). Here, the gate current I g corresponds to the drain current of the pFET 10A, and the drain current flowing through the pFET 10A decreases with increasing temperature. On the other hand, (Equation 2) also includes the gate voltage (Miller plateau voltage) V g This gate voltage V g decreases with increasing temperature.

[0179] In this way, the gate current I g The temperature dependence of the drain current flowing through the pFET 10A and the gate voltage V of the power transistor 100 areg It is necessary to consider both the temperature dependence of

[0180] In this regard, the drain current through pFET 10A decreases with increasing temperature, while the gate voltage V g Therefore, the temperature dependence of the drain current is as follows: g On the other hand, based on (Equation 3), the gate voltage V g The temperature dependence of the gate current I g In other words, the temperature dependence of the drain current flowing through the pFET 10A and the gate voltage V g This is the opposite characteristic to the temperature dependence of

[0181] Therefore, the temperature dependence of the drain current flowing through pFET 10A is greater than the gate voltage V g If the effect of temperature dependency is larger than that of g changes in a decreasing direction.

[0182] In contrast, the gate voltage V of the power transistor 100 g If the temperature dependency of the drain current through pFET10A is greater than the temperature dependency of the drain current through pFET10A, the gate current I g changes in an increasing direction.

[0183] From this, it can be seen that the temperature dependency of the drain current flowing through the pFET 10A is greater than the gate voltage V g When the influence of the temperature dependency of the resistance component Rpw(T) (resistance component 20) of the switching control unit 200 is greater than the temperature dependency of the resistance component Rpw(T), if the resistance value decreases with increasing temperature, the gate current I g The change in can be reduced.

[0184] On the other hand, the gate voltage V of the power transistor 100 gWhen the temperature dependency of the drain current flowing through the pFET 10A is greater than the temperature dependency of the drain current flowing through the pFET 10A, if the temperature dependency of the resistance component Rpw(T) (resistance component 20) of the switching control unit 200 is a temperature dependency in which the resistance value increases with an increase in temperature, the gate current I g The change in can be reduced.

[0185] From the above, as a basic concept (extension) of the "turn-on time", the temperature dependency of the drain current flowing through the pFET 10A is greater than the gate voltage V g When the influence of the temperature dependency of the power transistor 100 is larger than that of the gate voltage V g It is necessary to distinguish between cases where the temperature dependency of the drain current through the pFET 10A has a larger effect than the temperature dependency of the drain current through the pFET 10A.

[0186] The temperature dependence of the drain current flowing through the pFET 10A is greater than the gate voltage V g In the case where the influence of the temperature dependency is greater than the temperature dependency of the resistance component Rpw(T) (resistance component 20) of the switching control unit 200, the basic idea (extension) for the "turn-on time" is that if the temperature dependency of the resistance component Rpw(T) (resistance component 20) of the switching control unit 200 is a temperature dependency in which the resistance value decreases with the temperature rise, the gate current I g In this case, based on (Equation 1), it is possible to reduce the change in "turn-on time" that accompanies a temperature change.

[0187] On the other hand, the gate voltage V of the power transistor 100 g In the case where the temperature dependency of the drain current flowing through the pFET 10A has a larger effect than the temperature dependency of the drain current flowing through the pFET 10A, the basic idea (extension) of the "turn-on time" is that if the temperature dependency of the resistance component Rpw(T) (resistance component 20) of the switching control unit 200 is a temperature dependency in which the resistance value increases with the temperature rise, then the gate current I gIn this case, based on (Equation 1), it is possible to reduce the change in "turn-on time" that accompanies a temperature change.

[0188] Next, we will focus on the "turn-off time" of the switching time.

[0189] The gate current I of the power transistor 100 shown in (Equation 3) g corresponds to the drain current of nFET 10B, and this drain current decreases with increasing temperature. Also, in (Equation 3), the gate voltage (Miller plateau voltage) V g This gate voltage V g decreases with increasing temperature.

[0190] In this way, the gate current I g The temperature dependence of the drain current flowing through the nFET 10B and the gate voltage V g It is necessary to consider both the temperature dependence of

[0191] In this regard, the drain current through nFET 10B decreases with increasing temperature, while the gate voltage V g Therefore, based on (Equation 3), the temperature dependency of the drain current flowing through the nFET 10B and the gate voltage V g The temperature dependence of both is the change in the gate current I of the power transistor 100 as the temperature rises. g This contributes to reducing the temperature dependence of the drain current as well as the gate voltage V g Even if the temperature dependency of the resistance component Rnw(T) (resistance component 30) of the switching control unit 200 is taken into consideration, if the temperature dependency of the resistance component Rnw(T) (resistance component 30) is such that the resistance value decreases with increasing temperature, the gate current I g The change in can be reduced.

[0192] From the above, the basic idea of ​​the "turn-off time" is that if the temperature dependency of the resistance component Rnw(T) (resistance component 30) of the switching control unit 200 is a temperature dependency in which the resistance value decreases with the temperature rise, the gate current I of the power transistor 100 with the temperature rise g In this case, based on (Equation 1), it is possible to reduce the change in "turn-off time" that accompanies a temperature change.

[0193] From the above, the basic concept can be extended and applied even when the temperature dependency of the drain current of the CMOS transistor constituting the switching control unit 200 is a characteristic that decreases with increasing temperature rather than an increasing characteristic.

[0194] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention.

[0195] The embodiments include the following forms.

[0196] (Appendix 1) power transistors using semiconductor materials with a larger bandgap than silicon; a switching control unit that controls switching of the power transistor; A semiconductor device comprising: The switching control unit CMOS transistors made of semiconductor materials with a larger bandgap than silicon, a resistance component electrically connected to the CMOS transistor; Including, A semiconductor device in which a change in the switching time of the power transistor due to a change in temperature is suppressed by a change in the resistance value of the resistance component due to a change in temperature.

[0197] (Appendix 2): Corresponding to the expansion of the basic concept In the semiconductor device according to Supplementary Note 1, the switching time is the turn-on time of the power transistor; A semiconductor device, wherein an increase in the turn-on time of the power transistor due to an increase in temperature is suppressed by a change in the resistance component, the resistance value of which decreases with an increase in temperature.

[0198] (Appendix 3): Corresponding to the expansion of the basic concept In the semiconductor device according to Supplementary Note 1, the switching time is the turn-on time of the power transistor; A semiconductor device, wherein a decrease in the turn-on time of the power transistor due to an increase in temperature is suppressed by a change in the resistance component, the resistance value of which increases with an increase in temperature.

[0199] (Appendix 4): Corresponding to the expansion of the basic concept In the semiconductor device according to Supplementary Note 1, the switching time is the turn-off time of the power transistor; A semiconductor device, wherein an increase in the turn-off time of the power transistor due to an increase in temperature is suppressed by a change in the resistance component, the resistance value of which decreases with an increase in temperature. [Explanation of symbols]

[0200] 1. Silicon carbide power semiconductor device 10A pFET 10B nFET 20 Resistance component 30 Resistance component 100 Power Transistor 110 Schottky barrier diode 120 load 130 External power supply 200 Switching control section AR1 CMOS area BBL Embedded Base Layer BBL1 Embedded Base Layer BBL2 Embedded Base Layer BCP p-type body contact region BCN n-type body contact region BL Base Layer BR1 Power Transistor Area CHP semiconductor chip CHP1 semiconductor chip CHP2 semiconductor chip CHP3 semiconductor chip DE1 Drain electrode DE2 drain electrode DL Drift Layer DLS1 JFET layer DLS2 JFET layer DRN Drain region DRP drain region EA electrode EA2 electrode EB electrode EB2 electrode EBC buried channel region ED drain electrode EGU gate electrode EGN gate electrode EGP gate electrode GN gate electrode GIN gate insulating film GIP gate insulating film GIU gate insulating film GOX1 gate insulating film GOX2 gate insulating film GP gate electrode IL insulating layer NW n-type well region NW1 n-type well layer NW2 n-type well layer NW3 n-type well layer NWL n-type well PL p-type buried region RA area RCN channel region RD n-type resistor element RD2 p-type resistor element RDN drain region RDP Drain Area RN n-type semiconductor region RP p-type semiconductor region RPU p-type region RSN source region RSP source area RSU source region SB multilayer semiconductor substrate SE1 source electrode SE2 source electrode SRN source region SRP Source Region SUB p-type silicon carbide substrate SUB1 Semiconductor substrate TE1 terminal TE2 terminal TE3 terminal TE4 terminal TE5 terminal TE6 terminal TG Trench TPR trench protection area WB wiring board WL1 Metal Wiring WL2 Metal Wiring WL3 Metal Wiring WL4 Metal Wiring WL5 metal wiring

Claims

1. power transistors using semiconductor materials with a larger bandgap than silicon; a switching control unit that controls switching of the power transistor; Equipped with The switching control unit a CMOS transistor using a semiconductor material with a band gap larger than that of silicon; a resistance component electrically connected to the CMOS transistor; Including, A semiconductor device in which a change in a switching time of the power transistor due to a change in temperature is suppressed by a change in a resistance value of the resistance component due to a change in temperature, The switching time is the turn-on time or the turn-off time of the power transistor, A semiconductor device, wherein a decrease in the turn-on time or the turn-off time of the power transistor due to an increase in temperature is suppressed by a change in the resistance component whose resistance value increases with an increase in temperature.

2. 2. The semiconductor device according to claim 1, the switching time is the turn-on time, The CMOS transistor is a p-channel field effect transistor connected to a power supply potential; an n-channel field effect transistor connected to a reference potential; and a connection node between the drain of the p-channel field effect transistor and the drain of the n-channel field effect transistor is connected to the gate of the power transistor; a gate of the p-channel field effect transistor and a gate of the n-channel field effect transistor are electrically connected to each other; The semiconductor device, wherein the resistance component included in the switching control section includes a wiring resistance of a metal wiring electrically connected to the p-channel field effect transistor or a resistance of an n-type resistance element.

3. 2. The semiconductor device according to claim 1, The semiconductor device has a turn-on time of several nanoseconds or less.

4. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the fluctuation in the turn-on time is within 18% when the temperature of the semiconductor device is in the range of 25°C to 300°C.

5. 2. The semiconductor device according to claim 1, the switching time is the turn-off time, The CMOS transistor is a p-channel field effect transistor connected to a power supply potential; an n-channel field effect transistor connected to a reference potential; and a connection node between the drain of the p-channel field effect transistor and the drain of the n-channel field effect transistor is connected to the gate of the power transistor; a gate of the p-channel field effect transistor and a gate of the n-channel field effect transistor are electrically connected to each other; The resistance component included in the switching control section includes a wiring resistance of a metal wiring connected to the n-channel field effect transistor or a resistance of an n-type resistance element.

6. A power transistor using a semiconductor material with a band gap larger than that of silicon; a switching control unit that controls switching of the power transistor; Equipped with The switching control unit a CMOS transistor using a semiconductor material with a band gap larger than that of silicon; a resistance component electrically connected to the CMOS transistor; Including, A semiconductor device, wherein an increase in turn-off time of the power transistor due to a rise in temperature is suppressed by a change in the resistance component whose resistance value decreases with a rise in temperature, The CMOS transistor is a p-channel field effect transistor connected to a power supply potential; an n-channel field effect transistor connected to a reference potential; and a connection node between the drain of the p-channel field effect transistor and the drain of the n-channel field effect transistor is connected to the gate of the power transistor; a gate of the p-channel field effect transistor and a gate of the n-channel field effect transistor are electrically connected to each other; The semiconductor device, wherein the resistance component included in the switching control section includes a resistance of a p-type resistance element electrically connected to the n-channel field effect transistor.

7. 7. The semiconductor device according to claim 1, wherein The semiconductor device, wherein the turn-off time is on the order of several tens of nanoseconds.

8. The semiconductor device according to any one of claims 1 to 6, the power transistor is formed on a first semiconductor chip; the CMOS transistor is formed on a second semiconductor chip; The semiconductor device, wherein the semiconductor material is silicon carbide.

9. The semiconductor device according to any one of claims 1 to 6, the power transistor and the CMOS transistor are formed on a single semiconductor chip, The semiconductor device, wherein the semiconductor material is silicon carbide.

10. The semiconductor device according to any one of claims 1 to 6, the power transistor is a power MOSFET or an IGBT; The semiconductor device, wherein the semiconductor material is silicon carbide.

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