SRAM cell structure

Abstract

To design an SRAM cell such that the total area of the SRAM cell represented by λ2 can maintain within an allowable range even when the minimum feature size is reduced.SOLUTION: An SRAM cell includes a plurality of transistors, a set of contacts coupled to the plurality of transistors, a word-line electrically coupled to the plurality of transistors, a bit-line and a bit line bar electrically coupled to the plurality of transistors, a VDD contact line electrically coupled to the plurality of transistors, and a VSS contact line electrically coupled to the plurality of transistors, wherein as the minimum feature size of the SRAM cell gradually decreases from 28 nm, an area size (λ) of the SRAM cell in terms of square of a minimum feature size is the same or substantially the same.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to memory structures, and more particularly to static random access memory (SRAM) structures whose dimensions can be precisely controlled to effectively reduce the size of the SRAM structures. [Background technology]

[0002] Although improvements in the performance and cost of integrated circuits have been achieved to a large extent by process scaling technology following Moore's Law, process variations in transistor performance are a challenge when scaling down to the 28nm (or smaller) manufacturing process. In particular, scaling SRAM devices to increase storage density, reducing operating voltage (VDD) to reduce standby power consumption, and improving yield, which are necessary to realize large-capacity SRAM, are becoming increasingly difficult to achieve.

[0003] SRAM is a commonly used type of memory. An SRAM typically consists of an SRAM array and peripheral circuits such as a row address decoder, a column address decoder, and input / output circuits. The SRAM array contains multiple SRAM cells, each of which contains a static latch with two cross-coupled inverters. This means that as long as there are adequate power supply voltages (high-level voltage VDD and low-level voltage VSS) for the cells, periodic refreshing of the DRAM is not required to retain the stored information. The SRAM peripheral circuits (decoders, input / output circuits) are also connected to the same high-level voltage VDD and low-level voltage VSS. Furthermore, the high-level voltage VDD typically corresponds to a logic "1" stored in the SRAM, and the low-level voltage VSS typically corresponds to a logic "0" stored in the SRAM.

[0004] Figure 1 shows the architecture of a six-transistor (6-T) SRAM cell. It consists of two cross-coupled inverters (PMOS pull-up transistors PU-1 and PU-2, and NMOS pull-down transistors PD-1 and PD-2) and two access transistors (NMOS pass-gate transistors PG-1 and PG-2). A high-level voltage VDD is coupled to the PMOS pull-up transistors PU-1 and PU-2, and a low-level voltage VSS is coupled to the NMOS pull-down transistors PD-1 and PD-2. When a word line (WL) is enabled (i.e., a row is selected in the array), the access transistors are turned on, connecting the storage nodes (Node 1 / Node 2) to the vertical bit lines (BL and BL-bar).

[0005] Figure 2 is a "bar graph" showing the layout and connections of the six transistors in an SRAM. The bar graph usually includes only the active areas (vertical red lines) and gate lines (horizontal blue lines). Of course, some are directly connected to the six transistors, while others are connected to word lines (WL), bit lines (BTL), and so on. There are still many contacts, including those connected to the high-level voltage VDD and the low-level voltage VSS (BL and BL bar).

[0006] However, even if the manufacturing process is miniaturized to 28 nm or less (the so-called "minimum design dimension," "λ," or "F"), as shown in Figure 3, as the minimum design dimension becomes smaller, λ becomes smaller due to interference between the contact sizes and the layout of the metal lines connecting the word lines (WL), bit lines (BL and BL bar), high-level voltage VDD, low-level voltage VSS, etc. 2 or F 2 The total area of ​​the SRAM cell, expressed as

[0007] As the minimum design dimension decreases, λ 2 or F 2Some of the reasons for the dramatic increase in the total area of ​​an SRAM cell, represented by , can be explained as follows. A conventional 6T-SRAM connects six transistors with multiple interconnects, the first interconnect layer M1 of which connects the transistor's gate level (hereafter referred to as "gate") to the diffusion level (commonly referred to as "diffusion") of the source and drain regions. Without increasing the die size, M1 alone requires the addition of a second interconnect layer M2 and / or a third interconnect layer M3 to facilitate signal transmission (such as word lines (WL) and / or bit lines (BL and BL bar)). To connect M2 to M1, a structure called Via1 is formed using a certain conductive material. Thus, a vertical structure, i.e., "Diffusion-Contact-M1," is formed through a contact (Con) connection from the diffusion to M1. Similarly, another structure connecting the gate to M1 with a contact structure can also be formed as "Gate-Contact-M1." If a structure needs to be formed that connects the M1 interconnect to the M2 interconnect through Via1, it is called "M1-Via1-M2." A more complex wiring structure from the gate level to the M2 wiring can be described as "gate-contact-M1-Via1-M2." Furthermore, stacked wiring systems can have structures such as "M1-Via1-M2-Via2-M3" or "M1-Via1-M2-Via2-M3-Via3-M4." Because the gates and diffusions of two access transistors (NMOS pass-gate transistors PG-1 and PG-2 in Figure 1) connect to word lines (WL) and / or bit lines (BL and BL bar) located in the second wiring layer M2 or the third wiring layer M3, in conventional SRAMs, such metal connections must first pass through the wiring layer M1. This means that in state-of-the-art SRAM wiring systems, the gate or diffusion may not be able to connect directly to M2 without bypassing the M1 structure. As a result, the space required between one M1 wiring and another increases die size, and in some cases, this wiring connection may thwart the efficient channeling intent of directly using M2 to exceed the M1 region.Furthermore, it is difficult to form a self-aligned structure between the via 1 and the contact, and at the same time, both the via 1 and the contact are connected to their own wiring systems.

[0008] Furthermore, as shown in Figure 4, a conventional 6T-SRAM cell contains at least one NMOS transistor and one PMOS transistor in the adjacent regions of the p-type substrate and n-well, which are formed adjacent to each other. This creates a junction structure called an n+ / p / n / p+ parasitic bipolar device, which connects the n+ region of the NMOS transistor to the p-well, the adjacent n-well, and the p+ region of the PMOS transistor. If large noise occurs at the n+ / p junction or p+ / n junction, an abnormally large current flows through this n+ / p / n / p+ junction, potentially causing partial CMOS circuit operation to stop or even causing the entire chip to malfunction. This abnormal phenomenon, known as latch-up, adversely affects CMOS operation and must be avoided. One way to increase the resistance to latch-up, which is a weakness of CMOS, is to increase the distance from the n+ region to the p+ region. Therefore, increasing the distance from the n+ region to the p+ region to avoid latch-up also increases the size of the SRAM cell. [Prior art documents] [Non-patent literature]

[0009] [Non-Patent Document 1] J. Zhang et al., "15.1 A5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assisted Circuitry Schemes for High-Density and Low-VMIN Applications," 2020 IEEE International Semiconductor Circuits Conference (ISSCC), 2020, pp. 238-240. Summary of the Invention [Problem to be solved by the invention]

[0010] Therefore, even if the minimum design dimension is reduced, λ 2 The challenge is how to redesign the SRAM cell so that the total area of ​​the SRAM cell, expressed as , falls within an acceptable range. [Means for solving the problem]

[0011]

[0010] An embodiment of the present invention provides an SRAM structure. The SRAM cell includes a plurality of transistors, a set of contacts coupled to the plurality of transistors, a word line electrically coupled to the plurality of transistors, a bit line and a bit line bar electrically coupled to the plurality of transistors, a VDD contact line electrically coupled to the plurality of transistors, and a VSS contact line electrically coupled to the plurality of transistors. Even as the minimum design dimension (λ) of the SRAM cell gradually decreases from 28 nm (e.g., to 16 nm, 10 nm, 7 nm, 5 nm, or 3 nm), the square of the minimum design dimension (λ) decreases. 2 ) the area size of the SRAM cells is the same or substantially the same.

[0012] According to another aspect of the present invention, as the minimum design dimension of the SRAM cell gradually decreases from 28 nm, the area size (λ) of the SRAM cell converted into the square of the minimum design dimension 2 ) are the same or substantially the same.

[0013] According to another aspect of the present invention, when λ is reduced from 28 nm to 5 nm, the area size of the SRAM cell is 84λ 2 ~139λ 2 It is between.

[0014] According to another embodiment of the present invention, the length of one transistor is between 3 and 4λ.

[0015] According to another aspect of the present invention, the gate region of one of the plurality of transistors is directly connected to the source or drain region of the transistor through the first metal wiring, without going through another metal layer below the first metal wiring.

[0016] According to another aspect of the invention, a VDD or VSS contact line is placed below the original silicon surface of the substrate on which the plurality of transistors are formed.

[0017] According to another aspect of the present invention, a bottom surface of an n+ region of an NMOS transistor among the plurality of transistors is completely insulated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor among the plurality of transistors is completely insulated by a second insulator.

[0018] According to another aspect of the present invention, the edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor is between 2λ and 4λ.

[0019] According to another aspect of the present invention, the set of contacts comprises a set of first contacts and a set of second contacts, the first set of contacts being connected to a first metal layer and the second set of contacts being connected to a second metal layer but being decoupled from the first metal layer.

[0020] It is an object of the present invention to provide a smaller area SRAM structure, wherein the SRAM cell includes a plurality of transistors, a set of contacts coupled to the plurality of transistors, a word line electrically coupled to the plurality of transistors, a bit line and a bit line bar electrically coupled to the plurality of transistors, a VDD contact line electrically coupled to the plurality of transistors, and a VSS contact line electrically coupled to the plurality of transistors, and the area of ​​the SRAM cell is 84λ when the minimum design dimension is 5 nm. 2 ~672λ 2 When the minimum design dimension is 7 nm, the area of ​​the SRAM cell is 84λ 2 ~440λ 2 When the minimum design dimension is between 10 nm and over 7 nm, the area of ​​the SRAM cell is 84λ 2 ~300λ 2 When the minimum design dimension is between 16 nm and over 10 nm, the area of ​​the SRAM cell is 84λ 2 ~204λ 2 When the minimum design dimension is between 22 nm and over 16 nm, the area of ​​the SRAM cell is 84λ 2 ~152λ 2 When the minimum design dimension is between 28 nm and over 22 nm, the area of ​​the SRAM cell is 84λ 2 ~139λ 2 is within the range.

[0021] Another embodiment of the present invention provides an SRAM structure with direct connection from gate / diffusion to metal 2 layer, the SRAM including a plurality of transistors, a plurality of contacts coupled to the plurality of transistors, a first metal layer disposed over the plurality of transistors and electrically coupled to the plurality of transistors, a second metal layer disposed over the first metal layer and electrically coupled to the plurality of transistors, and a third metal layer disposed over the second metal layer and electrically coupled to the plurality of transistors, the plurality of contacts comprising a set of first contacts and a set of second contacts, the set of first contacts connected to the first metal layer and the set of second contacts connected to the second metal layer but decoupled from the first metal layer.

[0022] According to another aspect of the invention, the vertical length of the first contact is less than the vertical length of the second contact.

[0023] According to another aspect of the present invention, the gate region of one of the plurality of transistors is directly connected to the source or drain region of the transistor through the first metal wiring, without going through another metal layer below the first metal wiring.

[0024] According to another aspect of the present invention, a bottom surface of an n+ region of an NMOS transistor among the plurality of transistors is completely insulated by a first insulator, a bottom surface of a p+ region of a PMOS transistor among the plurality of transistors is completely insulated by a second insulator, and an edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor is between 2λ and 4λ.

[0025] Another object of the present invention is to provide an SRAM structure using miniaturized transistors, the SRAM including a plurality of transistors, wherein one transistor includes a gate structure having a length, a channel region, a first conductive region electrically coupled to the channel region, and a first contact hole located over the first conductive region, and the periphery of the first contact hole is not involved in the photolithography process.

[0026] According to another aspect of the present invention, the first contact hole includes a periphery surrounded by the periphery of the first conductive region.

[0027] According to another aspect of the present invention, the gate region of one of the plurality of transistors is directly connected to the source or drain region of the transistor through the first metal wiring, without going through another metal layer below the first metal wiring.

[0028] The advantages and spirit of the present invention can be understood from the following description taken in conjunction with the accompanying drawings: These and other objects of the present invention will no doubt become obvious to those skilled in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. [Brief explanation of the drawings]

[0029] The patent or patent application contains at least one drawing executed in color. Copies of the patent or patent application publication containing color drawing(s) will be provided by the United States Patent and Trademark Office (USPTO) upon request and payment of the necessary fee. [Figure 1] This is a circuit diagram of a normal 6T-SRAM. [Figure 2] This is a bar graph corresponding to the 6T-SRAM in Figure 1, where the active areas correspond to the vertical lines and the gate lines correspond to the horizontal lines. [Figure 3] FIG. 1 shows the total area of ​​an SRAM cell in units of λ2 (or F2) for different process dimensions λ (or F) according to currently available manufacturing processes. [Figure 4] 1A and 1B are cross-sectional views of conventional NMOS and PMOS structures. [Figure 5] FIG. 1 is a diagram showing a top view of a miniaturized metal-oxide-semiconductor field-effect transistor (mMOSFET) used in an SRAM according to the present invention. [Figure 6] FIG. 1 shows a cross section of a pad oxide layer, a pad nitride layer on a substrate, and an STI (Shallow Trench Isolation) oxide 1 formed on the substrate. [Figure 7] FIG. 1 illustrates a true gate (TG) and a dummy shield gate (DSG) formed above an active region. [Figure 8] FIG. 1 shows how a spin-on dielectric (SOD) is deposited and a well-designed gate mask layer is deposited and etched. [Figure 9] 1 shows the nitride layer over the dummy shield gate (DSG) with the DSG, a portion of the dielectric insulator corresponding to the DSG, and the p-type substrate 102 corresponding to the DSG removed. [Figure 10] FIG. 10 shows the removal of the gate mask layer, etching of the SOD, and deposition of an oxide 2 layer to form STI oxide 2. [Figure 11] FIG. 1 shows depositing an oxide 3 layer, etching to form oxide 3 spacers, forming lightly doped drains (LDDs) in a p-type substrate, depositing a nitride layer, etching back to form nitride spacers, and removing the dielectric insulator. [Figure 12] FIG. 1 shows an intrinsic silicon electrode being grown by selective epitaxy growth (SEG) technique. [Figure 13] FIG. 10 shows the deposition and etching back of a CVD-STI oxide trilayer to remove the intrinsic silicon electrodes and form the source (n+ source) and drain (n+ drain) of the mMOSFET. [Figure 14] FIG. 10 shows oxide spacers being deposited and etched to form contact hole openings. [Figure 15(a)] FIG. 1 shows how an SOD layer is deposited to fill the pores in the substrate and the surface is planarized by chemical mechanical polishing (CMP). [Figure 15(b)] FIG. 15(b) is a top view of FIG. [Figure 16] FIG. 15(b) shows a photoresistive layer formed on the structure in FIG. [Figure 17] FIG. 10 illustrates an anisotropic etching technique to remove the nitride cap layer in the exposed gate extension region, revealing the conductive metal gate layer. [Figure 18(a)] FIG. 10 shows the state after the photoresistive layer and the SOD layer are removed to form opening regions over both the source and drain regions, and spacers are formed. [Figure 18(b)] FIG. 18(b) is a top view of FIG. [Figure 19(a)] FIG. 10 is a diagram showing how a wiring network layer of Metal 1 is formed. [Figure 19(b)] 19(a) is a top view of FIG. 19(b), where the gate is connected to the source region through the metal 1 layer. [Figure 20(a)] 1 is a top view of the novel 6T-SRAM transistor up to the construction stage with multiple opening holes over both the gate extension and drain regions. [Figure 20(b)] 20(a) and 20(b) are cross-sectional views of two stages in the construction of a transistor along section lines 1 and 2 shown in FIG. 20(a). [Figure 20(c)] 20(a) and 20(b) are cross-sectional views of two stages in the construction of a transistor along section lines 1 and 2 shown in FIG. 20(a). [Figure 21(a)] FIG. 1 shows a top view of the transistors of the novel 6T-SRAM up to the construction stage where a highly doped conductive silicon plug (CoP) is grown using selective epitaxial growth (SEG) technology. [Figure 21(b)] 21(a) and 21(b) are cross-sectional views of two stages in the construction of a transistor along section lines 1 and 2 shown in FIG. 21(a). [Figure 21(c)] 21(a) and 21(b) are cross-sectional views of two stages in the construction of a transistor along section lines 1 and 2 shown in FIG. 21(a). [Figure 22(a)] This is a top view showing the transistors of the novel 6T-SRAM up to the construction stage where an oxide layer or low-k dielectric layer is deposited at a height above these conductor pillars (CoP). [Figure 22(b)] 22(a) and 22(b) are cross-sectional views of two stages in the construction of a transistor along section lines 1 and 2 shown in FIG. 22(a). [Figure 22(c)] 22(a) and 22(b) are cross-sectional views of two stages in the construction of a transistor along section lines 1 and 2 shown in FIG. 22(a). [Figure 23(a)] This figure shows a top view of the transistor of the novel 6T-SRAM up to the construction stage, in which a metal M1 layer is deposited, a thin oxide layer is deposited on the metal M1 layer, and a highly doped silicon pillar (CoP2) is formed by the SEG method using the top of these exposed conductor pillars (CoP) as a seed. [Figure 23(b)] 23(a) and 23(b) are cross-sectional views of two stages in the construction of a transistor along section lines 1 and 2 shown in FIG. 23(a). [Figure 23(c)] 23(a) and 23(b) are cross-sectional views of two stages in the construction of a transistor along section lines 1 and 2 shown in FIG. 23(a). [Figure 24(a)] Figure 1 shows a top view of the transistors of the novel 6T-SRAM up to the construction stage where a layer of oxide or low-k dielectric is deposited between and on top of the metal M1 layer, and a metal M2 layer is deposited to connect the heavily doped silicon pillars (CoP2). [Figure 24(b)] 24(a) and 24(b) are cross-sectional views of two stages in the construction of a transistor along section lines 1 and 2 shown in FIG. 24(a). [Figure 24(c)] 24(a) and 24(b) are cross-sectional views of two stages in the construction of a transistor along section lines 1 and 2 shown in FIG. 24(a). [Figure 25(a)] 1A and 1B are cross-sectional views of a PMOS transistor and an NMOS transistor used in an SRAM cell. [Figure 25(b)] 1A and 1B are cross-sectional views of a PMOS transistor and an NMOS transistor used in an SRAM cell. [Figure 26(a)]FIG. 25 is a top view showing a combined structure of the novel PMOS 52 and the novel NMOS 51 shown in FIGS. 25(a) and 25(b). [Figure 26(b)] 26(a) is a diagram showing a cross section of a combination of a novel PMOS 52 and a novel NMOS 51 along the cutting line (Y axis) of FIG. 26(a). [Figure 27] FIG. 1 illustrates a cross section of one conventional combination of PMOS and NMOS transistors. [Figure 28(a)] 25(a) and 25(b) show a top view of another combined structure of the novel PMOS 52 and the novel NMOS 51 shown in FIG. 25(a) and FIG. 25(b). [Figure 28(b)] 28(a) is a diagram showing a cross section of a combination of a novel PMOS 52 and a novel NMOS 51 along the cutting line (X-axis) in FIG. 28(a). [Figure 29] FIG. 2 shows a cross section of another combination of conventional PMOS and NMOS transistors. [Figure 30] 1 is a top view showing another combined structure of PMOS and NMOS transistors used in the novel SRAM cell. FIG. [Figure 31(a)] FIG. 3 is a diagram showing a "bar graph" as FIG. 2. [Figure 31(b)] 1 is a bar graph of a novel 6T-SRAM dimensioned according to the present invention. [Figure 32] 38 is a table showing definitions according to differences in mask layers used in FIGS. 33 to 37. [Figure 33(a)] 1 illustrates an embodiment according to the present invention. [Figure 33(b)] 1 illustrates an embodiment according to the present invention. [Figure 33(c)] 1 illustrates an embodiment according to the present invention. [Figure 33(d)] 1 illustrates an embodiment according to the present invention. [Figure 33(e)] 1 illustrates an embodiment according to the present invention. [Figure 33(f)] 1 illustrates an embodiment according to the present invention. [Figure 33(g)] 1 illustrates an embodiment according to the present invention. [Figure 34(a)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 34(b)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 34(c)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 34(d)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 34(e)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 34(f)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 34(g)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 34(h)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 35(a)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 35(b)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 35(c)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 35(d)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 35(e)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 35(f)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 35(g)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 35(h)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 36(a)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 36(b)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 36(c)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 36(d)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 36(e)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 36(f)]FIG. 10 illustrates another embodiment according to the present invention. [Figure 36(g)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 36(h)] FIG. 10 illustrates another embodiment according to the present invention. [Figure 37(a)] FIG. 10 illustrates yet another embodiment according to the present invention. [Figure 37(b)] FIG. 10 illustrates yet another embodiment according to the present invention. [Figure 37(c)] FIG. 10 illustrates yet another embodiment according to the present invention. [Figure 37(d)] FIG. 10 illustrates yet another embodiment according to the present invention. [Figure 37(e)] FIG. 10 illustrates yet another embodiment according to the present invention. [Figure 37(f)] FIG. 10 illustrates yet another embodiment according to the present invention. [Figure 37(g)] FIG. 10 illustrates yet another embodiment according to the present invention. [Figure 37(h)] FIG. 10 illustrates yet another embodiment according to the present invention. [Figure 38] FIG. 1 illustrates the difference in SRAM cell area (represented by λ2) between three different semiconductor foundries A, B, and C and different technology nodes obtained with the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0030] In conventional 6T-SRAM cells, even when the manufacturing process was scaled down to 28 nm or less (the so-called "minimum design dimension," "λ," or "F"), the transistor size did not shrink proportionally. This invention discloses a novel SRAM structure that precisely controls the linear dimensions of the source, drain, and gate of the transistors that make up the SRAM, making these linear dimensions as small as the minimum design dimension, lambda (λ). Therefore, when two adjacent transistors are connected through the drain / source, the distance between the edges of the gates of the two adjacent transistors can be as small as 2λ. Furthermore, by setting the linear dimensions of the source, drain, and gate contact holes to less than λ, for example, 0.6λ to 0.8λ, it is possible to achieve this within the drain region (as well as within the source and gate regions).

[0031] 5 is an example of a miniaturized metal-oxide-semiconductor field-effect transistor (mMOSFET) 100 used in an SRAM according to the present invention. As shown in FIG. 5, the mMOSFET 100 includes: (1) a gate structure 101 having a length G(L) and a width G(W); (2) a source 103 on the left side of the gate structure 101 having a length S(L) and a width S(W) which are linear dimensions from the edge of the gate structure 101 to the edge of the isolation region 105; (3) a drain 107 on the right side of the gate structure 101 having a length D(L) and a width D(W) which are linear dimensions from the edge of the gate structure 101 to the edge of the isolation region 105; (4) In the center of the source 103, a contact hole 109 formed by a self-aligned technique has an opening length and width marked CS(L) and CS(W), respectively. (5) Similarly, in the center of the drain 107, a contact hole 111 formed by a self-aligned technique has an opening length and width marked CD(L) and CD(W), respectively. The lengths G(L), D(L), and S(L) can be precisely controlled within the minimum design dimension λ. Furthermore, the length and width of the openings marked CS(L) and CS(W) or the length and width of the openings marked DS(L) and DS(W) can be less than λ, for example, 0.6λ to 0.8λ.

[0032] A brief description of the manufacturing process of the mMOSFET 100 used in the SRAM of the present invention follows. A detailed description of the structure of the mMOSFET 100 and its manufacturing process is provided in U.S. patent application Ser. No. 17 / 138,918, filed on December 31, 2020, and entitled "Miniaturized Transistor Structure with Controlled Source / Drain Dimensions and Contact Openings and Related Manufacturing Method," the entire contents of which are incorporated herein by reference.

[0033] As shown in Figure 6, a pad oxide layer 302 is formed on the substrate 102, and a pad nitride layer 304 is deposited. The active area of ​​the mMOSFET is defined, and a portion of the silicon material outside the active area is removed to create a trench structure. An oxide 1 layer is deposited within the trench structure and etched back to form a shallow trench isolation (STI oxide 1) 306 below the original horizontal surface of the silicon substrate (hereafter referred to as HSS).

[0034] The pad oxide layer 302 and pad nitride layer 304 are removed, and a dielectric insulator 402 is formed on the HSS. Next, as shown in Figure 7, a gate layer 602 and a nitride layer 604 are deposited on the HSS, and the gate layer 602 and the nitride layer 604 are etched to form a true gate of the mMOSFET and a dummy shield gate having a desired linear distance from the true gate. As shown in Figure 7, the length of the true gate and the dummy shield gate is λ, the length of the dummy shield gate is also λ, and the distance between the edges of the true gate and the dummy shield gate is also λ.

[0035] Next, a spin-on dielectric (SOD) 702 is deposited and the SOD 702 is etched back. As shown in Fig. 8, a well-designed gate mask layer 802 is formed by a photolithography mask technique. Then, as shown in Fig. 9, an anisotropic etching technique is used to remove the nitride layer 604 on the dummy shield gate (DSG), and remove the DSG, a portion of the dielectric insulator 402 corresponding to the DSG, and the p-type substrate 102 corresponding to the DSG.

[0036] 10, the gate mask layer 802 is removed, the SOD 702 is etched, and an STI oxide 2 1002 is deposited, followed by etching back. Next, as shown in FIG. 11, an oxide 3 layer is deposited and etched back to form oxide 3 spacers 1502, a lightly doped drain (LDD) 1504 is formed in the p-type substrate 102, a nitride layer is deposited and etched back to form nitride spacers 1506, and the dielectric insulator 402 is removed.

[0037] 13, an intrinsic silicon electrode 1602 is grown using a selective epitaxial growth (SEG) technique. Next, as shown in FIG. 13, a CVD-STI oxide 3 layer 1702 is deposited and etched back to remove the intrinsic silicon 1602, thereby forming a source region (n+ source) 1704 and a drain region (n+ drain) 1706 of the mMOSFET. The source region (n+ source) 1704 and the drain region (n+ drain) 1706 are formed between the true gate (TG) and the CVD-STI oxide 3 layer 1702 in the position that would normally be occupied by the dummy shield gate (DSG). Therefore, the length and width of the source region (n+ source) 1704 (or the drain region (n+ drain) 1706) are reduced to λ. The opening of the source region (n+ source) 1704 (or the drain region (n+ drain) 1706) can be less than λ, for example, 0.8λ. Such openings can be reduced by further forming oxide spacers 1802 as shown in FIG.

[0038] The novel SRAM structure also allows the first metal wiring (M1 layer) to directly connect the gate, source, and / or drain regions through self-aligned, scaled contacts, without the need for a conventional contact hole opening mask or metal 0 transition layer for M1 connection. Following Figure 13, a layer of SOD 1901 is deposited to fill the holes on the substrate, including the openings for the source region (n+ source) 1704 (or drain region (n+ drain) 1706). The surface is then planarized using CMP, as shown in Figure 15(a). Figure 15(b) is a top view of Figure 15(a), showing multiple horizontal fingers.

[0039] Furthermore, by using a well-designed mask, the photoresistive layer 1902 in several stripe patterns along the X-axis of FIG. 15(b) is implemented at another space of length GROC(L) to expose the area of ​​the gate extension region along the Y-axis of FIG. 15(b), and the result is as shown in the top view of FIG. 16. As shown in FIG. 16, this is the most aggressive design rule of GROC(L)=λ. Then, an anisotropic etching technique is used to remove the nitride cap layer in the exposed gate extension region to expose the conductive metal gate layer (FIG. 17).

[0040] The photoresistive layer 1902 is then removed, and the SOD layer 1901 is removed, so that the opening regions over both the source region 1704 and the drain region 1706 are exposed again. Next, a layer of oxide 1904 with a well-defined thickness is deposited, and then an anisotropic etching technique is used to form spacers on the opening regions of the source region 1704 and the drain region 1706 and on the four sidewalls of the exposed gate extension region 1903. Thus, naturally occurring contact hole openings are formed in the exposed gate extension region, source region 1704, and drain region 1706, respectively. Figure 18(a) is a cross-sectional view of such a transistor structure. Figure 18(b) is a top view of such a transistor structure of Figure 18(a). The vertical length CRMG(L) of the opening of the exposed gate extension region 1903 is smaller than the length GROC(L), which may be λ.

[0041] Finally, a layer of metal 1 1905 is formed with a well-designed thickness to fill all the contact hole openings and form a smooth plane that conforms to the wafer surface topography. Next, photolithography masking techniques are used to create all connections between these contact hole openings, respectively, to realize the necessary metal-1 wiring network, as shown in Figure 19(a). Figure 19(b) is a top view of the mMOSFET shown in Figure 19(a). Therefore, this metal 1 layer provides contact filling and plug connections for both the gate and source / drain, as well as direct wiring to connect all transistors. In particular, it eliminates the need for the expensive and highly controlled traditional contact hole masks and the subsequent highly challenging contact hole opening drilling process, which are considered the most challenging challenges in further scaling the horizontal geometries of billions of transistors. Furthermore, it eliminates the need for complex integrated processing steps (e.g., steps required for some cutting-edge technologies to create zero-metal structures) to insert metal plugs into contact hole openings and the CMP process to realize metal studs.

[0042] Furthermore, as mentioned above, in a conventional 6T-SRAM cell, the gate or diffusion may not be directly connected to M2 without bypassing the M1 structure. This invention discloses a novel SRAM structure in which either the gate region or the diffusion (source / drain) region is directly connected to the M2 wiring layer in a self-aligned manner without the transition layer M1 through a single vertical conductive plug consisting of Contact A and Via 1A, respectively, formed in the construction phase of Contact and Via 1 at another location on the same die. This reduces the space required between one M1 wire and another M1 wire, as well as blocking issues in some wiring connections. Below, we briefly describe a novel SRAM structure in which the gate region and the diffusion (source / drain) region are directly connected to the M2 wiring layer in a self-aligned manner without the transition layer M1.

[0043] FIG. 20 shows cross-sections and top views of a transistor of the novel 6T-SRAM up to the construction stage of forming multiple openings over both the gate extension region and the diffusion region, where FIG. 20(a) is a top view of the transistor construction stage, and FIGS. 20(b) and 20(c) are two cross-sectional views of the transistor construction stage along section lines 1 and 2 shown in FIG. 20(a). Similar to FIGS. 17 and 18(b), openings 2010 and 2012 are formed over both the gate extension region and the drain region, respectively. An insulator 2014 (e.g., oxide or low-k dielectric) is disposed around all of these openings 2010 and 2012. One major difference is that the gate extension region further includes a silicon region 608, which can be part of the polysilicon gate if a polysilicon gate is used as the gate conductor 602, or the silicon region 608 can be a layer formed over the gate metal if a gate metal is used as the gate conductor 602. As shown in Figure 20(c), the gate extension region further includes a nitride layer 604 over the silicon region 608. As shown in Figure 20(b), an opening hole 2010 exposes the silicon region 608 by etching at least a portion of the nitride layer 604.

[0044] Then, selective epitaxial growth (SEG) (or selective atomic layer deposition) is used to grow heavily doped conductive silicon plugs 2110, called conductor pillars (CoP), as shown in FIG. 21 (FIG. 21(a) is a top view of this transistor at this stage of construction, and FIGS. 21(b) and 21(c) are two cross-sectional views of this transistor at this stage of construction, taken along lines 1 and 2, respectively, shown in FIG. 21(a)). Next, either an oxide layer or a low-k dielectric layer 2120 is deposited at a height higher than these conductor pillars 2110. Next, either chemical mechanical polishing (CMP) or etch-back techniques are used to obtain a flat wafer surface, as shown in FIG. 22 (FIG. 22(a) is a top view of the transistor at this stage of construction, and FIGS. 22(b) and 22(c) are two cross-sectional views of this transistor at this stage of construction, taken along lines 1 and 2, respectively, shown in FIG. 22(a)). These "exposed heads" of the conductor pillars (CoP) 2110 are very useful landing pads for subsequent connection formation between the conductor pillars (CoP) 2110 and metal wiring connecting either the gate or drain regions, respectively. Form (LPad).

[0045] Further, a metal M1 layer 2140 is deposited, and a thin oxide layer 2160 is deposited on the metal M1 layer 2140. Using photolithography masking techniques, appropriate oxide removal techniques, and metal etching techniques, the design pattern of the metal M1 wiring is defined. Here, certain conductor pillar regions designed to directly connect either the gate region or the drain region, respectively, to the subsequent metal M2 layer are not covered by the metal M1 layer 2140 and are exposed again at their tops of the conductor pillars (CoP) 2110. These exposed tops of the conductor pillars (CoP) 2110 can be used to grow heavily doped silicon pillars (CoP2) 2180 on top of them, and these heavily doped silicon pillars (CoP2) 2180 will be used as vias 1-A, as shown in Figure 23 (Figure 23(a) is a top view of the transistor at this construction stage, and Figures 23(b) and 23(c) are two cross-sectional views of this construction stage along cut lines 1 and 2 shown in Figure 23(a), respectively).

[0046] Next, a layer of either oxide or low-k dielectric 2410 is deposited to a thickness sufficient to provide insulation between the metal M1 layer 2140 and subsequent metal layers. The thickness of this dielectric layer 2410 can be somewhat less than the height of the doped silicon pillar (CoP2) 2180, so that some exposed areas can naturally be used as via conductors (called Via 1A). Next, a metal M2 layer 2420 is deposited and defined using photolithographic masking techniques to complete the metal M2 wiring. This allows for the creation of a direct connection between the metal M2 layer and the gate or diffusion region, respectively, i.e., M2-Via 1A-CoP-gate or M2-Via 1A-CoP-drain (or source), as shown in FIG. 24 (FIG. 24(a) is a top view of the transistor at this stage of construction, and FIGS. 24(b) and 24(c) are two cross-sectional views of this stage of construction along section lines 1 and 2, respectively, shown in FIG. 24(a)). Of course, based on this embodiment, there may be other metal layer(s) or dielectric layer(s) between the first metal layer and the second metal layer, and the conductor pillar may connect to the second metal layer but be disconnected from the first metal layer and other metal layer(s).

[0047] Furthermore, the present invention discloses a novel SRAM structure in which the n+ and p+ regions of the source and drain regions of NMOS and PMOS transistors, respectively, are fully insulated by an insulator. Such an insulator not only increases resistance to latch-up issues, but also reduces the size of the SRAM by increasing the insulation distance to the silicon substrate to separate the junctions of the NMOS and PMOS transistors and reducing the surface distance between the junctions (e.g., 3λ). The following briefly describes the novel SRAM structure in which the n+ and p+ regions of the source and drain regions of NMOS and PMOS transistors, respectively, are fully insulated by an insulator. A detailed description of the novel combined PMOS and NMOS structure is provided in U.S. Patent Application No. 17 / 318,097, filed May 12, 2021, and entitled "Complementary MOSFET Structure with Local Insulator in Silicon Substrate to Reduce Leakage and Prevent Latch-Up," the entire contents of which are incorporated herein by reference.

[0048] See FIGS. 25(a) and 25(b). FIG. 25(a) is a cross-sectional view of a PMOS transistor 52, and FIG. 25(b) is a cross-sectional view of an NMOS transistor 51. A gate structure 33 having a gate dielectric layer 331 and a gate conductive layer 332 (e.g., a gate metal) is formed above a horizontal or original surface of a semiconductor substrate (e.g., a silicon substrate). A dielectric cap 333 (e.g., a composite of an oxide layer and a nitride layer) is provided on the gate conductive layer 332. Furthermore, a spacer 34 including a composite of an oxide layer 341 and a nitride layer 342 is used on the sidewall of the gate structure 33. Trenches are formed in the silicon substrate, and all or at least a portion of a source region 35 and a drain region 36 are disposed within the corresponding trenches. The source (or drain) region in the PMOS transistor 32 may include a P+ region or other suitable doping profile region (e.g., a gradual or step-like transition between a P− region and a P+ region). Additionally, a localized insulator 48 (e.g., nitride or other high-k dielectric material) is disposed in one trench and underlies the source region, and another localized insulator 48 is disposed in the other trench and underlies the drain region. Such localized insulator 48 is below the horizontal silicon surface (HSS) of the silicon substrate and can be referred to as localized insulator to silicon substrate (LISS) 48. The LISS 48 can be a composite of a thick nitride layer or a dielectric layer. For example, the localized insulator or LISS 48 can comprise a composite localized insulator including an oxide layer (referred to as oxide 3V layer 481) covering at least a portion of the sidewall of the trench and another oxide layer (referred to as oxide 3B layer 482) covering at least a portion of the bottom wall of the trench. The oxide 3V layer 481 and the oxide 3B layer 482 can be formed by a thermal oxidation process. The composite localized insulator 48 further includes a nitride layer 483 (referred to as nitride 3) overlying the oxide 3B layer 482 and in contact with the oxide 3V layer 481. It is said that the nitride layer 483 or nitride 3V may be replaced with any suitable insulating material as long as the oxide 3V layer remains as designed to the maximum extent possible.Furthermore, the STI (shallow trench isolation) regions of Figures 25(a) and 25(b) may have a composite STI 49 including an STI-1 layer 491 and an STI-2 layer 492, and the STI-1 layer 491 and the STI-2 layer 492 may each be composed of a thick oxide material by a different process.

[0049] Furthermore, the source (or drain) region in FIGS. 25(a) and 25(b) may comprise a composite source region 55 and / or drain region 56. For example, as shown in FIG. 25(a), in a PMOS transistor 52, the composite source region 55 (or drain region 56) comprises at least a lightly doped drain (LDD) 551 in a trench and a heavily P+ doped region 552. It is particularly noteworthy that the lightly doped drain (LDD) 551 abuts an exposed silicon surface having a uniform (110) crystal orientation. In contrast to the edge of the gate structure, labeled TEC (the well-defined etched transistor body thickness with a sharp edge having the effective channel length) in FIG. 25(a), the vertical boundary of the exposed silicon surface has a moderately recessed thickness. The exposed silicon surface is substantially conformal to the gate structure. The exposed silicon surface may also serve as the terminal surface of the transistor's channel.

[0050] The lightly doped drain (LDD) 551 and heavily P+ doped region 552 are formed based on a selective epitaxial growth (SEG) technique (or other suitable technique, which may be atomic layer deposition (ALD) or selective epitaxial growth (ALD-SALD)), in which silicon is grown from the exposed TEC region to be used as a crystalline seed to form a new, well-organized (110) lattice throughout the LISS region, which has no seeding effect on altering the (110) crystalline structure of the newly formed crystals of the composite source region 55 or drain region 56. Such newly formed crystals (including the lightly doped drain (LDD) 551 and heavily P+ doped region 552) may also be referred to as TEC-Si, as noted in FIG. 25( a). In one embodiment, the TEC is aligned or substantially aligned with the edge of the gate structure 33, the length of the LDD 551 is adjustable, and the sidewall of the LDD 551 on the opposite side of the TEC may be aligned with the sidewall of the spacer 34. Similarly, the TEC-Si (including the LDD region and the heavily n+ doped region) of the composite source / drain region of NMOS transistor 51 is shown in FIG. 25(b). The composite source (or drain) region may further comprise several tungsten (or other suitable metal material) plugs 553 formed in horizontal connection to the TEC-Si portion to complete the entire source / drain region, as shown in FIGS. 25(a) and 25(b). As shown in FIG. 25(a), active channel current flowing in a subsequent metal interconnect, such as a metal 1 layer, passes through LDD 551 and heavily doped conductive region 552 to tungsten 553 (or other metal material) that is directly connected to metal 1 by a good metal-to-metal ohmic contact, which has much lower resistance than conventional silicon-to-metal contacts.

[0051] One combined structure of a novel PMOS 52 and a novel NMOS 51 is shown in a top view in FIG. 26(a), and FIG. 26(b) is a cross-sectional view of the combined novel PMOS 52 and novel NMOS 51 along the cutting line (Y-axis) in FIG. 26(a). As shown in FIG. 26(b), since there is a composite local insulator (or LISS 48) between the bottom of the p+ source / drain region of the PMOS and the n-type N-well, there is also another composite local insulator (or LISS 48) between the bottom of the NMOS N+ source / drain region and the p-type P-well or substrate. The advantage of this novel CMOS structure shown in FIG. 26(b) is clearly shown to be that the bottoms of the n+ and p+ regions are completely isolated by an insulator. That is, any possible latch-up path from the bottom of the p+ region of the PMOS to the bottom of the n+ region of the NMOS is completely blocked by the LISS. On the other hand, in a conventional CMOS structure, the n+ and p+ regions are not completely isolated by an insulator, as shown in Figure 27. Therefore, the possible latch-up paths that exist from the n+ / p junction through the p-well / n-well junction to the n / p+ junction have lengths a, b, and c ("X" refers to a circled letter with the letter "X" in a circle). (FIG. 27). Therefore, from the viewpoint of device layout, the edge-to-edge distance (Xn+Xp) ensured between the NMOS and PMOS in FIG. 26(b) can be made smaller than that in FIG. 27. For example, the ensured edge-to-edge distance (Xn+Xp) can be about 2 to 4λ, e.g., about 3λ.

[0052] FIG. 28 is a top view of another combined structure of the novel PMOS 52 and the novel NMOS 51. 28(a), and FIG. 28(b) is a cross-sectional view of the combination of novel PMOS 52 and novel NMOS 51 along the cutting line (X-axis) in FIG. 28(a). As shown in FIG. 28(b), the path from the n+ / p junction through the p-well (or p-substrate) / n-well junction to the n / p+ junction is significantly longer. The possible latch-up paths from the LDD-n / p junction through the p-well / n-well junction to the n / LDD-p junction are length circle 1, length circle 2 (the length of the bottom wall of one LISS region), length circle 3, length circle 4, length circle 5, length circle 6, length circle 7 (the length of the bottom wall of another LISS region), and length circle 8 shown in FIG. 28(b). On the other hand, in a conventional CMOS structure that combines PMOS and NMOS structures as shown in FIG. 29, the possible latch-up paths from the n+ / p junction through the p-well / n-well junction to the n / p+ junction only have lengths d, e, f, and g (as shown in FIG. 29). The possible latch-up paths in FIG. 28(b) are longer than those in FIG. 29. Therefore, from the viewpoint of device layout, the edge-to-edge distance (Xn+Xp) ensured between the NMOS and PMOS in FIG. 28(b) can be smaller than that in FIG. 29. For example, the ensured edge-to-edge distance (Xn+Xp) can be about 2 to 4λ, e.g., about 3λ.

[0053] Furthermore, in conventional SRAMs, metal lines for the high-level voltage VDD and the low-level voltage VSS (or ground) are arranged above the original silicon surface of the silicon substrate. This distribution can cause interference if there is insufficient space between other word lines (WL), bit lines (BL, BL bar), or other connecting metal lines. The present invention discloses a novel SRAM structure that allows the metal lines for the high-level voltage VDD and / or the low-level voltage VSS to be arranged below the original silicon surface of the silicon substrate. Thus, even if the size of the SRAM cell is reduced, interference between the size of the contacts and the layout of the metal lines connecting the word lines (WL), bit lines (BL and BL bar), high-level voltage VDD, and low-level voltage VSS can be avoided. As shown in FIG. 27, in the drain region of PMOS 52, metal material 553 such as tungsten is directly coupled to an N-well electrically coupled to VDD. Meanwhile, in the source region of NMOS 51, metal material 553 such as tungsten is directly coupled to a P-well or P-type substrate electrically coupled to ground. Thus, openings for source / drain regions that would otherwise be used to electrically couple the source / drain regions to metal layer 2 or metal layer 3 for V or ground connection may be omitted in the novel SRAM structure. A detailed description of the structure and its fabrication process is provided in U.S. patent application Ser. No. 16 / 991,044, filed Aug. 12, 2020, and entitled "Transistor Structure and Related Inverter," the entire contents of which are incorporated herein by reference.

[0054] As described above, the new 6T-SRAM cell has at least the following advantages: (1) The linear dimensions of the source, drain, and gate of a transistor in an SRAM can be precisely controlled, making the linear dimensions as small as lambda (λ), the minimum design dimension. Therefore, when two adjacent transistors are connected through their drain / source, the length of the transistor can be as small as 3λ, and the distance between the edges of the gates of two adjacent transistors can be as small as 2λ. Of course, due to tolerances, the length of the transistor will be around 3λ to 4λ. (2) The first metal wiring (M1 layer) is directly connected to the gate, source, and / or drain regions through self-aligned, scaled contacts, without the need for conventional contact hole opening masks or metal 0 transition layers for M1 connection. (3) The gate and / or diffusion (source / drain) regions are directly connected to the M2 wiring layer in a self-aligned manner without an M1 transition layer, thereby reducing the space required between one M1 wire and another and reducing blocking issues in some wiring connections. (4) The n+ and p+ regions of the source and drain regions in NMOS and PMOS transistors, respectively, are completely isolated by an insulator, which not only increases the resistance to latch-up problems but also increases the insulation distance to the silicon substrate, separating the junctions of NMOS and PMOS transistors and reducing the surface distance between the junctions (for example, by 3λ), thereby reducing the size of the SRAM. (5) Metal lines for the high-level voltage VDD and / or low-level voltage VSS of the SRAM cell can be arranged below the original silicon surface of the silicon substrate, so that even if the size of the SRAM cell is reduced, interference between the size of the contacts and the layout of the metal lines connecting the word lines (WL), bit lines (BL and BL bar), high-level voltage VDD and low-level voltage VSS, etc. Furthermore, openings for the source / drain regions that are originally used for electrical coupling between the source / drain regions and metal layer 2 or metal layer 3 for VDD or ground connection may be omitted in the novel SRAM structure.

[0055] Figure 31(a) is a reproduction of Figure 2, showing a "bar graph" representing the layout and connections between the six transistors of the SRAM, and Figure 31(b) is a dimensional bar graph according to the advantages of the novel 6T-SRAM structure. As shown in Figure 31(b), the length dimension of the transistors can be as small as 3λ (enclosed by the dotted rectangle), and the distance between the edges of the gates of two adjacent transistors can be as small as 2λ. Furthermore, the insulation distance to the silicon substrate separating the junctions of the NMOS and PMOS transistors can be as small as 3λ (enclosed by the dashed rectangle). The insulation distance to the silicon substrate separating the junctions of two PMOS transistors can be between 1.5 and 2.5λ, e.g., 2λ (enclosed by the dashed-dotted rectangle).

[0056] In Figure 31(b), the dimensions of the active region (vertical lines) can be reduced to approximately λ, as can the dimensions of the gate lines (horizontal lines). Furthermore, in Figure 31(b), the upper left transistor, which corresponds to the PG transistor in Figure 31(a), has a horizontal distance of 1.5λ (surrounded by a two-dot dashed rectangle) between the edge of the active region and the boundary of the SRAM cell or bit cell to avoid interference between the two contact holes that will be formed later in the active region and gate region, respectively. The same is true for the transistor in the lower right corner of Figure 31(b), which corresponds to another PG transistor in Figure 31(a). Thus, in the bar graph of Figure 31(b), the horizontal length (x-direction) of the SRAM cell or bit cell is 15λ, and the vertical length (y-direction) of the SRAM cell or bit cell is 6λ. Therefore, the total area of ​​the SRAM cell or bit cell in Figure 31(b) is 90λ. 2 This becomes:

[0057] Using the bar graph in Figure 31(b) as a template, at least five SRAM cell structures are proposed in this invention, as shown in Figures 32 to 37. Figure 32 defines the different mask layers used in Figures 33 to 37, and the abbreviations have the meanings shown in Table 1 below. [Table 1]

[0058] As shown in FIG. 33(a), which is a copy of FIG. 31(b), the area of ​​the SRAM cell in this embodiment is 90λ. 2 In FIG. 33(b), multiple CT_As (open via mask layers for connecting AA (or Poly) to the Metal 1 layer) and multiple CT_Bs (open via mask layers for directly connecting AA (or Poly) to the Metal 2 layer, surrounded by dashed ellipses) are formed. In FIG. 33(c), a Metal 1 mask layer (M1) is formed to connect multiple CT_As, but multiple CT_Bs are not connected to the Metal 1 mask layer (M1). In FIG. 33(d), a Metal 2 mask layer (M2) is formed to connect at least multiple CT_Bs. Parts of the Metal 2 mask layer (M2), surrounded by two dashed ellipses, are used as bit lines (BL) and bit line bars (BLB). In FIG. 33(e), multiple vias 2 are formed, and in FIG. 33(f), a Metal 3 mask layer (M3) is formed to connect multiple vias 2, and the Metal 3 mask layer (M3) is used as a word line (WL). Figure 33(g) shows a two-dimensional array of six SRAM cells of the present invention. In this embodiment, there is no via 1, and metal lines for the high-level voltage VDD and / or low-level voltage VSS in the SRAM cell are placed below the original silicon surface of the silicon substrate, as shown in Figure 30. Also, as shown in Figure 33(c), a metal 1 mask layer (M1) directly penetrates and connects to the gate, source, and / or drain regions without using a conventional contact hole opening mask or metal 0 transition layer.

[0059] 34(a) to 34(h) are diagrams showing another embodiment of the present invention. As shown in FIG. 34(a), which is a copy of FIG. 31(b), the area of ​​the SRAM cell in this embodiment is also 90λ. 2In FIG. 34(b), multiple CT_As (open via mask layers for connecting AA (or Poly) to the Metal 1 layer) and multiple CT_Bs (open via mask layers for directly connecting AA (or Poly) to the Metal 2 layer) are formed. Compared to FIG. 33(b), two more CT_As are formed in FIG. 34(b) (encircled by dashed ovals) for later electrical coupling to VSS. In FIG. 34(c), a Metal 1 mask layer (M1) is formed to connect the multiple CT_As, but the multiple CT_Bs are not connected to the Metal 1 mask layer (M1). In FIG. 34(d), multiple vias 1 (encircled by dashed ovals) are formed to connect the Metal 1 layer and the Metal 2 layer. In FIG. 34(e), a Metal 2 mask layer (M2) is formed to connect at least multiple CT_Bs and multiple vias 1. Portions of the Metal 2 mask layer (M2) are used as bit lines (BL) and bit line bars (BLB). In FIG. 34(f), multiple vias 2 are formed, and some of the vias 2 (encircled by dashed ovals) will be used for electrical coupling to Vss. In FIG. 34(g), a metal 3 mask layer (M3) is formed to connect the multiple vias 2. One metal 3 mask layer (M3) is used as a word line (WL), and the remaining two metal 3 mask layers (shown by dashed ovals) are used as metal lines for Vss connection. FIG. 34(h) shows a two-dimensional array of six SRAM cells of the present invention. In this embodiment, the metal lines for the high-level voltage VDD in the SRAM cells are located below the original silicon surface, while the metal lines for the low-level voltage Vss are located above the silicon substrate. Also, as shown in FIG. 34(c), a metal 1 mask layer (M1) directly penetrates and connects to the gate, source, and / or drain regions without using a conventional contact hole opening mask or metal 0 transition layer.

[0060] 35(a) to 35(h) are diagrams showing another embodiment of the present invention. As shown in FIG. 35(a), which is a copy of FIG. 31(b), the area of ​​the SRAM cell in this embodiment is also 90λ. 2In FIG. 35(b), multiple CT_As (open via mask layers for connecting AA (or Poly) to the Metal 1 layer) and multiple CT_Bs (open via mask layers for directly connecting AA (or Poly) to the Metal 2 layer) are formed. Compared to FIG. 34(b), two more CT_Bs are formed in FIG. 35(b) for later electrical coupling to Vdd (encircled by dashed ovals). In FIG. 35(c), a Metal 1 mask layer (M1) is formed to connect multiple CT_As, but multiple CT_Bs are not connected to the Metal 1 mask layer (M1). In FIG. 35(d), multiple vias 1 are formed to connect the Metal 1 layer and the Metal 2 layer. In FIG. 35(e), a Metal 2 mask layer (M2) is formed to connect at least multiple CT_Bs and multiple vias 1. Some of the metal 2 mask layers (M2) are used as bit lines (BL) and bit line bars (BLB), and one metal 2 mask layer (M2) is used as a VDD metal line (shown by a dashed oval). In FIG. 35(f), multiple vias 2 are formed, and some of the vias 2 are used to electrically couple to Vss. In FIG. 35(g), a metal 3 mask layer (M3) is formed to connect the multiple vias 2. One metal 3 mask layer (M3) is used as a word line (WL), and the remaining two metal 3 mask layers are used as metal lines for Vss connection. FIG. 35(h) shows six SRAM cells of the present invention arranged in a two-dimensional array. In this embodiment, the metal lines for the high-level voltage VDD and the low-level voltage VSS are arranged above the silicon substrate. Also, as shown in FIG. 35(c), the metal 1 mask layer (M1) directly penetrates and connects to the gate, source, and / or drain regions without using a conventional contact hole opening mask or metal 0 transition layer.

[0061] 36(a) to 36(h) are diagrams showing another embodiment of the present invention. As shown in FIG. 36(a), a slight difference from FIG. 31(b) or FIG. 35(a) is that when a large current is applied, the insulation distance to the silicon substrate for separating the junctions of the NMOS transistor and the PMOS transistor is set to 4.5λ (indicated by the dashed oval). Furthermore, the horizontal distance between the edge of the active region and the boundary of the SRAM cell or bit cell is proactively set to 1λ (indicated by the dotted oval). Thus, in the case of the bar graph in FIG. 36(a), the horizontal length (x direction) of the SRAM cell or bit cell is 17λ, and the vertical length (y direction) of the SRAM cell or bit cell is also 6λ. Therefore, the area of ​​the SRAM cell in this embodiment is also 102λ. 2 The other processes in Figures 36(b) to 36(h) are the same as those in Figures 35(b) to 35(h), so the description of Figures 36(b) to 36(h) will not be repeated and will be omitted.

[0062] 37(a)-37(h) illustrate another embodiment according to the present invention. In this embodiment, horizontally adjacent SRAM bit cells share a bit line / bit line bar, and interleaved word lines are used to control the operation of the SRAM cells. A bar graph of two adjacent SRAM bit cells is shown in FIG. 37(a). The horizontal distance between the edge of the active area and the boundary of the SRAM bit cell is proactively set to 1λ (indicated by the dashed oval), and other dimensions of the SRAM bit cell are the same as those in FIG. 33(b). Thus, the horizontal (x-direction) length of the SRAM cell or bit cell is 14λ, and the vertical (y-direction) length of the SRAM cell or bit cell is also 6λ. Therefore, the area of ​​the SRAM cell in this embodiment is also 84λ. 2 is.

[0063] In FIG. 37(b), multiple CT_As (open via mask layers for connecting AA (or Poly) to the Metal 1 layer) and multiple CT_Bs (open via mask layers for directly connecting AA (or Poly) to the Metal 2 layer) are formed. Compared with FIG. 33(b), only two CT_Bs (shown by dashed ovals) are formed in FIG. 37(b) for later electrical coupling to interleaved word lines (WL1, WL2). In FIG. 37(c), a Metal 1 mask layer (M1) is formed to connect multiple CT_As, but multiple CT_Bs are not connected to the Metal 1 mask layer (M1). In FIG. 37(d), multiple vias 1 are formed to connect the Metal 1 layer and the Metal 2 layer. In FIG. 37(e), a Metal 2 mask layer (M2) is formed to connect at least multiple CT_Bs and multiple vias 1. Portions of the Metal 2 mask layer (M2), enclosed by dashed ovals, are used as shared bit lines (BL) and shared bit line bars (BLB). In FIG. 37(f), multiple vias 2 are formed, and some of the vias 2 are used to electrically couple to the interleaved word lines (WL1 / WL2). In FIG. 37(g), a metal 3 mask layer (M3) is formed to connect the multiple vias 2. The metal 3 mask layer (M3) is used as the interleaved word lines (WL1 / WL2). FIG. 37(h) shows a two-dimensional array of 12 SRAM cells of the present invention. In this embodiment, the metal lines for the high-level voltage VDD and the low-level voltage VSS are located below the silicon substrate. Also, as shown in FIG. 37(c), the metal 1 mask layer (M1) directly penetrates and connects to the gate, source, and / or drain regions without using a conventional contact hole opening mask or metal 0 transition layer. Of course, the embodiments of FIGS. 37(a) through 37(h) can be modified so that the metal lines for the high-level voltage VDD and / or the low-level voltage VSS are located above the silicon substrate.

[0064] Figure 38 shows the SRAM cell area (λ) among different technology nodes obtained from three different semiconductor foundries A, B, and C. 2As design dimensions become smaller, the size of the SRAM cell (λ 2 It can be seen that the SRAM cell area between different technology nodes can be kept flat or low sensitivity to the technology node by the design described in this invention and its derivative designs, which means that from the technology node of 28 nm to the technology node of 5 nm, the SRAM cell area according to this invention is 84λ 2 ~102λ 2 can be maintained within the range of

[0065] Of course, it is not necessary to utilize all of the proposed improvements in the novel SRAM cell structure of the present invention; only one of the proposed techniques can reduce the area of ​​the SRAM cell structure compared to a transitional SRAM cell. For example, by reducing the active area (or simply connecting the gate / source / drain contacts ("CT") with a second metal layer) in accordance with the present invention, the area of ​​the SRAM can be reduced by 84λ at the 5 nm technology node. 2 ~700λ 2 Within the range of 84λ at the 7nm technology node 2 ~450λ 2 Within the range of technology nodes from 10nm to over 7nm, 84λ 2 ~280λ 2 Within the range of technology nodes from 20nm to over 10nm, 84λ 2 ~200λ 2 Within the technology node range of 28nm to over 20nm, 84λ 2 ~150λ 2 For example, by reducing the area of ​​the active region, the area of ​​the SRAM can be reduced to 160λ at ​​the 5nm technology node. 2 ~240λ 2 (or more if further tolerance is required), and for the 16nm technology node, the area of ​​the SRAM is 107λ 2 ~161λ 2 (or more if further tolerance is required).

[0066] The area (λ 2 ), the linear dimensions of the present invention may be 0.9 (or less, e.g., 0.85, 0.8, or 0.7) times the linear dimensions of the conventional SRAM of FIG. 3, and the area of ​​the present invention may be at least 0.81 (or less, e.g., 0.72, 0.64, or 0.5) times the area of ​​the conventional SRAM of FIG. 3, as shown in Table 2 below. [Table 2]

[0067] Therefore, in another embodiment of the present invention, when the minimum design dimension (λ) is 5 nm, the area of ​​the SRAM cell of the present invention is 672λ 2 When the minimum design dimension is 7 nm, the area of ​​the SRAM cell is 440λ 2 (or 400λ 2 , 350λ 2 ) or less. When the minimum design dimension is between 10 nm and over 7 nm, the area of ​​the SRAM cell is 300λ 2 (or 268λ 2 When the minimum design dimension (λ) is between 16 nm and over 10 nm, the area of ​​the SRAM cell is 204λ 2 When the minimum design dimension (λ) is between 22 nm and over 16 nm, the area of ​​the SRAM cell is 152λ 2 When the minimum design dimension (λ) is between 28 nm and over 22 nm, the area of ​​the SRAM cell is 139λ 2 The following is the result.

[0068] Furthermore, in another embodiment, when the minimum design dimension is 5 nm, the area of ​​the SRAM cell is 84λ 2 ~672λ 2 When the minimum design dimension is 7 nm, the area of ​​the SRAM cell is 84λ 2 ~440λ 2 When the minimum design dimension is between 10 nm and over 7 nm, the area of ​​the SRAM cell is 84λ 2~300λ 2 When the minimum design dimension is between 16 nm and over 10 nm, the area of ​​the SRAM cell is 84λ 2 ~204λ 2 When the minimum design dimension is between 22 nm and over 16 nm, the area of ​​the SRAM cell is 84λ 2 ~152λ 2 When the minimum design dimension is between 28 nm and over 22 nm, the area of ​​the SRAM cell is 84λ 2 ~139λ 2 is within the range.

[0069] While the invention has been described with reference to embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. [Explanation of symbols]

[0070] 35 Source Region 36 Drain region 52 PMOS transistors 100mMOSFET 101 Gate Structure 102 Circuit Board 103 Source 105 spacer, isolation area 107 Drain 109 Contact Hole 302 Pad oxide layer 304 Pad nitride layer 306 STI Oxide 341 Oxide layer 342 nitride layer 483 nitride layer 481 Oxide 3V layer 482 Oxide 3B layer 402 Dielectric Insulators 602 Gate Layer 604 nitride layer 608 Silicon Region 702 Spin-on Dielectric 802 Gate Mask Layer 1504 Lightly doped drain 1506 Nitride Spacer 1602 Intrinsic Silicon Electrode 1702 STI Oxide 3 Layer 1704 Source Area 1706 Drain Region 1901 SOD layer 1902 Photoresistance layer 1904 Oxide 2010, 2012 Opening hole 2110 Conductor pillar 2140 Metal M1 layer 2180 Highly doped silicon pillars 2410 Dielectric layer 2420 Metal M2 layer WL Word Line BL bit line

Claims

1. An SRAM cell comprising: a plurality of transistors; a set of contacts coupled to the plurality of transistors; a word line electrically coupled to the plurality of transistors; bit lines and bit line bars electrically coupled to the plurality of transistors; a VDD contact wire electrically coupled to the plurality of transistors; a VSS contact wire electrically coupled to the plurality of transistors; The minimum design dimension (λ) of the SRAM cell is between 28 nm and 5 nm, and the square of the minimum design dimension (λ ２ The area size of the SRAM cell converted into ２ Smaller, 84λ ２ Bigger, a bottom surface of an n+ region of an NMOS transistor among the plurality of transistors is completely insulated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor among the plurality of transistors is completely insulated by a second insulator; SRAM cell.

2. 2. The SRAM cell of claim 1, wherein the length of one transistor is between 3λ and 4λ.

3. 2. The SRAM cell of claim 1, wherein a gate region of one of the plurality of transistors is directly connected to a source region or a drain region of the transistor through the first metal wiring without going through another metal layer below the first metal wiring.

4. 2. The SRAM cell of claim 1, wherein the edge-to-edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor is between 2λ and 4λ.

5. 2. The SRAM cell of claim 1, wherein the set of contacts comprises a first set of contacts and a second set of contacts, the first set of contacts being connected to a first metal layer and the second set of contacts being connected to a second metal layer but decoupled from the first metal layer.

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