Standard Cell Structure

Abstract

To provide a standard cell in which at least one of contacts is directly connected to a second metal line without passing through a first metal line.SOLUTION: In an inverter standard cell 500, a PMOS transistor has a first fin structure consisting of two fins (pitch of 3λ) in an n_well region of a semiconductor substrate and a gate covering it, and an NMOS transistor has a second fin structure consisting of two fins (pitch of 3λ) formed in a p_well region of the semiconductor substrate and a gate covering it. The NMOS transistor is spaced apart from the PMOS transistor by a gap having distance greater than the fin pitch, and there are two dummy fins disposed between the transistors. As a minimum processing dimension (λ) of the inverter standard cell decreases progressively for different technology nodes, an area dimension of the inverter standard cell in terms of λ2 is the same or approximately the same.SELECTED DRAWING: Figure 5(a)

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices within a monolithic semiconductor die, and more particularly to optimized standard cells incorporated within a monolithic semiconductor die based on an integrated scaling and stretching platform that can effectively reduce the size of logic circuits within the monolithic semiconductor die without reducing minimum feature size. [Background technology]

[0002] Improvements in the performance and cost of integrated circuits have been primarily achieved through process scaling techniques driven by Moore's Law, but as manufacturing processes shrink to a minimum of 28 nm (or even smaller), process variations in transistor performance pose a significant challenge. In particular, logic circuit scaling to increase memory density, reductions in operating voltage (Vdd) to reduce standby power consumption, and yield improvements, all of which are necessary to realize larger logic circuits, are becoming increasingly difficult to achieve.

[0003] Standard cells are commonly used and are fundamental elements in logic circuits. Standard cells may comprise basic logic function cells (such as an inverter cell, a NOR cell, and a NAND cell, two inverter cells, two NOR cells, and two NAND cells) as shown in Figures 1(a) to 1(f). However, even with scaling of manufacturing processes down to 22 nm or less (also known as "minimum feature size," "λ," or "F"), interference with contact dimensions and metal wiring layouts can cause λ to be too small. 2 or F 2 The total area of ​​a standard cell, represented by , increases dramatically as the minimum feature size decreases.

[0004] Some of the reasons why the total area of ​​a standard cell increases dramatically as the minimum feature size decreases can be explained as follows. A conventional standard cell, for example, an inverter as shown in FIG. 1(a), is connected by using multiple interconnects, each having its first interconnect layer M1 for connecting the diffusion levels (source and drain regions) of a transistor. There is a need to add a second interconnect layer M2 and / or a third interconnect layer M3 to facilitate signal transmission (such as input or output) without increasing the die size by using only M1. In this case, a structure via-1 composed of some kind of conductive material is formed to connect M2 to M1. Thus, there is a vertical structure formed by diffusion through a contact connection with M1, i.e., "Diffusion-Contact(Con)-M1." Similarly, another structure can be formed as "Gate-Con-M1" to connect a gate to M1 through a contact structure.

[0005] Furthermore, if a connection structure needs to be formed from the M1 interconnect through Via 1 to connect to the M2 interconnect, it is called "M1-Via 1-M2." A more complex interconnect structure from the gate level to the M2 interconnect may be represented as "Gate-Con-M1-Via 1-M2." Furthermore, the stacked interconnect system may have an "M1-Via 1-M2-Via 2-M3" or "M1-Via 1-M2-Via 2-M3-Via 3-M4" structure, etc. Because the gates of the two access transistors (the NMOS and PMOS transistors of the inverter as shown in FIG. 1(a)) are connected to the input located in the second interconnect layer M2, in a conventional inverter, such metal connection must first go through the interconnect layer M1. That is, a conventional interconnect system in an inverter cannot allow the gate to connect directly to M2 without bypassing the M1 structure. As a result, the required space between one M1 interconnect and another increases the die size, and in some cases, the wiring connection may interfere with the specific efficient channeling intent of using M2 directly across the M1 region. Furthermore, it is difficult to form a self-aligned structure between Via 1 and the contact, while simultaneously connecting both Via 1 and the contact to their own interconnect system.

[0006] Furthermore, in a conventional standard cell (such as an inverter shown in FIG. 1(a)), there are at least one NMOS transistor 11 and one PMOS transistor 12, each located in adjacent regions of the p-substrate (such as an n-well and a p-well), formed adjacent to each other. This creates a parasitic junction structure called an n+ / p / n / p+ parasitic bipolar element, which extends from the n+ region of the NMOS transistor 11 to the p-well, to the adjacent n-well, and finally to the p+ region (p-well) of the PMOS transistor 12, as shown in FIG. 2. If significant noise occurs in either the n+ / p junction or the p+ / n junction, a very large current can flow abnormally through this n+ / p / n / p+ junction, potentially disrupting the operation of a portion of the CMOS circuitry and causing the entire chip to malfunction. This abnormal phenomenon, called latch-up, adversely affects CMOS operation and must be avoided.

[0007] One way to increase resistance to latch-up, which is certainly a weakness of CMOS, is to increase the distance from the n+ region to the p+ region. Therefore, increasing the distance from the n+ region to the p+ region to avoid latch-up problems also increases the size of the standard cell.

[0008] Figure 3(a) shows a "stick diagram" representing the layout and connections between PMOS and NMOS transistors of a 5nm (UHD) standard cell from one semiconductor company (Samsung). The stick diagram only includes active areas (red horizontal lines) and gate lines (blue vertical lines). Hereinafter, the active areas may be referred to as "fins." Naturally, there are many more contacts, which are directly coupled to the PMOS and NMOS transistors on the one hand, and to input terminals, output terminals, high-level voltage Vdd, and low-level voltage VSS (or ground "GND") on the other. In particular, each transistor includes two active areas or fins (shown in dark red) for forming the transistor's channel so that the W / L ratio can be maintained within an acceptable range. The area dimension of the inverter cell is equal to X × Y, where X = 2 × Cpp, Y = cell_height, and Cpp is the distance from the contact to the poly pitch (Cpp). It is shown that some active areas or fins (called "dummy fins" and shown in light red) are not utilized in the PMOS / NMOS of this standard cell, and the potential reason for this is likely related to the latch-up problem between PMOS and NMOS. Therefore, the latch-up distance between PMOS and NMOS in Figure 3(a) is 3 × Fp-λ (e.g., = 14λ), where Fp is the fin pitch (e.g., = 5λ).

[0009] Based on available data for Cpp (54nm) and cell height (216nm) for Samsung 5nm (UHD) standard cells, the cell area is 23328nm x y. 2 (Or, when Lambda (λ) is the minimum feature size of 5 nm, 933.12λ 2 ) can be calculated by equating it to . Figure 3(b) shows a Samsung 5nm (UHD) standard cell and its dimensions. As shown in Figure 3(b), the latch-up distance between PMOS and NMOS is about 15λ, Cpp is 10.8λ, and cell_height is 43.2λ.

[0010] Additionally, publicly available information regarding Cpp and cell_height for different process technology nodes (or minimum feature sizes) is shown in the table below.

[0011] [Table 1]

[0012] [Table 2]

[0013] [Table 3]

[0014] Using the above table, the scaling trends for area dimensions (2 × Cpp × cell_height) versus different process technology nodes for the three foundries can be shown in Figure 4. As the technology node decreases (e.g., from 22 nm to 5 nm), λ 2 It is clear that the area dimension of a conventional standard cell (2 × Cpp × cell_height) increases dramatically. For conventional standard cells, the smaller the process node, the larger the λ 2 The equivalent area size increases. Such a dramatic increase can be caused by the difficulty of proportionally reducing the gate / source / drain contact dimensions as λ decreases, the difficulty of proportionally reducing the latch-up distance between PMOS and NMOS, and the decrease in interference within metal layers as λ decreases.

[0015] Therefore, there is a need to propose a new standard cell structure that can solve the above problems. Summary of the Invention

[0016] One embodiment of the present disclosure provides a standard cell including a plurality of transistors, a set of contacts coupled to the plurality of transistors, at least one input line electrically coupled to the plurality of transistors, an output line electrically coupled to the plurality of transistors, a VDD contact line electrically coupled to the plurality of transistors, and a VSS contact line electrically coupled to the plurality of transistors. As the minimum feature size (λ) of the standard cell decreases progressively for different technology nodes, e.g., from 22 nm to another, λ 2 In terms of conversion, the area sizes of the standard cells are the same or approximately the same.

[0017] According to one aspect of the present disclosure, the standard cells may be (but are not limited to) inverter cells, NAND cells, or NOR cells.

[0018] According to one aspect of the present disclosure, the standard cell further includes a metal contact line electrically coupled to a first contact of the set of contacts, the first contact not being completely covered by the metal contact line.

[0019] According to one aspect of the present disclosure, the width of the metal contact line is the same as or approximately the same as the width of the first contact.

[0020] According to one aspect of the present disclosure, the standard cell further includes a heavily doped silicon plug formed on a portion of the first contact that is not covered by the metal contact line, the heavily doped silicon plug contacting the metal contact line.

[0021] According to one aspect of the present disclosure, the standard cell further includes a first metal line electrically coupled to the plurality of transistors and a second metal line electrically coupled to the plurality of transistors, the second metal line being above the first metal line, and at least one of the set of contacts directly connects to the second metal line without passing through the first metal line.

[0022] According to one aspect of the present disclosure, at least one of the set of contacts is a gate contact.

[0023] Another embodiment of the present disclosure provides a standard cell including a semiconductor substrate having an original surface, a plurality of transistors, a set of contacts, a first metal line, and a second metal line, wherein the set of contacts, the first metal line, and the second metal line are electrically coupled to the plurality of transistors, wherein the plurality of transistors are formed based on the semiconductor substrate, and at least one of the plurality of transistors includes a channel layer and a conductive region, the channel layer or the conductive region being independent of the semiconductor substrate and doped without ion implantation.

[0024] According to one aspect of the present disclosure, the at least one transistor comprises a fin structure, and the channel layer covers a first sidewall and a second sidewall of the fin structure but does not cover a top surface of the fin structure.

[0025] According to one aspect of the present disclosure, at least one transistor comprises a fin structure, and the channel layer comprises a top portion covering a top surface of the fin structure and a side portion covering a first sidewall and a second sidewall of the fin structure, wherein the top portion and the side portion are not formed simultaneously.

[0026] According to one aspect of the present disclosure, the conductive regions are selectively grown based on the side edges of the semiconductor substrate.

[0027] According to one aspect of the present disclosure, the standard cell further comprises a trench and an isolation region, the trench being formed below an original surface of the semiconductor substrate, the isolation region being within the trench, the conductive region being disposed within the trench, and the bottom surface of the isolation region being separated from the semiconductor substrate by the isolation region.

[0028] According to one aspect of the present disclosure, only one side of the conductive region contacts the semiconductor substrate.

[0029] According to one aspect of the present disclosure, the standard cell further comprises a metal region contacting the conductive region, the metal region being disposed within the trench, and a bottom surface of the metal region being separated from the semiconductor substrate by an isolation region.

[0030] Yet another embodiment of the present disclosure is a standard cell including a substrate having a well region, a plurality of transistors, a plurality of contacts, at least one input line, an output line, a VDD contact line, and a VSS contact line. The plurality of transistors include first-type transistors and second-type transistors, the first-type transistors being formed within the well region and the second-type transistors being formed outside the well region. The plurality of contacts are coupled to the plurality of transistors. At least one input line is electrically coupled to the plurality of transistors. An output line is electrically coupled to the plurality of transistors. The VDD contact line is electrically coupled to the plurality of transistors. The VSS contact line is electrically coupled to the plurality of transistors. The first type transistor includes a first set of fin structures electrically coupled to each other, and the second type transistor includes a second set of fin structures electrically coupled to each other, and a gap between the first type transistor and the second type transistor is equal to or approximately equal to 3×Fp−λ, where Fp is a pitch distance between two adjacent fin structures in the first type transistor, λ is a minimum feature size of the standard cell, and the pitch distance between two adjacent fin structures in the first type transistor is between 3 and 5λ, for example, 3λ.

[0031] According to one embodiment of the present disclosure, the gap between the first type transistor and the second type transistor is between 8 and 12λ, for example, approximately equal to 8λ.

[0032] Yet another embodiment of the present disclosure provides a standard cell including: a plurality of transistors; a set of contacts coupled to the plurality of transistors; a first metal line electrically coupled to the plurality of transistors; and a second metal line electrically coupled to the plurality of transistors, the second metal line being above the first metal line, wherein at least one of the set of contacts connects directly to the second metal line without passing through the first metal line.

[0033] According to one aspect of the present disclosure, at least one of the set of contacts is a gate contact.

[0034] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with one or more color drawing(s) will be provided by the United States Patent and Trademark Office (USPTO) upon request and payment of the necessary fee.

[0035] The above and other aspects of the present disclosure will be better understood with regard to the following detailed description of one preferred, but non-limiting, embodiment(s), the following description being made with reference to the accompanying drawings. [Brief explanation of the drawings]

[0036] [Figure 1(a)] 1A-1C are equivalent circuit diagrams showing basic logic function cells of the prior art: an inverter cell, a NOR cell, and a NAND cell, respectively; [Figure 1(b)] 1A-1C are equivalent circuit diagrams showing basic logic function cells of the prior art: an inverter cell, a NOR cell, and a NAND cell, respectively; [Figure 1(c)] 1A-1C are equivalent circuit diagrams showing basic logic function cells of the prior art: an inverter cell, a NOR cell, and a NAND cell, respectively; [Figure 1(d)]1A-1C are equivalent circuit diagrams showing basic logic function cells of the prior art: an inverter cell, a NOR cell, and a NAND cell, respectively; [Figure 1(e)] 1A-1C are equivalent circuit diagrams showing basic logic function cells of the prior art: an inverter cell, a NOR cell, and a NAND cell, respectively; [Figure 1(f)] 1A-1C are equivalent circuit diagrams showing basic logic function cells of the prior art: an inverter cell, a NOR cell, and a NAND cell, respectively; [Figure 2] 1A-1C show cross sections of conventional NMOS and PMOS structures of a standard cell. [Figure 3(a)] FIG. 1 is a stick diagram representing the layout and connections of PMOS and NMOS transistors in a 5nm (UHD) standard cell from one semiconductor company (Samsung). [Figure 3(b)] FIG. 3(a) is a stick diagram showing the dimensions of a Samsung 5 nm (UHD) standard cell. [Figure 4] FIG. 10 shows the scaling trends for area dimensions (2×Cpp×cell_height) versus different process technology nodes for three foundries. [Figure 5(a)] FIG. 1 is a stick diagram illustrating a novel inverter standard cell layout style in accordance with the present invention. [Figure 5(b)] FIG. 5(b) is a stick diagram with dimensions of the inverter standard cell depicted in FIG. 5(a). [Figure 5(c)] FIG. 5 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIGS. 5(a) and 5(b). [Figure 5(d)] FIG. 5 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIGS. 5(a) and 5(b). [Figure 5(e)] FIG. 5 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIGS. 5(a) and 5(b). [Figure 5(f)] FIG. 5 is a diagram showing a series of process layouts for forming an inverter standard cell based on FIGS. 5(a) and 5(b). [Figure 6(a)] FIG. 1 illustrates a top view of a scaled metal-oxide-semiconductor field-effect transistor (mMOSFET) used in a novel standard cell in accordance with the present invention. [Figure 6(b)] FIG. 1 shows a cross section of a pad oxide layer, a pad nitride layer on a substrate, and an STI oxide 1 formed in the substrate. [Figure 6(c)] FIG. 1 illustrates an intrinsic gate (TG) and a dummy shield gate (DSG) formed on / above an active area. [Figure 6(d)] FIG. 1 shows that a spin-on dielectric (SOD) is deposited and a properly designed gate mask layer is deposited and etched. [Figure 6(e)] FIG. 10 shows that the nitride layer above the dummy shield gate (DSG), the DSG, a portion of the dielectric insulator corresponding to the DSG, and the p-type substrate corresponding to the DSG are removed. [Figure 6(f)] FIG. 10 shows that the gate mask layer is removed, the SOD is etched, and an oxide layer is deposited to form STI-oxide-2. [Figure 6(g)] FIG. 1 shows an oxide-3 layer being deposited and etched to form oxide-3 spacers, a lightly doped drain (LDD) being formed in a p-type substrate, a nitride layer being deposited and etched back to form nitride spacers, and the dielectric insulator being removed. [Figure 6(h)] FIG. 1 shows the growth of intrinsic silicon electrodes by selective epitaxial growth (SEG) technique. [Figure 6(i)] FIG. 10 shows that a CVD-STI-oxide trilayer is deposited and etched back to remove the intrinsic silicon electrodes and form the source (n+ source) and drain (n+ drain) of the mMOSFET. [Figure 6(j)]FIG. 10 shows that oxide spacers are deposited and etched to form contact hole openings. [Figure 6(k)] FIG. 10 shows that an SOD layer is deposited to fill the pores on the substrate and CMP is used to planarize the surface. [Figure 6(l)] FIG. 6(k) is a top view of FIG. [Figure 6(m)] FIG. 6(l) shows a photoresistive layer formed on the structure in FIG. 6(l). [Figure 6(n)] FIG. 10 illustrates the removal of the nitride cap layer in the exposed gate extension region by anisotropic etching techniques to reveal the conductive metal gate layer. [Figure 6(o)] FIG. 10 shows that the photoresistive layer and the SOD layer are removed to form open regions on top of both the source and drain regions and spacers are formed. [Figure 6(p)] This is a top view of FIG. 6(o). [Figure 6(q)] FIG. 1 shows the formation of a metal-1 layer interconnect network. [Figure 6(r)] The top view of FIG. 6(q) shows that the gate is connected to the source region by a metal-1 layer. [Figure 7(a)] FIG. 10 is a top view of a construction phase of an mMOSFET used in a novel standard cell according to another embodiment of the present disclosure. [Figure 7(b)] 7(a) is a cross-section of the transistor during the construction phase along section line C7A shown in FIG. 7(a). [Figure 7(c)] 7A is a cross-section of the transistor during the construction phase, taken along section line C7A2 shown in FIG. 7(a). [Figure 7(d)] FIG. 10 is a top view showing the structure after the second and fourth conductor pillars have been formed on the first and third conductor pillars. [Figure 7(e)] FIG. 7(d) is a cross-sectional view taken along the cutting line C7D1 shown in FIG. [Figure 7(f)] FIG. 7(d) is a cross-sectional view taken along the cutting line C1E2 shown in FIG. [Figure 7(g)] FIG. 8 is a top view illustrating the structure after a first conductive layer and a second dielectric sublayer 860 have been formed over the first dielectric layer, according to one embodiment of the present disclosure. [Figure 7(h)] FIG. 7(g) is a cross-sectional view taken along the cutting line C7G1 shown in FIG. [Figure 7(i)] FIG. 7(g) is a cross-sectional view taken along the cutting line C7G2 shown in FIG. [Figure 7(j)] FIG. 2 is a top view illustrating the structure after a conductive layer is formed over the upper dielectric layer, according to one embodiment of the present disclosure. [Figure 7(k)] FIG. 7(j) is a cross-sectional view taken along the cutting line C7J1 depicted in FIG. [Figure 7(l)] FIG. 7(j) is a cross-sectional view taken along the cutting line C7J2 shown in FIG. [Figure 8(a)] FIG. 1 is a top view of an mMOSFET used in a novel standard cell, according to one embodiment of the present disclosure. [Figure 8(b)] FIG. 4 is a cross-sectional view taken along the cutting line C4B1 depicted in FIG. [Figure 8(c)] FIG. 8(b) is a cross-sectional view taken along the cutting line C4B2 depicted in FIG. 8(a). [Figure 8(d)] FIG. 10 is a top view of another mMOSFET used in a novel standard cell according to another embodiment of the present disclosure. [Figure 8(e)] FIG. 8(d) is a cross-sectional view taken along the cutting line C8D1 in FIG. [Figure 8(f)] FIG. 8(d) is a cross-sectional view taken along the cutting line C8D2 in FIG. [Figure 9] FIG. 2 illustrates a cross section of an NMOS transistor used in a novel standard cell according to another embodiment of the present disclosure. [Figure 10(a)] FIG. 2 is a top view illustrating a combined structure of a PMOS transistor and an NMOS transistor used in a novel standard cell according to one embodiment of the present disclosure. [Figure 10(b)]10(a) is a cross-sectional view of a PMOS transistor and an NMOS transistor taken along the cutting line (X-axis) in FIG. 10(a). [Figure 10(c)] 10(a) is a cross-sectional view of a PMOS transistor and an NMOS transistor taken along the cutting line (Y-axis) in FIG. 10(a). [Figure 11] FIG. 1 is a diagram showing a comparison of the area dimensions of a new standard cell provided by the present invention with the area dimensions of conventional products provided by various other companies. [Figure 12(a)] 1A-1C are top views of a standard cell having one single NOR cell, one single NAND cell, and two inverter cells, and corresponding equivalent circuit diagrams, according to some embodiments of the present disclosure. [Figure 12(b)] 1A-1C are top views of a standard cell having one single NOR cell, one single NAND cell, and two inverter cells, and corresponding equivalent circuit diagrams, according to some embodiments of the present disclosure. [Figure 12(c)] 1A-1C are top views of a standard cell having one single NOR cell, one single NAND cell, and two inverter cells, and corresponding equivalent circuit diagrams, according to some embodiments of the present disclosure. [Figure 12(d)] 1A-1C are top views of a standard cell having two NOR cells and two NAND cells, and corresponding equivalent circuit diagrams, according to some embodiments of the present disclosure. [Figure 12(e)] 1A and 1B are top views of a standard cell having two NOR cells and two NAND cells, and corresponding equivalent circuit diagrams, according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0037] In conventional standard cells, even as feature sizes or technology nodes shrink to 28 nm (or less), transistor sizes cannot be scaled proportionally. The present invention discloses a novel standard cell with a compact layout style in a monolithic semiconductor die, whereby the area size of the standard cell across different technology nodes can remain uniform or insensitive to the technology node without increasing latch-up issues.

[0038] For example, Figure 5(a) is a stick diagram of a standard cell 500 according to the present invention. Figure 5(b) is a stick diagram with dimensions (in terms of λ) of the inverter cell 500 according to Figure 5(a). Only the gate and diffusion levels of the inverter standard cell 500 are depicted for the purpose of explaining the structure clearly and concisely.

[0039] The inverter standard cell 500 includes an NMOS transistor and a PMOS transistor, the PMOS transistor having a first fin structure consisting of two fins (with a pitch distance Fp of 3λ between them) formed in an n-well region of a semiconductor substrate (not shown) and a gate covering the fin structure, and the NMOS transistor having a second fin structure consisting of two fins (with a pitch distance Fp of 3λ between them) formed in a p-well region of the semiconductor substrate (not shown) and a gate covering the second fin structure. The NMOS transistor is separated from the PMOS transistor by a gap having a distance greater than the fin pitch, and there are two dummy fins disposed between the NMOS transistor and the PMOS transistor.

[0040] The area dimensions of the inverter standard cell 500 may enable a compact design, and as the minimum feature size (λ) of the inverter standard cell 500 decreases progressively for different technology nodes (e.g., from 22 nm to 16 nm, or from 22 nm to 5 nm), λ 2 The converted area dimensions of the inverter standard cell 500 are the same or approximately the same. In this embodiment, the width of the active region or fin is λ, the width of the gate line (or poly line) is also the same, Cpp is 4λ, the cell height is 24λ, and the cell area of ​​the inverter standard cell 500 (2×Cpp×cell height, as marked by the black dashed rectangle) is 192λ. 2 is.

[0041] 5(c)-5(f) are diagrams illustrating a series of process layouts for forming a novel inverter standard cell 500 based on FIGS. 5(a) and 5(b) when λ is set to 5 nm. As shown in FIG. 5(a), multiple sets of fin structures (e.g., multiple horizontal fins) are formed on a semiconductor substrate (not shown). Two adjacent fins 501 formed in an n-well region of the semiconductor substrate are used as active regions for PMOS transistors, and two adjacent fins 502 adjacent to the PMOS are used as active regions for NMOS transistors. Here, two adjacent fins 503 formed in the semiconductor substrate between the NMOS and PMOS transistors can serve as two dummy fins. In FIG. 5(c), the gap between the PMOS and NMOS transistors is equal to or approximately equal to 3×Fp-Fw, where Fp is the fin pitch distance shown in FIG. 5(a) between the two adjacent fin structures (e.g., Fp=3λ), and Fw is the fin width of the fin structure. In this embodiment, the fin width Fw is set to λ (minimum feature size), and therefore the gap between the PMOS transistor and the NMOS transistor is equal to or approximately equal to 3×Fp−λ (for example, gap=8λ).

[0042] Furthermore, multiple gate lines 504 (or poly lines) are formed on the semiconductor substrate and span the fin structures of the PMOS transistor, the NMOS transistor, and the dummy fins. In this embodiment, the gap (Cpp, shown in FIG. 5(a)) between two gate lines or poly lines is at least 4λ. In FIG. 5(c), a plurality of source / drain contacts AA_CT 505 (via mask openings for connecting the active areas of the source / drain regions to the metal-1 layer (M1) and a gate contact Gate_CT 506 (via mask openings for connecting poly lines directly to the metal-2 layer (M2)) are formed. In FIG. 5(d), a plurality of metal-1 layers (M1) 507 (width: λ or larger) are formed to connect the plurality of source / drain contacts 505 (AA_CT mask), but the gate contact Gate_C 506 is not connected to the metal-1 layer (M1) 507. In FIG. 5(e), a plurality of vias 1 508 are formed on top of the metal-1 layer (M1) 507 to connect the metal-1 layer (M1) 507 to the metal-2 layer (M2). In FIG. 5(f), a plurality of metal-2 layers (M2) 509 are formed to connect a plurality of vias 1 One further metal-2 layer (M2) 510 is formed connecting 508 to Vdd, the output terminal, and Vss respectively, and directly connecting the gate contact Gate_C 506 to the input terminal.

[0043] Conventional standard cells do not allow the gate or source / drain to be directly connected to the metal-2 layer (M2) without bypassing the metal-1 layer (M1). The present invention discloses a novel standard cell structure in which the gate / source / drain can be directly connected to the metal-2 interconnect layer in a self-aligned manner by one vertical conductive plug without the transition metal-1 layer, as follows:

[0044] In FIGS. 5(a) to 5(f), the meanings of the omitted symbols are as follows:

[0045] [Table 4]

[0046] Furthermore, the dimensions of the inverter standard cell 500 may be easily achieved by precisely controlling the linear dimensions of the source, drain, and gate of the PMOS and NMOS transistors in the novel inverter standard cell 500, and the linear dimensions may be as small as the minimum feature size Lambda (λ), regardless of the dimensions (or minimum feature size) of currently available technology nodes.

[0047] In conventional standard cells, even when the fabrication process is scaled down to a minimum of 28 nm or less (the so-called "minimum feature size," "λ," or "F"), the dimensions of the metal-oxide-semiconductor field-effect transistors (mMOSFETs) used in the standard cells cannot be scaled down proportionally. However, in this embodiment, when two adjacent transistors (such as the PMOS and NMOS transistors in FIG. 5(a)) are connected to each other via their drain / sources, the distance between the edges of the gates of the two adjacent transistors (i.e., the latch-up distance) can be as small as 8λ. Furthermore, linear dimensions of the contact holes for the source, drain, and gate can be realized in the drain region (and similarly in the source and gate regions) that are less than λ, e.g., 0.6λ to 0.8λ.

[0048] As shown in Figure 5(b), each of the PMOS and NMOS includes multiple active areas to maintain a reasonable W / L ratio. Source / drain contacts AA_CT (for connection to the metal-1 layer (M1)) can be formed within the active areas. The present invention achieves an increased gate edge-to-boundary edge designed distance (GEBESI) between the source and isolation regions by using a temporary dummy shield gate (DSG) added on the gate-level mask to avoid photolithography misalignment tolerance (MTP).

[0049] For example, FIG. 6(a) is an example of a scaled metal-oxide-semiconductor field-effect transistor (mMOSFET) 600 for use in a novel standard cell, according to one embodiment of the present invention. As shown in FIG. 6( a), mMOSFET 600 includes: (1) a gate structure 610 having a length G(L) and a width G(W); (2) a source 603 on the left side of gate structure 610 having a length S(L) and a width S(W), which are linear dimensions from the edge of gate structure 610 to the edge of isolation region 605; (3) a drain 607 on the right side of gate structure 610 having a length D(L) and a width D(W), which are linear dimensions from the edge of gate structure 610 to the edge of isolation region 605; (4) a contact hole 609 formed by a self-aligned technique at the center of source 603, the length and width of the opening being labeled CS(L) and CS(W), respectively; and (5) a contact hole 611 also formed by a self-aligned technique at the center of drain 607, the length and width of the opening being labeled CD(L) and CD(W), respectively. The lengths G(L), D(L), and S(L) can be accurately controlled to a minimum feature size λ. Furthermore, the length and width of the openings denoted as CS(L) and CS(W), or the length and width of the openings denoted as DS(L) and DS(W), can be less than λ, for example, 0.6λ to 0.8λ.

[0050] The following briefly describes the manufacturing process of the mMOSFET 600 used in the standard cell of the present invention. A detailed description of the structure of the mMOSFET 600 and its manufacturing process is disclosed in U.S. patent application Ser. No. 17 / 138,918, filed on December 31, 2020, and entitled "MINIATURIZED TRANSISTOR STRUCTURE WITH CONTROLLED DIMENSIONS OF SOURCE / DRAIN AND CONTACT-OPENING AND RELATED MANUFACTURE METHOD," the entire contents of which are incorporated herein by reference.

[0051] As shown in Figure 6(b), a pad oxide layer 602 is formed and a pad nitride layer 604 is deposited on the substrate 601. The active area of ​​the mMOSFET 600 is also defined, and portions of the silicon material outside the active area are removed to create a trench structure. Within the trench structure, an oxide-1 layer is deposited and etched back to form shallow trench isolation (STI-Oxide 1) 606 below the original horizontal surface ("HSS") of the silicon substrate.

[0052] The pad oxide layer 602 and pad nitride layer 604 are removed, and a dielectric insulator 612 is formed on the HSS. A gate layer 610 and a nitride layer 614 are then deposited above the HSS, and the gate layer 610 and the nitride layer 614 are etched to form the mMOSFET's intrinsic gate (TG) and a dummy shield gate (DSG) having a desired linear distance from the intrinsic gate. As shown in FIG. 6(c), the length of the intrinsic gate (TG) is λ, the length of the dummy shield gate (DSG) is also λ, and the distance between the edges of the intrinsic gate (TG) and the dummy shield gate (DSG) is also λ.

[0053] Next, a spin-on dielectric (SOD) 712 is deposited, and then the SOD 712 is etched back. As shown in FIG. 6(d), a gate mask layer 802 is formed by a photolithography mask technique, which is appropriately designed. Thereafter, as shown in FIG. 6(e), an anisotropic etching technique is used to remove the nitride layer 614 above the dummy shield gate (DSG), and the dummy shield gate (DSG), the portion of the dielectric insulator 612 corresponding to the dummy shield gate (DSG), and the p-type substrate 601 corresponding to the dummy shield gate (DSG).

[0054] 6(f), the gate mask layer 802 is removed, the SOD 712 is etched, and the STI-oxide-2 1002 is deposited and then etched back. Then, as shown in FIG. 6(g), an oxide-3 layer is deposited and etched back to form oxide-3 spacers 1502, a lightly doped drain (LDD) 1504 is formed in the p-type substrate 601, a nitride layer is deposited and etched back to form nitride spacers 1506, and the dielectric insulator 402 is removed.

[0055] Further, as shown in FIG. 6( h), a selective epitaxial growth (SEG) technique is used to grow an intrinsic silicon electrode 1602. Then, as shown in FIG. 6( i), a CVD-STI-oxide 3 layer 1702 is deposited and etched back to remove the intrinsic silicon 1602 and form a source region (n+ source) 1704 and a drain region (n+ drain) 1706 of the mMOSFET. The source region (n+ source) 1704 and the drain region (n+ drain) 1706 are formed between the intrinsic gate (TG) and the CVD-STI-oxide 3 layer 1702, whose position was originally occupied by the dummy shield gate (DSG). Therefore, the length and width of the source region (n+ source) 1704 (or the drain region (n+ drain) 1706) can be at least λ. The opening of the source region (n+ source) 1704 (or drain region (n+ drain) 1706) can be less than λ, for example 0.8λ. As shown in FIG. 6(j), such opening can be reduced if additional oxide spacers 1802 are formed.

[0056] Furthermore, the novel standard cell allows the first metal interconnect (M1 layer) to directly connect the gate, source, and / or drain regions through self-aligned, scaled contacts, without using a conventional contact hole opening mask and / or a metal-0 translation layer for M1 connections. Following FIG. 6(i), an SOD layer 1901 is deposited to fill the holes on the substrate, including the opening 1804 for the source region (n+ source) 1704 (or the drain region (n+ drain) 1706). CMP is then used to planarize the surface, as shown in FIG. 6(k). FIG. 6(l) is a top view of FIG. 6(k), showing multiple fingers in the horizontal direction.

[0057] Furthermore, using a properly designed mask, a photoresistive layer 1902 is implemented, resulting in a specific stripe pattern along the X-axis in FIG. 6(l) with distinct spaces of length GROC(L) to expose areas of the gate extension region along the Y-axis in FIG. 6(l), where the result is shown as a top view in FIG. 6(m). As shown in FIG. 6(m), the most aggressive design rule is when GROC(L)=λ. Then, an anisotropic etching technique (shown in FIG. 6(n)) is used to remove the nitride cap layer in the exposed gate extension region to reveal the conductive metal gate layer.

[0058] The photoresistive layer 1902 is then removed, followed by the SOD layer 1901, so that the opening regions on the tops of both the source region 1704 and the drain region 1706 are again exposed. An oxide layer 1904 having an appropriately designed thickness is then deposited, and an anisotropic etching technique is then used to form spacers on the four sidewalls within the opening regions of the source region 1704, the drain region 1706, and the exposed gate extension region 1903. Thus, naturally-constructed contact hole openings are formed in the exposed gate extension region, the source region 1704, and the drain region 1706, respectively. Figure 6(o) shows a cross-section of such a transistor structure. Figure 6(p) shows a top view of such a transistor structure in Figure 6(o). The vertical length CRMG(L) of the opening in the exposed gate extension region 1903 is smaller than the length GROC(L), which may be λ.

[0059] Finally, a metal-1 layer 1905 with an appropriately designed thickness is formed to fill all of the aforementioned contact hole openings and form a smooth, planar surface that conforms to the wafer surface topography. Then, as shown in FIG. 6(q), photolithography masking techniques are used to create all of the connections between each of the contact hole openings, realizing the required metal-1 interconnect network. FIG. 6(r) is a top view of the mMOSFET 600 shown in FIG. 6(q). Thus, this metal-1 layer completes the task of fulfilling both the contact filling and plug connection functions for the gate and source / drain, as well as the direct interconnect function connecting all transistors. There is no need to proceed with the subsequent, extremely difficult process of drilling contact hole openings using conventional contact hole masks, which are expensive and very tightly controlled, and which may be the most challenging challenge, especially in further scaling the horizontal geometries of billions of transistors. Furthermore, it precludes both the insertion of a metal plug into the contact hole opening and the CMP process to realize the metal stud, a complex integrated processing step that is clearly required for certain state-of-the-art technologies that produce, for example, metal zero structures.

[0060] As a result, the dimensions of source / drain contacts (such as AA_CT as shown in FIG. 5(b)) can be as small as λ×λ, regardless of the technology node dimensions (or minimum feature size). Similarly, gate contacts (such as Gate_CT for direct connection to the Metal 2 layer (M2 shown in FIG. 5(b)) may be formed on gates or poly lines, and the dimensions of the gate contacts are also λ×λ. That is, the linear dimensions of the source, drain, and gate of a transistor (such as the PMOS transistor or NMOS transistor in FIG. 5(a)) and their contacts in a standard cell may be precisely controlled, and the linear dimensions can be as small as Lambda (λ), the minimum feature size. In this embodiment, the source / drain contact dimensions are larger (e.g., λ (width in the Y direction) × 2λ (length in the X direction)), and the gap between two gates or poly lines is larger than 3λ (e.g., 4 or 5λ).

[0061] Furthermore, as mentioned above, conventional standard cells may not allow the gate or diffusion to be directly connected to M2 without bypassing the M1 structure. The present invention discloses a novel standard cell in which the gate or diffusion (source / drain) area is directly connected to the M2 interconnect layer in a self-aligned manner, without the transition layer M1, elsewhere on the same die, by one vertical conductive plug consisting of Contact-A and Via-1-A, respectively, formed during the build phase of creating Contact and Via-1. As a result, the required space between one M1 interconnect and another M1 interconnect, as well as blocking issues in certain wiring connections, are reduced.

[0062] The following briefly describes an mMOSFET 700 used in a standard cell according to another embodiment of the present invention, in which the gate and diffusion (source / drain) areas are directly connected to the M2 interconnect layer in a self-aligned manner, without the transition layer M1. Figure 7(a) is a top view of the mMOSFET 700 during the construction phase, and Figures 7(b) and 7(c) are two cross-sections of the transistor during the construction phase, along cut lines C7A1 and C7A2, respectively, shown in Figure 7(a).

[0063] As shown in Figures 7(b) and 7(c), an mMOSFET 700 is defined and confined by a shallow trench isolator (STI) 705. The mMOSFET 700 has a gate terminal 702, a transistor channel region 703 below the gate terminal 702, and source / drain regions 704. The gate terminal 702 includes a gate dielectric layer 702a, a gate conductive layer 702b formed on the gate dielectric layer 702a, and a silicon region (or seed region) 702c formed on the gate conductive layer 702b. The silicon region 702c may be made of polysilicon or amorphous silicon. The gate terminal 702 further includes a cap layer 702d (e.g., a nitride layer) on top of the silicon region 702c, and at least one spacer (e.g., including a nitride spacer 702s1 and a thermal oxide spacer 702s2) on sidewalls of the gate dielectric layer 702a, the gate conductive layer 702b, and the silicon region 702c. A first dielectric layer 720 is formed on the semiconductor substrate 701, covering at least the active region of the mMOSFET 700, including the gate terminal 702 and the source / drain regions 704, along with the STI 705.

[0064] A plurality of open holes (such as open holes 707a and 707b) are formed in the first dielectric layer 720, exposing a top portion 71 of the silicon region 702c and a top portion 72 of the source / drain region 704. In some embodiments, the open holes 707a and 707b are formed by a photolithography process to remove portions of the first dielectric layer 720 and expose the portions of the silicon region 702c and the silicon regions of the drain terminals of the source / drain regions 704. In one example, each of the open holes 707a and 707b may have a dimension equal to a minimum feature dimension (e.g., a critical dimension of the mMOSFET 700). Of course, the dimension of the open holes 707a and 707b may be larger than the minimum feature dimension. The bottoms of the open holes 707a and 707b (i.e., the exposed top portions 71 and 72) are made of a material having either polycrystalline / amorphous silicon or crystalline silicon with a high impurity concentration having high conductivity. The exposed silicon regions 702c of the gate terminal and the exposed silicon regions of the source / drain terminals are seed regions for growing pillars based on the seed regions by selective epitaxial growth (SEG) technology.

[0065] 7(d) to 7(f), heavily doped conductive silicon plugs (or conductor pillars) are then grown by SEG based on the exposed top portions 71 and 72 to form first and third conductor pillar portions 731a and 731b. A first dielectric sublayer 740 is then formed on the first dielectric layer 720 such that a top surface 740s of the first dielectric sublayer 740 is substantially flush with the top surfaces of the first and third conductor pillar portions 731a and 731b. The "exposed heads" (or exposed top surfaces) of the first and third conductor pillar portions 731a and 731b can be used as seeds for subsequent SEG processes. Furthermore, each of the first conductor pillar portion 731a and the third conductor pillar portion 731b has a seed region or seed pillar in its upper portion, which can be used for the following selective epitaxial growth. Subsequently, a second conductor pillar portion 732a is formed on the first conductor pillar portion 731a by a second selective epitaxial growth, and a fourth conductor pillar portion 732b is formed on the third conductor pillar portion 731b. Figure 7(d) is a top view illustrating the structure after the second conductor pillar portion 732a and the fourth conductor pillar portion 732b are formed on the first conductor pillar portion 731a and the third conductor pillar portion 731b, respectively, according to one embodiment of the present disclosure. Figure 7(e) is a cross-sectional view taken along the cutting line C7D2 depicted in Figure 7(d). FIG. 7(f) is a cross-sectional view taken along the cutting line C7D1 depicted in FIG. 7(d).

[0066] Further, as shown in FIGS. 7(g)-7(i), a first conductive layer 750, such as copper (Cu), aluminum (Al), tungsten (W), or other suitable conductive material, may be deposited on the top surface 740s of the first dielectric sublayer 740. A second conductive sublayer 760 is then deposited on the first conductive layer 750. The first conductive layer 750 and the second dielectric sublayer 760 are patterned to define an open cavity 709, and the first conductor pillar 730A penetrates the open cavity 709 without contacting the first conductive layer 750 and the second dielectric sublayer 760. FIG. 7(g) is a top view illustrating the structure after the first conductive layer 750 and the second dielectric sublayer 760 have been formed on the first dielectric sublayer 740, according to one embodiment of the present disclosure. Figure 7(h) is a cross-sectional view taken along the cutting line C7G1 in Figure 7(g), and Figure 7(i) is a cross-sectional view taken along the cutting line C7G2 in Figure 7(g).

[0067] 7(j) to 7(l), an upper dielectric layer 770 is deposited to cover the second dielectric sublayer 760 and the first dielectric sublayer 740 and fill the open hollow 709. A top surface 770s of the upper dielectric layer 770 is lower than a top surface 730t of the first conductor pillar 730A (including the first conductor pillar portion or subpillar 731a and the second conductor pillar portion or subpillar 732a) and the second conductor pillar 730B (including the third conductor pillar portion or subpillar 731b and the fourth conductor pillar portion or subpillar 732b). Next, an upper conductive layer 780 is formed on the upper dielectric layer 770, and the first conductor pillar 730A connects to the upper conductive layer 780 but is not connected to the first conductive layer 750. In this example, Figure 7(j) is a top view of the structure after a conductive layer 780 has been formed on the upper dielectric layer 770, according to one embodiment of the present disclosure. Figure 7(k) is a cross-sectional view taken along section line C7J1 depicted in Figure 7(j). Figure 7(l) is a cross-sectional view taken along section line C7J2 depicted in Figure 7(j).

[0068] As described above, the exposed silicon region 702c of the gate terminal and the exposed silicon region of the source / drain terminal each have a seed region for growing a pillar based on the seed region by selective epitaxial growth (SEG). Furthermore, the first conductor pillar portion 731a and the third conductor pillar portion 731b also each have a seed region or seed pillar in their upper portion, which can be used for the following selective epitaxial growth. This embodiment can also be applied to enable the M1 interconnect (a type of conductive terminal) or conductive layer to be directly connected to the MX interconnect layer (without connecting to the conductive layers M2, M3, . . MX-1) in a self-aligned manner by one vertical conductive or conductor plug, as long as the seed region or seed pillar exists on the upper portion of the conductive terminal and the conductor pillar portion is configured for the following selective epitaxial growth. The seed region or seed pillar is not limited to silicon, and any material acceptable as a seed configured for the following selective epitaxial growth can be used.

[0069] In summary, the novel standard cell and the standard cell have at least the following advantages: (1) The linear dimensions of the source, drain, and gate of a transistor in a standard cell are precisely controlled, and the linear dimensions can be as small as Lambda (λ), the minimum feature size. Thus, if two adjacent transistors are connected to each other via their drain / source, the linear dimension of the transistor can be as small as 3λ, and the distance between the edges of the gates of the two adjacent transistors can be as small as 2λ. Of course, for tolerance purposes, the linear dimension of the transistor can be about 3λ to 6λ or larger, and the distance between the edges of the gates of the two adjacent transistors can be 8λ or larger. (2) The first metal interconnect (M1 layer) directly connects the gate, source and / or drain regions by self-aligned scaled contacts without using conventional contact hole opening masks and / or metal-0 intervening layers for M1 connections. (3) The gate and / or diffusion (source / drain) areas are directly connected to the metal 2 (M2) interconnect layer in a self-aligned manner without connecting the metal 1 layer (M1). Thus, the required space between one metal 1 (M1) interconnect layer and the other metal 1 (M1) interconnect layer and the blocking problem in some wiring connections are reduced. Furthermore, the same structure can be applied when the lower metal layer is directly connected to the upper metal layer by a conductor pillar, but the conductor pillar is not electrically connected to any intermediate metal layer between the lower and upper metal layers. (4) The metal wiring for the high-level voltage Vdd and / or the low-level voltage VSS in the standard cell may be located below the original silicon surface of the silicon substrate, so that interference between the dimensions of the contacts and the layout of the metal wiring connecting the high-level voltage Vdd and the low-level voltage VSS, etc. can be avoided even when the dimensions of the standard cell are reduced. Furthermore, the openings for the source / drain regions originally used to electrically couple the source / drain regions to the metal 2 layer (M2) or metal 3 layer (M3) for Vdd or ground connection can be omitted in the new standard cell and in the standard cell.

[0070] In some alternative embodiments, the conductor pillar may be a metal conductor pillar, or may be a composite conductor pillar having a metal conductor pillar and a seed region or seed pillar on top of it. For example, FIG. 8(a) is a top view of an mMOSFET 800 used in a novel standard cell according to one embodiment of the present disclosure. FIG. 8(b) is a cross-sectional view taken along the cut line C8A1 depicted in FIG. 8(a). FIG. 8(c) is a cross-sectional view taken along the cut line C8A2 depicted in FIG. 8(a). In this embodiment, the conductor pillar mMOSFET 800 used to connect interconnect layers includes a tungsten pillar and a first heavily doped silicon pillar, with a seed region or seed pillar in its top portion.

[0071] As shown in Figures 8(a)-8(c), the heavily doped N+ polysilicon pillars 731a, 732a, 731b, and 732b in Figures 7(j)-7(l) can be removed and replaced with tungsten pillars 830w, TiN layers 830n, and heavily doped silicon pillars. The first conductor pillar includes a metal pillar portion 830A (including tungsten pillars 830w and TiN layers 830n) and a heavily doped silicon pillar 810a, and the second conductor pillar includes a metal pillar portion 830B (including tungsten pillars 830w and TiN layers 830n) and a heavily doped silicon pillar 810b. The heavily doped silicon pillars 810a and 810b serve as seed regions or seed pillars for growing conductor pillars configured to connect the metal connections formed below. For example, the heavily doped silicon pillars 810 a and 810 b can serve as a seed region or seed pillar for the following SEG process to grow another silicon pillar thereon to connect the first conductive layer 850 (e.g., the first metal sublayer 850 a or the second metal sublayer 850 b) formed on the first dielectric sublayer 840 and electrically connected to the heavily doped silicon pillars 810 a and 810 b. The conductor pillar may have a seed region or seed pillar in its top portion, and the borderless contact is filled because it is the seed region or seed pillar of the conductor pillar that the following SEG process is configured to grow another silicon pillar thereon.

[0072] In some embodiments, the width of a metal contact line (such as the first metal sublayer 850a or 850b) can be the same as or approximately the same as the width of a contact (such as the heavily doped silicon pillar 810a or 810b). Of course, the width of the metal contact line can be different from the width of the first contact. As shown in Figures 8(d)-8(f), the width of a metal contact line (such as the first metal sublayer 850a or the second metal sublayer 850b) is also not the same as the width of the underlying contact plug (which may be, at a minimum, the minimum feature size of the heavily doped silicon pillar 810a or 810b). However, although there is misalignment between the metal conductive line and the underlying contact plug, and photolithography mask misalignment tolerances may result in the metal conductive line (such as the first metal sub-layer 850a or the second metal sub-layer 850b) not being able to completely cover the contact (such as the heavily doped silicon pillar 810a or 810b as shown in Figures 8(e) and 8(f)), there is no concern that the resistance between the metal conductive layer and the contact may be too high due to insufficient contact area.

[0073] Therefore, the resistance between the metal conductor line and the underlying contact can be properly controlled. Here, the present invention uses SEG to grow a specific, highly doped silicon material that connects both the metal conductor line and the underlying contact plug, thereby improving the resistance problem caused by misalignment between the metal conductor line and the underlying contact plug. In this embodiment, an additional SEG process is performed to grow a specific, highly doped silicon material (side pillars 820) to attach the vertical walls of the metal conductive layers 850a and 850b. Figure 8(d) is a top view of another mMOSFET 800' used in a novel standard cell according to another embodiment of the present disclosure, and Figure 8(e) is a cross-sectional view taken along the cut line C8D1 depicted in Figure 8(d). Figure 8(f) is a cross-sectional view taken along the cut line C8D2 depicted in Figure 8(d).

[0074] Conventional standard cells cannot allow the gate or source / drain to be directly connected to the metal 2 layer (M2) without bypassing the metal 1 layer (M1). The present invention discloses a novel standard cell structure in which the gate / source / drain can be directly connected to the metal-2 interconnect layer (M2) in a self-aligned manner by one vertical conductive plug, without the transition metal-1 layer (M1). A detailed description of the gate area / active region directly connected to the metal-2 interconnect layer (M2) is disclosed in U.S. Patent Application No. 17 / 528,957, filed November 17, 2021, and entitled "INTERCONNECTION STRUCTURE AND MANUFACTURE METHOD THEREOF," the entire contents of which are incorporated herein by reference.

[0075] Furthermore, the present invention discloses a novel MOS structure in which the source and drain regions are completely separated by an insulator, which not only improves immunity to latch-up problems but also increases the isolation distance into the silicon substrate, separating junctions in adjacent transistors and reducing the surface distance between junctions (e.g., 3λ), as well as standard cell dimensions. Below, we briefly describe a novel CMOS structure in which the n+ and p+ regions of the source and drain regions in NMOS and PMOS transistors, respectively, are completely separated by an insulator.

[0076] 9, which illustrates a cross section of an NMOS transistor 51 used in a novel standard cell according to another embodiment of the present disclosure. A gate structure 33, including a gate dielectric layer 331 and a gate conductive layer 332 (such as a gate metal), resides above a horizontal or original surface of a semiconductor substrate (such as a silicon substrate). A dielectric cap 333 (such as a composite of an oxide and nitride layer) resides above the gate conductive layer 332. Additionally, a spacer 34, which may include a composite of an oxide layer 341 and a nitride layer 342, is used to cover the sidewalls of the gate structure 33. Trenches are formed in the silicon substrate, and all or at least a portion of a source region 55 and a drain region 56 are positioned within the corresponding trenches. The source (or drain) regions in the MOS transistor 52 may include N+ regions or other suitable doping profile regions (e.g., a gradual or step change from P− and P+ regions).

[0077] Additionally, a local isolation 48 (such as a nitride or other high-k dielectric material) is disposed within the trench and positioned below the source region, and another local isolation 48 is disposed within another trench and positioned below the drain region. Such local isolation 48 is below the horizontal silicon surface (HSS) of the silicon substrate and may be referred to as local isolation into the silicon substrate (LISS) 48. The LISS 48 may be a composite of a thick nitride layer or a dielectric layer. For example, the local isolation or LISS 48 may comprise a composite local isolation including an oxide layer (referred to as an oxide-3V layer 481) covering at least a portion of the sidewall of the trench and another oxide layer (oxide-3B layer 482) covering at least a portion of the bottom wall of the trench. The oxide-3V layer 481 and the oxide-3B layer 482 may be formed by a thermal oxidation process.

[0078] Composite local isolation 48 further includes a nitride layer 483 (referred to as a nitride-3 layer) on top of oxide-3B layer 482 and in contact with oxide-3V layer 481. It is noted that nitride layer 483 or nitride-3 can be replaced by any suitable insulating material as long as the oxide-3V layer remains maximally as designed. Furthermore, the STI (Shallow Trench Isolation) region in FIG. 9 may include a composite STI 49 including an STI-1 layer 491 and an STI-2 layer 492, and STI-1 layer 491 and STI-2 layer 492 can each be made of a thick oxide material by a different process.

[0079] Furthermore, the source (or drain) region in FIG. 9 may comprise a composite source region 55 and / or drain region 56. For example, in NMOS transistor 52, composite source region 55 (or drain region 56) comprises at least a lightly doped drain (LDD) 551 and an N+ heavily doped region 552 within a trench. Notably, lightly doped drain (LDD) 551 abuts an exposed silicon surface having a uniform (110) crystal orientation. The exposed silicon surface has its vertical boundary with a suitable recessed thickness, labeled in FIG. 9 as the transistor body (thickness), appropriately defined and etched to form a sharp edge of the TEC (effective channel length), as opposed to the edge of the gate structure. The exposed silicon surface is substantially aligned with the gate structure. The exposed silicon surface may be the terminal surface of the transistor's channel.

[0080] A lightly doped drain (LDD) 551 and a heavily N+ doped region 552 may be formed based on a selective epitaxial growth (SEG) technique (or other suitable technique, which may be atomic layer deposition ALD or selective growth ALD-SALD) to grow silicon from the exposed TEC area, which is used as a crystal seed to form a properly ordered (110) new lattice over the LISS region without having a seeding effect on the changing (110) crystal structure of the newly formed crystals of the composite source region 55 or drain region 56. Such newly formed crystals (including the lightly doped drain (LDD) 551 and the heavily N+ doped region 552) may be referred to as TEC-Si, as noted in FIG.

[0081] In one embodiment, the TEC is aligned or substantially aligned with the edge of the gate structure 33, the length of the LDD 551 is adjustable, and the sidewall of the LDD 551 opposite the TEC can be aligned or substantially aligned with the sidewall of the spacer 34. The composite source (or drain) region may further comprise several tungsten (or other suitable metal material) plugs 553 formed in horizontal connection with the TEC-Si portion for completion of the entire source / drain region. As shown in FIG. 9 , active channel current flowing to a subsequent metal interconnect, such as a metal-1 layer, flows through the LDD 551 and the N+ heavily doped region 552 to the tungsten 553 (or other metal material) directly connected to metal-1, due to a particularly good metal-to-metal ohmic contact, with much lower resistance than conventional silicon-to-metal contacts.

[0082] The source / drain contact resistance of the NMOS transistor 52 can be kept within a reasonable range depending on the structure of the merged metal-semiconductor junction utilized in the source / drain structure, as shown in FIG. 9 . The merged metal-semiconductor junction in this source / drain structure can improve current crowding effects and reduce contact resistance. Furthermore, because the bottom of the source / drain structure is isolated from the substrate by a bottom oxide (oxide-3B layer 482) (shown in FIG. 9 ), the n+-to-n+ or p+-to-p+ isolation can be kept within a reasonable range. Therefore, the spacing between two adjacent active regions of a PMOS transistor (not shown) can be reduced to 2λ. The bottom oxide (oxide-3B layer 482) can significantly reduce the source / drain junction leakage current, which in turn reduces the n+-to-n+ or p+-to-p+ leakage current.

[0083] Furthermore, in currently available standard cells, metal wiring for the high-level voltage Vdd and the low-level voltage Vss (or ground) is placed above the original silicon surface of the silicon substrate, which can interfere with other metal wirings if there is not enough space between them. The present invention discloses a novel standard cell in which the metal wiring for the high-level voltage Vdd and / or the low-level voltage Vss can be placed below the original silicon surface of the silicon substrate, thereby avoiding interference with the dimensions of contacts and the layout of metal wiring connecting the high-level voltage Vdd and the low-level voltage Vss, etc., even when the dimensions of the standard cell are reduced.

[0084] As shown in FIG. 9 , in the drain region of NMOS 51, tungsten or other metal material 553 is directly coupled to a P-well electrically coupled to Vdd. Meanwhile, in the source region of NMOS 51, tungsten or other metal material 553 is directly coupled to a p-well or P-substrate electrically coupled to ground. Thus, the openings for the source / drain regions originally used to electrically couple the source / drain regions to the metal 2 layer (M2) or metal 3 layer (M3) for Vdd or ground connection can be omitted in the new standard cell and standard cell. A detailed description of the structure and its fabrication process is disclosed in U.S. patent application Ser. No. 16 / 991,044, filed August 11, 2020, and entitled “TRANSISTOR STRUCTURE AND RELATED INVERTER,” the entire contents of which are incorporated herein by reference.

[0085] FIG. 10(a) is a top view illustrating the combined structure of PMOS transistor 52 and NMOS transistor 51 used in a novel standard cell according to one embodiment of the present disclosure. FIG. 10(b) is a cross-sectional view of PMOS transistor 52 and NMOS transistor 51 taken along the cut line (X-axis) in FIG. 10(a). As shown in FIG. 10(b), this results in a much longer path from the n+ / p junction through the p-well (or p-substrate) / n-well junction to the n / p+ junction. Possible latch-up paths from the LDD-n / p junction through the p-well / n-well junction to the n / LDD-p junction include length (1), length (2) (the length of the bottom wall of one LISS region), length (3), length (4), length (5), length (6), length (7) (the length of the bottom wall of another LISS region), and length (8), as shown in FIG. 10(b). On the other hand, in a conventional CMOS structure combining PMOS transistor 12 and NMOS transistor 11 shown in FIG. 2, a possible latch-up path from an n+ / p junction through a p-well / n-well junction to an n / p+ junction only includes lengths (d), (e), (f), and (g) (shown in FIG. 2). Such a possible latch-up path in FIG. 10(b) is longer than the path in FIG. 2. Therefore, from a device layout perspective, the ensured edge distance (Xn+Xp) between PMOS transistor 52 and NMOS transistor 51 in FIG. 10(b) can be smaller than the edge distance in FIG. 2. For example, the ensured edge distance (Xn+Xp) can be approximately 2 to 4λ, e.g., 3λ.

[0086] Furthermore, unlike the conventional standard cells described above, the present invention utilizes cross-shaped local isolation in the silicon substrate (LISS) (e.g., nitride-3+oxide-3) between the PMOS transistor 52 and the NMOS transistor 51 of the standard cell, so that the possible latch-up path between the PMOS transistor 52 and the NMOS transistor 51 can be longer than that in conventional CMOS, and the latch-up distance or ensured edge distance between the PMOS transistor 52 and the NMOS transistor 51 can be shorter than that used in conventional standard cells.

[0087] Therefore, in the present invention, the latch-up distance between PMOS transistor 52 and NMOS transistor 51 is a minimum of 8λ, regardless of the size (or minimum feature size) of the technology node. In the present invention, the n+ and p+ regions of the source and drain regions in the NMOS and PMOS transistors, respectively, are completely separated by an insulator, which not only improves resistance to latch-up problems but also increases the isolation distance into the silicon substrate, separating the junctions in PMOS transistor 52 and NMOS transistor 51 so that the surface distance between the junctions can be reduced. A detailed description of the novel combined PMOS and NMOS structure is disclosed in U.S. patent application Ser. No. 17 / 318,097, filed May 12, 2021, and entitled "COMPLEMENTARY MOSFET STRUCTURE WITH LOCALIZED ISOLATIONS IN SILICON SUBSTRATE TO REDUCE LEAKAGES AND PREVENT LATCH-UP," the entire contents of which are incorporated herein by reference.

[0088] To solve the problem of small I-on current when the source / drain contact dimensions are scaled down, the present invention further employs selective epitaxial growth (SEG) technology to grow a thin channel layer 1001 covering the original body of the active region (such as the fin structure 1003) below the gate structure 33 of the PMOS transistor 52 (or the NMOS transistor 51) to improve electron / hole mobility. For example, FIG. 10(c) is a cross-sectional view of the PMOS transistor 52 and the NMOS transistor 51 taken along the cutting line (Y-axis) in FIG. 10(a). The thin channel layer 1001 is a doped channel layer formed without ion implantation. Furthermore, the thin channel layer 1001 is not part of the original silicon substrate, and thus, the thin channel layer 1001 is independent of the semiconductor substrate. Furthermore, in one embodiment, the thin channel layer 1001 covers the first and second sidewalls of the fin structure 1003 but does not cover the top surface of the fin structure 1003. In another embodiment, the thin channel layer 1001 comprises a top portion (not shown) covering a top surface of the fin structure 1003 and a side portion covering a first sidewall and a second sidewall of the fin structure, wherein the top portion and the side portion are not formed simultaneously. A detailed description of the improved I-on current of the transistor is disclosed in U.S. Provisional Patent Application No. 63 / 226,787, filed July 29, 2021, and entitled "New Transistor Structure and Processing Method Thereof," the entire contents of which are incorporated herein by reference.

[0089] According to the above, a standard cell that houses an inverter (such as the novel inverter cell 500 shown in FIGS. 5(a) and 5(b)) has an area dimension of (2×Cpp×cell_height) 192λ in the novel structure of the present invention. 2 and λ 2Such converted area dimensions are approximately the same at least from technology nodes 22 nm to 5 nm as compared with conventional products provided by various companies (such as Company A, Company B, and Company C), as shown in Figure 11. Figure 11 is a diagram showing the results of a comparison between the area dimensions of the new standard cell provided by the present invention and the area dimensions of conventional products provided by various other companies.

[0090] However, the layout style and area dimensions of the novel standard cells are not limited to these. In some other embodiments, the present invention may be utilized in a variety of standard cells (e.g., a standard cell with one single NOR cell, one single NAND cell, two NOR cells, or two NAND cells) having different layout styles and cell dimensions (e.g., 3×Cpp×cell_height, or 5×Cpp×cell_height).

[0091] For example, Figures 12(a)-12(c) are top views and corresponding equivalent circuit diagrams of a standard cell having one single NOR cell, one single NAND cell, and two inverter cells according to some embodiments of the present disclosure. Figures 12(d)-12(e) are top views and corresponding equivalent circuit diagrams of a standard cell having two NOR cells and two NAND cells according to some embodiments of the present disclosure. A standard cell having one single NOR cell, one single NAND cell, and two inverter cells may have cell dimensions of 3 x Cpp x cell_height, and a standard cell having two NOR cells and two NAND cells may have cell dimensions of 5 x Cpp x cell_height.

[0092] The present invention develops a compact layout style in a novel standard cell design. In some embodiments of the present disclosure, the novel, compact layout style achieves an area dimension λ that can be independent of technology scaling in terms of λ (Lambda is the minimum feature size of a technology node). 2The layout design described herein allows the area dimensions of the standard cells across different technology nodes to remain uniform or insensitive to the technology node. Furthermore, the latch-up problem does not increase as the standard cell dimensions decrease.

[0093] While the present invention has been described by way of example and in terms of preferred embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims should therefore be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims

1. A standard cell, a plurality of transistors; a set of contacts coupled to the plurality of transistors; at least one input line electrically coupled to the plurality of transistors; an output line electrically coupled to the plurality of transistors; a VDD contact line electrically coupled to the plurality of transistors; VSS contact lines electrically coupled to the plurality of transistors; Equipped with Regarding the minimum processing dimension (λ) of the standard cell, λ 2 In terms of conversion, the area dimension of the standard cell is 192λ 2 or more, and when λ=5 nm, it is 600λ 2 or less, and 450λ when λ=7 nm. 2 or less, and 250λ when λ=10 nm. 2 or less, and 200λ when λ=16 nm. 2 or less, and 200λ when λ=22 nm. 2 is as follows: A standard cell in which, among the plurality of transistors, the bottom of the n+ region of the NMOS transistor is completely insulated by a first insulator, and the bottom of the p+ region of the PMOS transistor is completely insulated by a second insulator.

2. The standard cell according to claim 1 , wherein the standard cell is an inverter cell, a NAND cell, or a NOR cell.

3. 2. The standard cell of claim 1, further comprising a metal contact line electrically coupled to a first contact of the set of contacts, the first contact not being completely covered by the metal contact line.

4. The standard cell of claim 3 , wherein the width of the metal contact line is the same as or approximately the same as the width of the first contact.

5. 4. The standard cell of claim 3, further comprising a heavily doped silicon plug formed on a portion of said first contact not covered by said metal contact line, said heavily doped silicon plug contacting said metal contact line.

6. a first metal line electrically coupled to the plurality of transistors; a second metal line electrically coupled to the plurality of transistors, the second metal line being above the first metal line; Furthermore, 2. The standard cell of claim 1, wherein at least one of the set of contacts connects directly to the second metal line without going through the first metal line.

7. The standard cell of claim 6 , wherein said at least one of said set of contacts is a gate contact.

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