Refresh command control for host assistance in mitigating low hammer

Abstract

To provide a method for refreshing potential victim rows for potential attack rows using additional refresh commands.SOLUTION: In a system 100, a memory device having internal row hammer mitigation is coupled to a memory controller. The memory controller or a host assists in row hammer mitigation by sending additional refresh cycles or refresh commands. In response to the additional refresh command, the memory device performs refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can track the number of activation commands sent to the memory device and the memory controller sends additional refresh commands in response to the threshold number of activation commands.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The description relates generally to computer memory systems, and more particularly to mitigating row hammer events. [Background technology]

[0002] As computer devices continue to shrink in size and increase in capacity and functionality, the minimum devices used to manufacture components Geometry continues to decrease. Geometry This reduction enables continued system scaling, but introduces the potential for data loss due to row hammer or row disturb events. "Row hammer" refers to a failure caused by repeatedly accessing a target or aggressor row within a period of time. Repeated activation to access the aggressor row can cause a failure in a victim row adjacent or nearby to the target / aggressor row, and repeated activation of the target row can cause charge transfer across the pass gates of the victim row, resulting in a non-deterministic state of the victim row. Row hammer is a known issue in DRAM (dynamic random access memory) devices.

[0003] device Geometry decrease Along with , specific lines that may cause a low hammer event to Number of activations teeth From 500K to 300K It It is now predicted to be 100K, and about 30K to 50K Activating a range of to It is even predicted to decrease . twist For low hammer events caused by fewer activations, more rows are attacked within the refresh window. line This can lead to increased risk of data loss, requiring more Row Hammer mitigation.

[0004] Traditional row hammer mitigation, managed by the memory controller, places a heavy burden on the memory controller and increases the latency between the memory controller and the DRAM. collaborative management This puts a strain on memory bus bandwidth. Currently, most DRAM devices typically require a R Fresh Cycle To "steal" Therefore, the DRAM device itself handles the Row Hammer mitigation internally. M Refresh cycles issued by the memory controller How many to use for low hammer mitigation Determine.

[0005] However, the threshold for low hammering decreases. As , a memory device may require more refreshes than can reasonably be obtained without compromising the data integrity of the device. seize One option is to increase the refresh rate. However, increasing the refresh rate can result in a lower hammer refresh, even if it is not required. M to the memory subsystem Sustained power and bandwidth Therefore, changing the refresh rate is inefficient due to the risk of over-refreshing when no low hammer conditions exist. [Brief explanation of the drawings]

[0006] The following description includes a discussion of figures having illustrations given as examples of implementations. The figures should be understood as examples, not limitations. As used herein, reference to one or more examples should be understood as describing particular features, structures, or characteristics included in at least one implementation of the invention. Phrases such as "in one example" or "in an alternative example" appearing herein provide examples of implementations of the invention, and do not necessarily all refer to the same implementation. However, they are not necessarily mutually exclusive.

[0007] [Figure 1]FIG. 1 is a block diagram of an embodiment of a system for performing host-assisted Rowe hammer mitigation.

[0008] [Figure 2] FIG. 10 is a timing diagram of an example command sequence for an extra external refresh for Row Hammer mitigation refresh.

[0009] [Figure 3] FIG. 1 is a block diagram of an example memory subsystem that can implement redundant external refresh from a host to assist with row hammer mitigation.

[0010] [Figure 4] FIG. 2 is a block diagram illustrating an example of multiple counters for tracking Row Hammer mitigation information for different memory portions.

[0011] [Figure 5] 1 illustrates an example of a selected command truth table for a system that supports host-assisted low hammer mitigation.

[0012] [Figure 6] 1 is a flow diagram of an example process for host-assisted row hammer mitigation.

[0013] [Figure 7] FIG. 1 is a block diagram illustrating an example of a memory subsystem capable of implementing host-assisted row hammer mitigation.

[0014] [Figure 8] FIG. 1 is a block diagram illustrating an example of a computing system in which host-assisted row hammer mitigation can be implemented.

[0015] [Figure 9] FIG. 1 is a block diagram illustrating an example of a mobile device capable of implementing host-assisted row hammer mitigation.

[0016] A description of specific details and implementations follows, including a non-limiting description of figures that may show some or all examples, as well as other possible implementations. DETAILED DESCRIPTION OF THE INVENTION

[0017] As described herein, Low Hammer relaxation By support And, and memory devices By management And The memory device performs internal row hammer mitigation, and the memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. The system can track the need to send additional refresh cycles to prevent using power and bandwidth on unnecessary refreshes.

[0018] For example, the memory controller may R You can track the number of activation commands, The memory controller has a threshold number of Activate Command to pls respond, Follow up Send an additional refresh command. M The memory device In response to an extra refresh command , Standard data integrity refresh instead of , a refresh can be performed to mitigate the low hammer. surplus Refresh command in Instead of simply refreshing rows that have not been accessed for a period of time, the memory device by Potential victim rows can be refreshed. In such an implementation: Instead of simply increasing the refresh rate, The memory device has enough refresh cycles available to perform Row Hammer mitigation. in spite of ,this Extra The cycle is Depends yet still be able to respond to requests effectively. surplus The refresh command for Extra This can be called a refresh command. surplusThe refresh command can be issued as a Refresh Management (RFM) command from the host, which is designed to address the row hammer issue.

[0019] The host controller or memory controller must have the necessary surplus To compensate for the refresh of the memory device, for example, a dynamic random access memory (DRAM) device, additional refresh commands are sent to the memory device. By providing the additional refresh cycles, the memory device can reduce the number of cycles without compromising data integrity by still providing enough refresh cycles for a standard refresh operation. seizure In one example, the memory controller determines the number of activation commands sent to the memory device. surplus Determine the number of refresh commands sent to the memory device; The memory device To implement Rouhamma mitigation seizure There is a high correlation between the number of refreshes that need to be performed and the time it takes to complete the refresh.

[0020] Host-assisted row hammer mitigation as provided eliminates the need for a Targeted Row Refresh (TRR) protocol in the host controller. The controller itself Monitoring By This occurs when the controller becomes aware of a potential row hammer event, either through signaling from the memory device or by a TRR command. TRR allows the controller to send a specific refresh command indicating the target row, and the memory device refreshes one or more victim rows. Host-assisted row hammer mitigation is achieved by the controller issuing a TRR command. For You don't need to know the target row. Furthermore, host-assisted low hammer mitigation is possible if a specific target row is Threshold number Activation versus The need for low-hammer mitigation can be easily estimated by monitoring the number of activations in general, without considering whether they are elephants or not.

[0021] Host-assisted row hammer mitigation puts the decision of which rows to refresh into the control of the memory device. Entrust The internal operation of refresh tends to have a fair amount of margin, and memory device manufacturers simply do not consider worst-case scenarios. Instead of working on rather, the company's own devices unique of ability and needs. ability This allows memory devices to implement row hammer mitigation and refresh control in a device-specific or manufacturer-specific manner. Thus, for example, DRAM manufacturers can safely implement row hammer mitigation and refresh control without affecting data integrity. seizure Know the number of refreshes you can perform, Manufacturer specific For devices Some kind of rational relief of It can be executed.

[0022] FIG. 1 (WAS1) is a block diagram of an embodiment of a system for performing host-assisted row hammer mitigation. System 100 includes a memory device 120 coupled to a memory controller 110, also referred to as a host controller or simply a controller. Memory device 120 can include any type of memory technology having adjacent rows of memory cells, with data accessible via word lines or the like. In one example, memory device 120 includes DRAM technology. Rows of memory device 120 need to be refreshed to maintain a deterministic state.

[0023] Memory device 120 includes memory array 130, which represents an array of memory cells or storage cells. A memory cell stores one bit of data, or multiple bits for multi-level cells. Memory array 130 includes a representation of potential row hammer situations. By way of example, memory array 130 shows bank 140 and bank 150. It will be understood that memory array 130 can include multiple banks. Generally, a bank or sub-bank of memory is a bank of memory that stores memory cells of another bank or sub-bank. What isIt contains separately addressable memory cells and therefore separate portions of the memory array 130 and The memory array 130 may include portions of the system 100 that are not shown.

[0024] The memory device 120 applies charge to the columns based on the access command. El In one example, the column decoder (dec) 132 represents a circuit for: The relevant The circuitry selects a column in response to a column address strobe (CAS) command. The memory device 120 includes a row decoder (dec) 134, which represents circuitry for applying select voltages to rows based on memory access commands. In one example, The relevant The circuitry selects columns in response to a row address strobe (RAS) command.

[0025] The memory controller 110 includes command logic 112 that generates commands for the memory device 120. The commands may include commands such as a Write command or a Read command. The commands may also include an Activate command, a Precharge command, a Refresh command, or other commands. In one example, the memory controller 110 includes refresh logic 172, which represents logic that controls the refresh of the memory device 120. The refresh logic 172 may include one or more counters for determining the need for a refresh of the memory device 120 and a register space for tracking the transmission of refresh commands. The refresh commands may include external refresh commands (e.g., REF, REFpb), in which case the memory device continues to operate according to a clock signal from the memory controller 110. The refresh commands may include self-refresh commands (e.g., SRE), in which case the memory device operates on an internal clock rather than based on a clock signal from the memory controller. An external refresh may be theA memory device has a specific window for completing a command, and self-refresh means that the memory device is able to possible It is a state of being.

[0026] The memory controller 110 sends commands to the memory device 120. Sequence The memory controller 110 includes a scheduler 116 for managing the scheduling and transmission of commands. The scheduler 116 includes logic for determining the order of commands, as well as the timing requirements of the commands. Which command Send mosquito and The memory controller 110 The scheduler 116 also determines the order of commands to ensure compliance with timing requirements. The scheduler 116 can enable the memory controller 110 to make specific decisions regarding commands and timing. In one example, the scheduler 116 schedules commands during a refresh window. How many External Refresh Command Whether to send The scheduler 116 determines the surplus The refresh command can be generated.

[0027] In one example, the memory controller 110 The controller has a threshold number of Activate command or Activate but The time when the data was sent to the memory device 120 judgment To be able to determine ofThe memory controller 110 includes row hammer (RH) logic 174. For example, the row hammer logic 174 may include one or more counters or other logic for monitoring potential row hammer conditions. In one example, the row hammer logic 174 includes a comparator that determines when an activation counter reaches a threshold number. In one example, the threshold number is programmable, such as in register 122, such as by a mode register or other register or configuration. The memory controller 110 may read the configuration and store it in a register or other device (specifically not shown) internal to the memory controller 110.

[0028] Memory controller 110 includes I / O (input / output) hardware 114. I / O 114 represents transceivers and signal line interface hardware that allows memory controller 110 to connect to memory devices 120 via one or more buses. I / O 114 allows memory controller 110 to send commands to memory devices 120. Memory controller 110 includes buffers 176 that buffer a series of commands to send to memory devices 120. In one example, buffers 176 are part of scheduler 116. Scheduler 116 determines the commands and the order in which they are sent, and then: The command is The signal may be queued in the buffer 176 for transmission via the I / O 114 .

[0029] To illustrate the row hammer condition, memory array 130 includes a target row 142 within bank 140. A physically adjacent or physically adjacent row is defined as: The adjacent Before a refresh operation on a row To, Within a certain period of Target row 142 to repetition of Based on access tree , The adjacentA row may be subject to unintended programming or disruption of one or more values ​​stored in the row. Victim row 144 represents a row that is affected by row hammer when target row 142 is repeatedly accessed. If victim row 144 is at risk of a row hammer event, target row 142 may be referred to as an attacking row. There may be another row in bank 140 that is a victim row to target row 142.

[0030] In one example, bank 140 also includes target row 146. Target row 146 is considered to be at or near a bank boundary. Let's try It will be appreciated that rows in memory array 130 may have the same spacing even if the rows are in different banks. Rather, the separation from one bank to another is Selection Select or decode Hardware elements of Therefore, depending on the architecture of the physical layout of the rows, rows on the boundaries of the bank 150 may also be at risk of a row hammer event based on accesses to the target row 146. In one example, the target row to Repeated visits but Multiple adjacent line obstructions of occurrence Let As shown, target row 146 may cause a row hammer event to both victim row 148 in bank 140 and victim row 152 in bank 150.

[0031] The memory device 120 includes an I / O 126 that interfaces with the I / O 114 of the memory controller 110. The I / O 126 receives commands and address information for receiving activate and refresh commands, among other commands. corresponding signal line to I / O 114 to receive of In one example, I / O 126 includes an interface to a data bus to exchange data with memory controller 110.

[0032] Memory device 120 includes registers 122 representing one or more registers or memory locations for storing configuration information or values ​​related to the operation of memory device 120. In one example, registers 122 include one or more mode registers. In one example, registers 122 include configuration information for controlling the application of refreshes internal to memory device 120. In one example, registers 122 include information related to row hammer operations, such as a threshold number of activations prior to a row hammer state.

[0033] Memory device 120 includes controller 180, which represents a controller local to the memory device. Controller 180 includes hardware logic that performs operations in response to commands. Controller 180 includes software or firmware logic that controls the hardware logic and controls the operations and sequence of operations within the memory device. In one example, controller 180 includes refresh logic 160. In one example, controller 180 includes RH counter 124. Controller 180 manages I / O 126.

[0034] In one example, memory device 120 includes refresh logic 160, which represents logic within memory device 120 for managing the refresh of memory array 130. In one example, refresh logic 160 includes a refresh (ref) counter 162 and row hammer (RH) logic 164. Refresh counter 162 indicates when a refresh is to be performed. Should The row address may indicate the row address. Refresh counter 162 may represent multiple counters since different banks or sub-banks may have different addresses identified for refresh. Row hammer logic 164 enables memory device 120 to manage row hammer mitigation. Row hammer logic 164 may include one or more counters, a list of potentially attacking rows, or other logic to perform row hammer mitigation. In one example, row hammer mitigation is enabled by receiving an activate command. mostThis is done by performing a refresh of the potential victim row at the later row address. Accompany The heuristic recognizes that when a row is hammered, the address of that row is most likely to have just received an activate command before receiving a refresh command for use in row hammer mitigation. On average ,Such an approach should refresh potentially victim rows if sufficient Row Hammer mitigation ,operations are performed.

[0035] In one example, memory device 120 includes one or more row hammer (RH) counters 124. Counters 124 may be or include row hammer detection logic. In one example, memory device 120 detects potential row hammer conditions and performs actions to mitigate risks associated with row hammer events. In one example, counters 124 maintain counts associated with one or more rows that are repeatedly accessed. For example, counters 124 may maintain an optional address (addr) list of rows with the highest activation counts within a refresh window. The counts may be reset after a refresh.

[0036] It will be appreciated that tracking the number of activations per row is impractical as it would require over a million counters per bank in certain memory devices. To apply low hammer mitigation , employ heuristics, or Probability-basedInstead of tracking activations of all rows, only selected rows can be tracked. When the counter reaches a threshold number, refresh logic 160 can perform a row hammer refresh. In such an implementation, each time a new row is activated, it can replace the lowest count. In one example, counter 124 maintains a list of rows with the highest number of activations, and when an external refresh command is received, it performs row hammer mitigation on the row or rows with the highest number of activations. Thus, refresh logic 160 does not necessarily have to wait until the threshold number is reached before performing row hammer refresh mitigation.

[0037] Another heuristic approach is to randomly assign row hammer refreshes to randomly selected rows that receive activations. In such an implementation, Counter 124 Optionally stores the address of the most recently activated row thing just need That's fine. In theory, it is possible that a row that is repeatedly activated could be randomly selected for Row Hammer mitigation refresh. twist High. Therefore, probability is Ha Will you be attacked? or repeat The rows accessed are also the rows that are likely to be selected for Row Hammer mitigation. The logic and circuit requirements of such an approach are simpler than those required to maintain a list of rows, but the Row Hammer mitigation accuracy is reduced.

[0038] Refresh logic 160 represents logic within memory device 120 for controlling the refresh of rows in memory array 130. Refresh logic 160 responds to external refresh commands sent by refresh logic 172 of memory controller 110. Refresh logic 160 controls refresh operations during self-refresh operations of memory device 120. Refresh logic 160 also controls refresh operations for scheduled refresh operations. ofIt includes a refresh (ref) counter 162 to track row addresses. A scheduled refresh operation involves refreshing all rows within a refresh period. guarantee that , sequential The refresh logic 160 of the memory controller 110 includes: R To meet freshness requirements Sufficient refresh operations are performed on the memory device 120. Responsible for ensuring that the schedule is met.

[0039] In one example, the refresh logic 172 schedules more refresh operations than necessary for a refresh period. Refresh logic 160 for use in low hammer mitigation based on the number of activations sent to memory device 120 Surplus of of or Extra With the additional row hammer mitigation refresh provided by memory controller 110, even heuristic techniques can be used to mitigate row hammer. due to It will be appreciated that this significantly reduces the likelihood of data loss.

[0040] In one example, refresh logic 160 includes row hammer logic 164 that provides refresh operations for row hammer mitigation. Row hammer mitigation refers to refreshing a potential victim row to avoid disturbing the row. In operation, counter 124 Can indicate target row for Rowhammer Logic 164 , Low Hammer Logic 164 Refresh logic 160 R "Refresh Seizing " can be triggered. 。 What is Refresh Stealing? The refresh logic 160 Instead of performing a refresh of the row indicated in the refresh counter 162, perform a refresh of the victim row associated with the indicated target row. thing Therefore, the row hammer mitigation refresh operation is out of order with respect to the refresh row pointer or counter. (out of order) The Row Hammer mitigation requires one full refresh operation or1 Refresh every refresh of the refresh cycle, or just 1 Refresh one or more of the refresh operations seizure This includes: and tagged or shown as (explained in more detail below) For commands, or The refresh logic 160 detects that a certain refresh command Activation of Threshold In terms of arrival and time When corresponding judgment If you specify Refresh The logic can determine that it is safe to use all cycles for Rowe Hammer mitigation.

[0041] Typically, the memory device 120 includes: In response to an external refresh command Complex Performs a refresh of several rows. A refresh operation is one that is refreshed in response to a single refresh command. Should Refers to the refresh of all rows. A refresh operation has a time, tRFC (row refresh cycle time), and the number of refresh operations within a refresh period or refresh window between has an average refresh interval called tREFI (time between refreshes). The refresh period refers to the time between refreshes of any given row to ensure that data in the row is not lost. Refreshes are performed in response to a refresh command. Should All rows Our It can refer to a single row refresh, and a single refresh operation has a time period shorter than tRFC because it involves multiple refreshes.

[0042] It will be appreciated that there can be multiple target rows in the same bank, as shown in bank 140. As the critical number of row hammers decreases, the number of activations required to cause a row block continues to decrease, thus increasing the number of potential attacking rows. It will beTherefore, the number of Row Hammer mitigation operations required per refresh period continues to increase. To allow for more Row Hammer mitigation operations, the memory controller 110 specifically: How many Activate Command has been sent The refresh (both external and internal) is performed by the memory controller and the memory device. to access but This is the only time we can guarantee that this won't happen. different Bank different It may be refreshed in time. the law of nature , Therefore, different On time Okeru Access Not being available It will be understood that the unrefreshed bank teeth access can be Therefore, the scheduler 116 different Manages the scheduling of bank refreshes.

[0043] The row hammer logic 174 of the memory controller 110 M Tracks the number of activation commands sent to memory device 120. to trigger the sending of additional refresh commands. Such a mechanism is much simpler than having the memory device 120 track the need for additional refreshes and attempt to signal the memory controller. Extra Tracking the threshold for sending refreshes do In this case, actions can be taken based on configurable parameters such as activation thresholds. teeth , different Operating status for , different device or Manufacturer Ma or impact the need for additional low hammer mitigation. can have an effect Other variables configurability for Enable vinegar do.

[0044] The operation of row hammer logic 174 may vary for different implementations. In one example, row hammer logic 174 sends an additional refresh command whenever a programmable threshold is reached, regardless of the time window. In one example, row hammer logic 174 sends an additional refresh only if a count is reached within a specific time segment. For example, the count may be reset every normal refresh period, and the count triggers an additional external refresh only if a threshold is reached within the refresh window.

[0045] In one example, the period of interest for sending additional refresh commands is a sliding window. The sliding window can be established, for example, using a leaky bucket technique. In the leaky bucket technique, the Row Hammer logic 174 decrements (or increments, depending on the technique) a count in response to each activate command. Can In a decrementing scheme, when the count reaches zero, an additional refresh is triggered. In one example, the row hammer logic 174 decrements on a time basis, resulting in a nominal rate of activations per μs (microseconds) that does not trigger additional refresh cycles. In such a scheme, the row hammer logic 174 only triggers when cycles above the nominal rate are detected. surplus Such a technique simply a Activation Total number of Instead, it may be based on the assumption that only the rate of activation over a certain time will trigger a low hammer event.

[0046] In the counter-up approach, the refresh is done by e.g. General This can be done with a sub-refresh period which can be 1 / 4 or 1 / 2 of the normal refresh time. Thus, during each fixed period, the Row Hammer logic 174: surplus This can trigger the sending of a refresh command. 100,000 yen Causes row blockage one Consider an example TryThen, Low Hammer Logic 174 will either fail after 80,000 activations, or after 60,000 activations, or The relevant After some other programmable count below the row disturb value, sending of an additional refresh command can be triggered.

[0047] surplus The timing of sending refreshes can be adjusted in one of several different ways. surplus The frequency of the refresh is adjusted by programmability or configuration. surplus The refresh frequency of surplus Refresh of It depends on how the monitoring is performed. The frequency can be adjusted by the combination of the monitoring method and programmability. As mentioned above, the monitoring method is independent of the time window. Threshold number Activation detection , or the number of activations within a fixed time window Detection of , or in response to detecting the number of activations within a sliding window surplus In one example, the period is programmable rather than fixed at the refresh period. In one example, the sliding window is programmable. In one example of a leaky bucket approach, the rate at which the leaky bucket fills is programmable.

[0048] The granularity of the Row Hammer mitigation tracking can be implementation dependent. Tracking granularity is discussed in more detail below. In general, the granularity depends on the level at which monitoring is performed. In one example, monitoring is performed at the device level. In one example, monitoring is performed at the channel level. In one example, monitoring is performed at the rank level. In one example, monitoring is performed at the bank group level. In one example, monitoring is performed at the bank level.

[0049] Figure 2 shows the Low Hammer relaxation refresh Extra200 is a timing diagram of an example command sequence for external refresh. With 2 illustrates a timing diagram for a refresh. Diagram 200 illustrates multiple interconnections between a host or memory controller and an associated memory device, as well as certain internal functions within the memory device. The interconnections are provided via one or more signal lines.

[0050] CLK 210 represents the system's clock, with both a clock (CK_t) and a complementary clock (CK_c) shown. In the example diagram 200, the clock is a solid signal with an arrow indicating a rising edge. The complementary clock is shown as a dashed line. CA 212 represents the command / address (C / A) signal transmitted on the C / A signal line and indicates the command encoding provided by the host. CMD 216 represents the decoding of the command encoding and therefore may represent signals internal to the memory device for operations generated to execute the command. RH CTR 214 represents the memory controller's row hammer counter. Refresh 218 represents refresh operations within the memory device.

[0051] CA212 shows a REF command at 220. The REF command represents a standard external refresh command from the memory controller. At 222, the memory device The relevant The command is interpreted as an external (EXT) refresh command on CMD 216 and an internal operation is generated at 224 to perform the refresh. The relevant Until the row is refreshed in response to an external refresh command of A series of refresh commands can be included, including REF for CTR0, followed by CTR1, etc. CTR0 and CTR1 are Which line Refresh Or The refresh cycle parameter represents a value indicating the number of refresh cycles, which may be a counter or pointer for tracking internal refresh operations. In one example, although not specifically shown, the memory device may perform one or more refresh cycles. seizureThen perform a low hammer mitigation refresh.

[0052] Dashed line 226 represents a time break. CA 212 shows an ACT command at 228. In one example, the ACT command is followed by row hammer counter 214 performing a row hammer increment (RH INCR) at 230. The relevant The increment represents the tracking of activation commands by the memory controller, but not the tracking of row hammer mitigation. implementation It will be understood that a decrement may be used instead of an increment depending on The relevant After the activate command teeth , To execute the activation command One or more internal operations On CMD216 232 To be continued In one example, the memory device may include: R Fresh 218 on 234 , activation command low hammer Suggestion It will be appreciated that row hammer tracking occurs in addition to executing the activate command at the row indicated by the address accompanying the activate command. In systems that track multiple counters for row hammer mitigation, row hammer tracking can include updating counter information.

[0053] The dashed line 236 represents a time break. CA 212 indicates a subsequent ACT command at 238. The relevant Subsequent activate commands are It will be observed that the same actions can be triggered by , B Uhamma Counter 214 In the above 240 RH INCR 、 On CMD216 in of In 242 ACT, and R Fresh 218 Upper in of In 244 As shown by RH tracing. From this part, When an activate command is received, the memory controller these commands can be tracked, but will not trigger Low Hammer mitigation unless a threshold is reached. Things you don't need to do It will be understood.

[0054] The dashed line 246 represents a time break. In one example, After the time break, on CA212 Regardless of what may occur , B A time threshold is reached in a system implementing the leaky bucket approach to Uhamma detection. In one example, time Reaching In response to M The memory controller B Uhamma Counter 214 In 248 Execute Rohanma Decrement (RH DECR).

[0055] The dashed line 250 represents a time break. CA 212 indicates a subsequent ACT command at 252. The relevant It will be observed that a subsequent activation command triggers the Row Hammer mitigation threshold. Low hammer counter 214 on 254 RH INCR Departure When this occurs, the memory controller surplus In response to an ACT on CA212, The memory device As indicated by 256 in CMD216, a Decode the activation operation and refresh 218 to 258 Okeru RH Tracking but Performs internal low hammer tracking. Threshold of In response to an activate command, at some point after the activate command, The memory controller CA212 In 260 above , B Send a RH REF command. The refresh command is Shown adjacent to the ACT command that triggered the Low Hammer state is A It may or may not be sent immediately adjacent to the CT command. The relevant The REF command is, for example: this Detect the condition, The relevant Schedule a REF command, KatsukoThis command is sent adjacent to the ACT command by logic within the memory controller that buffers it for sending to the memory device.

[0056] If the activate command triggers row hammer mitigation, CMD 216 indicates row hammer mitigation (RH MIT) selection by the memory device at 262. Row hammer mitigation selection is The memory device For refreshment of Select the victim row thing may include: M The memory device In response to the selection of one or more victim rows , R Fresh 218 on In 264 A low hammer mitigation refresh, represented by RH REF, can be performed. The refresh is a signal that the memory device has received from the host that the host will not attempt to access the memory device. confirmation This is the only time to but , memory devices but Instead of following the refresh counter, the damage caused by the low hammer On top Run Refresh to make it possible Thus, the Row Hammer mitigation refresh performed during the refresh cycle provides an operation that ensures there are no other operations by the memory device or access attempts by the memory controller.

[0057] Figure 3 shows the host's response to assist in mitigating low-hammer attacks. surplus 1 is a block diagram of an example of a memory subsystem that can implement external refresh. System 300 represents elements of a computing system. System 300 provides an example of a system that may include system 100. System 300 can be thought of as having a memory subsystem having a memory controller 320 and memory 330. Host 310 represents a hardware platform that controls the memory subsystem. Host 310 includes one or more processors 312 (e.g., central processing units (CPUs) or graphics processing units (GPUs)) that generate requests for data stored in memory 330.

[0058] The host 310 includes a memory controller 320, which may be integrated into a processor device. The memory controller 320 includes I / O (input / output) 326 for connecting to memory 330. The I / O includes connectors, signal lines, drivers, and other hardware for interconnecting a memory device to the host 310. The I / O 326 may include command I / O represented by a command (CMD) bus 314 and data I / O via a DQ (data) bus (not specifically shown). The CMD bus 314 includes command signal lines that allow the memory controller 320 to send commands to the memory 330, including an activate command (ACT) and a refresh command (REF).

[0059] Memory controller 320 includes command (CMD) logic 322 that generates commands to memory in response to operations by processor 312. The commands can be for data access (such as Read, Write, Refresh, or other commands) or for configuration (such as mode register commands). Memory controller 320 includes a scheduler 324 that schedules when to send commands in a sequence of operations. Scheduler 324 can control the timing of I / O according to known timing to increase the likelihood that I / O will be error-free. The timing is set by training.

[0060] The memory 330 is Multiple may include individual memory devices, or 1 The system 300 shows two ranks of memory devices in the memory 330: rank[0] and rank[1]. A rank refers to a collection or group of memory devices that share a select line (e.g., a CS signal line). Thus, One Within the ranks MultipleThe memory devices perform operations in parallel. Rank[0] and Rank[1] are shown to contain N DRAM devices or DRAMs. Typically, systems with multiple ranks have the same number of DRAMs in each rank.

[0061] DRAM[0] of Rank[0] and DRAM[0] of Rank[1] are shown to include I / O 332, control (CTRL) 336, and register (REG) 334. It will be understood that other DRAMs also include such components. I / O 332 represents connection hardware equivalent to I / O 326 of memory controller 320. I / O 332 enables connection of the DRAM to memory controller 320. Register 334 represents one or more registers within the DRAM, including one or more configuration registers, such as a mode register. Register 334 can store configuration information and information that determines the operating mode of the DRAM in response to signals on the command and data lines. In one example, the DRAM includes register 334 that stores a programmable value indicating a row hammer mitigation threshold.

[0062] Control logic 336 represents the control components within the DRAM for decoding and executing commands and access operations. Control 336 causes the DRAM to perform the internal operations necessary to execute accesses initiated by memory controller 320. In one example, the DRAM includes row hammer (RH) logic 338 representing row hammer logic in accordance with the teachings described herein. In one example, row hammer logic 338 is part of control logic 336. Row hammer logic 338 allows the DRAM to determine how to perform refreshes to manage row hammer mitigation. For example, row hammer logic 338 may determine the refresh cycle Seizing can be controlled to perform low hammer mitigation.

[0063] In one example, the memory controller 320 includes one or more row hammer counters (RH CTR) 328 to monitor the status of row hammer mitigation. R Detecting the number of activation commands. Tracking the commands scheduled to be sent to memory 330 is useful for Row Hammer mitigation. surplus The refresh of when may be necessary Showing excellent It serves as an indicator.

[0064] In one example, memory controller 320 includes a number of counters 328 sufficient to provide the level of tracking granularity desired in system 300. The highest granularity is a channel. System 300 does not specifically show a second channel. A channel refers to all memory devices that connect to the same command bus. Command bus 314 connects to all DRAM devices shown and is therefore assumed to be a single channel.

[0065] The DRAM device is shown as having multiple banks (banks [0:7]). It will be understood that eight banks is an example and not a limitation. Other systems may include four banks, sixteen banks, thirty-two banks, or some other number of banks. While binary banks are simpler from an addressing perspective, they are not required for operational purposes, and any number of banks may be used. Banks 340 may be utilized as separate banks that are separately addressable by bank number. In one example, banks 340 are organized into bank groups, such as bank [0:3] as BG0 (bank group 0) and bank [4:7] as BG1. Bank groups may alternatively be, for example, BG0 with banks [0, 2, 4, 6], or some other grouping. Bank groups can typically be accessed separately, which may allow for shorter access times than sequential accesses to banks of the same bank group, for example.

[0066] A lower level of granularity can be the rank level, where each rank can be tracked separately. surplus The refresh command for Threshold number Activate Command of Another level of granularity can be package or die-based on the memory device die or package. Such a level can provide balance for the system 300, since tracking by the memory controller 320 matches tracking performed by the DRAM devices. As before, surplus Refreshes can be limited to be sent only when necessary, surplus The refresh can be sent only to the device(s) that are detected as needing a refresh.

[0067] The lower level of granularity (finer granularity) can be based on the granularity of the refresh commands of the particular DRAM technology of memory 330. For example, different DRAM technology teeth Refresh can be performed on a bank set, bank group, or bank-by-bank basis. A bank refers to a group of rows that are addressed with a row decoder and a column decoder. A bank group refers to a group of banks that can be accessed together based on a bank group decoder based on a bank group address. A bank set can refer to the identification of banks across a bank group that have a common bank address within the bank group.

[0068] The advantage of finer granularity is that it only targets the affected area, rather than the entire chip or channel. surplus The drawback of finer granularity is the addition of tracking logic in memory controller 320, such as counter 328. Whatever level of granularity is used, surplus The refresh command is sent only to the particular segment for which the activation threshold is detected.

[0069] bank Every or per bankset of Refresh yourself possible In current implementations of DRAM devices, there is a common row counter, which means that the row counter for a particular bank or set of banks is surplus Refreshing is usually Not possible The implementation of the low hammer mitigation described is May require exceptions to typical rules , in this case, DRAM is a specific set of banks or specific Additional refreshes to the bank can be detected and used for row hammer mitigation. 。

[0070] 4 is a block diagram illustrating an example of multiple counters for tracking row hammer mitigation information for different memory portions. System 400 represents elements of a memory controller according to any example herein. System 400 includes a scheduler 430 that schedules and sends commands to the memory device.

[0071] In one example, system 400 includes a plurality of row hammer counters 410. System 400 shows N counters, where N is the number of counters tracked for row hammer states. Should For example, the Row Hammer mitigation monitoring level occurs at the memory device die level. character where N is equal to the number of device dies connected to the memory controller. It's okay .

[0072] In one example, the system 400 includes: From counter 410, In which part of memory surplus Whether to send a refresh command Decision The row hammer decode 420 allows the scheduler 430 to determine whether a row hammer condition exists. to , surplus It is possible to ensure that the refresh of grain degree The finer the , the memory controller identifies the row hammer mitigation state necessary Counter 410 There are many It will be understood that

[0073] 5 illustrates an example of selected commands in a command truth table for a system that supports host-assisted Row Hammer mitigation. Command table 700 illustrates an example of command encoding for a memory device that performs Row Hammer mitigation refresh according to any of the descriptions herein.

[0074] For command table 500, the command bus signals may include CS for chip select and multiple CA (command / address) signals identified as CA[0:13]. The number of CA signal lines may be more or less than shown. The legend for the signal line values ​​is as follows: BG = Bank Group Address, BA = Bank Address, R = Row Address, C = Column Address, BC8 = Burst Chop 8, MRA = Mode Register Address, OP = Opcode, CID = Chip Identifier, CW = Control Word, H = Logic High, L = Logic Low, X = Don't Care or the signal may float regardless of the state of the signal. V = Valid means any valid signal state, more specifically, high or low.

[0075] ACT represents the Activate command that can be used in memory array accesses. As shown above, a number of activations above a threshold can cause a row hammer event. In one example, the memory controller counts the number of activations and M Allows memory devices to perform low hammer mitigation Sending extra refresh commands Provides additional refresh cycles.

[0076] Command table 500 refreshes all rows 、 Refresh All Command R The REF command causes the memory device to refresh a row according to the row address indicated in the refresh counter. In one example, in accordance with the above, the memory device refreshes a row according to the row address indicated in the refresh counter. What isIn no particular order (out of order) The memory device can refresh rows that are at risk of data loss due to a row hammer event. Randomization row choice Execute.

[0077] In one example, the command table 500 includes a REFsb command to refresh the same bank for refreshing the same bank in a different group. Stolen A low hammer mitigation refresh can be performed as a refresh cycle. In one example, command table 500 includes an SRE command in a self-refresh entry that puts the memory device into a low power state and performs a self-refresh. It will be understood that an SRE is a different type of command than a REF or REFsb. The REF and REFsb commands can be referred to as external refresh commands.

[0078] In one example, 1 Multiple refresh commands is used by the memory controller to mark it as a redundant refresh or row hammer refresh command. Tagged R The memory device The relevant Detect the bit, From the bit, It can be determined that the refresh command is for Row Hammer mitigation. In one example, the refresh command can be extended with a header or other bit to indicate Row Hammer mitigation. The command table 500 includes a field 510 containing finger It is determined R It will be observed that there are bits CA8 and CA9 that only require a valid signal to comply with the command encoding. can be used as a tag For example, if the memory controller The relevant Bit Our One Bit Value B Uhamma relaxation refreshment Set it to , the memory device The relevantThe logic value of the bit is detected to determine whether it is a standard refresh command or a row hammer refresh command. M Memory device specifications (for example, CA8 and CA9 for the Double Data Rate (DDR) standard) Modified to have information in bits not specified below but acceptable The command can be thought of as a refresh management command.

[0079] It will be understood that the tagging shown is just one possible example, and commands can be tagged for low hammer mitigation in other ways.

[0080] 6 is a flow diagram of an example process for host-assisted row hammer mitigation. Process 600 may be performed by a system having host-assisted row hammer mitigation according to any example herein.

[0081] In one example, the memory controller determines whether there is an activate command to send to the memory device at 602. If there is an activate command (602, "yes" branch), the memory controller can increment a counter at 604. In one example, if no activate command is detected (602, "no" branch), the memory controller does not increment the counter.

[0082] In one example, After confirming the activation command, M The memory controller is 606. time Intermittent Does it exist? In one example, the timer time Intermittent existsIf so (606, "Yes" branch), the memory controller decrements the counter. Such an implementation can be called a leaky bucket implementation, which creates a sliding window for checking the state of the row hammer. In the leaky bucket approach, the detection of an activate command increments the counter, and the expiration of the timer decrements the counter. The decrement can be a single decrement depending on the frequency of the timer expiration, or multiple units for slower counters. If the timer expiration is not detected (606, "No" branch), the counter is not changed.

[0083] In one example, after checking for the activation command and timer expiration, the memory controller at 608 determines whether the counter is the limit value It can be determined whether , which indicates that the threshold has been reached . In one example, When the threshold is reached, M The memory controller sends an additional refresh command and resets the counter at 610. In one example, if the counter has not reached the threshold, the memory system continues to monitor for an activate command at 602.

[0084] 7 is a block diagram illustrating an example of a memory subsystem that can implement host-assisted row hammer mitigation. System 700 includes elements of a processor and memory subsystem of a computing device. System 700 can follow an example of system 100 of FIG. 1.

[0085] In one example, memory device 740 includes row hammer logic 780 representing row hammer logic that enables the memory device to manage row hammer mitigation internal to the memory device. In one example, memory controller 720 includes row hammer logic 790 that provides host-assisted row hammer mitigation according to any example provided herein. Row hammer logic 790 includes: The memory device 740 Refresh potential victim rows via Rowhammer Logic 780 fruit line So that to surplus This allows the controller to send a refresh command.

[0086] In one example, memory module 770 represents a DIMM and includes registers (e.g., RDIMM, i.e., registered DIMM). In one example, memory module 770 includes multiple separately addressable buffers. In an RDIMM, the registers not only buffer the C / A bus but can also buffer the data lines. The command bus-specific PDA operations described herein can be utilized in system 700 with or without registers or buffers or registered clock devices.

[0087] Processor 710 represents a processing unit of a computing platform that may run an operating system (OS) and applications; processing units may collectively be referred to as hosts or users of memory. The OS and applications perform operations that result in memory accesses. Processor 710 may include one or more separate processors. Each separate processor may include a single processing unit, a multi-core processing unit, or a combination thereof. A processing unit may be a primary processor, such as a central processing unit (CPU), a peripheral processor, such as a graphics processing unit (GPU), or a combination thereof. Memory accesses may also be initiated by devices such as a network controller or hard disk controller. Such devices may be integrated with the processor in some systems or connected to the processor via a bus (e.g., PCI Express), or a combination thereof. System 700 may be implemented as a system-on-chip (SOC) or a standalone component.

[0088] References to memory devices can apply to various memory types. Memory devices often refer to volatile memory technology. Volatile memory is memory whose state (and the data stored in it) is indeterminate when power is removed from the device. Non-volatile memory is memory whose state is determinable even when power is removed from the device. Dynamic volatile memory requires the data stored in the device to be refreshed in order to maintain its state. An example of dynamic volatile memory is DRAM (dynamic random access memory) or some of its derivatives, such as synchronous DRAM (SDRAM). The memory subsystems described herein may be compatible with multiple memory technologies, such as DDR4 (DDR version 4, JESD79, initial specification published by JEDEC in September 2012), LPDDR4 (Low Power DDR version 4, JESD209-4, first published by JEDEC in August 2014), WIO2 (Wide I / O 2 (WideIO2), JESD229-2, first published by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235A, first published by JEDEC in November 2015), DDR5 (DDR version 5, currently under discussion by JEDEC), LPDDR5 (currently under discussion by JEDEC), HBM2 (HBM version 2, currently under discussion by JEDEC), or other or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications.

[0089] In one example, in addition to or alternatively to volatile memory, references to memory devices can refer to nonvolatile memory devices whose state is determined even when power to the device is interrupted. In one example, the nonvolatile memory device is a block-addressable memory device such as NAND or NOR technology. Thus, the memory device can also include next-generation nonvolatile devices such as three-dimensional cross-point memory devices, other byte-addressable nonvolatile memory devices, or memory devices using chalcogenide phase-change materials (e.g., chalcogenide glass). In one example, the memory device can be or include multi-threshold level NAND flash memory, NOR flash memory, single- or multi-level phase-change memory (PCM) or switched phase-change memory (PCMS), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory incorporating memristor technology, or spin-transfer torque (STT)-MRAM, or any combination of the above, or other memories.

[0090] References herein to "RAM" or "RAM device" may apply to any memory device that allows random access, whether volatile or nonvolatile. References to "DRAM" or "DRAM device" may refer to a volatile random access memory device. A memory device or DRAM may refer to the die itself, a packaged memory product that includes one or more dies, or both. In one example, a system with volatile memory that needs to be refreshed may also include nonvolatile memory.

[0091] The memory controller 720 represents one or more memory controller circuits or devices for the system 700. The memory controller 720 represents control logic that generates memory access commands in response to the execution of operations by the processor 710. The memory controller 720 accesses one or more memory devices 740. The memory devices 740 can be DRAM devices according to any of the above-mentioned methods. In one example, the memory devices 740 are organized and managed as different channels, each coupled to buses and signal lines that couple multiple memory devices in parallel. Each channel is independently operable. Thus, each channel is independently accessed and controlled, and timing, data transfer, command and address exchange, and other operations are separate for each channel. Coupling can refer to electrical coupling, communicative coupling, physical coupling, or a combination thereof. Physical coupling can include direct contact. Electrical coupling includes interfaces or interconnections that allow electrical flow between components, signal transmission between components, or both. Communicative coupling includes connections, including wired or wireless, that allow components to exchange data.

[0092] In one example, the settings for each channel are controlled by a separate mode register or other register setting. In one example, each memory controller 720 manages a separate memory channel, although system 700 can be configured to have multiple channels managed by a single controller or to have multiple controllers on a single channel. In one example, memory controller 720 is part of host processor 710, such as logic implemented on the same die or in the same package space as the processor.

[0093] The memory controller 720 includes I / O interface logic 722 for coupling to a memory bus, such as the memory channel mentioned above. The I / O interface logic 722 (as well as the I / O interface logic 742 of the memory device 740) may include pins, pads, connectors, signal lines, traces, or wires, or other hardware connecting devices, or a combination thereof. The I / O interface logic 722 may include a hardware interface. As shown, the I / O interface logic 722 includes at least drivers / transceivers for the signal lines. Typically, wires in an integrated circuit interface couple with pads, pins, or connectors to interface signal lines or traces or other wires between devices. The I / O interface logic 722 may include drivers, receivers, transceivers, or terminations, or other circuits or combinations of circuits, to exchange signals on the signal lines between devices. The exchange of signals includes at least one of sending or receiving. While shown coupling I / O 722 from memory controller 720 to I / O 742 of memory device 740, it will be understood that in implementations of system 700 where a group of memory devices 740 are accessed in parallel, multiple memory devices can include I / O interfaces to the same interface of memory controller 720. In implementations of system 700 that include one or more memory modules 770, I / O 742 can include interface hardware for the memory modules in addition to the interface hardware for the memory devices themselves. Other memory controllers 720 include separate interfaces to other memory devices 740.

[0094] The bus between the memory controller 720 and the memory devices 740 can be implemented as multiple signal lines coupling the memory controller 720 to the memory devices 740. The bus may typically include at least a clock (CLK) 732, a command / address (CMD) 734, write data (DQ) and read data (DQ) 736, and zero or more other signal lines 738. In one example, the bus or connection between the memory controller 720 and the memory can be referred to as a memory bus. The CMD signal line can be referred to as a “C / A bus” (or an ADD / CMD bus, or some other name indicating the transfer of command (C or CMD) and address (A or ADD) information), and the write and read DQ signal lines can be referred to as a “data bus.” In one example, independent channels have different clock signals, C / A buses, data buses, and other signal lines. Thus, the system 700 can be considered to have multiple “buses,” in the sense that independent interface paths can be considered separate buses. It will be understood that in addition to the lines explicitly shown, the bus can include at least one of a strobe signal line, an alert line, an auxiliary line, or other signal lines, or a combination thereof. It will also be understood that serial bus technology can be used for the connection between the memory controller 720 and the memory devices 740. One example of a serial bus technology is the transmission of high-speed data with 8B10B encoding and an embedded clock over a single differential pair signal in each direction. In one example, CMD 734 represents a signal line shared with multiple memory devices in parallel. In one example, multiple memory devices share the encoded command signal line of CMD 734 and each have a separate chip select (CS_n) signal line for selecting an individual memory device.

[0095] It will be appreciated that in the example system 700, the bus between the memory controller 720 and the memory devices 740 includes an auxiliary command bus CMD 734 and an auxiliary bus carrying write and read data DQ 736. In one example, the data bus may include bidirectional lines for read data and write / command data. In another example, the auxiliary bus DQ 736 may include a unidirectional write signal line for writing and data from the host to the memory, and a unidirectional line for reading data from the memory to the host. Depending on the selected memory technology and system design, other signals 738 may accompany the bus or sub-buses, such as a strobe line DQS. Depending on the design of the system 700, or the implementation if the design supports multiple implementations, the data bus may have more or less bandwidth per memory device 740. For example, the data bus may support memory devices with a x32 interface, a x16 interface, a x8 interface, or other interfaces. The W in the nomenclature "xW" is an integer that refers to the interface size or width of the interface of the memory device 740, representing the number of signal lines for exchanging data with the memory controller 720. The interface size of a memory device is a controlling factor for the number of memory devices that can be used simultaneously per channel in the system 700 or coupled in parallel to the same signal lines. In one example, high-bandwidth memory devices, wide-interface devices, or stacked memory configurations, or a combination thereof, can enable a wider interface, such as a x128 interface, a x256 interface, a x512 interface, a x1024 interface, or other data bus interface width.

[0096] In one example, the memory device 740 and memory controller 720 exchange data over the data bus in bursts, or a series of consecutive data transfers. A burst corresponds to a number of transfer cycles related to the bus frequency. In one example, a transfer cycle can be a full clock cycle of transfers occurring on the same clock or strobe signal edge (e.g., rising edge). In one example, all clock cycles, referring to cycles of a system clock, are divided into multiple unit intervals (UIs), with each UI being a transfer cycle. For example, double data rate transfers trigger on both edges of a clock signal (e.g., rising and falling). A burst can last for a configured number of UIs, which can be a configuration stored in a register or triggered on the fly. For example, a series of eight consecutive transfer periods can be considered a burst length of 8 (BL8), with each memory device 740 transferring data in each UI. Thus, a x8 memory device operating at BL8 can transfer 64 bits of data (8 data signal lines x 8 data bits transferred per line via bursts). It will be understood that this simple example is merely illustrative and not limiting.

[0097] The memory devices 740 represent memory resources of the system 700. In one example, each memory device 740 is a separate memory die. In one example, each memory device 740 can interface with multiple (e.g., two) channels per device or per die. Each memory device 740 includes I / O interface logic 742 with a bandwidth (e.g., x16 or x8 or some other interface bandwidth) determined by the device's implementation. The I / O interface logic 742 allows the memory device to interface with the memory controller 720. The I / O interface logic 742 can include a hardware interface and can be along the I / O 722 of the memory controller or at the end of the memory device. In one example, multiple memory devices 740 are connected in parallel to the same command and data bus. In another example, multiple memory devices 740 are connected in parallel to the same command bus and to different data buses. For example, the system 700 can be configured with multiple memory devices 740 coupled in parallel, each responding to commands and accessing its own internal memory resources 760. For a Write operation, each memory device 740 can write a portion of an entire data word, and for a Read operation, each memory device 740 can fetch a portion of an entire data word. As a non-limiting example, a particular memory device can provide or receive 8 bits of a 128-bit data word, or 8 or 16 bits of a 256-bit data word (depending on the x8 or x16 device), for a Read or Write transaction, respectively. The remaining bits of the word are provided or received in parallel by the other memory device.

[0098] In one example, memory device 740 is located directly on a motherboard of a computing device or host system platform (e.g., a PCB (printed circuit board) on which processor 710 is located). In one example, memory device 740 can be organized into memory module 770. In one example, memory module 770 represents a dual in-line memory module (DIMM). In one example, memory module 770 represents other organization of multiple memory devices that share at least a portion of access or control circuitry, which may be a separate circuit, separate device, or separate board from the host system platform. Memory module 770 can include multiple memory devices 740, and memory modules can include support for multiple separate channels to the contained memory devices located therein. In another example, memory device 740 can be incorporated in the same package as memory controller 720 by techniques such as multi-chip module (MCM), package-on-package, through silicon via (TSV), or other techniques or combinations thereof. Similarly, in one example, multiple memory devices 740 can be incorporated into memory module 770, which may itself be incorporated in the same package as memory controller 720. It will be understood that in these and other implementations, memory controller 720 may be part of host processor 710.

[0099] Each memory device 740 includes memory resources 760. Memory resources 760 represent memory locations or individual arrays of storage locations of data. Typically, memory resources 760 are managed as rows of data accessed via word line (row) and bit line (individual bits within a row) control. Memory resources 760 can be organized as separate channels, ranks, and memory banks. A channel may refer to an independent control path to storage locations within memory device 740. A rank may refer to a common location of multiple memory devices (e.g., the same row address in different devices). A bank may refer to an array of memory locations within memory device 740. In one example, a bank of memory is divided into sub-banks with at least some of the shared circuitry (e.g., drivers, signal lines, control logic) for the sub-banks to enable separate addressing and access. It will be understood that channels, ranks, banks, sub-banks, bank groups, or other organizations of memory locations, and combinations of these organizations, may overlap in application to physical resources. For example, the same physical memory location may be accessed through a particular channel as a particular bank, which may also belong to a rank. Thus, the organization of memory resources may be understood in an inclusive manner, rather than an exclusive manner.

[0100] In one example, memory device 740 includes one or more registers 744. Register 744 represents one or more storage devices or locations that provide configuration or settings for operation of the memory device. In one example, register 744 can provide memory device 740 storage locations that store data for access by memory controller 720 as part of control or management operations. In one example, register 744 includes one or more mode registers. In one example, register 744 includes one or more general-purpose registers. Configuration of locations in register 744 can configure memory device 740 to operate in different “modes,” and command information can trigger different operations in memory device 740 based on the mode. Additionally or alternatively, different modes can also trigger different operations from address information or other signal lines depending on the mode. Settings in register 744 can indicate configuration of I / O settings (e.g., timing, termination or ODT (on-die termination) 746, driver configuration, or other I / O settings).

[0101] In one example, the memory device 740 includes an ODT 746 as part of the interface hardware associated with the I / O 742. The ODT 746 can be configured as described above to provide an impedance setting applied to the interface to specific signal lines. In one example, the ODT 746 is applied to the DQ signal lines. In one example, the ODT 746 is applied to the command signal lines. In one example, the ODT 746 is applied to the address signal lines. In one example, the ODT 746 can be applied to any combination of the above. The ODT setting can be changed based on whether the memory device is the selected target or non-target device of an access operation. The ODT 746 setting can affect the timing and reflection of signaling on the termination lines. Careful control of the ODT 746 can improve the matching of the applied impedance and load, enabling high-speed operation. The ODT 746 can be applied to specific signal lines of the I / O interface 742, 722, but not necessarily to all signal lines.

[0102] The memory device 740 includes a controller 750, which represents control logic within the memory device for controlling internal operations within the memory device. For example, the controller 750 decodes commands sent by the memory controller 720 and generates internal operations to execute or satisfy the commands. The controller 750 may be referred to as an internal controller and is separate from the host's memory controller 720. The controller 750 may determine which mode is selected based on the register 744 and configure internal execution for operations to access memory resources 760 or other operations based on the selected mode. The controller 750 generates control signals that control the routing of bits within the memory device 740 to provide an appropriate interface for the selected mode and to send commands to the appropriate memory locations or addresses. The controller 750 includes command logic 752 that can decode command encodings received on the command and address signal lines. Thus, the command logic 752 may be or include a command decoder. The command logic 752 enables the memory device to identify commands and generate internal operations to execute the requested commands.

[0103] Referring again to memory controller 720, memory controller 720 includes command (CMD) logic 724, which represents logic or circuitry that generates commands to send to memory device 740. Command generation can refer to the preparation of a command prior to scheduling or a queued command ready to be sent. Generally, signaling in a memory subsystem includes address information within or accompanying a command to indicate or select one or more memory locations where the memory device should execute the command. In response to scheduling a transaction for memory device 740, memory controller 720 can issue a command via I / O 722 to cause memory device 740 to execute the command. In one example, controller 750 of memory device 740 receives and decodes command and address information received from memory controller 720 via I / O 742. Based on the received command and address information, controller 750 can control the timing of operation of logic and circuitry within memory device 740 to execute the command. Controller 750 is responsible for compliance with standards or specifications within memory device 740, such as timing and signaling requirements. The memory controller 720 may implement compliance with a standard or specification by scheduling and controlling access.

[0104] The memory controller 720 includes a scheduler 730, which represents logic or circuitry for generating and ordering transactions to send to the memory device 740. From one perspective, the primary function of the memory controller 720 can be said to be to schedule memory accesses and other transactions to the memory device 740. Such scheduling can include generating the transactions themselves to implement requests for data by the processor 710 and to maintain data integrity (e.g., with refresh-related commands). A transaction can include one or more commands, resulting in the transfer of commands, data, or both over one or more timing cycles, such as a clock cycle or unit interval. Transactions can be for accesses, such as reads or writes, or related commands, or combinations thereof, while other transactions can include memory management commands for configuration, settings, data integrity, or other commands or combinations thereof.

[0105] The memory controller 720 typically includes logic, such as a scheduler 730, that enables transaction selection and ordering to improve performance of the system 700. Thus, the memory controller 720 can select which of the outstanding transactions to send to the memory device 740 and in what order, which is typically achieved with logic that is much more complex than a simple first-in, first-out algorithm. The memory controller 720 manages the sending of transactions to the memory device 740 and manages the timing associated with the transactions. In one example, the transactions are managed by the memory controller 720 and have deterministic timing that can be used in determining how to schedule the transactions using the scheduler 730.

[0106] In one example, the memory controller 720 includes refresh (REF) logic 726. The refresh logic 726 can be used for memory resources that are volatile and need to be refreshed to maintain a deterministic state. In one example, the refresh logic 726 indicates the location of the refresh and the type of refresh to perform. The refresh logic 726 can trigger a self-refresh in the memory device 740 by sending a refresh command or a combination thereof, or perform an external refresh, which can be referred to as an auto-refresh command. In one example, the system 700 supports all-bank refreshes as well as per-bank refreshes. An all-bank refresh refreshes banks in all memory devices 740 coupled in parallel. A per-bank refresh refreshes a specific bank in a specific memory device 740. In one example, the controller 750 in the memory device 740 includes refresh logic 754 for applying refreshes in the memory device 740. In one example, the refresh logic 754 generates internal operations to perform refreshes according to the external refresh received from the memory controller 720. The refresh logic 754 can determine whether a refresh is directed to the memory device 740 and which memory resources 760 to refresh in response to the command.

[0107] 8 is a block diagram illustrating an example of a computing system in which host-assisted row hammer mitigation can be implemented. System 800 represents a computing device according to any example herein and may be a laptop computer, a desktop computer, a tablet computer, a server, a gaming or entertainment control system, an embedded computing device, or other electronic device. System 800 provides an example of a system according to system 100.

[0108] In one example, memory subsystem 820 includes row hammer logic 890, which represents row hammer logic that enables host-assisted row hammer mitigation according to any example herein. Row hammer logic may include logic within a memory device to manage row hammer mitigation internal to the memory device. In one example, row hammer logic 890 includes row hammer logic in memory controller 822 to provide host-assisted row hammer mitigation according to any example provided herein. Row hammer logic 890 may be configured to enable the controller to surplus refresh commands to enable memory 830 to perform refresh of potential victim rows based on the number of activate commands.

[0109] System 800 includes processor 810, which may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or combination thereof, to provide processing or execution of instructions for system 800. Processor 810 controls the overall operation of system 800 and may be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations of such devices.

[0110] In one example, system 800 includes an interface 812 coupled to processor 810, which can represent a high-speed or high-throughput interface for system components requiring a higher bandwidth connection, such as memory subsystem 820 or graphics interface component 840. Interface 812 represents interface circuitry, which can be a standalone component or can be integrated onto the processor die. Interface 812 can be integrated into the processor die as a circuit or as a component of a system-on-chip. When present, graphics interface 840 interfaces to the graphics component to provide a visual display to a user of system 800. Graphics interface 840 can be a standalone component or can be integrated into the processor die or system-on-chip. In one example, graphics interface 840 can drive a high-definition (HD) display that provides output to a user. In one example, the display can include a touchscreen display. In one example, graphics interface 840 generates a display based on data stored in memory 830, based on operations performed by processor 810, or both.

[0111] Memory subsystem 820 represents the main memory of system 800 and provides storage for code executed by processor 810 or data values ​​used in executing routines. Memory subsystem 820 may include one or more memory devices 830, such as read-only memory (ROM), flash memory, one or more random access memories (RAM) such as DRAM, or other memory devices, or a combination of such devices. Memory 830 stores and hosts, among other things, an operating system (OS) 832, providing a software platform for executing instructions in system 800. Additionally, applications 834 may execute on the OS 832's software platform in memory 830. Applications 834 represent programs having their own operating logic for performing the execution of one or more functions. Processes 836 represent agents or routines that provide auxiliary functionality to OS 832 or one or more applications 834, or a combination thereof. OS 832, applications 834, and processes 836 provide the software logic that provides functionality to system 800. In one example, memory subsystem 820 includes memory controller 822, which is a memory controller that generates and issues commands to memory 830. It will be understood that memory controller 822 can be a physical part of processor 810 or a physical part of interface 812. For example, memory controller 822 can be an integrated memory controller that is integrated into circuitry with processor 810, such as integrated into a processor die or a system-on-chip.

[0112] Although not specifically shown, it will be understood that system 800 can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, etc. A bus or other signal line can communicatively or electrically couple components to each other, or can couple components both communicatively and electrically. A bus can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuits, or combinations thereof. A bus can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or other buses, or combinations thereof.

[0113] In one example, system 800 includes interface 814, which can be coupled to interface 812. Interface 814 can be a slower interface than interface 812. In one example, interface 814 represents an interface circuit, which can include standalone components and integrated circuits. In one example, multiple user interface components and / or peripheral components are coupled to interface 814. Network interface 850 provides system 800 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 850 can include an Ethernet adapter, a wireless interconnection component, a cellular network interconnection component, a USB (Universal Serial Bus), or an interface based on other wired or wireless standards or a proprietary interface. Network interface 850 can exchange data with remote devices, which can include transmitting data stored in memory or receiving data stored in memory.

[0114] In one example, system 800 includes one or more input / output (I / O) interfaces 860. I / O interface 860 can include one or more interface components (e.g., voice, alphanumeric, haptic / touch, or other interfaces) through which a user interacts with system 800. Peripheral interface 870 can include any hardware interface not specifically mentioned above. Peripherals generally refer to devices that depend on system 800 for connectivity. A dependent connection is a connection provided by system 800 to a software platform, a hardware platform, or both, on which operations are performed and with which a user interacts.

[0115] In one example, system 800 includes a storage subsystem 880 for storing data in a nonvolatile manner. In one example, in a particular system implementation, at least certain components of storage 880 can overlap with components of memory subsystem 820. Storage subsystem 880 includes storage device(s) 884, which can be or can include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic disks, solid-state disks, or optical-based disks, or a combination thereof. Storage device 884 holds code or instructions and data 886 in a persistent state (i.e., values ​​are retained despite interruption of power to system 800). While storage device 884 can be generally considered to be “memory,” memory 830 is typically an execution or operating memory that provides instructions to processor 810. While storage device 884 is nonvolatile, memory 830 can include volatile memory (i.e., the value or state of the data is indeterminate if power is interrupted to system 800). In one example, storage subsystem 880 includes a controller 882 that interfaces with storage 884. In one example, controller 882 can be a physical part of interface 814 or processor 810, or can include circuitry or logic in both processor 810 and interface 814.

[0116] The power source 802 provides power to the components of the system 800. More specifically, the power source 802 typically interfaces with one or more power supplies 804 of the system 800 to provide power to the components of the system 800. In one example, the power supply 804 includes an AC-DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power can be a renewable energy (e.g., solar-powered) power source 802. In one example, the power source 802 includes a DC power source, such as an external AC-DC converter. In one example, the power source 802 or the power supply 804 includes wireless charging hardware for charging in proximity to a charging field. In one example, the power source 802 can include an internal battery or fuel cell power source.

[0117] 9 is a block diagram illustrating an example of a mobile device in which host-assisted row hammer mitigation can be implemented. System 900 represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wearable computing device, or other mobile device, or an embedded computing device. It will be understood that certain components are shown generically and that not all components of such a device are shown in system 900. System 900 provides an example of a system according to system 100.

[0118] In one example, memory subsystem 960 includes row hammer logic 990 representing row hammer logic that enables host-assisted row hammer mitigation according to any example herein for any memory 962 that requires refresh. Row hammer logic may include logic within a memory device to manage row hammer mitigation internal to the memory device. In one example, row hammer logic 990 includes row hammer logic in memory controller 964 to provide host-assisted row hammer mitigation according to any example provided herein. Row hammer logic 990 may be configured to enable the controller to surplusrefresh commands to enable memory 962 to perform refresh of potential victim rows based on the number of activate commands.

[0119] The device 900 includes a processor 910 that performs the primary processing operations of the system 900. The processor 910 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. The processing operations performed by the processor 910 include the execution of an operating platform or operating system on which applications and device functions run. The processing operations include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to connecting the system 900 to another device, or any combination thereof. The processing operations may also include operations related to audio I / O, display I / O, or other interfaces, or any combination thereof. The processor 910 may execute data stored in memory. The processor 910 may write or edit data stored in memory.

[0120] In one example, the system 900 includes one or more sensors 912. The sensors 912 represent embedded sensors or interfaces to external sensors, or a combination thereof. The sensors 912 enable the system 900 to monitor or detect one or more conditions of the environment or device in which the system 900 is implemented. The sensors 912 may include environmental sensors (such as temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide sensors, carbon dioxide sensors, or other chemical sensors)), pressure sensors, accelerometers, gyroscopes, medical or physiological sensors (e.g., biosensors for detecting physiological attributes, heart rate monitors, or other sensors), or other sensors, or combinations thereof. The sensors 912 may also include sensors for biometric systems, such as fingerprint recognition systems, face detection or recognition systems, or other systems that detect or recognize user characteristics. The term sensor 912 should be understood broadly and is not limiting of the many different types of sensors that can be implemented in the system 900. In one example, the one or more sensors 912 couple to the processor 910 via front-end circuitry integrated with the processor 910. In one example, one or more sensors 912 are coupled to the processor 910 through another component of the system 900 .

[0121] In one example, system 900 includes an audio subsystem 920 that represents hardware (e.g., audio hardware and circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to a computing device. Audio functionality may include a speaker or headphone output, as well as a microphone input. Devices for such functionality may be integrated into or connected to system 900. In one example, a user interacts with system 900 by providing voice commands that are received and processed by processor 910.

[0122] The display subsystem 930 represents hardware (e.g., display devices) and software components (e.g., drivers) that provide a visual display for presentation to a user. In one example, the display includes a tactile component or touchscreen element through which a user interacts with the computing device. The display subsystem 930 includes a display interface 932 that includes the particular screen or hardware device used to provide the display to the user. In one example, the display interface 932 includes logic separate from the processor 910 (such as a graphics processor) that performs at least some processing related to the display. In one example, the display subsystem 930 includes a touchscreen device that provides both output and input to the user. In one example, the display subsystem 930 includes a high-definition (HD) or ultra-high-definition (UHD) display that provides output to the user. In one example, the display subsystem includes or drives a touchscreen display. In one example, the display subsystem 930 generates display information based on data stored in memory, based on operations performed by the processor 910, or both.

[0123] I / O controller 940 represents hardware devices and software components related to interaction with a user. I / O controller 940 may operate to manage hardware that is part of audio subsystem 920 or display subsystem 930, or both. Additionally, I / O controller 940 represents connection points for additional devices that connect to system 900 through which a user can interact with the system. For example, devices that may connect to system 900 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices for use in specific applications, such as a card reader or other device.

[0124] As described above, I / O controller 940 can interact with audio subsystem 920 or display subsystem 930, or both. For example, input via a microphone or other audio device can provide input or commands to one or more applications or functions of system 900. Furthermore, audio output can be provided instead of or in addition to display output. In another example, if the display subsystem includes a touchscreen, the display device also functions as an input device that can be at least partially managed by I / O controller 940. Additional buttons or switches may also be present on system 900 to provide I / O functions managed by I / O controller 940.

[0125] In one example, I / O controller 940 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, gyroscopes, global positioning systems (GPS), or other hardware that may be included in system 900, or sensors 912. The inputs may be part of direct interaction with a user as well as providing the system with environmental inputs that affect the operation of the system (such as filtering noise, adjusting a display for brightness detection, applying a camera flash, or other functions).

[0126] In one example, system 900 includes power management 950 that manages functions related to battery power usage, battery charging, and power-saving operation. Power management 950 manages power from a power source 952 that provides power to components of system 900. In one example, power source 952 includes an AC-DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power can be renewable energy (e.g., solar power, motion-based power). In one example, power source 952 includes only DC power, which can be provided by a DC power source such as an external AC-DC converter. In one example, power source 952 includes wireless charging hardware for charging in proximity to a charging field. In one example, power source 952 can include an internal battery or a fuel cell power source.

[0127] The memory subsystem 960 includes memory device(s) 962 for storing information in the system 900. The memory subsystem 960 may include non-volatile memory devices (whose state does not change even when power is removed from the memory device) or volatile memory devices (whose state is indeterminate when power is removed from the memory device), or a combination thereof. The memory 960 may store application data, user data, music, photos, documents, or other data, as well as system data (both long-term and temporary) related to the execution of applications and functions of the system 900. In one example, the memory subsystem 960 includes a memory controller 964 (which may be considered part of the control of the system 900 and may be considered part of the processor 910). The memory controller 964 includes a scheduler that generates and issues commands that control access to the memory device 962.

[0128] The connectivity functionality 970 includes hardware devices (e.g., wireless or wired connectors and communications hardware, or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) to enable the system 900 to communicate with external devices. The external devices can also be separate devices, such as other computing devices, wireless access points or base stations, and peripherals such as headsets, printers, or other devices. In one example, the system 900 exchanges data with the external devices for storage in memory or for display on a display device. The exchanged data can include data to be stored in memory or data already stored in memory, for reading, writing, or editing data.

[0129] Connectivity function 970 can include multiple different types of connectivity functions. For generalization, system 900 is shown with cellular connectivity function 972 and wireless connectivity function 974. Cellular connectivity function 972 generally refers to cellular network connectivity functions provided by a wireless carrier, such as those provided via GSM (Global System for Mobile Communications) or variants or derivatives, CDMA (Code Division Multiple Access) or variants or derivatives, TDM (Time Division Multiplexing) or variants or derivatives, LTE (Long Term Evolution, also known as "4G"), or other cellular service standards. Wireless connectivity function 974 refers to non-cellular wireless connectivity functions and can include personal area networks (e.g., Bluetooth), local area networks (e.g., WiFi), wide area networks (e.g., WiMax), or other wireless communications, or combinations thereof. Wireless communications refers to the transfer of data through the use of modulated electromagnetic radiation over a non-solid medium. Wired communications occur over a fixed communications medium.

[0130] The peripheral connections 980 include hardware interfaces and connectors as well as software components (e.g., drivers, protocol stacks) for making the peripheral connections. It will be understood that the system 900 can be a peripheral device to other computing devices (“out” 982) or have peripheral devices connected to the system 900 (“from” 984). The device 900 typically has a “docking” connector for connecting to other computing devices for purposes such as managing (e.g., downloading, uploading, modifying, syncing) content on the system 900. Additionally, the docking connector can enable the system 900 to connect to certain peripherals that allow the system 900 to control content output to, for example, audiovisual or other systems.

[0131] In addition to dedicated docking connectors or other dedicated connection hardware, system 900 can provide peripheral connectivity 980 via common or standards-based connectors. Common types include Universal Serial Bus (USB) connectors (which can include any of several different hardware interfaces), DisplayPorts, including Mini DisplayPort (MDP), High-Definition Multimedia Interface (HDMI), or other types.

[0132] Generally, with respect to the description herein, in one example, a dynamic random access memory (DRAM) device includes a memory array having multiple rows of memory and input / output (I / O) hardware that receives commands from an associated memory controller, including multiple activation commands and multiple refresh commands, wherein in response to receiving a threshold number of activation commands, the memory controller sends excess refresh commands beyond the number of refresh commands necessary to refresh the multiple rows within a refresh window, and the DRAM device performs a row hammer refresh in response to the excess refresh commands to refresh potential victim rows of the potential aggressor rows.

[0133] In one example, threshold Value number Activation Reception is within a specific time window. threshold Value number Activation In one example, the threshold Value number Activation Reception has a sliding window, with each activation command incrementing the count and time decrementing the count. Threshold number Activate Command but , per channel or per rank, threshold Number of values Activate command In one example, the threshold number Activate command However, for each bank or bank group, threshold Number of values Activate command In one example, Extra Refresh Command teeth , Extra refresh commands Rouhanma Refresh is for The refresh command includes a tag indicating that the refresh command is

[0134] Generally, in the context of the present description, in one example, a memory controller may include a buffer for queuing commands for transmission to a memory device having multiple rows of memory; to a counter that tracks the number of activation commands, and I / O hardware for sending commands to a memory device, the commands including a plurality of activate commands and a plurality of refresh commands;Input / Output (I / O) Hardware in response to detecting a threshold number of activation commands, In the refresh window in exceeding the number of refresh commands required to refresh the rows. Extra Send a refresh command and R Fresh Commands teeth , memory devices but , run Rohanma refresh Submissive Potential attacks by Refresh potential victim rows Trigger .

[0135] In one example, Threshold number Activation Examination output within a specific time window Threshold number Activation of One example includes detecting Threshold number Activation Examination The output has a sliding window, where each activation command increments a counter and time decrements the counter. Threshold number Activate Command but , for each channel or rank of multiple memory devices including the memory device The threshold number of Activate Command of In one example, Threshold number Activate Command but , per bank or bank group of the memory device The threshold number of Activate Command of In one example, Extra Refresh Command teeth , Extra refresh commands Rouhanma Refresh It is for The refresh command includes a tag indicating:

[0136] Generally, in the context of the present description, in one example, a system includes a plurality of dynamic random access memory (DRAM) devices having a plurality of rows of memory, and a memory controller coupled to the plurality of DRAM devices, the memory controller toA memory controller including a counter that tracks the number of activate commands, and input / output (I / O) hardware that sends multiple commands to the memory device, including multiple activate commands and multiple refresh commands. and equipped , Threshold number The activate command Examination In response to the output, the I / O hardware in exceeding the number of refresh commands required to refresh the rows. Extra Send a refresh command, Extra The refresh command is used to 、 Run Rohanma Refresh hand , potential attack vectors by Refresh potential victim rows Trigger .

[0137] In one example, Threshold number Activation Examination output within a specific time window Threshold number Activation of One example includes detecting Threshold number Activation Examination The output has a sliding window, where each activation command increments a counter and time decrements the counter. Threshold number Activate Command but , per channel or per rank of the DRAM device The threshold number of Activate Command of In one example, Threshold number Activate Command but , per DRAM device The threshold number of Activate Command of In one example, Threshold number Activate Command but , per bank or bank group for a particular DRAM device The threshold number of Activate Command of In one example, Extra Refresh Command is an extra refresh command But Rohanma Refresh is forIn one example, the system includes one or more of a host processor device coupled to a memory controller, a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or a battery that powers the system.

[0138] The flow charts shown herein provide example sequences of various process actions. The flow charts may depict operations performed by software or firmware routines as well as physical operations. The flow charts may depict an example implementation of states of a finite state machine (FSM), which may be implemented in hardware and / or software. Although shown in a particular sequence or order, unless otherwise noted, the order of actions can be changed. Therefore, the illustrated diagrams should be understood as examples only, and processes can be performed in a different order and some actions can be performed in parallel. Additionally, one or more actions can be omitted, and therefore, not all implementations perform all actions.

[0139] To the extent that various operations or functions are described herein, they may be described or defined as software code, instructions, configurations, and / or data. Content may be directly executable ("object" or "executable" format), source code, or differential code ("delta" or "patch" code). The software content described herein may be provided via a product on which the content is stored or via a method of operating a communications interface to transmit data through the communications interface. A machine-readable storage medium can cause a machine to perform the described functions or operations and includes any mechanism for storing information in a form accessible by a machine (e.g., computing device, electronic system, etc.), such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communications interface includes any mechanism for interfacing with a hardwired, wireless, optical, or other medium for communicating with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communications interface may be configured to provide data signals describing software content by providing configuration parameters and / or sending signals that prepare the communications interface. The communications interface may be accessed via one or more commands or signals sent to the communications interface.

[0140] Various components described herein can be means for performing the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. A component can be implemented as a software module, a hardware module, dedicated hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), an embedded controller, a hardwired circuit, etc.

[0141] In addition to what is described herein, various modifications can be made to the disclosed content and implementations of the invention without departing from their scope. Accordingly, the illustrations and examples herein should be construed in an illustrative, rather than a limiting, sense. The scope of the invention should be measured solely by reference to the claims that follow. (Item 1) 1. A dynamic random access memory (DRAM) device comprising: a memory array having multiple rows of memory; Input / Output (I / O) hardware that receives commands from an associated memory controller, the commands including a plurality of activate commands and a plurality of refresh commands; in response to receiving a threshold number of activation commands. , in the refresh window in Beyond the number of refresh commands required to refresh the above multiple rows, Extra Refresh command Reception and the DRAM device is Extra In response to a refresh command, it performs a row hammer refresh. hand Potential aggressor row by Input / Output (I / O) hardware to refresh potential victim rows Equipped with DRAM devices. (Item 2) the above Threshold number Activation Receiving The signal is the number of times the above occurs within a specific time window. Threshold numberActivation of Item 1. The DRAM device of item 1, including receiving. (Item 3) Within the specified time window in The above Threshold number Activation Receiving 3. The DRAM device of item 2, wherein the signal has a sliding window, each activation command increments a count and time decrements the count. (Item 4) the above Threshold number Activate Command but , by channel or by rank The threshold number of Activate Command of Item 1. The DRAM device of item 1, comprising: (Item 5) the above Threshold number Activate Command but , per bank or per bank group The threshold number of Activate Command of Item 1. The DRAM device of item 1, comprising: (Item 6) the above Extra Refresh Command teeth , The extra refresh command above Rouhanma Refresh is for Item 10. The DRAM device of item 1, including a refresh command having a tag indicating that (Item 7) A memory controller, a buffer for queuing commands to be sent to a memory device having multiple rows of memory; a counter that tracks the number of activation commands to the memory device; Input / Output (I / O) hardware that sends commands to the memory device, the commands including a plurality of activation commands and a plurality of refresh commands; Threshold number The activate command Examination In response to the output, the I / O hardware in the above line exceeding the number of refresh commands required to refresh the Extra Send a refresh command and Extra A refresh command is issued to the memory device. B Perform Uhamma Refresh hand , potential attack vectors by Refresh potential victim rows Trigger , input / output (I / O) hardware and Equipped with a memory controller. (Item 8) the above Threshold number Activation Examination output, but the above within a specific time window Threshold number Activation of Item 8. The memory controller of item 7, including detecting (Item 9) Within the specified time window Threshold number Activation of Item 10. The memory controller of item 8, wherein detection has a sliding window, where each activation command increments a counter and time decrements the counter. (Item 10) the above Threshold number Activate Command but , for each channel or rank of multiple memory devices including the memory device The threshold number of Activate Command of Item 8. The memory controller of item 7, comprising: (Item 11) the above Threshold number Activate Command but , for each bank or bank group of the memory device The threshold number of Activate Command of Item 8. The memory controller of item 7, comprising: (Item 12) the above Extra Refresh Command teeth , The extra refresh command above Rouhanma Refresh is for 8. The memory controller of claim 7, further comprising a refresh command having a tag indicating (Item 13) 1. A system comprising: a plurality of dynamic random access memory (DRAM) devices having a plurality of memory rows; a memory controller coupled to the plurality of DRAM devices, the memory controller comprising: The above memory devices to a counter that tracks the number of activation commands; Input / Output (I / O) hardware that sends commands to the memory device, including activate commands and refresh commands; Threshold number In response to detecting an activate command, the I / O hardware in the above line exceeding the number of refresh commands required to refresh the Extra Send a refresh command and Extra The refresh command is used to 、 Run Rohanma Refresh hand , potential attack vectors by Refresh potential victim rows Trigger a memory controller, including input / output (I / O) hardware; A system that includes: (Item 14) the above Threshold number Activation Examination output is the above within a specific time window. Threshold number Activation of Item 14. The system of item 13, comprising detection. (Item 15) Within the specified time window Threshold number Activation of Item 15. The system of item 14, wherein the detection has a sliding window, where each activation command increments a counter and time decrements said counter. (Item 16) the above Threshold number Activate Command but , per channel or per rank of the DRAM device The threshold number of Activate Command ofItem 14. The system according to item 13, comprising: (Item 17) the above Threshold number Activate Command but , per DRAM device Threshold number Activate Command of Item 14. The system according to item 13, comprising: (Item 18) the above Threshold number Activate Command but , per bank or bank group of a particular DRAM device Threshold number Activate Command of Item 14. The system according to item 13, comprising: (Item 19) the above Extra Refresh Command teeth , Extra refresh commands Rouhanma Refresh is for Item 14. The system of item 13, including a refresh command having a tag indicating that (Item 20) a host processor device coupled to the memory controller; a display communicatively coupled to the host processor; a network interface communicatively coupled to the host processor; or A battery that powers the above system Item 14. The system of item 13, further comprising one or more of:

Claims

1. 1. A dynamic random access memory (DRAM) device comprising: a row of memory to be refreshed during normal operation; input / output (I / O) hardware that receives additional refresh commands during periods of high access to the row of memory as indicated by the number of activation commands received, the additional refresh commands being extra refresh commands beyond the number of refresh commands required to refresh the row of memory within a refresh window, the additional refresh commands providing additional refresh time for the DRAM device to internally manage refreshes, including internally indicating addresses for refresh; and Equipped with the I / O hardware receives the additional refresh command in response to a threshold number of activate commands within a sliding time window. DRAM device.

2. 2. The DRAM device of claim 1, wherein the I / O hardware receives the additional refresh commands in response to the threshold number of activate commands per bank.

3. 10. The DRAM device of claim 1 further comprising a refresh counter indicating the address of the row to be refreshed.

4. 4. The DRAM device of claim 1, wherein the additional refresh command includes a refresh command having a tag indicating that the additional refresh command is for a row hammer refresh.

5. 5. The DRAM device of claim 4, wherein the tag comprises unused bits of a refresh command encoding.

6. a counter in the DRAM device that tracks receipt of the activate command; The DRAM device of claim 1 , further comprising:

7. A memory controller, a buffer for queuing commands to be sent to a dynamic random access memory (DRAM) device having multiple rows of memory; input / output (I / O) hardware that sends additional refresh commands in response to sending a threshold number of activate commands to the DRAM device, the additional refresh commands being extra refresh commands beyond the number of refresh commands needed to refresh the multiple rows of memory within a refresh window, the additional refresh commands providing additional refresh time for the DRAM device to internally manage refreshes, including internally indicating addresses for refresh; and Equipped with The memory controller, wherein the threshold number of activation commands comprises the threshold number of activation commands within a sliding time window.

8. 8. The memory controller of claim 7, wherein the threshold number of activation commands comprises the threshold number of activation commands per bank.

9. 9. The memory controller of claim 7, wherein the additional refresh command includes a refresh command having a tag indicating that the additional refresh command is for a row hammer refresh.

10. a counter in the memory controller that tracks the sending of the activate command; The memory controller of claim 7 , further comprising:

11. A dynamic random access memory (DRAM) device according to any one of claims 1 to 6; a memory controller coupled to the DRAM device; A system comprising:

Images