Dynamic Address Translation Protection Reset Instruction

Abstract

Instructions are provided that, when executed, perform an address translation protection reset operation. Executing the instructions includes determining, by the processor, to reset an address translation protection bit in a particular translation table entry associated with the storage block. Based on the determination to reset the address translation protection bit, executing the instructions includes resetting the address translation protection bit to disable write protection for the storage block. The reset occurs without waiting for action by one or more other processors of the computing environment.

Description

[Technical Field]

[0001] One or more aspects relate generally to facilitating processing within a computing environment, and more particularly to improving such processing. [Background technology]

[0002] Computer architectures typically provide mechanisms for operating system (OS) programs to activate and deactivate write protection for blocks of storage. In such cases, the memory management provided by the operating system may, in one or more embodiments, include a sequence of events, such as the operating system activating write protection for a particular storage block and, when an application program attempts to write to the particular storage block, the processor or central processing unit (CPU) blocking the write and notifying the operating system of the write attempt. In response, the operating system performs appropriate memory management actions to deactivate write protection for the particular storage block. The application program then attempts to write to the particular storage block again, and this time the operation is allowed.

[0003] When the operating system changes the write permissions for a storage block, all processors in the computing environment are notified of the change via a broadcast operation. Each processor then takes action to ensure that the change is observed locally. The required broadcast and serialization process among all processors in the computing environment is called a quiescing operation. As part of the quiescing operation, each processor must reach an interruptible point, perform any necessary local actions to ensure that the change is observable (e.g., remove unused translation lookaside buffer (TLB) data), and acknowledge this to the initiating processor. All instruction processing that may depend on the updated permissions is suspended until all processors in the configuration have acknowledged their acknowledgement and the initiator has performed a system-wide update to the write permissions for the particular storage block.

[0004] The sequence of events described can occur during frequent memory management operations such as copy-on-write and change-tracking. The more processors in a computing environment, the longer it takes to perform a quiesce operation. Summary of the Invention

[0005] Shortcomings of the prior art are overcome and further advantages are achieved through the provision of a computer program product for facilitating processing within a computing environment. The computer program product includes at least one computer-readable storage medium having program instructions embodied thereon. The program instructions are readable by a processor and cause the processor to perform a method including executing instructions to perform an address translation protection reset operation. Executing the instructions includes determining, by the processor, to reset an address translation protection bit in a particular translation table entry associated with a storage block, and, based on the determination, resetting the address translation protection bit to disable write protection for the storage block. The reset occurs without waiting for action by one or more other processors of the computing environment. By performing the reset without waiting for action by other processors of the computing environment, the instructions are used to improve performance.

[0006] In one or more embodiments, executing the instruction includes terminating execution of the instruction based on resetting the address translation protection bit to disable write protection for the storage block without requiring a quiesce operation by the one or more other processors of the computing environment. Note that a quiesce operation in this context typically requires serialization among all processors in the computing environment. Because a quiesce operation is avoided, serialization among processors is not required to disable write protection for the storage block using an instruction. This reduces interruptions to instruction processing by other processors in the computing environment, improving performance. Furthermore, contention of quiesce serialization mechanisms within the system is reduced. The instruction provides an operating system with the option to disable write protection for a storage block without requiring serialization among all processors in the computing environment to respond to the change. Furthermore, the instruction that performs the address translation protection reset operation is a single instruction that performs a decision operation and a reset operation, improving performance and reducing resource usage. By providing a single instruction that performs a decision operation and a reset operation, certain tasks can be performed more efficiently than using a software paradigm. Decision and reset operations are performed faster, reducing execution time and improving processor and overall system performance.

[0007] In one example, executing the instructions further includes clearing a translation lookaside buffer entry within the processor associated with the translation table entry. In another example, executing the instructions further includes resetting a protection indication for a translation lookaside buffer entry within the processor associated with the particular translation table entry. Advantageously, rather than clearing the translation lookaside buffer entry, the processor can simply reset the protection indication within the entry and leave the remainder of the entry intact. This allows writes to continue and complete without requiring address retranslation to reconstruct the necessary translation lookaside buffer entry.

[0008] In one or more implementations, executing the instruction further includes broadcasting a signal to one or more other processors in the computing environment to clear or modify a translation lookaside buffer entry in the one or more other processors associated with the particular translation table entry. In one example, executing the instruction further includes testing the address translation protection bit in the particular translation table entry associated with the storage block, the broadcasting being based at least in part on a result of the test. Using an address translation protection reset instruction to perform the determination, reset, and broadcast operations improves performance and reduces resource utilization.

[0009] In one or more embodiments, another processor of the one or more other processors in the computing environment attempts a write access to the storage block without clearing or modifying the other processor's associated translation lookaside buffer entry, resulting in an address translation protection exception condition. Based on the address translation protection exception condition, the other processor checks the address translation protection bits to identify that the address translation protection exception condition is an over-indication, and write access to the storage block is granted based on the check identifying that the address translation protection exception condition is an over-indication. Advantageously, checking the address translation protection bits to identify that the address translation protection exception condition is an over-indication may allow access, thereby improving processing performance in this situation by avoiding the need for an operating system program interrupt handler.

[0010] In one or more embodiments, another processor of the one or more other processors in the computing environment attempts a write access to the storage block without clearing or modifying the other processor's associated translation lookaside buffer entry, resulting in an address translation protection exception condition. Based on the address translation protection exception condition, the other processor examines the address translation protection bits to identify that the address translation protection exception condition is over-indicated, and based on the examination identifying that the address translation protection exception condition is over-indicated, the other processor clears or modifies the other processor's associated translation lookaside buffer entry that includes the over-indicated address translation protection bit. Advantageously, examining the address translation protection bits to identify that the address translation protection exception condition is over-indicated can improve processing performance in this situation by allowing the write access to proceed.

[0011] In one or more embodiments, another processor of the one or more other processors attempts a write access to the storage block without clearing or modifying the other processor's associated translation lookaside buffer entry, resulting in an address translation protection exception condition, and based on that, the other processor reports the exception condition to an operating system of the computing environment. Based on the reporting of the exception condition, the operating system issues an instruction to the other processor to perform the address translation protection reset operation at the other processor of the one or more other processors. Advantageously, the instruction to perform the address translation protection reset operation can provide the operating system with the option to easily disable write protection for the storage block without requiring a quiesce operation among all processors of the computing environment in response to the change.

[0012] Computer systems and computer-implemented methods relating to one or more aspects are also described and claimed herein. Additionally, services relating to one or more aspects may also be described and claimed herein.

[0013] Additional features and advantages are realized by the techniques described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects.

[0014] One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the end of this specification. The foregoing, together with objects, features, and advantages of one or more aspects, will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0015] [Figure 1A] FIG. 1 illustrates an example of a computing environment that incorporates and uses one or more aspects of the present invention. [Figure 1B] FIG. 1B illustrates further details of the processor of FIG. 1A in accordance with one or more aspects of the present invention. [Figure 2A] FIG. 2 illustrates an example of address translation and address translation protection bits being reset in accordance with one or more aspects of the present invention. [Figure 2B] FIG. 10 illustrates another example of address translation and address translation protection bits being reset in accordance with one or more aspects of the present invention. [Figure 2C] FIG. 2 illustrates one embodiment of an address translation lookaside buffer in accordance with one or more aspects of the present invention. [Figure 3] 10A-10E illustrate an example format of a dynamic address translation protection reset instruction according to one or more aspects of the present invention. [Figure 4A] FIG. 1 illustrates one embodiment of a process associated with executing a dynamic address translation protection reset instruction in accordance with one or more embodiments of the present invention. [Figure 4B] FIG. 10 illustrates another embodiment of a process associated with executing a dynamic address translation protection reset instruction in accordance with one or more embodiments of the present invention. [Figure 5A] FIG. 1 illustrates one embodiment of a workflow illustrating certain aspects of one or more embodiments of the present invention. [Figure 5B] FIG. 1 illustrates one embodiment of a workflow illustrating certain aspects of one or more embodiments of the present invention. [Figure 5C] FIG. 1 illustrates one embodiment of a workflow illustrating certain aspects of one or more embodiments of the present invention. [Figure 6A] FIG. 1 illustrates an example of facilitating processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 6B] FIG. 1 illustrates an example of facilitating processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 7A] FIG. 1 illustrates another example of a computing environment that incorporates and uses one or more aspects of the present invention. [Figure 7B]FIG. 7B illustrates an example of further memory details for the computing environment of FIG. 7A in accordance with one or more aspects of the present invention. [Figure 7C] FIG. 7B illustrates another example of further memory details for the computing environment of FIG. 7A in accordance with one or more aspects of the present invention. [Figure 8A] FIG. 1 illustrates yet another example of a computing environment incorporating and using one or more aspects of the present invention. [Figure 8B] FIG. 8B illustrates further details of the memory of FIG. 8A in accordance with one or more embodiments of the present invention. [Figure 9] FIG. 1 illustrates an embodiment of a cloud computing environment in accordance with one or more aspects of the present invention. [Figure 10] FIG. 2 illustrates an example of an abstraction model layer in accordance with one or more aspects of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] According to one aspect of the present invention, functionality is provided to facilitate processing within a computing environment. As one example, a single instruction (e.g., a single architected machine instruction at a central processing unit / software interface) is provided to perform a reset operation. This instruction, referred to herein as the reset dynamic address translation protection instruction, or the address translation protection reset instruction, is part of a general-purpose processor instruction set architecture (ISA) and is dispatched by a program on a processor, such as a general-purpose processor (in another example, this instruction may be part of a special-purpose processor, such as a coprocessor configured for a specific function).

[0017] As part of the execution of a single instruction (e.g., a dynamic address translation protection reset instruction), various operations are performed. These operations include determining, by the processor, to reset an address translation protection bit in a particular translation table entry associated with a storage block, and, based on the determination, resetting the address translation protection bit and disabling write protection for the storage block. Here, the reset operation and instruction execution are independent of related operations of one or more other processors in the computing environment. For example, resetting write protection for a storage block in a processor occurs without or requiring a quiesce operation by one or more other processors in the computing environment. Each of these operations is performed as part of the execution of the single instruction. This improves system performance and reduces system resource usage.

[0018] As discussed above, computing environments, or computer architectures, typically provide a process or sequence of events by which an operating system (OS) program selectively enables and / or disables write protection for one or more blocks of storage. Memory management provided by an operating system typically involves the following sequence of events: 1) the operating system enables write protection for a particular storage block, 2) an application program attempts to write to that particular storage block and a processor or central processing unit (CPU) notifies the OS of the attempted write access, 3) the OS performs appropriate memory management reaction actions and disables write protection for that particular storage block, and 4) the application program again attempts to write to that particular storage block, and this time the operation is allowed.

[0019] When an OS changes write permissions to a storage block, all processors in a computing configuration or environment traditionally receive notification and take relevant action to ensure the change is honored. The process of broadcasting and serialization required for such a change is referred to as a quiesce operation among processors in the computing environment. As part of the quiesce operation, after each processor responds to the change, each processor suspends instruction processing until all processors in the computing configuration indicate they have responded.

[0020] The sequence of events described occurs during frequent memory management operations, such as copy-on-write and change tracking. Furthermore, the greater the number of processors or CPUs in a computing environment, the longer it takes to perform a quiesce operation. Therefore, eliminating the quiesce operation reduces the time required for the computing configuration to respond to this common write permission change, improving the performance of these operations and accelerating processing within the computing environment. Furthermore, the serialization requirements of the quiescing hardware make these resources limited within the system. In this case, eliminating the need for quiescing also reduces the system-wide constraints experienced by this hardware.

[0021] Advantageously, the address translation protection reset instruction disclosed herein may provide an option for an OS to disable write protection for a storage block without requiring serialization between processors or CPUs as part of the computing configuration's response to the change. The change is applied to the processor executing the write protection disable instruction (i.e., information based on the previous (protection-enabled) table entry is cleared from the processor's translation lookaside buffer (TLB)). The change may then be applied to one or more other processors (e.g., all other processors) in the computing configuration, or none of them. If the OS chooses to use the address translation protection reset instruction operation, the OS understands that another processor may still report a write protection violation, i.e., address translation protection exception conditions, for the particular storage block. In such a case, the OS may recognize this as an over-indication and may disable write protection for the storage block on the processor that indicated the violation (by clearing or modifying the TLB of this (second) processor). In one or more embodiments, an OS may use the address translation protection reset instruction provided herein, for example, when it is unlikely that other processors in a computing configuration are also accessing a particular storage block. Because execution of the address translation protection reset operation does not require serialization between processors, disruption of instruction processing by other processors in the computing environment is reduced, resulting in improved performance.

[0022] One embodiment of a computing environment incorporating and using one or more aspects of the present invention is described with reference to FIG. 1A. By way of example, the computing environment is based on the z / Architecture® instruction set architecture (manufactured by International Business Machines Corporation, Armonk, New York). One embodiment of the z / Architecture instruction set architecture is described in the publication entitled “z / Architecture Principles of Operation” (IBM Publication No. SA22-7832-12, 13th Edition, September 2019), which is incorporated herein by reference in its entirety. However, the z / Architecture instruction set architecture is merely an example, and other architectures and / or types of computing environments from International Business Machines Corporation and / or other entities may include and / or use one or more aspects of the present invention. Note that z / Architecture and IBM are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction.

[0023] 1A, a computing environment 100 includes, for example, a computer system 102. The computer system 102 is illustrated, for example, as a general-purpose computing device. The computer system 102 may include, but is not limited to, one or more processors or processing units 104 (e.g., central processing units (CPUs)), memory 106 (also referred to as, for example, system memory, main memory, main storage, central storage, or storage), and one or more input / output (I / O) interfaces 108 coupled together via one or more buses and / or other connections 110.

[0024] The memory 106 may include a cache 112, such as a shared cache that can be coupled to a local cache 114 of the processor 104. Additionally, the memory 106 may include one or more programs or applications 116 and at least one operating system 118. One example of an operating system is the z / OS® operating system (manufactured by International Business Machines Corporation, Armonk, New York). z / OS is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Other operating systems provided by International Business Machines Corporation and / or other entities may also be used. The memory 106 may also include one or more computer-readable program instructions 120 that can be configured to perform functions of embodiments of aspects of the present invention.

[0025] The computer system 102 may communicate with one or more external devices 130, such as a user terminal, a tape drive, a pointing device, a display, and one or more data storage devices 134, for example, via an I / O interface 108 (e.g., a Peripheral Component Interconnect (PCI) or other I / O interface connection, or both). The data storage devices 134 may store one or more programs 136, one or more computer-readable program instructions 138, or data, or a combination thereof. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0026] The computer system 102 may also communicate with a network interface 132, for example, via the I / O interface 108. This enables the computer system 102 to communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, to facilitate communication with other computing devices or systems.

[0027] Computer system 102 may include, be coupled to, or both removable and non-removable, volatile and non-volatile computer system-readable media. For example, computer system 102 may include, be coupled to, or both non-removable, non-volatile magnetic media (commonly referred to as a "hard drive"), a magnetic disk drive for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), or an optical disk drive for reading from and writing to removable, non-volatile optical disks (e.g., CD-ROMs, DVD-ROMs, or other optical media). It should be noted that other hardware and / or software components may be used with computer system 102. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data archive storage systems, etc.

[0028] Computer system 102 may operate with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, suitable for use with computer system 102 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0029] As an example, a processor (e.g., processor 104) includes multiple functional components used to execute instructions. As shown in FIG. 1B , these functional components include, for example, an instruction fetch component 150 that fetches instructions to be executed, an instruction decode unit 152 that decodes the fetched instructions and obtains operands for the decoded instructions, one or more instruction execution components 154 that execute the decoded instructions, a memory access component 156 that accesses memory as needed for instruction execution, and a write back component 158 ​​that provides results of the executed instructions. One or more of the components may access and / or use one or more registers 160 in instruction processing. Furthermore, one or more of the components may include at least a portion of or have access to one or more other components used in executing a reset operation in accordance with one or more aspects of the present invention, for example, of a dynamic address translation protection reset instruction described herein (or other processing capable of using one or more aspects of the present invention). These one or more other components may include, for example, an address translation protection reset component (or one or more other components) 170.

[0030] The computing environment described herein supports architectural features such as dynamic address translation (DAT). With appropriate support from the operating system, the dynamic address translation feature can be used to present a user with a system that appears to have more storage than the main storage (also known as main memory) available in the configuration. This apparent main storage is referred to as virtual storage, and addresses used to specify locations within virtual storage are referred to as virtual addresses. The user's virtual storage may far exceed the size of the main storage available in the configuration and is typically maintained in auxiliary storage (e.g., storage that is not directly addressable). Virtual storage can be thought of as consisting of blocks of addresses called pages. Only the most recently referenced pages of virtual storage are allocated to blocks of physical main storage (e.g., random access memory (RAM)). When a user references pages in virtual storage that are not in main storage, these pages are replaced with pages in main storage that are less likely to be needed. The swapping of storage pages may be performed by the operating system without the user's knowledge.

[0031] Furthermore, in a virtual computing environment, an interpretive execution architecture provides a storage mode for absolute storage called pageable storage mode. Pageable storage mode uses dynamic address translation at the host level to map the guest's main storage. The host has the ability to distribute guest real storage in pageable storage mode to available frames anywhere in the host real storage using the host DAT and to page out guest data to auxiliary storage. This technique can provide flexibility in allocating real machine resources while maintaining the expected view of a contiguous range of absolute storage for the guest.

[0032] A virtual machine environment may require the application of a DAT multiple times: first at the guest level to translate guest virtual addresses to guest non-virtual addresses through guest-managed translation tables, and then, for pageable guests, at the host level to translate corresponding host virtual addresses (i.e., guest non-virtual addresses) to host non-virtual addresses, such as host real or absolute addresses.

[0033] A sequence of virtual addresses associated with virtual storage is called an address space, and dynamic address translation can be used to provide multiple address spaces. These address spaces can be used to provide degrees of isolation between users. Such support can include completely different address spaces for each user, thereby providing complete isolation. Alternatively, a shared area can be provided by mapping portions of each address space into a single common storage area. Instructions are also provided that allow semi-privileged programs to access two or more such address spaces. Dynamic address translation allows, for example, the translation of virtual addresses from multiple different address spaces without changing translation parameters in control registers.

[0034] Dynamic address translation is the process of converting a virtual address to a corresponding real or absolute address during storage reference. Dynamic address translation can be specified for instruction and data addresses generated by the CPU. The real or absolute addresses formed by dynamic address translation, and the absolute addresses formed subsequently by prefixing, are 64 bits long in one embodiment. A virtual address may be a primary virtual address, a secondary virtual address, an access register (AR)-directed virtual address, or a home virtual address. The address is translated by the primary, secondary, AR-directed, or home address space control element (ASCE), respectively. After the appropriate address space control element is selected, the translation process is identical for all four types of virtual addresses. The address space control element may be a segment table designation or a region table designation. The segment table designation or region table designation causes the translation to be performed by a table established by the operating system in real or absolute storage.

[0035] The translation process when using segment table or region table designations recognizes three types of information units: region, segment, and page. Accordingly, the virtual address is divided into four fields. As an example, bits 0-32 are called the region index (RX), bits 33-43 are called the segment index (SX), bits 44-51 are called the page index (PX), and bits 52-63 are called the byte index (BX). The RX portion of the virtual address is itself divided into three fields. In one embodiment, bits 0-10 are called the region first index (RFX), bits 11-21 are called the region second index (RSX), and bits 22-32 are called the region third index (RTX).

[0036] Referring to FIG. 2A, an example of translating a virtual address into a real address is described. This process, referred to herein as a DAT walk (or page walk), involves walking an address translation table to translate one address (e.g., a virtual address) into another address (e.g., a real address). In this example, an address space control element (ASCE) 200 includes a table origin 202 and a designation type (DT) control 204, which indicates the starting level of the translation (i.e., the level in the hierarchy at which the address translation begins). The table origin 202 and DT 204 are used to locate the origin of a particular table. Next, based on the table, bits of the virtual address are used as an index into the particular table to obtain the origin of the next level table. For example, if a region first table (RFT) 206 is selected, bits 0-10 (RFX) 208 of the virtual address are used to index into the region first table to obtain the origin of a region second table (RST) 210. Next, bits 11-21 (RSX) 212 of the virtual address are used to index into region second table 210 to obtain the origin of region third table (RTT) 214. Similarly, bits 22-32 (RTX) 216 of the virtual address are used to index into region third table 214 to obtain the origin of segment table 218. Next, bits 33-43 (SX) 220 of the virtual address are used to index into segment table 218 to obtain the origin of page table 222. Then, bits 44-51 (PX) 224 of the virtual address are used to index into page table 222 to obtain page table entry (PTE) 225, which has page frame real address (PFRA) 226. Next, the page frame real address is combined (e.g., concatenated) with offset 228 (bits 52-63) to obtain the real address. Prefix translation may then be applied to obtain the corresponding absolute address.

[0037] In one embodiment, one or more translation table entries, such as page table 222, include an address translation protection bit P, which can be used to control write access to one or more storage blocks associated with the translation table entry. When the bit is a first value, e.g., "0," write protection for the storage block is disabled, and when the bit is a second value, e.g., "1," write protection for the storage block is enabled. For example, when the address translation protection bit is set, it indicates that address translation protection applies to a particular page, e.g., in the context of the page table entry (for a segment table entry, the address translation protection bit controls whether write access is possible to the entire segment). In one embodiment, this bit does not affect fetch accesses, only write accesses. When the protection bit is "0" (in one embodiment), write accesses are allowed, and when the bit is "1," write accesses are prohibited.

[0038] Referring to FIG. 2B, another example of address translation is described. In this example, a DAT walk is performed to translate an initial guest virtual address to a final host real address. In this example, address space control element (ASCE) 200 is a guest address space control element, and DT 204 of ASCE 200 indicates that the guest translation determined by guest address translation structure 260 begins at region first table 206, pointed to by table origin 202. Therefore, appropriate bits of the initial guest virtual address (e.g., RFX 208) are used to index into region first table 206 to obtain a pointer to an entry in the region first table. The address of the region first table entry (RFTE) is a guest real address or absolute address. This guest real address or absolute address, subject to main storage origin and limit, corresponds to a host virtual address. This intermediate host virtual address is then translated using host address translation structure 270. In particular, address space control element (ASCE) 250 is a host address space control element used to indicate the starting level of translation in host address translation structure 272. Based on the starting level (e.g., region first table) indicated by DT 254 of ASCE 250, as described with reference to Figure 2A, certain bits of the host virtual address are used to index into a table indicated by table origin 252, which is used for translation using host address translation structure 272. Translation of the host virtual address corresponding to the guest RFTE continues until a host page frame real address (PFRA) 274a is obtained.

[0039] The data in the intermediate host page frame real address is a pointer to the next level of the guest address translation structure (e.g., in this particular example, guest region second table 210), and the translation continues as described above. Specifically, host address translation structures 276, 278, 280, and 282 are used to translate the intermediate host virtual addresses associated with guest region second table 210, region third table 214, segment table 218, and page table 222, respectively, to obtain host PFRAs 274b, 274c, 274d, and 274e, respectively. Host page frame real address 274e includes the address of guest page table entry 225. Guest page table entry 225 includes guest page frame real address 226. Guest page frame real address 226 is concatenated with an offset from the initial guest virtual address to obtain the corresponding guest absolute address. Next, the main storage origin and limit are applied to calculate the corresponding host virtual address, which is then translated using address translation structure 284 as described above to obtain host page frame real address 274f. The host page frame real address is then combined (e.g., concatenated) with the host virtual address's offset (e.g., bits 52-63) to obtain the final host real address. This completes the translation of the guest virtual address to a host real address.

[0040] In the above example, the translation begins at the region first table, but this is merely an example. The translation can begin at any region or segment table level, either in the guest or the host. It should also be noted that, as part of one or more translation table entries, such as the region second table, region third table, segment table, or page table, an address translation protection bit P can be included in the table entry and referenced during processing of a write access to one or more associated storage blocks to determine whether the write access is allowed to proceed. If the address translation protection bit is a first value (e.g., “0”), the write access to the one or more storage blocks is permitted, and if the address translation protection bit is a second value (e.g., “1”), write protection is enabled for the one or more storage blocks, and the write access is prohibited.

[0041] Furthermore, in one embodiment, to improve address translation, the translation mapping from virtual addresses to real or absolute addresses can be stored in entries in a structure associated with address translation, such as a translation lookaside buffer (TLB). A TLB is a cache used by memory management hardware to improve virtual address translation speed. The next time a translation of a virtual address is requested, the TLB is checked, and if a corresponding entry exists in the TLB, there is a TLB hit and the real or absolute address is obtained from there. Otherwise, a page walk is performed as described above.

[0042] As shown in FIG. 2C , in one example, translation lookaside buffer 290 can include one or more entries 292. A given translation lookaside buffer entry can include an address translation protection bit P 296. The address translation protection bit P 296 can be used to control write access to one or more storage blocks associated with the translation table entry, as described herein. Additionally, a TLB entry may be associated with a region table entry, a segment table entry, or a page table entry of the address translation table. In one or more embodiments, region table entries and segment table entries can also have protection bits in addition to the address translation protection bit P in the page table entry. In the translation lookaside buffer, all address translation protection bits P are ORed to translate from a guest (or virtual) address to a real address. An entry may be for the host or guest (or both) of a computing environment and may be marked as such by an indicator (e.g., H / G indicator 294). For example, if H / G 294 is set to 1, the entry is a host entry, and if set to 0, the entry is a guest entry. Or vice versa. In some embodiments, both guest-level and host-level translations are performed in order, each progressing through these table levels, and the protection bits from all guest-level and host-level table entries are ORed together to form the protection bits for the composite translation lookaside buffer entry. Many implementations of the translation lookaside buffer are possible.

[0043] As shown here, guest translations can be included in the TLB. These entries may be combined guest / host entries that implicitly include one or more host translations. For example, a guest virtual TLB entry may buffer the entire translation from an initial guest virtual address to a final host real or absolute address. In this case, as described above in FIG. 2B, the guest TLB entry implicitly includes all intermediate host translations 272, 276, 278, 280, and 282, as well as the final host translation 284. In another example, a hierarchical TLB may include a first-level entry in the TLB that buffers the translation from an initial guest virtual address to an associated origin in guest page table 222. This first-level entry, for example, may represent a combined region and segment table entry (CRSTE), and may be referred to as the CRSTE portion of the TLB. Furthermore, a hierarchical TLB may include a separate entry from a second level of the TLB that buffers the translation from a guest page table entry address to a final host real or absolute address. In this example, as described in Figure 2B, guest entries in the first level of the TLB implicitly contain intermediate host translations 272, 276, 278, and 280 corresponding to host translations that back the guest's region and segment tables, and guest entries in the second level implicitly contain intermediate host translations 282 that back the guest page tables and final host translation 284. Translation lookaside buffers have many possible implementations.

[0044] According to one aspect of the present invention, an instruction, referred to herein as a dynamic address translation protection reset instruction, DAT protection reset instruction, or address translation protection reset instruction, is provided for execution by a processor or CPU executing the instruction, as part of executing a single instruction, to determine to reset an address translation protection bit in a particular translation table entry associated with a storage block, and, based on the determination to reset the protection bit, reset the address translation protection bit to disable write protection for the storage block. The reset occurs without or requiring a quiesce operation by other processors in the computing environment. In one or more embodiments, executing the instruction is based on attempted write access to the storage block, which write access was blocked by the address translation protection bit in the particular translation table entry prior to executing the instruction. Furthermore, executing the instruction may include terminating execution of the instruction based on resetting the address translation protection bit to disable write protection for the storage block without waiting for associated action by one or more other processors in the computing environment. In this manner, a processor executing an address translation protection reset instruction proceeds independently of associated processing in one or more other processors in the computing environment.

[0045] An operating system may enable and / or disable address translation protection exceptions for one or more blocks of storage, for example, as part of a copy-on-write operation or tracking changes to a particular storage location. As described above, the address translation protection bits of the appropriate translation table entries specify when an address translation protection exception condition exists. Existing methods for modifying address translation protection generally involve a quiesce operation involving all other processors in a computing environment. As previously described, in one or more embodiments, an address translation protection reset instruction is provided herein, the execution of which provides a mechanism to clear the address translation protection bits of translation table entries, clear or modify local copies of associated TLB entries, and, if necessary, broadcast the changes to other CPUs in the configuration, when appropriate, without requiring the serialization component of the quiesce operation. In this manner, the address translation protection reset operation of the present disclosure provides improved performance compared to typical approaches that require quiesce operations between processors in a computing environment for the reset operation to proceed and complete. Furthermore, the address translation protection reset operation of the present disclosure may prevent the consumption of limited system-wide quiesce operation resources, freeing up resources for other operations.

[0046] As described above, the address translation protection bit (e.g., the DAT protection bit) of the specified translation table entry is set to or verified to be 0 as part of the dynamic address translation protection reset instruction execution. In addition, the associated translation lookaside buffer entry in the processor or CPU executing the instruction is cleared or modified. If the local clearing control is 0, the associated translation lookaside buffer entries in other processors in the computing environment may or may not be cleared or modified asynchronously with the execution of the instruction. Note that in one embodiment, the associated translation lookaside buffer in the processor executing the reset instruction is cleared or modified even if the specified address translation protection bit is not active at the start of instruction execution.

[0047] One embodiment of a dynamic address translation protection reset instruction used to perform a reset operation is described below with reference to FIGS. 3A-3E. In one example, this instruction is executed using a general-purpose processor (e.g., processor 104 of FIG. 1A). In the description herein, a particular location, a particular field, or a particular size of a field, or a combination thereof, may be indicated (e.g., a particular byte or bit, or both). However, other locations, fields, or sizes, or combinations thereof, may be provided. Furthermore, while it may be specified that a bit be set to a particular value, e.g., 1 or 0, this is by way of example only. In other examples, the bit may be set to a different value, such as the opposite or another value. Many variations are possible.

[0048] In one example, the dynamic address translation protection reset instruction has a format that indicates registers and register operations by an extended operation code (opcode) and additional registers. As shown in FIG. 3A, in one example, the dynamic address translation protection reset instruction 300 has multiple fields, and each field may have an associated subscript number. The subscript number associated with each field of the instruction indicates the operand to which the field applies. For example, subscript number 1 associated with register R1 indicates that the register specified using R1 contains the first operand. The length of the register operand is one register, e.g., 64 bits.

[0049] In one embodiment, the dynamic address translation protection reset (RDP) instruction 300 includes an operation code (opcode) field 302 (e.g., bits 0-15) indicating a reset operation, a first register (R1) field 308 (e.g., bits 24-27) used to specify at least one first register, a second register (R2) field 310 (e.g., bits 28-31) used to specify at least one second register, a third register (R3) field 304 (e.g., bits 16-19) used to specify at least one third register, and a mask (M4) field 306 (e.g., bits 20-23). ​​Each of these fields is described below. In one embodiment, the fields are separate and independent from one another, but in other embodiments, two or more fields may be combined. More information regarding these fields is provided below.

[0050] In one embodiment, the register (R1) field 308 contains contents having the format of a segment table entry, as shown in FIG. 3(B), where only the page table origin is used.

[0051] In one example, the register (R2) field 310 can have the format of a virtual address, as shown in FIG. 3(C), where only the page index is used.

[0052] In one or more embodiments, the register (R3) field 304 of the reset instruction has the format of an Address Space Control Element (ASCE), with only the table origin and designated type control (DT) being used. Figure 3(D) shows an example of this, where the register (R3) field 304 contains the region table origin or segment table origin of the ASCE used to clear. These contents can then be used to select the translation lookaside buffer entries to clear or modify. If the R3 field of the instruction is 0, then all contents of R3 are ignored and translation lookaside buffer entries are cleared regardless of the ASCE used to form them.

[0053] In one example, one or more controls are used in the execution of an instruction. Examples of controls are contained in the M4 field 306. Referring to Figure 3(E), the M4 field 306 includes (in one embodiment) a local clear control (LC) bit 350 which, when set, indicates that only the associated translation lookaside buffer entry in the local processor or CPU is cleared or modified; and when not set, in addition to clearing the associated translation lookaside buffer entry in the local processor, the associated translation lookaside buffer entries in all processors of the computing environment or computer configuration may or may not be cleared or modified.

[0054] In one or more specific embodiments, the page table origin and page index specify a page table entry according to dynamic address translation rules for page table lookups. In z / Architecture® architecture mode, the page table origin is treated as a 64-bit address, and the addition is performed using the rules of 64-bit address arithmetic, regardless of the current addressing mode. The address formed from these two components is a real or absolute address.

[0055] During this procedure, the page table entry does not need to be checked for format errors, and the page frame real address contained in the entry does not need to be checked for addressing exceptions. Additionally, the Address Translation Protection (or DAT Protection) bit is set to (or verified to be) 0, regardless of the value of the page-invalid bit.

[0056] The entire page table entry appears to be fetched from storage simultaneously when observed by other processors. The DAT protection bit is checked. If the DAT protection bit is '1' at the start of the instruction, the byte containing the DAT protection bit is stored. If the DAT protection bit is '0' at the start of the instruction, whether the byte containing the DAT protection bit is stored is model dependent.

[0057] If no exception is recognized, the processor clears the selected entry from its translation lookaside buffer. And, if the LC bit is 0, the processor can signal all processors in the configuration to clear or modify selected entries from their translation lookaside buffers at an appropriate time without performing a quiesce operation. The affected translation lookaside buffers clear entries for which at least the following conditions are met: 1) the page table origin in general register R1 matches the page table origin used to form the TLB table entry, 2) the page index in general register R2 matches the page index of the TLB table entry, 3) the R3 field is 0 or the table origin and designated type fields of general register R3 match the table origin and designated type fields of the address space control element (ASCE) used to form the TLB table entry, and 4) the page frame real address (PFRA) contained in the designated page table entry matches the PFRA used to form the TLB table entry.

[0058] In one or more embodiments, a serialization function is performed on the processor executing the instruction before the reset operation begins, and again after the operation is completed. As with all serialization operations, this serialization applies only to the processor executing the address translation protection reset instruction. Advantageously, other processors do not need to be serialized or quiesced to execute the instructions disclosed herein.

[0059] As described below, after execution of the address translation protection reset instruction, other processors in the configuration may still recognize an address translation protection exception for the page (i.e., storage block) corresponding to the page table entry modified by the instruction. In this case, in the processor that did not execute the instruction, the translation lookaside buffer entry corresponding to the modified page table entry has not yet been cleared or modified. Furthermore, in this case, the processor that did not execute the instruction may observe that the address translation protection bit of the modified page table entry is 0. An operating system or control program running within the computing environment recognizes and handles the potential scenario, as further described below with reference to Figures 4A-5C.

[0060] To further improve performance, other processors in the computing environment can minimize cases where they present unnecessary address translation protection exceptions to the operating system when the associated translation lookaside buffer entry has not yet been cleared or modified. For example, before presenting a DAT protection exception, a processor can examine the contents of the DAT protection bit of a translation table entry. If this bit is found to be 0, the processor can discard the protection exception condition, clear or modify its local TLB for the entry containing the old protection instruction, and re-execute the instruction that triggered the exception. Furthermore, for a processor that executed an RDP instruction, if the DAT protection bit of a particular page table entry was 0 at the start of the instruction, the processor did not make any changes and therefore does not need to signal the operation to other processors in the computing environment. Furthermore, if a prior processor had made a change, that processor would have already broadcast a signal appropriately. Furthermore, the other processors will recognize and handle the over-instruction or present an exception, as described herein, causing the operating system to issue another RDP on that processor, ensuring proper operation even without further signal broadcasts.

[0061] As mentioned above, in another embodiment, instead of clearing the TLB entry containing the protection instruction, the processor can modify or alter the TLB entry in-place to disable the protection, which advantageously eliminates the need to perform another page walk to rebuild the entry when the instruction is re-executed.

[0062] Note that in one or more embodiments, the address translation protection reset instruction can be applied to page table entries. In one or more other embodiments, the address translation protection reset instruction can be applied not only to page table entries, but also to segment table entries or region table entries.

[0063] Also, while various fields and registers of the dynamic address translation protection reset instruction are described, one or more aspects of the present invention may use other, additional, and / or fewer fields and / or registers, and / or fields and / or registers of other sizes. Many variations are possible. For example, implicit registers may be used in place of explicitly specified registers and / or fields of the instruction, and / or explicitly specified registers and / or fields may be used in place of implicit registers and / or fields. Other variations are also possible.

[0064] As described herein, address translation protection bits (e.g., DAT protection bits) can be provided in address translation table entries as a means or mechanism for an operating system to enable and disable write protection for a storage block. To enable write protection, the operating system sets the address translation protection bit to “1” in the translation table entry used during an attempted write access to the target storage block. To disable write protection, the operating system sets the same address translation protection bit to 0. In some implementations, a computing environment (e.g., IBM z / Architecture®) can provide an address translation protection program exception as a mechanism by which the computing environment notifies the operating system that an application program has attempted to write to a storage block that has a corresponding translation table entry (TTE) that prevents write access. As described above, to improve performance, a processor in a computing environment can implement a translation lookaside buffer (TLB). Information related to address translation can be maintained in TLB entries. Such information can include the contents of translation table entries used during address translation, such as the address translation protection bits. When an address translation is required as part of instruction execution, the processor can use a TLB entry, if available, instead of processing a translation table entry, since using the TLB can save the processor time.

[0065] Computing architectures (such as the IBM z / Architecture®) may provide instructions for an operating system to modify the contents of a translation table entry in a manner that results in consistent results across all processors in the computing configuration. Currently, modifications to a translation table entry involve clearing the associated TLB entry in the processors in the computing configuration and performing a quiesce operation.

[0066] As mentioned above, in one or more aspects, a dynamic address translation (DAT) protection reset instruction (or RDP instruction) is provided herein. The RDP instruction provides an option for an operating system to set the address translation protection bit (e.g., the DAT protection bit) of a translation table entry to 0 (disable write protection) for a storage block without requiring the operating system to broadcast or serialize among all processors as part of the computing environment's response to the change (i.e., without requiring a quiesce operation). A processor executing the address translation protection reset instruction can test the address translation protection bit in a particular translation table entry. If the address translation protection bit is '1', it is changed to 0. Regardless of the value at the start of execution of the instruction, any associated TLB entries are cleared or modified in the processor executing the address translation protection reset instruction. If the local clear option is not specified, the processor executing the address translation protection reset instruction can broadcast a signal to all other processors in the computing environment to clear or modify the associated TLB entries in those other processors, indicating instruction completion without waiting for all processors to clear or modify the TLBs. Advantageously, a quiesce operation is not required during execution of the address translation protection reset instruction.

[0067] 4A and 4B illustrate different embodiments of processing based on execution of a dynamic address translation protection reset instruction in accordance with one or more aspects of the present invention. In one example, a processor or CPU, such as a general-purpose processor or CPU 104 (FIG. 1A), is used to execute the instructions. In one example, processor hardware and firmware are used to execute the instructions. The hardware and firmware may be located within or coupled to the processor to receive instructions from the processor, which may, for example, retrieve, decode, and set up the instructions for execution on the hardware. Other variations are possible.

[0068] 4A illustrates an example of a process associated with executing a dynamic address translation protection reset instruction to disable write protection for storage block X in a multi-processor (i.e., multi-CPU) computing environment or configuration. As illustrated, the process begins in step 400 when an application program running on a processor (CPU-A) attempts to write to storage block X and is blocked in step 402. In this case, the processor (CPU-A) reports an address translation protection exception (e.g., a DAT-P exception) to the operating system (OS). The operating system performs a memory management operation on storage block X, which includes issuing a dynamic address translation protection reset (RDP) instruction on the processor (CPU-A) in step 404 (in one example), in accordance with one or more aspects of the present invention. In step 406, the processor (CPU-A) retrieves (e.g., receives, fetches, etc.) the RDP instruction and executes the instruction.

[0069] In one embodiment, execution of the instruction may include testing a DAT protection bit (TTE.P) in a translation table entry, and if set to write-protected, updating the translation table entry for storage block X to disable write protection for the storage block (e.g., setting TTE.P for storage block X to “0”). Additionally, execution of the RDP instruction clears or modifies an associated translation lookaside buffer (TLB) entry in the processor (CPU-A). If the local clear control is not set (i.e., LC=0), a signal may be broadcast to other processors in the computing environment to clear or modify associated translation lookaside buffer entries in those other processors in the computing environment at the appropriate times. In one embodiment, the signal is sent to all other processors in the computing environment. Execution of the RDP instruction is independent of any associated processing by other processors in the computing environment and, therefore, completes without waiting for action by other processors in the computing environment (e.g., does not require a serialize or quiesce operation by one or more other processors in the computing environment). Note that in the context of the description herein, serialization means, in some embodiments, that updates to configuration-wide resources (such as translation table entries) are made visible to all processors in the configuration before the instruction completes.

[0070] In step 408, the application program resumes operation on the processor (CPU-A), and this time, writing to storage block X is permitted. This completes processing associated with the RDP instruction on the processor (CPU-A) in step 410. Furthermore, as shown in FIG. 4A , when one or more other processors (e.g., CPU-B) receive a broadcast signal requesting the clearing or modification of the associated TLB entry, these other processors (e.g., CPU-B) queue requests to clear or modify the associated TLB entry in a timely manner in step 412. It should be noted that a TLB may have multiple levels. In one implementation, the TLB may include a level 1-TLB and a level 2-TLB. After receiving a request to clear or modify the associated TLB entry in a timely manner, CPU-B should, but is not required to, clear or modify the TLB entry. For example, the level 1-TLB entry need not be cleared, and other processors rely on the aging out of the associated entry. Level 2 TLB entries can then be cleared or modified in a background process, requiring less overhead. The specific approach to handling broadcast signals requesting the clearing or modification of associated TLB entries is implementation dependent.

[0071] 4A, a second start step 420, which is not simultaneous with the first start step 400, occurs when an application program executing on another processor (CPU-B) attempts to write to storage block X in step 422. Based on this, the process determines whether a DAT-P exception condition was detected by CPU-B in step 424. If not, the application program is allowed to write to storage block X in step 426, and the process completes in step 410.

[0072] If a DAT-P exception condition is detected by CPU-B, processing continues at step 428 with CPU-B examining the translation table entry protection bit (TTE.P) to determine whether TTE.P is 0 for storage block X. If not, at step 430, CPU-B reports the DAT-P exception to the operating system for further processing.

[0073] Based on the content of the translation table entry protection bit (TTE.P) being 0, the condition is determined to be over-detected. Therefore, in step 432, the associated TLB entry in CPU-B is cleared or modified, and the condition is determined to be over-detected and is not reported to the operating system. In step 434, the application program resumes operation on CPU-B, this time allowing writes to storage block X, and processing concludes in step 410. Note that with respect to the above discussion, over-detection of address translation protection exceptions is expected to be rare when the operating system selectively utilizes the address translation protection reset instruction disclosed herein.

[0074] 4B illustrates an alternative embodiment of processing associated with executing a dynamic address translation protection reset instruction to disable write protection for storage block X in a multi-processor (i.e., multi-CPU) computing environment or configuration. While the embodiment of FIG. 4A presents a CPU implementation that is capable of verifying the detected condition before notifying the operating system, the embodiment of FIG. 4B assumes a CPU implementation that does not or cannot verify the detected condition before notifying the operating system.

[0075] As shown, the process begins in step 400 when an application program running on a processor (CPU-A) attempts to write to storage block X and is blocked in step 402. In this case, the processor (CPU-A) reports an address translation protection exception (e.g., a DAT-P exception) to the operating system (OS). The operating system performs a memory management operation on storage block X, which, in one example, includes issuing a dynamic address translation protection reset (RDP) instruction to the processor (CPU-A) in step 404, in accordance with one or more aspects of the present invention. In step 406, the processor (CPU-A) retrieves (e.g., receives, fetches, etc.) the RDP instruction and executes the instruction.

[0076] In one embodiment, execution of the instruction may include testing the DAT protection bit (TTE.P), and if set to write-protected, updating the translation table entry for storage block X to disable write protection for the storage block (e.g., setting TTE.P for storage block X to “0”). Additionally, execution of the RDP instruction clears or modifies associated translation lookaside buffer (TLB) entries in the processor (CPU-A). If the local clear control is not set (i.e., LC=0), a signal may be broadcast to other processors in the computing environment to clear or modify associated translation lookaside buffer entries in those other processors in the computing environment at the appropriate times. In one embodiment, the signal is sent to all processors in the computing environment. Execution of the RDP instruction is independent of any associated processing in other processors in the computing environment and, therefore, completes without waiting for actions by other processors in the computing environment, such as serialization or quiesce operations by one or more other processors in the computing environment.

[0077] In step 408, the application program resumes operation on the processor (CPU-A), this time allowing it to write to storage block X. This ends the processing associated with the RDP instruction on the processor (CPU-A) in step 410. As shown in FIG. 4B, in the case of a broadcast signal, when one or more other processors (e.g., CPU-B) receive the broadcast signal requesting the clearing or modification of the associated TLB entries, these other processors (e.g., CPU-B) queue requests to clear or modify the associated TLB entries at the appropriate time in step 412.

[0078] In a second, non-concurrent start step 420, an application program executing on another processor (CPU-B) attempts to write to storage block X in step 422. Based on this, the process determines whether an address translation protection exception (e.g., a DAT-P exception) condition is detected by CPU-B for storage block X in step 424. If not, the application program is allowed to write to storage block X in step 426, and the process completes in step 410.

[0079] If a DAT-P exception condition is detected by CPU-B, the operating system is notified of an address translation protection exception (e.g., a DAT-P exception) for storage block X by another processor (CPU-B) in step 440. The operating system tests the translation table entry protection bit (e.g., TTE.P) in step 442, thereby recognizing the reported condition as an over-indication and issues another address translation protection reset instruction, this time to the other processor (CPU-B). This causes the other processor (CPU-B) to execute the address translation protection reset instruction in step 444 to reset the address translation protection bit and disable write protection for the examined (and confirmed to be 0) storage block. Furthermore, the associated TLB entry on the other processor (CPU-B) is cleared or modified to prevent future over-indications of the condition on that processor. Furthermore, because the translation table entry protection bit (e.g., TTE.P) is confirmed to be '0', there is no need to broadcast a signal to other processors in the computing environment. Thereafter, in step 446, the application program on the other processor can resume operation, this time being permitted to write to storage block X, and processing terminates in step 410. In this regard, it is noted that if an operating system selectively utilizes the address translation protection reset instruction disclosed herein, over-indications of address translation protection exceptions are expected to be rare.

[0080] 5A-5C illustrate another embodiment of a workflow illustrating certain aspects of one or more embodiments of the present invention.

[0081] 5A, in step 500, the operating system receives a request from an application program executing on a processor (CPU-A) in a multiprocessor computing environment to reset write protection for storage block X. Based on receiving the request, the operating system locks the dynamic address translation (DAT) entry associated with storage block X in step 502 and issues a reset DAT protection (RDP) instruction without specifying local clear if write protection is active in step 504. The processor (CPU-A) retrieves (e.g., receives, fetches, etc.) the RDP instruction and executes the instruction in step 506.

[0082] In one or more embodiments, execution of the instruction may include testing the DAT protection bit (TTE.P), and if set to write-protected, updating the translation table entry for storage block X to disable write protection for the storage block (e.g., setting TTE.P for storage block X to “0”). Additionally, execution of the RDP instruction clears or modifies an associated translation lookaside buffer (TLB) entry in the processor (CPU-A). If the local clear control is not set (i.e., LC=0), a signal may be broadcast to other processors in the computing environment to clear or modify associated translation lookaside buffer entries in those other processors in a timely manner. In one embodiment, the signal is sent to all other processors in the computing environment. Execution of the RDP instruction is independent of any associated processing by other processors in the computing environment and, therefore, completes without waiting for action by other processors in the computing environment (e.g., does not require a serialize or quiesce operation by one or more other processors in the computing environment).

[0083] As shown in one embodiment, the operating system (OS) obtains information indicating that the processor (CPU-A) executed the RDP instruction in step 508, proceeds to step 510 to unlock the DAT entry, and completes the process in step 512.

[0084] In a multi-system or multi-processor computing environment, an application program may access the same storage block from multiple different processors (CPUs). This access may allow TLB entries to be stored on multiple different processors. As disclosed herein, operating system services are used to enable and disable write protection for storage blocks. Referring to FIG. 5B, in one or more implementations, at step 520, an application program running on CPU-B attempts to write to storage block X before processing a received broadcast signal to clear or modify the associated TLB entry of processor (CPU-B).

[0085] Based on this, the operating system receives a write protection exception interrupt issued to the operating system from the hardware in step 522. The operating system gains control to process the write protection exception interrupt in step 524 and checks the storage block entry indicating that write protection is not active (e.g., based on the processing described above in connection with FIG. 5A) in step 526. The operating system executes or initiates an RDP instruction for storage block X in step 528 and specifies a local clear to clear or modify the associated TLB entry on the processor (CPU-B) (that attempted the write access that caused the write protection exception interrupt). The operating system sends a request signal to CPU-B to retry the instruction attempting to write to storage block X in step 530, completing the write protection exception interrupt. The processor (CPU-B) retries the write access to storage block X in step 532, and the write access is completed. Processing then completes in step 534.

[0086] Eventually, all processors (CPUs) in the computing environment will process the original broadcast signal or locally clear or modify the associated TLB entries while handling the write operation exception for the storage block. As shown in FIG. 5C, a situation may arise in which an application requests that write protection be enabled for the same storage block X before all processors have processed the broadcasted invalidation request (e.g., based on the execution of an RDP instruction by a previous processor (CPU-A) (see FIG. 5A)) at step 540. Based on this enablement request, the operating system can issue a quiesce operation instruction to clear the associated TLB entries on all processors (CPUs) in the multiprocessor system at step 542 before updating the DAT entry associated with storage block X to indicate that write protection is active. This completes the process at step 544.

[0087] As described herein, in one aspect, an instruction for performing a reset operation (e.g., a single architected machine instruction (e.g., a dynamic address translation protection reset instruction) at a hardware / software interface is provided. The instruction is, for example, an instruction defined in an instruction set architecture (ISA), which determines to reset an address translation protection bit in a particular translation table entry associated with a storage block, and, based on the determination, resets the address translation protection bit to disable write protection for the storage block. The reset does not require a quiesce operation by one or more other processors in the computing environment, i.e., is independent of associated processing by one or more other processors in the computing environment. Furthermore, the reset can be performed without broadcasting the operation to other processors in the system. Therefore, processing complexity associated with performing the reset operation is reduced. Furthermore, the reset operation, and therefore processor performance, is improved. Such instruction execution can reduce execution time, improve performance, and further free up system-wide quiesce resources for use by other processors.

[0088] One or more aspects of the present invention are closely tied to computer technology and facilitate processing within a computer and improve its performance. The use of a single architected machine instruction to perform reset-related operations improves performance within a computing environment by reducing complexity, reducing resource usage, and increasing processing speed. This instruction can be used in many technical fields, such as computer processing, medical processing, engineering, automotive technology, and manufacturing. Providing an optimized method for resetting write access to storage blocks can reduce execution time and improve these technical fields.

[0089] Further details of one embodiment that facilitates processing within a computing environment in accordance with one or more aspects of the present invention are described with reference to FIGS. 6A and 6B.

[0090] Referring to FIG. 6A , in one embodiment, an instruction to perform a reset operation is executed at step 600. Executing the instruction includes, for example, determining by a processor at step 602 to reset an address translation protection bit in a particular translation table entry associated with a storage block, and resetting the address translation protection bit to disable write protection for the storage block based on the determination at step 604. Here, the reset is performed without waiting for action by one or more other processors in the computing environment. By performing the reset without requiring a quiesce operation by one or more other processors in the computing environment (i.e., independently of associated processing of one or more other processors in the computing environment), interruptions to instruction processing in the computing environment are reduced, improving performance. Furthermore, using an RDP instruction to perform at least the determination operation and the reset operation improves performance and reduces resource utilization.

[0091] In one example, executing the instruction includes terminating execution of the instruction based on resetting the address translation protection bit to disable write protection for the storage block without requiring a quiesce operation by one or more other processors in the computing environment in step 606. Advantageously, terminating execution of the instruction without requiring a quiesce operation by one or more other processors in the computing environment may improve performance of the computing environment and free up system-wide quiesce resources for use by other processors.

[0092] In one embodiment, executing the instruction further includes clearing a translation lookaside buffer entry within the processor associated with the particular translation table entry, at step 608. In another example, executing the instruction further includes resetting a protection indication for a translation lookaside buffer entry within the processor associated with the particular translation table entry, at step 610. Advantageously, rather than clearing the translation lookaside buffer entry, the processor may simply reset the protection indication within the entry and leave the remainder of the entry intact, thereby allowing the write to continue and complete without requiring address retranslation to reconstruct the necessary translation lookaside buffer entry.

[0093] In one embodiment, executing the instruction further includes, at step 612, broadcasting to one or more other processors in the computing environment a signal to clear or modify a translation lookaside buffer entry in the one or more other processors associated with the particular translation table entry. In one embodiment, executing the instruction further includes, at step 614, testing an address translation protection bit in a particular translation table entry associated with the storage block, wherein the broadcast is based at least in part on the result of the test. Using the address translation protection reset instruction to perform the determination, reset, and broadcast operations improves performance and reduces resource utilization.

[0094] 6B , in one example, in step 616, another processor of the one or more other processors attempts write access to the storage block without the other processor's associated translation lookaside buffer entry being cleared or modified, resulting in an excessively detected address translation protection exception condition, and based on that, the other processor checks the address translation protection bits to identify that the address translation protection exception condition is an excessively detected condition, and based on the check identifying that the address translation protection exception condition is an excessively detected condition, write access to the storage block is granted. Advantageously, by checking the address translation protection bits to identify that the address translation protection exception condition is an excessively detected condition, processing performance in this situation can be improved by allowing access and avoiding the need for an operating system program interrupt handler.

[0095] In a further example, in step 618, another processor of the one or more other processors attempts a write access to the storage block without clearing or modifying the other processor's associated translation lookaside buffer entry, resulting in an address translation protection exception condition, based on which the other processor checks the address translation protection bits to identify that the address translation protection exception condition is over-indicated, and based on the check identifying that the address translation protection exception condition is over-indicated, the other processor clears or modifies the associated translation lookaside buffer entry that includes the over-indicated address translation protection bit. Advantageously, checking the address translation protection bits to identify that the address translation protection exception condition is over-indicated can improve processing performance in this situation by allowing the write access to proceed.

[0096] In one example, in step 620, if another processor of the one or more other processors attempts a write access to the storage block without the other processor's associated translation lookaside buffer entry being cleared or modified, resulting in excessive detected address translation protection exception conditions, the other processor reports the exception condition to an operating system of the computing environment, and based thereon, the operating system issues an instruction to the other processor to perform an address translation protection reset operation at the other processor of the one or more other processors. Advantageously, the instruction to perform an address translation protection reset operation can provide the operating system with the option to easily disable write protection for the storage block without requiring a quiesce operation among all processors of the computing environment in response to the change.

[0097] Other variations and embodiments are possible. For example, in one or more other implementations, the translation protection indication may be reset within an existing TLB entry rather than requiring the entry to be cleared and rebuilt.

[0098] Aspects of the present invention can be used in many types of computing environments. Another example of a computing environment incorporating and using one or more aspects of the present invention is described with reference to FIG. 7A. By way of example, the computing environment of FIG. 7A is based on the z / Architecture® instruction set architecture manufactured by International Business Machines Corporation (Armonk, New York). However, the z / Architecture hardware architecture is only one example of an architecture. Again, the computing environment may be based on other architectures, including, but not limited to, the Intel® x86 architecture, other International Business Machines Corporation architectures, or architectures of other companies, or combinations thereof. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0099] As an example, computing environment 10 includes a central electronics complex (CEC) 11. Central electronics complex 11 includes multiple components, including, for example, memory 12 (also known as system memory, main memory, main storage, central storage, or storage) coupled to one or more processors (also known as central processing units (CPUs)) 13 and an input / output (I / O) subsystem 14.

[0100] I / O subsystem 14 may be part of or separate from the central electronic processing unit. I / O subsystem 14 directs the flow of information between main storage 12 and input / output control unit 15 and input / output (I / O) devices 16 coupled to the central electronic processing unit.

[0101] Many types of I / O devices can be used. One particular type is a data storage device 17. The data storage device 17 can store one or more programs 18, one or more computer readable program instructions 19, or data, or a combination thereof. The computer readable program instructions can be configured to perform the functions of embodiments according to aspects of the present invention.

[0102] Central electronic processing unit 11 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, central electronic processing unit 11 may include and / or be coupled to non-removable, non-volatile magnetic media (commonly referred to as "hard disks"), magnetic disk drives for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and / or optical disk drives for reading from and writing to removable, non-volatile optical disks, such as CD-ROMs, DVD-ROMs, and other optical media. Note that other hardware and / or software components may also be used in combination with central electronic processing unit 11. Examples of these components include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0103] Additionally, central electronic processing unit 11 is operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, suitable for use with central electronic processing unit 11 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0104] In one or more embodiments, central electronic processing unit 11 provides logical partitioning and / or virtualization support. In one embodiment, as shown in FIG. 7B, memory 12 includes, for example, one or more logical partitions 20, a hypervisor 21 that manages the logical partitions, and processor firmware 22. One example of a hypervisor 21 is the Processor Resource / System Manager (PR / SM) manufactured by International Business Machines Corporation of Armonk, NY. TM ). As used herein, firmware includes, for example, processor microcode. Firmware includes, for example, hardware-level instructions and / or data structures used in implementing higher-level machine code. In one embodiment, firmware includes, for example, proprietary code that controls operating system access to system hardware, typically provided as microcode with trusted software or microcode specific to the underlying hardware. PR / SM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0105] Each logical partition 20 can function as a separate system. That is, each logical partition can be reset independently, run a guest operating system 23 (such as the z / OS® operating system manufactured by International Business Machines Corporation, Armonk, New York), or other control code 24 (such as coupling facility control code (CFCC)), and operate with different programs 25. An operating system or application program running within a logical partition appears to have access to the entire, complete system, but in fact only a portion of it is available. Note that while the z / OS operating system is illustrated, other operating systems provided by International Business Machines Corporation and / or other companies may also be used in accordance with one or more aspects of the present invention.

[0106] Memory 12 is coupled to CPU 13 (FIG. 7A). CPU 13 is a physical processor resource that can be assigned to a logical partition. For example, logical partition 20 includes one or more logical processors, each of which represents all or a portion of physical processor resource 13 that can be dynamically assigned to a logical partition.

[0107] In a further embodiment, the central electronic processing unit provides virtual machine support (either with or without logical partitioning support). As shown in FIG. 7C, memory 12 of central electronic processing unit 11 includes, for example, one or more virtual machines 26, a virtual machine manager, such as hypervisor 27, that manages the virtual machines, and processor firmware 28. An example of hypervisor 27 is the z / VM® hypervisor manufactured by International Business Machines Corporation (Armonk, New York). A hypervisor is sometimes referred to as a host. Note that z / VM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0108] The central electronic processing unit's virtual machine support provides the ability to operate multiple virtual machines 26, each capable of running a different program 29 and a guest operating system 30, such as the Linux operating system. Each virtual machine 26 can function as a separate system; that is, each virtual machine can be reset independently, run a guest operating system, and operate with different programs. An operating system or application program running within a virtual machine appears to have access to the entire, complete system, but in fact only a portion of it is available. While z / VM and Linux are illustrated, other virtual machine managers and / or operating systems may be used in accordance with one or more aspects of the present invention. The registered trademark Linux is used pursuant to a sublicense from the Linux Foundation, the exclusive licensee of Linus Torvalds, the owner of such trademarks worldwide.

[0109] Another embodiment of a computing environment incorporating and using one or more aspects of the present invention is described with reference to FIG. 8A. In this example, computing environment 36 includes, for example, a native central processing unit (CPU) 37, memory 38, and one or more input / output devices 39 and / or input / output interfaces 39 coupled to one another, for example, via one or more buses 40 and / or other connections. By way of example, computing environment 36 may include a PowerPC® processor manufactured by International Business Machines Corporation (Armonk, New York), an HP Superdome with an Intel® Itanium® II processor manufactured by Hewlett-Packard Company (Palo Alto, California), or other machines based on architectures offered by International Business Machines Corporation, Hewlett-Packard, Intel Corporation, Oracle, or other companies, or combinations thereof. Note that PowerPC is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Itanium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0110] The native central processing unit 37 includes one or more native registers 41, such as one or more general purpose registers and / or one or more special purpose registers that are used during processing within the environment. These registers contain information that represents the state of the environment at any particular time.

[0111] Additionally, native central processing unit 37 executes instructions and code stored in memory 38. In one specific example, central processing unit executes emulator code 42 stored in memory 38. This code allows a computing environment configured with one architecture to emulate another architecture. For example, emulator code 42 allows a machine based on an architecture other than the z / Architecture hardware architecture (e.g., PowerPC processors, HP Superdome servers, etc.) to emulate the z / Architecture hardware architecture and execute software and instructions developed based on the z / Architecture hardware architecture.

[0112] Further details related to emulator code 42 are described with reference to FIG. 8B . Guest instructions 43 stored in memory 38 include software instructions (e.g., correlated with machine instructions) developed to execute on an architecture other than that of native CPU 37. For example, guest instructions 43 may have been designed to execute on a processor based on the z / Architecture hardware architecture, but instead are emulated on native CPU 37 (which may be, for example, an Intel Itanium II processor). As an example, emulator code 42 includes an instruction fetching routine 44 for retrieving one or more guest instructions 43 from memory 38 and providing a local buffer for the retrieved instructions, if necessary. Emulator code 42 also includes an instruction translation routine 45 for determining the type of the retrieved guest instruction and converting the guest instruction into one or more corresponding native instructions 46. This conversion may include, for example, identifying a function performed by the guest instruction and selecting a native instruction to perform the function.

[0113] Additionally, emulator code 42 includes an emulation control routine 47 for causing the execution of native instructions. Emulation control routine 47 may cause native CPU 37 to execute a routine of native instructions that emulates one or more previously fetched guest instructions, and upon completion of such execution, return control to an instruction fetch routine to emulate the fetch of the next guest instruction or group of guest instructions. Execution of native instructions 46 may include loading data from memory 38 into registers, storing data from registers back to memory, or performing some type of arithmetic or logical operation as determined by a translation routine.

[0114] Each routine is implemented, for example, in software stored in memory and executed by native central processing unit 37. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software, or a combination thereof. The emulated processor's registers may be emulated using the native CPU's registers 41 or may be emulated using locations in memory 38. In an embodiment, guest instructions 43, native instructions 46, and emulator code 42 may reside in the same memory or may be distributed among different memory devices.

[0115] One instruction that can be emulated is the dynamic address translation protection reset instruction described herein, in accordance with one aspect of the present invention.

[0116] The computing environments described above are merely examples of computing environments that may be used. Other environments (including, but not limited to, non-partitioned, partitioned, cloud, or emulated environments, or combinations thereof) may also be used, and embodiments are not limited to any one environment. Although various examples of computing environments are described herein, one or more aspects of the present invention may be used with many types of environments. The computing environments provided herein are merely examples.

[0117] Each computing environment can be configured to include one or more aspects of the present invention.

[0118] One or more aspects may relate to cloud computing.

[0119] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the teachings described herein is not limited to cloud computing environments. Rather, embodiments of the present invention may be practiced in conjunction with any other type of computing environment now known or later developed.

[0120] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a service provider. This cloud model includes at least five characteristics, at least three service models, and at least four deployment models.

[0121] The characteristics are as follows:

[0122] On-Demand Self-Service: Cloud consumers can unilaterally provision computing capacity, such as server time or network storage, automatically as needed, without the need for human interaction with the service provider.

[0123] Broad network access: Computing power is available over the network and can be accessed through standard mechanisms, facilitating use by heterogeneous thin or thick client platforms (e.g., cell phones, laptops, PDAs).

[0124] Resource Pooling: Computing resources from a provider are pooled and offered to multiple consumers using a multi-tenant model. Various physical and virtual resources are dynamically allocated and reallocated based on demand. Consumers generally have no control or knowledge of the exact location of the resources they are provided with, resulting in a sense of location independence. However, consumers may be able to determine location at a higher level of abstraction (e.g., country, state, data center).

[0125] Rapid Elasticity: Computing capacity can be provisioned quickly and elastically, sometimes automatically, to instantly scale out and quickly release to instantly scale in. To the consumer, the computing power available for provisioning often appears unlimited, and can be purchased at any time and in any quantity.

[0126] Service Metering: Cloud systems leverage metering capabilities at a level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, active user accounts) to automatically control and optimize resource usage. Resource usage can be monitored, controlled, and reported to provide transparency to both providers and consumers of utilized services.

[0127] The service model is as follows:

[0128] Software as a Service (SaaS): The functionality offered to the consumer is the availability of a provider's applications running on a cloud infrastructure that can be accessed from a variety of client devices through a thin client interface such as a web browser (e.g., webmail). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application functionality, except for limited user-specific application configuration settings.

[0129] Platform as a Service (PaaS): The capability offered to consumers is to deploy applications they create or acquire using programming languages ​​and tools supported by the provider onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the configuration of their hosting environment.

[0130] Infrastructure as a Service (IaaS): The functionality offered to consumers is the provisioning of processors, storage, networking, and other basic computing resources on which they can deploy and run any software, including operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but has control over the operating system, storage, and deployed applications, and in some cases partial control over some network components (e.g., host firewalls).

[0131] The deployment model is as follows:

[0132] Private Cloud: This cloud infrastructure is dedicated to a specific organization and can be managed by that organization or a third party, and can exist on-premise or off-premise.

[0133] Community Cloud: This cloud infrastructure is shared by multiple organizations to support a specific community with common concerns (e.g., mission, security requirements, policies, and compliance). This cloud infrastructure can be managed by those organizations or a third party and can exist on-premises or off-premises.

[0134] Public cloud: This cloud infrastructure is available to the general public or large industry organizations and is owned by an organization that sells cloud services.

[0135] Hybrid cloud: This cloud infrastructure combines two or more cloud models (private, community, or public), each of which retains its inherent nuances but is bound by standards or specific technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds).

[0136] A cloud computing environment is a service-oriented environment that emphasizes statelessness, low coupling, modularity, and semantic interoperability. At the core of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0137] FIG. 9 illustrates an exemplary cloud computing environment 50. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 52, with which local computing devices used by cloud consumers (e.g., PDAs or cell phones 54A, desktop computers 54B, laptop computers 54C, or automobile computer systems 54N, or combinations thereof) can communicate. The nodes 52 can communicate with each other. The nodes 52 can be physically or virtually grouped (not shown) in one or more networks, such as the private, community, public, or hybrid clouds described above, or combinations thereof. This enables the cloud computing environment 50 to provide infrastructure, platform, or software as a service, or combinations thereof, for which cloud consumers are not required to maintain resources on their local computing devices. It should be understood that the types of computing devices 54A-N illustrated in FIG. 9 are merely exemplary, and that the computing nodes 52 and the cloud computing environment 50 can communicate with any type of electronic device via any type of network or network-addressable connection (e.g., using a web browser), or both.

[0138] A set of functional abstraction layers provided by the cloud computing environment 50 (FIG. 9) is now shown in FIG. 10. It should be understood in advance that the components, layers, and functions shown in FIG. 10 are merely exemplary, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0139] Hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframe 61, reduced instruction set computer (RISC) architecture-based server 62, server 63, blade server 64, storage device 65, and network and network components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0140] The virtualization layer 70 provides an abstraction layer from which virtual entities such as virtual servers 71, virtual storage 72, virtual networks including virtual private networks 73, virtual applications and operating systems 74, and virtual clients 75 can be provided.

[0141] By way of example, the management layer 80 may provide the following functionality: Resource provisioning 81 enables dynamic procurement of computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 82 enables cost tracking as resources are utilized within the cloud computing environment and billing or invoicing for the consumption of these resources. By way of example, these resources may include application software licenses. Security enables identification and verification of cloud consumers and tasks, as well as protection for data and other resources. User portal 83 provides consumers and system administrators with access to the cloud computing environment. Service level management 84 enables allocation and management of cloud computing resources so that requested service levels are met. Service level agreement (SLA) planning and fulfillment 85 enables advance arrangement and procurement of anticipated future cloud computing resources required in accordance with SLAs.

[0142] The workload layer 90 provides examples of functionality that can be leveraged in a cloud computing environment. Examples of workloads and functionality that can be provided from this layer include mapping and navigation 91, software development and lifecycle management 92, virtual classroom instruction delivery 93, data analytics processing 94, transaction processing 95, and reset processing 96.

[0143] Aspects of the invention may be a system, method, or computer program product, or combination thereof, integrated at any possible level of technical detail. The computer program product may include a computer-readable storage medium having stored thereon computer-readable program instructions for causing a processor to perform aspects of the invention.

[0144] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or a suitable combination thereof. More specific examples of computer-readable storage media include portable computer diskettes, hard disks, RAM, ROM, erasable programmable ROM (EPROM or flash memory), static random access memory (SRAM), CD-ROMs, DVDs, memory sticks, floppy disks, punch cards, or mechanically encoded devices that have instructions recorded on ridge-in-groove structures, and the like, and suitable combinations thereof. As used herein, a computer-readable storage medium should not be construed as a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or an electrical signal transmitted over a wire.

[0145] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing device / processing device. Alternatively, they can be downloaded to an external computer or external storage device via a network (e.g., the Internet, a LAN, a WAN, or a wireless network, or a combination thereof). The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing device / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to a computer-readable storage medium in the respective computing device / processing device for storage.

[0146] The computer-readable program instructions for carrying out the operations of the present invention can be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk and C++, and procedural programming languages ​​such as the "C" programming language and similar programming languages. The computer-readable program instructions can execute entirely on the user's computer as a stand-alone software package, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a LAN or WAN, or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry, including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), can execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to customize the electronic circuitry for carrying out aspects of the present invention.

[0147] Aspects of the present invention are described herein with reference to flowchart and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. Each block of the flowchart and / or block diagrams, and combinations of blocks in the flowchart and / or block diagrams, can be implemented by computer-readable program instructions.

[0148] These computer-readable program instructions can be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, whereby the instructions, executed by the processor of such computer or other programmable data processing apparatus, create means for performing the functions / acts identified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions can also be stored on a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner. The computer-readable storage medium having instructions stored thereon thereby constitutes an article of manufacture including instructions for performing aspects of the functions / acts identified in one or more blocks of the flowcharts and / or block diagrams.

[0149] Computer-readable program instructions may also be loaded into a computer, other programmable apparatus, or other device and a series of operational steps executed on the computer, other programmable apparatus, or other device to create a computer-implemented process, whereby the instructions executing on the computer, other programmable apparatus, or other device perform the functions / operations identified in one or more blocks in the flowcharts and / or block diagrams.

[0150] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for performing specific logical functions. In some implementations, the functions shown in the blocks may be performed in an order different from that shown in the figures. For example, depending on the functionality involved, two blocks shown in succession may actually be accomplished as a single step, may be executed simultaneously or substantially simultaneously, may be executed in a partially or fully overlapping manner, or the blocks may even be executed in reverse order. Note that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs specific functions or operations or executes a combination of dedicated hardware and computer instructions.

[0151] In addition to the above, one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider that offers management of a customer environment. For example, the service provider may create, maintain, support, etc., computer code and / or computer infrastructure that implements one or more aspects for one or more customers. In return, the service provider may receive payments from the customer, for example, based on a subscription and / or fee agreement. Additionally or alternatively, the service provider may receive payments from the sale of advertising content to one or more third parties.

[0152] In one aspect, an application may be deployed to implement one or more embodiments. By way of example, deploying an application includes providing a computer infrastructure operable to implement one or more embodiments.

[0153] As a further aspect, a computing infrastructure may be deployed that includes integrating computer-readable code into a computing system, where the code in combination with the computing system is capable of implementing one or more embodiments.

[0154] In yet another aspect, a process for integrating a computing infrastructure may be provided, the process comprising integrating computer-readable code into a computer system. The computer system includes a computer-readable medium. The computer medium includes one or more embodiments. The code in combination with the computer system may implement one or more embodiments.

[0155] Although various embodiments have been described above, these are merely examples. For example, computing environments of other architectures may be used to incorporate and / or use one or more aspects. Furthermore, different instructions or operations may be used. Furthermore, different types of registers and / or different registers may be used. Many variations are possible.

[0156] Various aspects are described herein. Furthermore, many variations are possible without departing from the spirit of the aspects of the present invention. Unless otherwise contradictory, each aspect or feature described herein, and variations thereof, may be combined with any other aspect or feature.

[0157] Additionally, other types of computing environments can also benefit from and be used with the present invention. As an example, a data processing system suitable for storing and / or executing program code can be used that includes at least two processors coupled directly or indirectly via a system bus to memory elements, such as local memory used during the actual execution of the program code, bulk storage, and cache memory that provides temporary storage of at least some program code to reduce the number of times the code must be retrieved from bulk storage during execution.

[0158] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, DASDs, tapes, CDs, DVDs, thumb drives, and other memory media) may be coupled to the system either directly or through intervening I / O controllers. Network adapters may also be coupled to the system to enable the data processing system to be coupled to other data processing systems, remote printers, or storage devices through intervening private or public networks. Available network adapters include modems, cable modems, and Ethernet cards, to name a few.

[0159] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit various embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Furthermore, as used herein, the terms "comprises" and / or "comprising" specify the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups or combinations thereof.

[0160] Where present in the following claims, the corresponding structure, material, acts, and equivalents of all means-plus-function or step-plus-function elements are intended to include any structure, material, or acts for performing the function in combination with other specifically claimed claim elements. The description of one or more embodiments has been presented for purposes of illustration and description and is not intended to be exhaustive or limited to the precise form disclosed. Many modifications and variations will be apparent to those skilled in the art. The present embodiments were chosen and described to best explain various aspects and practical applications and to enable others skilled in the art to recognize various embodiments with various modifications suited to the particular use contemplated.

Claims

1. 1. A computer program for facilitating processing within a computing environment, comprising: causing a processor to perform a method comprising executing instructions to perform an address translation protection reset operation; Executing such an instruction is determining, by the processor, to reset an address translation protection bit in a particular translation table entry associated with a storage block; resetting the address translation protection bit to disable write protection for the storage block based on the determination, the reset occurring without waiting for action by one or more other processors of the computing environment; and Including, another processor of the one or more other processors attempts write access to the storage block without the other processor's associated translation lookaside buffer entry being cleared or modified, resulting in an address translation protection exception condition, based thereon, the other processor examines the address translation protection bits to identify that the address translation protection exception condition is an over-indication, and based on the examination identifying that the address translation protection exception condition is an over-indication, write access to the storage block is granted; Computer program.

2. 2. The computer program product of claim 1, wherein executing the instructions further comprises: terminating execution of the instructions based on resetting the address translation protection bit to disable write protection for the storage block without requiring a quiesce operation by the one or more other processors of the computing environment.

3. 2. The computer program product of claim 1, wherein executing the instructions further comprises clearing a translation lookaside buffer entry within the processor that is associated with the particular translation table entry.

4. 2. The computer program product of claim 1, wherein executing the instructions further comprises resetting a protection indication of a translation lookaside buffer entry within the processor that is associated with the particular translation table entry.

5. 2. The computer program product of claim 1, wherein executing the instructions further comprises broadcasting a signal to one or more other processors of the computing environment that clears or modifies a translation lookaside buffer entry in the one or more other processors that is associated with the particular translation table entry.

6. 6. The computer program product of claim 5, wherein executing the instructions further comprises testing the address translation protection bit in the particular translation table entry associated with the storage block, and wherein the broadcast is based at least in part on a result of the test.

7. 6. The computer program product of claim 5, wherein another processor of the one or more other processors attempts a write access to the storage block without an associated translation lookaside buffer entry of the other processor being cleared or modified, resulting in an address translation protection exception condition, and based thereon, the other processor examines the address translation protection bits to identify that the address translation protection exception condition is over-indicated, and based on the examination identifying that the address translation protection exception condition is over-indicated, the other processor clears or modifies the associated translation lookaside buffer entry of the other processor that includes the over-indicated address translation protection bit.

8. 8. The computer program product of claim 6, wherein another of the one or more other processors attempts a write access to the storage block without the other processor's associated translation lookaside buffer entry being cleared or modified, resulting in an address translation protection exception condition, based on which the other processor reports the exception condition to an operating system of the computing environment, based on which the operating system issues an instruction to the other of the one or more other processors to perform the address translation protection reset operation at the other of the one or more other processors.

9. 1. A computer system for facilitating processing within a computing environment, comprising: Memory and a processor in communication with the memory, wherein the computer system comprises: configured to execute, by the processor, a method including executing instructions to perform an address translation protection reset operation, the executing instructions comprising: determining, by the processor, to reset an address translation protection bit in a particular translation table entry associated with a storage block; resetting the address translation protection bit to disable write protection for the storage block based on the determination, the reset occurring without waiting for action by one or more other processors of the computing environment; and Including, a processor among the one or more other processors attempts write access to the storage block without clearing or modifying the associated translation lookaside buffer entry of the other processor, resulting in an address translation protection exception condition, and based on this, causes the other processor to check the address translation protection bits to identify that the address translation protection exception condition is an over-direction, and based on the check identifying that the address translation protection exception condition is an over-direction, allows write access to the storage block.

10. 10. The computer system of claim 9, wherein executing the instruction further comprises: terminating execution of the instruction based on resetting the address translation protection bit to disable write protection for the storage block without requiring a quiesce operation by the one or more other processors of the computing environment.

11. 10. The computer system of claim 9, wherein executing the instruction further comprises clearing a translation lookaside buffer entry within the processor that is associated with the particular translation table entry.

12. 10. The computer system of claim 9, wherein executing the instruction further comprises resetting a protection indication of a translation lookaside buffer entry within the processor that is associated with the particular translation table entry.

13. 13. The computer system of claim 9, wherein executing the instructions further comprises broadcasting a signal to one or more other processors of the computing environment that clears or modifies a translation lookaside buffer entry in the one or more other processors that is associated with the particular translation table entry.

14. 14. The computer system of claim 13, wherein executing the instructions further comprises testing the address translation protection bit in the particular translation table entry associated with the storage block, and wherein the broadcast is based at least in part on a result of the test.

15. 1. A computer-implemented method for facilitating processing within a computing environment, comprising: Executing, by the processor, instructions to perform an address translation protection reset operation, the executing instructions comprising: determining, by the processor, to reset an address translation protection bit in a particular translation table entry associated with a storage block; resetting the address translation protection bit to disable write protection for the storage block based on the determination, the reset occurring without waiting for action by one or more other processors of the computing environment; and Including, a processor of the one or more other processors attempts write access to the storage block without clearing or modifying its associated translation lookaside buffer entry, resulting in an address translation protection exception condition; and based on this, causes the other processor to examine the address translation protection bits to identify that the address translation protection exception condition is an over-direction; and based on the examination identifying that the address translation protection exception condition is an over-direction, allows write access to the storage block.

16. 16. The computer-implemented method of claim 15, wherein executing the instruction further comprises: terminating execution of the instruction based on resetting the address translation protection bit to disable write protection for the storage block without requiring a quiesce operation by the one or more other processors of the computing environment.

17. 16. The computer-implemented method of claim 15, wherein executing the instructions further comprises clearing a translation lookaside buffer entry within the processor that is associated with the particular translation table entry.

18. 16. The computer-implemented method of claim 15, wherein executing the instructions further comprises resetting a protection indication of a translation lookaside buffer entry within the processor that is associated with the particular translation table entry.

19. 19. The computer-implemented method of claim 15, wherein executing the instructions further comprises broadcasting a signal to one or more other processors of the computing environment that clears or modifies a translation lookaside buffer entry in the one or more other processors that is associated with the particular translation table entry.

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