Image pickup device and method for manufacturing the same

Abstract

To provide an imaging apparatus and a manufacturing method thereof that enable high-definition imaging with high signal-to-noise ratio and low crosstalk.SOLUTION: An imaging apparatus 2 includes a photodetector array 4 that includes a plurality of semiconductor layers 502. The plurality of semiconductor layers 502 is provided with a plurality of first mesas M1, a plurality of second mesas M2 having crest intervals narrower than the crest intervals of the plurality of first mesas M1, and a slab. The slab has an upper surface with which the plurality of first mesas M1 are in contact, and another upper surface which is in contact with the plurality of second mesas M2 and is located above the upper surface. The plurality of semiconductor layers 502 include a plurality of contact layers 612, and a stopper layer 510 in contact with the lower surfaces of the plurality of contact layers. The constituent element of the stopper layer 510 lacks any of the constituent elements of the plurality of contact layers 612 or contains a constituent element different from any constituent element of the plurality of contact layers.SELECTED DRAWING: Figure 21

Description

[Technical Field]

[0001] The present invention relates to an imaging device and a method for manufacturing an imaging device. [Background technology]

[0002] A photodetector array, in which photodetectors are arranged in a two-dimensional array, is an important device that determines the performance of an imaging device (for example, Patent Documents 1 and 2). The image obtained by the imaging device (hereinafter referred to as a captured image) can be made higher-definition by narrowing the pitch of the photodetectors arranged in the photodetector array (for example, Patent Document 1).

[0003] Regarding the pitch of the photodetectors, a technology has been reported that narrows the pitch of the photodetectors by surrounding multiple photodetectors arranged in a two-dimensional array with a terrace and arranging the electrodes that were previously provided between the photodetectors between the photodetectors and the terrace (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-206898 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-107383 Summary of the Invention [Problem to be solved by the invention]

[0005] To manufacture a photodetector array, first, semiconductor layers stacked on a substrate (hereinafter referred to as a semiconductor multilayer film) are etched by, for example, reactive ion etching to form multiple mesas, and then individual electrodes are connected to each of the multiple mesas to form multiple photodetectors arranged in a two-dimensional array.

[0006] The performance (e.g., signal-to-noise ratio and crosstalk) of the photodetector array is optimized by stopping the etching when the etched grooves separating the mesas (i.e., the grooves formed by etching) reach a specific semiconductor layer. The timing at which the etched grooves reach a specific semiconductor layer (hereinafter referred to as the stopper layer) can be detected, for example, by using an endpoint detector to monitor elements released into the plasma atmosphere during etching of the semiconductor multilayer film.

[0007] The mesas formed by reactive ion etching or other techniques are forward mesas, with widths gradually increasing toward the bottom. Therefore, narrowing the mesa pitch achieved by etching also narrows the bottom of the etched grooves, ultimately transforming them from flat surfaces into lines. Even when the etched grooves with linear bottoms reach the stopper layer, only a very small amount of elements are released from the stopper layer, so the types and amounts of elements in the plasma atmosphere remain almost unchanged.

[0008] Therefore, if the pitch of the photodetector array is narrowed to increase the resolution of the captured image, the output of the end point detector (hereinafter referred to as the end point detector signal) will hardly change even when the etching groove reaches the stopper layer.

[0009] In this case, it is difficult to detect the timing when the etching groove reaches the stopper layer using the endpoint detector signal, and it is difficult to optimize the performance of the photodetector array (specifically, the signal-to-noise ratio and crosstalk). Therefore, an object of the present invention is to solve these problems. [Means for solving the problem]

[0010] In one embodiment, an imaging device includes a photodetector array having a plurality of semiconductor layers and a readout circuit connected to the photodetector array, the plurality of semiconductor layers being arranged to form a plurality of first mesas, a plurality of second mesas each having a peak spacing narrower than a peak spacing of the plurality of first mesas, and a slab in contact with the plurality of first mesas and the plurality of second mesas, the slab having a bottom surface, a top surface on which the plurality of first mesas are arranged, and another top surface on which the plurality of second mesas are arranged and spaced apart from the bottom surface, the plurality of semiconductor layers being arranged to form a plurality of contact layers each having a constant distance from the bottom surface of the slab, and a readout circuit connected to the photodetector array, the plurality of semiconductor layers being arranged to form a plurality of contact layers each having a constant distance from the bottom surface of the slab, the plurality of contact layers being spaced apart ... and a stopper layer arranged between the tops of the plurality of first mesas and the upper surface of the slab so as to be in contact with the plurality of contact layers, the plurality of contact layers having a plurality of first contact layers arranged between the tops of the plurality of first mesas and the upper surface of the slab so as to be spaced apart from the upper surface, and at least one second contact layer arranged between the tops of the plurality of second mesas and the lower surface of the slab, the constituent elements of the stopper layer lacking a first constituent element among the constituent elements of the plurality of contact layers or including a second constituent element different from any of the constituent elements of the plurality of contact layers, and the readout circuit is configured to generate an image signal from photocarriers generated in the plurality of second mesas. [Effects of the Invention]

[0011] In one aspect, the present invention provides an imaging device that can detect the timing at which the etching groove reaches the stopper layer using an endpoint detector signal, even if the pitch of the photodetector array is narrowed. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a cross-sectional view showing an example of an imaging device 2 according to an embodiment. [Figure 2] 2A to 2C are cross-sectional views showing steps in an example of a method for manufacturing the imaging device 2. FIG. [Figure 3] 3A to 3C are cross-sectional views showing steps in an example of a method for manufacturing the imaging device 2. FIG. [Figure 4] 4A to 4C are cross-sectional views showing steps in an example of a method for manufacturing the imaging device 2. FIG. [Figure 5] 5A to 5C are cross-sectional views showing steps in an example of a method for manufacturing the imaging device 2. FIG. [Figure 6] 6A to 6C are cross-sectional views showing steps in an example of a method for manufacturing the imaging device 2. FIG. [Figure 7] 7A to 7C are cross-sectional views showing steps in an example of a method for manufacturing the imaging device 2. FIG. [Figure 8] 8A to 8C are cross-sectional views showing steps in an example of a method for manufacturing the imaging device 2. FIG. [Figure 9] 9A to 9C are cross-sectional views showing steps in an example of a method for manufacturing the imaging device 2. FIG. [Figure 10] FIG. 10 is a plan view showing a part of the first to third hard masks 22a, 22b, and 22c formed on the surface of the upper electrode layer 18. As shown in FIG. [Figure 11] FIG. 11 is a diagram showing the change over time in the output of the quadrupole mass spectrometer. [Figure 12] FIG. 12 is a plan view showing some of the hard masks used in Comparative Example 1. As shown in FIG. [Figure 13] FIG. 13 is a graph showing the change over time in the QMS signal intensity obtained by etching in Comparative Example 1. [Figure 14] FIG. 14 is a cross-sectional view of the semiconductor layers 102 in which the lower contact layer 12 is just etched through the hard masks C 122a and 22c. [Figure 15] FIG. 15 is a plan view showing some of the hard masks used in Comparative Example 2. As shown in FIG. [Figure 16] FIG. 16 is a graph showing the change over time in the QMS signal intensity obtained by etching in Comparative Example 2. [Figure 17] FIG. 17 is a cross-sectional view of the plurality of semiconductor layers 102 in which the lower contact layer 12 is just etched through the hard masks C222b and C22c. [Figure 18] FIG. 18 is a cross-sectional view of the plurality of semiconductor layers 102 in Comparative Example 2 at a timing immediately after the QMS signal intensity starts to decrease. [Figure 19] FIG. 19 is a diagram showing an example of the QMS signal intensity obtained by etching in Comparative Example 3. [Figure 20] FIG. 20 is a cross-sectional view of the semiconductor layers 102 at the etching endpoint EFT3 shown in FIG. [Figure 21] FIG. 21 is a diagram illustrating an example of an imaging device 2 manufactured by the manufacturing method according to the embodiment. [Figure 22] FIG. 22 is a cross-sectional view showing the shape of a region 49 of the photodetector array 4 that is occupied by a semiconductor. [Figure 23] FIG. 23 is a diagram showing an example of the layer structure of the semiconductor region 49. As shown in FIG. [Figure 24] FIG. 24 is a diagram comparing the plurality of unprocessed semiconductor layers 102 with the plurality of semiconductor layers 502 of the photodetector array 4. In FIG. [Figure 25] FIG. 25 is a diagram showing cross sections of a plurality of semiconductor layers 502 obtained by the manufacturing method of the first modification. [Figure 26] FIG. 26 is a diagram showing cross sections of a plurality of semiconductor layers 502 obtained by the manufacturing method of the second modification. [Figure 27] FIG. 27 is a cross-sectional view showing an example of a plurality of semiconductor layers 102 processed by the manufacturing method of the second modification. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and their equivalents. Parts having the same structure are designated by the same reference numerals even in different drawings, and their description will be omitted.

[0014] (Embodiment) (1) Manufacturing method 1 is a cross-sectional view showing an example of an imaging device 2 according to an embodiment. The imaging device 2 according to the embodiment includes a photodetector array 4 and a readout circuit 6 connected to the photodetector array 4.

[0015] The photodetector array 4 has a plurality of first mesas M1 and a plurality of second mesas M2 whose top spacing is narrower than that of the first mesas M1. The readout circuit 6 is an integrated circuit that generates image signals from photocarriers generated in the plurality of second mesas M2.

[0016] 2 to 9 are cross-sectional views showing steps in an example of a method for manufacturing the imaging device 2. Hereinafter, the method for manufacturing the imaging device 2 will be described with reference to FIGS.

[0017] (1-1) Growth of semiconductor layer (see Figure 2(a)) 2 to 9, for example, a buffer layer 8, a stopper layer 10, a lower contact layer 12 in contact with the stopper layer 10, a light absorption layer 14, an upper contact layer 16, and an upper electrode layer 18 are grown in this order on a semiconductor substrate (not shown). These semiconductor layers are grown by, for example, molecular beam epitaxy or metal organic chemical vapor deposition.

[0018] The semiconductor substrate (not shown) is, for example, n-type GaSb. The buffer layer 8 is non-doped GaSb (i.e., GaSb that is not intentionally doped) with a thickness of 0.5 to 2.0 μm (preferably, 1 μm). The carrier concentration of the buffer layer 8 is 5×10 15 ~1×10 16 cm -3 The conductivity type may be either n-type or p-type.

[0019] The stopper layer 10 is an InAs layer having a thickness of 1 to 4 μm (preferably 2 μm). 0.91 Sb 0.09 The conductivity type of the stopper layer 10 is p-type, and the carrier concentration is 5×10 17 ~2×10 18 cm -3 (Preferably 1 × 10 18 cm -3 ) InAs 0.91 Sb 0.09is a semiconductor that is lattice-matched to the GaSb substrate. The stopper layer 10 is provided to determine the etching endpoint (i.e., the timing to end the etching). In the examples shown in FIGS. 2 to 9, the stopper layer 10 is also used as a semiconductor layer (so-called common electrode layer) that connects a common electrode, which will be described later.

[0020] The stopper layer 10 is preferably a semiconductor layer whose cutoff wavelength is shorter than that of the light absorbing layer 14. For example, if the cutoff wavelength of the light absorbing layer 14 is 5.5 μm, the cutoff wavelength of the stopper layer 10 is 4.0 μm. If the cutoff wavelength of the light absorbing layer 14 is 9.5 μm, the cutoff wavelength of the stopper layer 10 is 7.0 μm.

[0021] The stopper layer 10 may be a semiconductor superlattice (e.g., an InAs / InAsSb superlattice). A semiconductor superlattice is a semiconductor layer in which ultra-thin films of a semiconductor (e.g., InAs) and ultra-thin films of another semiconductor (e.g., InAsSb) are alternately stacked to form a miniband. The thickness of each semiconductor included in the semiconductor superlattice is, for example, 10 nm or less.

[0022] A semiconductor superlattice with a cutoff wavelength of 7.0 μm is, for example, a 6.1 nm thick InAs layer and a 1.6 nm thick InAs 0.5 Sb 0.5 A semiconductor superlattice with a cutoff wavelength of 4.0 μm is, for example, an InAs / InAsSb superlattice with a thickness of 2.4 nm and an InAs layer with a thickness of 0.63 nm. 0.5 Sb 0.5 It is an InAs / InAsSb superlattice with alternating layers.

[0023] The lower contact layer 12 is a semiconductor superlattice in which InAs layers and GaSb layers are alternately stacked (i.e., an InAs / GaSb superlattice). The InAs / GaSb superlattice is a type-2 superlattice.

[0024] The number of InAs layers and GaSb layers in the lower contact layer 12 is 50 to 200 (preferably 100). The thickness of the InAs is 4.2 nm, and the thickness of the GaSb is 2.1 nm. The conductivity type of the lower contact layer 12 is p-type, and the carrier concentration is 2×10 17 ~1×10 18 cm -3 (Preferably 5 × 10 17 cm -3 )

[0025] The light absorbing layer 14 is a non-doped InAs / GaSb superlattice. The number of InAs and GaSb layers in the light absorbing layer 14 is 250 to 1000 (preferably 500). The thickness of the InAs is 4.2 nm, and the thickness of the GaSb is 2.1 nm. The curing concentration of the light absorbing layer 14 is, for example, 5×10 15 ~1×10 16 cm -3 is.

[0026] The light absorbing layer 14 may be intentionally doped. In this case, the conductivity type of the light absorbing layer 14 may be either n-type or p-type. The carrier concentration of the intentionally doped light absorbing layer 14 is, for example, sufficiently lower than the carrier concentration of the lower contact layer 12 and the upper contact layer 16 (preferably, 1×10 16 ~5×10 16 cm -3 )

[0027] The upper contact layer 16 is also an InAs / GaSb superlattice, like the lower contact layer 12. The number of InAs and GaSb layers in the upper contact layer 16 is 50 to 200 (preferably 100). The thickness of the InAs is 4.2 nm, and the thickness of the GaSb is 2.1 nm. The conductivity type of the upper contact layer 16 is n-type, and the carrier concentration is 2×10 17 ~1×10 18 cm -3 (Preferably 5 × 10 17 cm -3 )

[0028] The upper electrode layer 18 is made of InAs and has a thickness of 10 to 40 nm (preferably 20 nm). The conductivity type of the upper electrode layer 18 is n-type, and the carrier concentration is 5×10 17 ~2×10 18 cm -3 (Preferably 1 × 10 18 cm -3 )

[0029] The optical absorption layer 14 is configured to absorb light (e.g., infrared light) incident on the second mesa M2 (see FIG. 1) through the stopper layer 10 and generate photocarriers. The superlattice structure (composition and thickness of each superlattice layer) of the optical absorption layer 14 is the same as that of the lower contact layer 12. Therefore, no band discontinuity occurs at the interface between the optical absorption layer 14 and the lower contact layer 12.

[0030] Therefore, photocarriers (e.g., holes) generated in the photoabsorption layer 14 can move smoothly to the lower contact layer 12. Similarly, photocarriers (e.g., electrons) generated in the photoabsorption layer 14 can move smoothly to the upper contact layer 16. Note that since the photoabsorption layer 14 and the lower contact layer 12 have the same band gap, photocarriers are also generated in the lower contact layer 12. However, most of the photocarriers generated in the lower contact layer 12 recombine and disappear. Similarly, photocarriers are also generated in the upper contact layer 16, but most of the photocarriers generated in the upper contact layer 16 recombine and disappear.

[0031] The cutoff wavelength of the light absorption layer 14 can be adjusted by the thickness of each superlattice layer of the InAs / GaSb superlattice. For example, the cutoff wavelength of an InAs / GaSb superlattice in which 4.2 nm thick InAs and 2.1 nm thick GaSb are alternately stacked is 10.3 μm.

[0032] The InAs / GaSb superlattice of each of the lower contact layer 12, the light absorption layer 14, and the upper contact layer 16 may include an InSb layer sandwiched between an InAs layer and a GaSb layer. The InSb layer suppresses strain that occurs in the InAs / GaSb superlattice due to lattice mismatch with the GaSb substrate.

[0033] As shown in the above example, the manufacturing method of the embodiment grows a plurality of unprocessed semiconductor layers 102 (i.e., a semiconductor multilayer film) including, in this order, a stopper layer 10, a semiconductor layer 112 (hereinafter referred to as a contact layer) in contact with the stopper layer 10, and a top layer 118. A semiconductor layer is a layer of one type of semiconductor (i.e., a single semiconductor layer) or a layered composite formed by combining multiple semiconductors (e.g., a semiconductor superlattice or quantum dots). In the example shown in FIG. 2, the contact layer 112 is the lower contact layer 12. The top layer 118 is the upper electrode layer 18.

[0034] The stopper layer 10 has a lower surface 204 in contact with the underlayer 108 and an upper surface 202 (hereinafter referred to as the stopper upper surface) in contact with the contact layer 112. In the example shown in FIG.

[0035] The stopper layer 10 and the contact layer 112 are configured so that a certain element is contained in only one of the constituent elements of the stopper layer 10 and the constituent elements of the contact layer 112 .

[0036] Constituent elements are elements that make up an element (e.g., Si) or a compound (e.g., GaSb), and are included in the respective chemical formulas (e.g., Si, Ga, and Sb).Dopants in semiconductors are impurities, not constituent elements.

[0037] The stopper layer 10 (i.e., InAs 0.91 Sb 0.09 The constituent elements of the stopper layer 10 (i.e., a single layer of InAs / GaSb) are In, As, and Sb. The constituent elements of the lower contact layer 12 (i.e., an InAs / GaSb superlattice) are In, As, Ga, and Sb. Therefore, the element contained in only one of the constituent elements of the stopper layer 10 and the constituent elements of the contact layer 112 (hereinafter referred to as the "specific constituent element") is Ga.

[0038] The composition ratio of an element (i.e., a "specific constituent element") contained in only one of the constituent elements of the stopper layer 10 and the constituent elements of the contact layer 112 is preferably 1% or more. If the composition ratio is 1% or more, it becomes easy to detect an end-point detector signal (e.g., a QMS signal described later) generated by the element (i.e., the "specific constituent element").

[0039] (1-2) Formation of hard mask (see Figures 2(b) to 3(a) and Figure 10) Finally, an SiO2 film 20 having a thickness of 250 to 1000 nm (preferably 500 nm) is formed on the surface of the grown upper electrode layer 18 (see FIG. 2(b)). A photoresist film pattern (hereinafter referred to as a resist pattern) is formed on the surface of the formed SiO2 film 20 by photolithography.

[0040] The SiO2 film 20 is etched using the formed resist pattern to form a plurality of first hard masks 22a (see FIG. 3(a)) and a plurality of second hard masks 22b spaced apart by a spacing MG2 narrower than the spacing MG1 between the plurality of first hard masks 22a. Furthermore, a third hard mask 22c is formed together with the plurality of first hard masks 22a and the plurality of second hard masks 22b. Hereinafter, the spacing MG1 between the plurality of first hard masks 22a will be referred to as the first mask spacing. Hereinafter, the spacing MG2 between the plurality of second hard masks 22b will be referred to as the second mask spacing. The SiO2 film 20 is etched by, for example, reactive ion etching. A fluorine-based gas is used as the reactive gas.

[0041] Fig. 10 is a plan view showing a portion of the first to third hard masks 22a, 22b, and 22c formed on the surface of the upper electrode layer 18. Fig. 3(a) is a cross-sectional view taken along line III(a)-III(a) in Fig. 10. Fig. 10 also shows line iii(a)-iii(a) perpendicular to line III(a)-III(a). The cross-sectional view taken along line iii(a)-iii(a) is substantially the same as the cross-sectional view shown in Fig. 3(a).

[0042] That is, the multiple first hard masks 22a are arranged so as to be spaced apart from one another by a first mask spacing MG1 along both the direction in which the III(a)-III(a) line extends (hereinafter referred to as the horizontal direction) and the direction in which the iii(a)-iii(a) line extends (hereinafter referred to as the vertical direction). On the other hand, the multiple second hard masks 22b are arranged so as to be spaced apart from one another by a second mask spacing MG2 that is narrower than the first mask spacing MG1 along both the horizontal direction and the vertical direction. The multiple first hard masks 22a and the multiple second hard masks 22b are preferably rectangular masks (e.g., square masks) of the same size in a plan view (i.e., when viewed from directly above).

[0043] 10, the plurality of second hard masks 22b are formed in a two-dimensional array in the pixel region R on the upper electrode layer 18. Outside the plurality of second hard masks 22b, a plurality of first hard masks 22a are formed in, for example, three layers so as to surround the pixel region R. Outside the plurality of first hard masks 22a, a frame-shaped third hard mask 22c is formed so as to surround the plurality of first hard masks 22a.

[0044] The first mask interval MG1 is, for example, 8 μm to 32 μm (preferably 16 μm). The second mask interval MG2 is, for example, 0.5 μm to 2 μm (preferably 1 μm). In the following description, the first mask interval MG1 is set to 16 μm, and the second mask interval MG2 is set to 1 μm.

[0045] The first mask interval MG1 is approximately the same as the interval MI1 (hereinafter referred to as the first mesa interval) between the tops T1 of adjacent first mesas M1 (see FIG. 22 described later). The second mask interval MG2 is approximately the same as the interval MI2 between the tops T2 of adjacent second mesas M2.

[0046] A "mesa" is a table-like protrusion with a flat top and steeply sloping sides. "Spacing" is the distance between an object (or a part thereof) and another object (or a part thereof). For example, the "first mask spacing MG1" is the distance between one end of a certain hard mask among the plurality of first hard masks 22a (see FIG. 3(a)) and another hard mask among the plurality of first hard masks 22a that is closest to the said end. The "first mesa spacing MI1" is the distance between the top of a certain mesa among the plurality of first mesas M1 (see FIG. 22) and the top of another mesa among the plurality of first mesas M1 that is closest to the said top.

[0047] As shown in the above example, in the manufacturing method of the embodiment, a plurality of first hard masks 22a and a plurality of second hard masks 22b spaced apart by a spacing MG2 narrower than the spacing MG1 between the plurality of first hard masks 22a are formed on the surface of the top layer 118.

[0048] (1-3) Etching of the semiconductor layer (see Figures 3(b) to 4(b)) After the first to third hard masks 22a to 22c are formed, the semiconductor layers 102 are etched through the first to third hard masks 22a to 22c. The etching is performed by, for example, reactive ion etching. The reactive gas is, for example, a chlorine-based gas.

[0049] FIG. 3(b) shows a cross section at a point in time (hereinafter referred to as a first point in time Tm1) when etching has progressed to form a groove (hereinafter referred to as an etched groove) EG1 between the first hard mask 22a and the lower contact layer 12. FIG. 4(a) shows a cross section at a point in time (hereinafter referred to as a second point in time Tm2) when etching has further progressed to form the etched groove EG1 between the first hard mask 22a and the upper surface 202 of the stopper layer 10. FIG. 4(b) shows a cross section at a point in time (hereinafter referred to as a third point in time Tm3) when etching has further progressed to form the etched groove EG2 between the second hard mask 22b and the stopper layer 10. In this embodiment, etching of the semiconductor layers 102 is terminated at the third point in time Tm3. That is, the third point in time Tm3 is the etching endpoint in this embodiment.

[0050] The etching rate of the region sandwiched between multiple closely spaced second hard masks 22b is slower than the etching rate of the region sandwiched between multiple widely spaced first hard masks 22a due to the microloading effect (see Figures 3(b) to 4(b)).

[0051] In this embodiment, Ga (i.e., the above-mentioned "specific constituent element") released from the semiconductor layers 102 (see FIG. 2(a)) is monitored using, for example, a quadrupole mass spectrometer (hereinafter referred to as QMS) during etching of the semiconductor layers 102. FIG. 11 is a diagram showing the time change in the output of the quadrupole mass spectrometer (hereinafter referred to as QMS signal). The vertical axis represents the intensity of the QMS signal generated by Ga. The QMS signal is one of the endpoint detector signals mentioned above.

[0052] The horizontal axis represents the time (hereinafter referred to as etching time) that has elapsed since the start of etching of the semiconductor layers 102. The vertical and horizontal axes are linear scales (the same applies to FIG. 13 and the like, which will be described later).

[0053] 11 shows the intensity of the QMS signal (hereinafter referred to as QMS signal intensity) generated during etching of the plurality of semiconductor layers 102 (the same applies to the QMS signals described in Comparative Examples 1 to 3 below). The dashed line shows the intensity of the QMS signal generated when etching of the plurality of semiconductor layers 102 is continued beyond the original etching end point (the same applies to the QMS signals described in Comparative Examples 1 to 3).

[0054] The horizontal axis of FIG. 11 represents the first to third points in time Tm1 to Tm3 described with reference to FIGS. 3(b) to 4(b). An InAs / GaSb superlattice extends from the upper contact layer 16 (see FIG. 2(a)) to the lower contact layer 12. Therefore, the QMS signal intensity of Ga remains substantially constant until the second point in time Tm2, ​​when the etching grooves EG1 between the first hard masks 22a (see FIG. 4(a)) reach the upper surface 202 of the stopper layer 10 (i.e., the upper surface of the stopper). After the second point in time Tm2, ​​the stopper layer 10, which does not contain Ga, is exposed between the first hard masks 22a, and the QMS signal intensity rapidly decreases.

[0055] As etching progresses further and reaches a third time point Tm3 (see FIG. 4(b)), the etching groove EG2 between the second hard masks 22b reaches the stopper upper surface 202. As shown in FIG. 11, at the third time point Tm3, there is almost no characteristic change in the QMS signal intensity (e.g., a sudden increase in the rate of decrease). Therefore, it is difficult to detect the third time point Tm3, which is the most preferable etching end point, from the QMS signal intensity.

[0056] Therefore, in this embodiment, the etching end point EFT is calculated based on the etching time dt at the timing DT immediately after the decrease in the Ga QMS signal intensity starts (hereinafter referred to as the decrease start timing).

[0057] Specifically, the etching time dt at the decrease start timing DT is multiplied by a correction coefficient C (described later) to calculate the time (= dt × C) during etching, and the etching is terminated when the calculated time (= dt × C) has elapsed. In other words, the etching time deft at the etching end point EFT is the time obtained by multiplying the etching time dt at the decrease start timing DT by the correction coefficient C.

[0058] The decrease start timing DT can be easily detected by monitoring the QMS signal intensity, so etching can be terminated at the third time Tm3 (see FIG. 4(b)) when the etching grooves EG2 (see FIG. 4(b)) between the multiple second hard masks 22b reach the stopper upper surface 202.

[0059] The correction coefficient C is the ratio (=V1 / V2) of the etching rate V1 between the plurality of first hard masks 22a to the etching rate V2 between the plurality of second hard masks 22b. The etching rate is the rate at which the thickness of the semiconductor layer is reduced by etching.

[0060] The etching rate depends on the spacing between the hard masks. Therefore, the etching rate V1 is measured in advance using hard masks spaced at the same spacing MG1 as the plurality of first hard masks 22a. Similarly, the etching rate V2 is measured in advance using hard masks spaced at the same spacing MG2 as the plurality of second hard masks 22b. The correction coefficient C is calculated based on the measured values ​​of the etching rates V1 and V2 thus obtained.

[0061] According to measurements by the inventors, in regions where the spacing between hard masks (hereinafter referred to as mask spacing) is 5 μm or more, the etching rate of the multiple semiconductor layers 102 described with reference to FIG. 2(a) hardly changes. On the other hand, in regions where the mask spacing is narrower than 5 μm, the etching rate gradually decreases as the mask spacing decreases. For example, the etching rate when the mask spacing is 1 μm is 0.8 times the etching rate when the mask spacing is 16 μm.

[0062] 2 to 9, the gap MG1 of the first hard mask 22a is 16 μm and the gap MG2 of the second hard mask 22b is 1 μm, so the correction coefficient C is 1.25. Therefore, in the example described with reference to FIGS. 2 to 9, etching is terminated when the etching time dt is multiplied by 1.25 immediately after the decrease in the QMS signal intensity of Ga begins.

[0063] As a result, as shown in FIG. 4(b), protrusions 23 are formed on the surface of the stopper layer 10, and a plurality of first mesas M1, each including this protrusion 23, are formed. Furthermore, a frame-shaped terrace 48 is formed surrounding the plurality of first mesas M1, and a plurality of second mesas M2 are formed, each lower than the plurality of first mesas M1 and having a bottom surface substantially coinciding with the upper surface of the stopper layer 10 (i.e., the stopper upper surface 202). Furthermore, a slab (see "(2) Structure and Operation" described later) is formed, including the portions of the stopper layer 10 other than the protrusions 23. The spacing MI2 (see FIG. 22) between the tops of the plurality of second mesas M2 is narrower than the spacing MI1 between the tops of the plurality of first mesas M1 (i.e., the first mesa spacing), reflecting the spacing MG2 between the plurality of hard masks 22b.

[0064] Even if the third hard mask 22c is not formed, it is possible to obtain a signal that is substantially the same as the QMS signal in Fig. 11. For example, by arranging multiple hard masks that are the same size and spaced apart as the multiple first hard masks 22a instead of the third hard mask 22c, it is possible to obtain a QMS signal that is substantially the same as that in Fig. 11.

[0065] Therefore, even if the third hard mask 22c is not formed, it is possible to calculate the etching end point EFT based on the decrease start timing DT described with reference to Fig. 11. Therefore, in such a case, the terrace 48 does not need to be formed.

[0066] As shown in the above example, in the manufacturing method of the embodiment, the semiconductor layers 102 are etched via the first hard masks 22a and the second hard masks 22b to form the first mesas M1 and the second mesas M2. When the first to third hard masks 22a, 22b, and 22c are formed on the surface of the top layer 118, the semiconductor layers 102 are etched via these hard masks to form the first mesas M1, the second mesas M2, and the terrace 48.

[0067] The manufacturing method of the embodiment further monitors, during etching of the semiconductor layers 102, a signal (e.g., a QMS signal) generated by a specific element emitted from the semiconductor layers 102 by the etching. The "specific element" refers to an element contained in only one of the elements constituting the stopper layer 10 and the elements constituting the contact layer 112.

[0068] In the manufacturing method of the embodiment, etching of the multiple semiconductor layers 102 is terminated based on the intensity of the above signal so that each of the multiple first mesas M1 (see Figure 4(b)) includes a portion of the stopper layer 10 (specifically, the convex portion 23 on the surface of the stopper layer).

[0069] According to the embodiment, the height of the second mesa M2 can be controlled to be lower than the height of the first mesa M1, thereby preventing the second mesa M2 from becoming thinner due to excessive etching (see Comparative Example 2). The height of the first mesa refers to the distance H1 between the top T1 and the bottom B1 of the first mesa M1 (see FIG. 22). The height of the second mesa refers to the distance H2 between the top T2 and the bottom B2 of the second mesa M2.

[0070] The distance MG1 between adjacent first hard masks 22a (i.e., the first mask distance) is preferably constant. If the distance MG1 between adjacent first hard masks 22a is constant, etching of the stopper layer 10 starts simultaneously between the plurality of first hard masks 22a. As a result, the decrease in the QMS signal starts suddenly, making it easy to detect the decrease start timing DT.

[0071] More preferably, the distance MG3 between the first hard mask 22a (referred to as the fourth hard mask 22d) closest to the pixel region R (see FIG. 3(a)) and the second hard mask 22e closest to this hard mask 22d is the first mask distance MG1 (constant distance). Similarly, the distance MG4 between the first hard mask 22f closest to the third hard mask 22c and the third hard mask 22c is also preferably the first mask distance MG1 (constant distance).

[0072] When these conditions are met, etching of the stopper layer 10 starts simultaneously in a wide region sandwiched between the third hard mask 22c and the pixel region R, making it even easier to detect the decrease start timing DT.

[0073] Pixels are formed from the second mesas M2 (see FIG. 1) formed from the portions covered with the plurality of second hard masks 22b. Since the pitch and spacing of pixels in an imaging device are often constant, it is preferable that the spacing between adjacent second hard masks 22b is also constant.

[0074] (1-4) Formation of electrodes (see Figures 5(a) to 6(a)) After the first mesas M1, the second mesas M2, and the terrace 48 are formed, the first to third hard masks 22a, 22b, and 22c are removed. Then, an SiO2 film 24 is formed to a thickness of 250 to 1000 nm (preferably 500 nm) to cover the first mesas M1, the second mesas M2, and the terrace 48 (see FIG. 5(a)). The SiO2 film 24 is formed by, for example, chemical vapor deposition.

[0075] A resist pattern (not shown) with openings is formed on the surface of the deposited SiO2 film 24 by photolithography. The SiO2 film 24 is etched using this resist pattern to form contact holes 26b, 26c on the tops of the second mesas M2 and between the first mesas M1 (see FIG. 5(b)). The SiO2 film 24 with the contact holes 26b, 26c formed therein is hereinafter referred to as a sidewall protective film. The SiO2 film 24 is etched by, for example, reactive ion etching. A fluorine-based gas, for example, is used as the reactive gas.

[0076] Thereafter, a common electrode 28 (see FIG. 6(a)) filling the contact holes 26c between the plurality of first mesas M1 and a plurality of individual electrodes 30 filling the contact holes 26b on the tops of the plurality of second mesas M2 are formed.

[0077] The common electrode 28 covers the tops of the first mesas M1, the sidewalls of the first mesas M1, and the spaces between the first mesas M1 via the sidewall protective film 124. The common electrode 28 and the individual electrodes 30 are formed by, for example, lift-off. The arrangement of the common electrode 28 and the individual electrodes 30 in a planar view will be described later in "(3-1-4) Electrodes, etc."

[0078] The portion of the common electrode 28 that fills the contact hole 26c and the individual electrode 30 form an ohmic contact. The common electrode 28 and the individual electrode 30 are, for example, a laminated film of a Ti film, a Pt film, and an Au film. The thickness of the Ti film is, for example, 25 nm to 100 nm (preferably, 50 nm). The thickness of the Pt film and the Au film is, for example, 100 nm to 400 nm (preferably, 200 nm).

[0079] Among the multiple second mesas M2, the multiple mesas DM (see FIG. 6(a)) formed along the periphery of the multiple second mesas M2 are hereinafter referred to as dummy mesas. Due to non-uniformity in photolithography and reactive ion etching, the dimensional error (difference between the design value and the actual dimension) of the dummy mesas DM often exceeds the tolerance. Therefore, elements in which individual electrodes 30b are connected to the dummy mesas DM (hereinafter referred to as dummy pixels) are not used as photodetectors. In this case, it is not necessary to form contact holes on the tops of the dummy mesas DM.

[0080] Of the plurality of second mesas M2, the mesas EM other than the dummy mesas DM are called effective mesas, and elements (hereinafter referred to as effective pixels) in which the individual electrodes 30c are connected to the effective mesas EM are used as photodetectors.

[0081] However, if the photolithography and reactive ion etching are performed with high accuracy and the dimensional error of the dummy mesas DM is within the allowable range, all of the multiple second mesas M2 connected to the individual electrodes 30 may be used as photodetectors.

[0082] (1-5) Connection of the readout circuit (see Figures 6(b) to 7) Solder bumps 32 are formed on the tops of the multiple first mesas M1 and the tops of the multiple second mesas M2 via the common electrode 28 or the individual electrodes 30 (see FIG. 6(b)). The solder bumps 32 are formed by, for example, lift-off.

[0083] After the solder bumps 32 are formed, the GaSb substrate on which the plurality of first mesas M1 and the plurality of second mesas M2 are formed is divided into a plurality of semiconductor chips (hereinafter referred to as sensor chips).

[0084] The sensor chip 34 (see FIG. 7) is connected by flip-chip bonding to the readout circuit 6. During connection, the solder bumps 32 (see FIG. 6(b)) formed on the sensor chip 34 are fused with the solder bumps (not shown) formed on the readout circuit 6 to form joints 38a, 38b, and 38c (see FIG. 7).

[0085] One end of each of the bonding portions 38a, 38b, and 38c is welded to the common electrode 28 or the individual electrode 30 (see FIG. 6(a)) of the sensor chip 34. The other end of each of the bonding portions 38a, 38b, and 38c is welded to an electrode 40 arranged on the surface of the readout circuit 6 (see FIG. 7).

[0086] The bonding portion 38a welded to the common electrode 28 connects the stopper layer 10 of the sensor chip 34 to a ground wiring 42 (i.e., a wiring connected to a reference potential) of the readout circuit 6. The bonding portion 38b (see FIG. 7) welded to the individual electrode 30b (see FIG. 6(a)) of the dummy mesa DM connects the dummy mesa DM to the readout circuit 6. The bonding portion 38c welded to the individual electrode 30c (see FIG. 6(a)) of the effective mesa EM connects the effective pixel (i.e., a photodetector having the effective mesa EM and the individual electrode 30c) to a pixel circuit 44 of the readout circuit 6.

[0087] (1-6) Removing the substrate (see Figures 8 and 9) An underfill 46 (see FIG. 8) is filled between the connected sensor chip 34 and readout circuit 6 and cured. The GaSb substrate (not shown) and buffer layer 8 are then removed by backside polishing and chemical etching to expose the stopper layer 10 (see FIG. 9). The photodetector array 4 described with reference to FIG. 1 is the sensor chip 34 with the stopper layer 10 exposed. An anti-reflection film may be formed on the backside of the exposed stopper layer 10. Through the above steps, the imaging device 2 is completed.

[0088] In the above example, the sensor chip 34 (see FIG. 9) obtained by dividing the GaSb substrate on which effective pixels are formed is connected to the readout circuit 6. However, the GaSb substrate on which effective pixels are formed may be directly connected to a plurality of readout circuits 6 and finally divided into a plurality of image pickup devices 2.

[0089] (2) Comparative Example (2-1) Comparative Example 1 The manufacturing method of Comparative Example 1 is similar to the manufacturing method of the embodiment described with reference to Figures 1 to 11. Therefore, the description of the same parts as those in the manufacturing method of the embodiment will be omitted or simplified.

[0090] 12 is a plan view showing some of the multiple hard masks used in Comparative Example 1. The hard masks in Comparative Example 1 are multiple hard masks C122a spaced apart by a first mask interval MG1, and a third hard mask 22c surrounding the multiple hard masks C122a.

[0091] The first mask spacing MG1 is the spacing between the multiple first hard masks 22a described with reference to FIG. 10. That is, the spacing MG1 between the multiple hard masks C122a is a spacing (e.g., 16 μm) at which the microloading effect hardly occurs. The structure (shape, size, material) of the multiple hard masks C122a is the same as the structure of the first hard mask 22a described with reference to FIG. 10, etc. The third hard mask 22c is the hard mask described with reference to FIG. 10 (the same applies to Comparative Example 2).

[0092] In Comparative Example 1, the plurality of semiconductor layers 102 (see FIG. 2(a)) are etched by reactive ion etching through hard masks C 122a and 22c. FIG. 13 is a graph showing the time change in QMS signal intensity obtained by etching in Comparative Example 1. The vertical axis represents the QMS signal intensity of Ga released from the plurality of semiconductor layers 102 (similar to FIGS. 16 and 19). The horizontal axis represents the etching time of the plurality of semiconductor layers 102 (similar to FIGS. 16 and 19).

[0093] 14 is a cross-sectional view of a plurality of semiconductor layers 102 in which the lower contact layer 12 is just etched through hard masks C122a and C22c. Just etching means that etching is stopped when the etching groove reaches the lower surface (i.e., the surface on the substrate side) of a certain semiconductor layer (e.g., the lower contact layer 12).

[0094] As is clear from FIG. 14, when the lower contact layer 12 is just etched, the stopper layer 10, which does not contain Ga as a constituent element, suddenly appears at the bottom of the etching groove C1EG1 between the hard masks C122a and C22c.

[0095] For this reason, after the just-etching timing JET1 (see FIG. 13), the Ga QMS signal intensity rapidly decreases. Therefore, in Comparative Example 1, etching is terminated at timing DT1 (decrease start timing) immediately after the Ga QMS signal intensity starts to decrease. That is, the etching end point EFT1 in Comparative Example 1 is the decrease start timing DT1. Because the decrease start timing DT1 is easy to detect, Comparative Example 1 makes it possible to form a mesa C1M1 (see FIG. 14) that includes just the right amount of semiconductor layers (specifically, the lower contact layer 12 to the upper electrode layer 18) that realize the function of an effective pixel.

[0096] 14, however, the spacing between mesas C1M1 formed by Comparative Example 1 is approximately the same as the spacing between hard masks C122a, and is therefore wide. Therefore, the manufacturing method of Comparative Example 1 cannot form fine pixels.

[0097] 1 to 11, effective mesas EM (see FIG. 9) that become minute pixels are formed using a plurality of closely spaced second hard masks 22b. Therefore, according to the manufacturing method of the embodiment, unlike the manufacturing method of Comparative Example 1, minute pixels that enable capturing of high-resolution images can be formed.

[0098] (2-2) Comparative Example 2 The manufacturing method of Comparative Example 2 is similar to the manufacturing method of the embodiment and the manufacturing method of Comparative Example 1. Therefore, explanations of the same steps as those of the manufacturing method of the embodiment or the manufacturing method of Comparative Example 1 will be omitted or simplified.

[0099] 15 is a plan view showing some of the multiple hard masks used in Comparative Example 2. The hard masks in Comparative Example 2 are multiple hard masks C222b spaced apart by second mask intervals MG2 and a third hard mask 22c surrounding the multiple hard masks C222b.

[0100] The second mask spacing MG2 is the spacing between the plurality of second hard masks 22b described with reference to Fig. 10. That is, the spacing MG2 between the plurality of hard masks C222b is a spacing (e.g., 1 µm) at which the microloading effect is significant. The structure (shape, size, material) of the plurality of hard masks C222a is the same as the structure of the second hard mask 22b described with reference to Fig. 10 etc.

[0101] In Comparative Example 2, multiple semiconductor layers 102 (see FIG. 2(a)) are etched by reactive ion etching through hard masks C222b and C22c. FIG. 16 shows the change over time in the QMS signal intensity obtained by etching in Comparative Example 2. As in Comparative Example 1, the etching end point EFT2 in Comparative Example 2 is the easily detectable decrease start timing DT2 (i.e., the timing immediately after the decrease in the QMS signal intensity begins).

[0102] 17 is a cross-sectional view of the semiconductor layers 102 in which the lower contact layer 12 is just-etched via the hard masks C222b and C22c. As shown in FIG. 17, the bottom of the etching groove C2EG2 obtained by just-etching the lower contact layer 12 is a linear narrow region (an extremely narrow region extending perpendicular to the paper surface).

[0103] For this reason, the stopper layer 10 is hardly etched even after the timing JET2 (see FIG. 16) of just etching the lower contact layer 12. Therefore, the QMS signal intensity of Ga is kept approximately constant for a while after just etching the lower contact layer 12.

[0104] During the etching of the semiconductor layers 102, the width of the hard mask C222b is gradually reduced, and as a result, the spacing between the hard masks C222b gradually increases. Therefore, after a while from the timing JET2 of just etching, the bottom of the etching groove C2EG2 increases, and the QMS signal intensity begins to decrease.

[0105] 18 is a cross-sectional view of the plurality of semiconductor layers 102 at the timing immediately after the decrease in the QMS signal intensity starts (i.e., decrease start timing DT2) in Comparative Example 2. As shown in FIG. 18, the width of the mesa C2M2 (see FIG. 17), which was wide up until the timing JET2 of just etching the lower contact layer 12, becomes narrower at the decrease start timing DT2. Because the etching endpoint ETF2 in Comparative Example 2 is the decrease start timing DT2, the width of the mesa C2M2 obtained in Comparative Example 2 is significantly narrower than the initial width of the hard mask C222b, as shown in FIG.

[0106] Therefore, the volume of the light absorption layer 14 included in the mesa C2M2 is smaller than the design value (i.e., the volume based on the initial width of the hard mask C222b), and the image signal generated from the photocarriers generated in the mesa C2M2 is smaller. Therefore, the signal-to-noise ratio of the image signal obtained from the effective pixel formed by Comparative Example 2 is low.

[0107] In the manufacturing method of Comparative Example 2, effective pixels are formed using multiple hard masks C222b with close spacing, and therefore it is possible to form fine pixels according to Comparative Example 2. However, in the manufacturing method of Comparative Example 2, the volume of the light absorption layer 14 is small, making it difficult to form effective pixels with a high signal-to-noise ratio.

[0108] 4(b), the manufacturing method of the embodiment can terminate etching when the etching grooves EG2 separating the multiple second mesas M2 reach the stopper layer 10, thereby preventing a decrease in the volume of the light absorption layer 14 due to a decrease in the mesa width. Therefore, the manufacturing method of the embodiment can form fine pixels that can obtain image signals with a high signal-to-noise ratio, unlike the manufacturing method of Comparative Example 2.

[0109] (2-3) Comparative Example 3 The manufacturing method of Comparative Example 3 is similar to that of Comparative Example 2. Therefore, the same steps as those in the manufacturing method of Comparative Example 2 will be omitted or simplified for description. Comparative Example 2 uses the hard masks C222b and C22c of Comparative Example 2 described with reference to FIG. 15. The difference between Comparative Example 3 and Comparative Example 2 is the etching end point.

[0110] 19 is a diagram showing an example of the QMS signal intensity obtained by etching in Comparative Example 3. The etching end point EFT2 (see FIG. 16) in Comparative Example 2 is the decrease start timing DT2, which is easy to detect. On the other hand, in Comparative Example 3, the etching end point EFT3 (see FIG. 19) is set before the decrease start timing DT2.

[0111] Specifically, in Comparative Example 3, first, the timing at which the lower contact layer 12 is just etched is calculated based on the etching rate between the narrowly spaced hard masks C222b (see FIG. 15). When the etching time reaches the calculated timing (i.e., the etching end point EFT3), the etching of the multiple semiconductor layers 102 is terminated. However, it is rare that the etching end point EFT3 calculated based on the etching rate between the hard masks coincides with the just-etching timing JET2.

[0112] 19 shows a case where the calculated etching end point EFT3 occurs before the timing JET2 of just etching. FIG. 20 is a cross-sectional view of the plurality of semiconductor layers 102 at the etching end point EFT3 shown in FIG. 19. Because the etching end point EFT3 in FIG. 19 occurs before the timing JET2 of just etching of the lower contact layer 12, the vicinity of the lower surface of the lower contact layer 12 remains unetched. As a result, a plurality of mesas C3M2 connected by the lower contact layer 12 are formed.

[0113] The lower contact layer 12 generates photocarriers because it has the same band gap as the light absorption layer 14. Some of the photocarriers generated in the lower contact layer 12 diffuse into the light absorption layer 14 and become a photocurrent.

[0114] Photocarriers generated in the lower contact layer 12 diffuse not only into the light absorption layer 14 directly above it, but also into the light absorption layer 14 of another mesa C3M2 through the lower contact layer 12, becoming a photocurrent. As a result, crosstalk of image signals occurs.

[0115] On the other hand, in the manufacturing method of the embodiment, as shown in FIG. 4(b), etching ends when the etching grooves EG2 separating the multiple second mesas M2 reach the stopper layer 10. Therefore, the multiple second mesas M2 in the embodiment are not connected by the lower contact layer 12. Therefore, according to the manufacturing method of the embodiment, unlike the manufacturing method of Comparative Example 3, it is possible to form fine pixels that can obtain image signals with a high signal-to-noise ratio and little crosstalk.

[0116] As is clear from the above description, the manufacturing method of the first embodiment makes it possible to manufacture an imaging device capable of capturing high-definition images with a high signal-to-noise ratio and little crosstalk.

[0117] (3) Structure and operation 21A and 21B are diagrams illustrating an example of an imaging device 2 obtained by the manufacturing method of the embodiment. Fig. 21A is a cross-sectional view of the imaging device 2. As shown in Fig. 21A, the imaging device 2 has a photodetector array 4 having a plurality of semiconductor layers 502, and a readout circuit 6 connected to the photodetector array 4. Fig. 21A is a reduced-scale drawing of Fig. 9, and some of the reference numerals shown in Fig. 9 are omitted.

[0118] Figure 21(b) is an enlarged plan view of one of the four corners of the photodetector array 4. The common electrode 28 (see Figure 9) and the individual electrodes 30a, 30b, and 30c are omitted in Figure 21(b). The cross-sectional view of the imaging device 2 shown in Figure 21(a) is taken along line XXI(a)-XXI(a) in Figure 21(b).

[0119] (3-1) Photodetector array The photodetector array 4 has a plurality of semiconductor layers 502, a sidewall protective film 124 (see FIG. 21(b)) that covers the plurality of semiconductor layers 502, and a plurality of electrodes, each connected to one of the plurality of semiconductor layers 502.

[0120] (3-1-1) Shape of semiconductor region 49 22 is a cross-sectional view showing the shape of a region 49 (hereinafter referred to as the semiconductor region) occupied by a plurality of semiconductor layers 502. The plurality of semiconductor layers 502 are arranged in the semiconductor region 49 so as to form a plurality of first mesas M1, a plurality of second mesas M2 whose spacing MI2 between their tops T2 is narrower than the spacing MI1 between their tops T1 (i.e., the first mesa spacing), and a terrace 48. The plurality of semiconductor layers 502 are further arranged in the semiconductor region 49 so as to form a slab 50 in contact with the plurality of first mesas M1, the plurality of second mesas M2, and the terrace 48.

[0121] A slab is a plate-shaped object (or plate-shaped portion). Slab 50 has a lower surface 52 (hereinafter referred to as the slab lower surface) and an upper surface (hereinafter referred to as the first slab upper surface 54a) on which a plurality of first mesas M1 are arranged. Slab 50 further has another upper surface (hereinafter referred to as the second slab upper surface 54b) on which a plurality of second mesas M2 are arranged, the other upper surface being more distant from slab lower surface 52 than first slab upper surface 54a.

[0122] The second mesas M2 (see FIG. 21(b)) are arranged in a two-dimensional array. The first mesas M1 are arranged in a two-dimensional array. The second mesas M2 include, for example, effective mesas EM arranged in a two-dimensional array and dummy mesas DM (see "(1-4) Formation of electrodes") surrounding the effective mesas EM. The terrace 48 is a frame-shaped protrusion surrounding the first mesas M1.

[0123] 22, the plurality of semiconductor layers 502 are arranged to form terraces 48. However, the terraces 48 may be omitted (see "(1-3) Etching of semiconductor layers").

[0124] (3-1-2) Layer structure of semiconductor region 49 23 is a diagram showing an example of the layer structure of the semiconductor region 49. The multiple semiconductor layers 502 include a stopper layer 510, a lower contact layer 512, a light absorption layer 514, an upper contact layer 516, and an upper electrode layer 518, in this order.

[0125] The stopper layer 510 is a semiconductor layer formed by subjecting the unprocessed stopper layer 10 described with reference to FIG. 2 to reactive ion etching or the like (see "(1) Manufacturing method"). The same applies to the lower contact layer 512 and the like.

[0126] The lower contact layer 512 is a plurality of semiconductor layers (hereinafter referred to as contact layers 612) arranged in the semiconductor region 49 so that the distance d from the slab lower surface 52 is a constant value. The stopper layer 510 is a semiconductor layer arranged in the semiconductor region 49 between the plurality of contact layers 612 and the slab lower surface 52 so as to be in contact with the plurality of contact layers 612.

[0127] 23, the contact layer 612 includes a plurality of first contact layers 612a disposed between the tops T1 of the plurality of first mesas M1 and the first slab upper surface 54a so as to be spaced apart from the first slab upper surface 54a. The contact layer 612 further includes a second contact layer 612b disposed between the tops T2 of the plurality of second mesas M2 and the slab lower surface 52.

[0128] -Constituent elements of stopper layer 510- As described above, the plurality of semiconductor layers 502 (see FIG. 23) are semiconductor layers formed from the plurality of unprocessed semiconductor layers 102 described with reference to FIG. 2. Therefore, the stopper layer 510 shown in FIG. 23 is made of InAs 0.91 Sb 0.09 The stopper layer 510 is a single layer of InAs / GaSb, and the lower contact layer 512 is an InAs / GaSb superlattice. Therefore, the constituent elements (In, As, and Sb) of the stopper layer 510 do not include Ga, which is one of the constituent elements (In, As, Ga, and Sb) of the lower contact layer 512.

[0129] As shown in the above example, the constituent elements of the stopper layer 510 (see FIG. 23) do not include a specific constituent element (hereinafter referred to as a first constituent element) among the constituent elements of the plurality of contact layers 612. The first constituent element is, for example, Ga.

[0130] The area of ​​the portion of the first slab upper surface 54a (see FIG. 22) surrounding the first mesas M1 in plan view is preferably 1% or more of the area of ​​the portion of the second slab upper surface 54b surrounding the second mesas M2 in plan view. When this condition is met, a sufficient amount of the first constituent element is released from between the first mesas M1 to measure an end-point detector signal (e.g., a QMS signal), making it easy to detect the decrease start timing DT (see FIG. 11).

[0131] (3-1-3) Mesa spacing, etc. As is clear from the explanation of "(1-3) Etching of the semiconductor layer," the interval MI1 (i.e., the first mesa interval) between the tops T1 of adjacent first mesas M1 (see FIG. 22) is preferably a constant interval. In other words, the interval between the top of each of the multiple first mesas M1 and the top of another mesa that is closest to the mesa among the multiple first mesas M1 is preferably constant.

[0132] Furthermore, the interval MI3 between the top T3 of the third mesa M3 of the plurality of first mesas M1 that is closest to the second slab upper surface 54b and the top T4 of the mesa M4 of the plurality of second mesas M2 that is closest to the third mesa M3 is also preferably the above-mentioned constant interval. Furthermore, the interval MI4 between the top T5 of the mesa M5 of the plurality of first mesas M1 that is closest to the terrace 48 and the top of the terrace 48 is also preferably the above-mentioned constant interval (first mesa interval MI1).

[0133] The top of the first mesa M1 and the top of the second mesa M2 are, for example, rectangular (e.g., square) shapes of the same size (see FIG. 21(b)). The top of the first mesa M1 and the top of the second mesa M2 preferably have a side length of 7 μm to 28 μm (e.g., 14 μm).

[0134] The horizontal pitch and vertical pitch of the multiple first mesas M1 are the same (hereinafter referred to as the first pitch). The horizontal pitch and vertical pitch of the multiple second mesas M2 are also the same (hereinafter referred to as the second pitch). The first pitch is preferably 15 μm to 60 μm (e.g., 30 μm). The second pitch is narrower than the first pitch, and is preferably 7.5 μm to 30 μm (e.g., 15 μm).

[0135] The first mesa interval MI1 is, for example, 8 μm to 32 μm (preferably 16 μm). The interval MI2 between the tops of adjacent second mesas M2 is, for example, 0.5 μm to 2 μm (preferably 1 μm).

[0136] (3-1-4) Electrodes, etc. The photodetector array 4 further includes a sidewall protective film 124 (see FIG. 21(b) and FIG. 9) that covers the surfaces of the multiple semiconductor layers 502, a common electrode 28 (see FIG. 9), and multiple individual electrodes 30. The sidewall protective film 124 (see FIG. 21(b)) includes a contact hole 26b that exposes the tops of the multiple second mesas M2, and a double contact hole 26c that passes between the multiple first mesas M1 and surrounds the multiple second mesas M2.

[0137] The common electrode 28 (see FIG. 9) fills contact holes 26c (see FIG. 21(b)) that pass between the multiple first mesas M1, and is connected to the first slab upper surface 54a (see FIG. 22) between the multiple first mesas M1. The common electrode 28 is further connected to the readout circuit 6 via a junction 38a (see FIG. 9) that is disposed between the first mesa M1 and the readout circuit 6 (see "(1-5) Connection of the readout circuit").

[0138] The multiple individual electrodes 30 (see FIGS. 9 and 6(a)) include multiple individual electrodes 30b filling contact holes on the dummy mesas DM and multiple individual electrodes 30c filling contact holes on the effective mesas EM. The multiple individual electrodes 30b are electrodes connected to the tops of the multiple dummy mesas DM, respectively. The multiple individual electrodes 30c are electrodes connected to the tops of the multiple effective mesas EM, respectively.

[0139] An element (i.e., an effective pixel) in which an individual electrode 30c is connected to an effective mesa EM is connected to a pixel circuit 44 of the readout circuit 6 by a junction 38c (see FIG. 9). The effective pixel is, for example, a VGA (Video Graphics Array) with 640 rows and 480 columns. A dummy mesa DM to which an individual electrode 30b is connected is connected to the readout circuit 6 by a junction 38b.

[0140] The common electrode 28 (see FIG. 9) may be connected to the stopper layer 510 in a region other than between the plurality of first mesas M1 (for example, between the plurality of first mesas M1 and the terrace 48). However, such a structure includes a region dedicated to connecting the common electrode 28 to the stopper layer 510 (hereinafter referred to as a dedicated connection region), which increases the size of the photodetector array 4.

[0141] Furthermore, forming a dedicated connection region increases the measurement error of the timing DT at which the end-point detector signal starts to decrease (see FIG. 11), thereby reducing the yield of the photodetector array 4. Therefore, it is preferable that the common electrode 28 be connected to the surface of the stopper layer 510 (i.e., the first slab upper surface 54a) between the multiple first mesas M1.

[0142] The measurement error of the decrease start timing DT is thought to increase for the following reasons: The width of the connection-only region is formed wide to reduce the contact resistance between the common electrode 28 and the stopper layer 510. As a result, the etching rate of the multiple semiconductor layers 102 (see FIG. 2(a)) is faster in the connection-only region (more precisely, the region etched to form the connection-only region) than between the multiple first mesas M1.

[0143] Therefore, the timing at which etching of the stopper layer 510 starts differs between the connection-only region and the plurality of first mesas M1, and as a result, the decrease start timing DT of the endpoint detector signal becomes unclear, which increases the measurement error of the decrease start timing DT.

[0144] (3-1-5) Comparison of the unprocessed semiconductor layer 102 and the semiconductor layer 502 of the photodetector array 4 2A and 2B are diagrams comparing the plurality of unprocessed semiconductor layers 102 with the plurality of semiconductor layers 502 of the photodetector array 4. Each of the plurality of semiconductor layers 502 of the photodetector array 4 (see FIG. 24A) is a semiconductor layer obtained by shaping any of the plurality of unprocessed semiconductor layers 102 (see FIG. 24B) by reactive ion etching or the like.

[0145] Therefore, the distance from the slab lower surface 52 of each of the multiple semiconductor layers 502 (see FIG. 24(a)) of the photodetector array 4 is the distance from the underlayer 108 (see FIG. 24(b)) of any one of the multiple unprocessed semiconductor layers 102 stacked on the underlayer 108. For example, the distance d (see FIG. 24(a)) from the slab lower surface 52 of the lower contact layer 512 of the photodetector array 4 is the distance D (see FIG. 24(b)) from the underlayer 108 of the unprocessed lower contact layer 12.

[0146] Furthermore, the structure in the thickness direction of each of the plurality of semiconductor layers 502 of the photodetector array 4 (hereinafter referred to as a first structure) is the structure in the thickness direction of any one of the plurality of unprocessed semiconductor layers 102 (hereinafter referred to as a second structure). For example, the structure in the thickness direction of the lower contact layer 512 of the photodetector array 4 is the structure in the thickness direction of the unprocessed lower contact layer 12.

[0147] The "structure of the semiconductor layer in the thickness direction" refers to a structure represented by the thickness of the "semiconductor layer" and the composition of the "semiconductor" when the "semiconductor layer" is a single semiconductor. When the "semiconductor layer" is a semiconductor superlattice, the "structure of the semiconductor layer in the thickness direction" refers to a structure represented by the stacking order of the superlattice layers of the "semiconductor superlattice," the thickness of each superlattice layer, and the composition of each superlattice layer.

[0148] For example, the stopper layer 510 of the photodetector array 4 (see FIG. 24(a)) is made of InAs 0.91 Sb 0.09In this case, the plurality of unprocessed semiconductor layers 102 (see FIG. 24(b)) includes a semiconductor layer (here, the unprocessed stopper layer 10) whose distance from the underlayer 108 is the same as the distance (here, zero) from the slab lower surface 52 of the stopper layer 510 (see FIG. 24(a)) of the photodetector array 4. This semiconductor layer (i.e., the unprocessed stopper layer 10) is a single layer of InAsSb whose thickness and composition are the same as those of the stopper layer 510 of the photodetector array 4.

[0149] To summarize the above explanation, the "structure in the thickness direction" of each of the plurality of semiconductor layers 502 (see FIG. 24(a)) in the photodetector array 4b and the plurality of unprocessed semiconductor layers 102 is a structure expressed as follows: First, when a certain semiconductor layer (hereinafter referred to as a first semiconductor layer) among the plurality of semiconductor layers 502 in the photodetector array 4 is a single layer of a first semiconductor, the "structure in the thickness direction" of the first semiconductor layer is a structure expressed by the thickness of the first semiconductor layer and the composition of the first semiconductor.

[0150] When the first semiconductor layer is a semiconductor superlattice (hereinafter referred to as the first semiconductor superlattice), the "thickness direction structure" of the first semiconductor layer is a structure represented by the order in which each superlattice layer of the first semiconductor superlattice is stacked, the thickness of each superlattice layer, and the composition of each superlattice layer.

[0151] On the other hand, when a semiconductor layer (hereinafter referred to as the second semiconductor layer) among the plurality of unprocessed semiconductor layers 102 is a single layer of the second semiconductor, the "thickness direction structure" of the second semiconductor layer is a structure represented by the thickness of the second semiconductor layer and the composition of the second semiconductor.

[0152] When the second semiconductor layer is a semiconductor superlattice (hereinafter referred to as the second semiconductor superlattice), the "thickness direction structure" of the second semiconductor layer is a structure represented by the order in which each superlattice layer of the second semiconductor superlattice is stacked, the thickness of each superlattice layer, and the composition of each superlattice layer.

[0153] (3-2) Readout circuit The light absorption layers 514 of the multiple effective mesas EM (see FIG. 9) absorb light (e.g., far-infrared light) incident on the photodetector array 4 from the slab lower surface 52, and generate photocarriers. The readout circuit 6 is configured to generate image signals from the photocarriers generated in the light absorption layers 514 of the multiple effective mesas EM by applying a voltage between the multiple individual electrodes 30c connected to the tops of each of the multiple effective mesas EM and the common electrode 28.

[0154] Specifically, the readout circuit 6 is, for example, an integrated circuit having a plurality of pixel circuits 44 connected to the effective pixels of the photodetector array 4. The effective pixels are elements having effective mesas EM and individual electrodes 30c, and are quantum-type photodetectors that output photocurrent in response to incident light.

[0155] Each pixel circuit 44 applies a constant voltage between the individual electrode 30c of the effective pixel and the common electrode 28, generating a photocurrent from photocarriers generated in the light absorption layer 514. Each pixel circuit 44 inputs the generated photocurrent to a capacitor (hereinafter referred to as a pixel capacitor) that each pixel circuit 44 has, and accumulates charge in the pixel capacitor (or releases charge that has been accumulated in the pixel capacitor in advance). The readout circuit 6 amplifies the potential of each pixel capacitor, which has changed due to the input of the photocurrent, using an amplifier (for example, a source follower amplifier), and outputs the amplified potential in sequence. The signal output from the readout circuit 6 at this time is an image signal.

[0156] (4) Variations (4-1) Variation 1 The manufacturing method of Modification 1 is similar to the manufacturing method described with reference to Figures 2 to 11. Therefore, the description of the same parts as those in the manufacturing method described with reference to Figures 2 to 11 will be omitted or simplified. The same applies to the imaging device obtained by the manufacturing method of Modification 1. The same applies to the manufacturing method and imaging device of Modification 2 described below.

[0157] 25 is a diagram showing cross sections of the semiconductor layers 502 obtained by the manufacturing method of Modification 1. In the example shown in Fig. 23, the lower contact layer 512 is just etched between the second mesas M2. Therefore, the second contact layers 612b are disposed between the tops T2 of the second mesas M2 and the second slab upper surface 54b so as to contact the second slab upper surface 54b.

[0158] On the other hand, in the manufacturing method of Modification 1, the etching grooves between the multiple second mesas M2 (see FIG. 25) penetrate through the lower contact layer 512 and invade the stopper layer 510. Therefore, the second contact layer 612b of Modification 1 is disposed between the tops T2 of the multiple second mesas M2 and the second slab upper surface 54b so as to be spaced apart from the second slab upper surface 54b.

[0159] It is not easy to accurately calculate the timing at which the lower contact layer 512 is just etched between the multiple second mesas M2 (i.e., just etch timing). Therefore, in Modification 1, the multiple semiconductor layers 102 (see FIG. 2) are etched until a timing slightly later than the just etch timing calculated from the QMS signal of Ga or the like, thereby slightly overetching the lower contact layer 512 between the multiple second mesas M2.

[0160] According to the first modification, crosstalk caused by insufficient etching of the lower contact layer 512 can be reliably suppressed.

[0161] (4-2) Variation 2 26 is a diagram showing cross sections of a plurality of semiconductor layers 502 obtained by the manufacturing method of Modification 2. The imaging device of Modification 2 has a plurality of quantum well infrared photodetectors arranged in a two-dimensional array.

[0162] The multiple semiconductor layers 502 of Modification 2 include, in this order, a stopper layer 566 for substrate removal, a lower electrode layer 568, a stopper layer 510 for etching endpoint detection, and a lower contact layer 512. The multiple semiconductor layers 502 of Modification 2 further include, in this order, a light absorption layer 514, an upper contact layer 516, a stopper layer 570 for coupler processing, and a coupler 572.

[0163] 23 and 25, the stopper layer 510 for etching endpoint detection is in contact with the slab lower surface 52. On the other hand, in Modification 2, the semiconductor layer in contact with the slab lower surface 52 is not the stopper layer 510 for etching endpoint detection, but the stopper layer 566 for substrate removal. Furthermore, the common electrode 28 (see FIG. 9) is connected to the lower electrode layer 568, not the stopper layer 510 for etching endpoint detection. In the example shown in FIG. 26, the slab of Modification 2 is occupied by the stopper layer 566 for substrate removal, most of the lower electrode layer 568, and the portion of the stopper layer 510 for etching endpoint detection that is in contact with the second contact layer 612b.

[0164] 27 is a cross-sectional view showing an example of a plurality of semiconductor layers 102 processed by the manufacturing method of Modification 2. The plurality of semiconductor layers 102 of Modification 2 include, in this order, a buffer layer 8 in contact with a substrate (not shown), a stopper layer 66 for removing the substrate, a lower electrode layer 68, a stopper layer 10 for detecting the etching end point, and a lower contact layer 12. The plurality of semiconductor layers 102 shown in FIG. 27 further include, in this order, a light absorption layer 14, an upper contact layer 16, a stopper layer 70 for coupler processing, and a coupler layer 72.

[0165] The lower electrode layer 568 (see FIG. 26) is a semiconductor layer formed by shaping the unprocessed lower electrode layer 68 (see FIG. 27) by reactive ion etching or the like. The same applies to the stopper layer 510 for detecting the etching end point, etc.

[0166] In the example shown in Figure 27, the substrate and buffer layer 8 are made of GaAs. The stopper layer 66 for substrate removal is made of InGaP. The lower electrode layer 68 is made of n-type GaAs. The stopper layer 10 is made of n-type InGaP. The lower contact layer 12 is made of n-type GaAs.

[0167] The light absorbing layer 14 is a GaAs / AlGaAs multiple quantum well (i.e., a multiple quantum well in which GaAs layers and AlGaAs layers are alternately stacked) doped with n-type impurities. Both ends of the light absorbing layer 14 are AlGaAs layers.

[0168] The upper contact layer 16 is made of p-type GaAs. The stopper layer 70 for coupler processing is made of AlGaAs. The coupler layer 72 is made of GaAs.

[0169] In the coupler layer 72, a coupler 572 is formed that obliquely reflects infrared light that has passed through the light absorption layer 514 (see FIG. 26) and causes it to re-enter the light absorption layer 514. The coupler 572 is a diffraction grating. A stopper layer 70 for coupler processing (see FIG. 27) is used to form the coupler 572.

[0170] The light absorption layer 514 (see FIG. 26) generates photocarriers in response to the electric field component of the infrared light reflected by the coupler 572 that is parallel to the GaAs / AlGaAs multiple quantum well of the light absorption layer 514. The photocarriers are generated by intersubband transitions in the GaAs / AlGaAs multiple quantum well. The first to third hard masks 22a, 22b, and 22c (see FIG. 3(a)) are formed on the surface of the coupler layer 72.

[0171] The individual electrodes 30b, 30c (see FIG. 9) connected to the plurality of second mesas M2 are connected to the upper contact layer 516 through openings provided in the coupler 572. The common electrode 28 is connected to the lower electrode layer 568. The substrate removal stopper layer 66 is provided to prevent the lower electrode layer 68 (GaAs layer) from being eroded by chemical etching for removing the GaAs substrate and buffer layer 8 (GaAs layer).

[0172] 27, the constituent elements of the stopper layer 10 used for detecting the etching endpoint are In, Ga, and P. On the other hand, the constituent elements of the lower contact layer 12 are Ga and As. That is, the constituent elements of the stopper layer 10 include In, which is different from any of the constituent elements of the lower contact layer 12. In Modification 2, when etching the multiple semiconductor layers 102 in FIG. 27, the QMS signal of In is monitored, and the etching endpoint is calculated based on the timing immediately after the QMS signal of In starts to increase.

[0173] The light absorption layer 14 may be a multiple quantum dot structure in which InAs quantum dots and AlGaAs barrier layers are repeatedly stacked, instead of a GaAs / AlGaAs multiple quantum well. In this case, the coupler layer 72 and the coupler stopper layer 70 are not required. Except for the above points, the manufacturing method of the second modification is substantially the same as the manufacturing method of the embodiment described with reference to FIGS.

[0174] 23 to 25, the constituent elements of the stopper layer 510 in contact with the contact layer 612 (i.e., the lower contact layer 512) lack a specific element (first constituent element, specifically Ga) of the contact layer 612. On the other hand, in the example described with reference to FIGS. 26 to 27, the constituent elements of the stopper layer 510 in contact with the contact layer 612 contain a second constituent element (specifically In) that is different from any of the constituent elements of the contact layer 612. The first constituent element and the second constituent element are elements that are contained only in either the constituent elements of the stopper layer 510 in contact with the contact layer 612 or the constituent elements of the contact layer 612, respectively.

[0175] 23 to 25, the QMS signal of the first constituent element (specifically, Ga) is monitored during etching of the plurality of semiconductor layers 102, and the etching endpoint is calculated based on the timing immediately after the endpoint detection signal of the first constituent element starts to decrease. On the other hand, in the manufacturing method of Modification 2 described with reference to FIGS. 26 to 27, the QMS signal of the second constituent element (specifically, In) is monitored during etching of the plurality of semiconductor layers 102, and the etching endpoint is calculated based on the timing immediately after the endpoint detection signal of the second constituent element starts to increase.

[0176] According to the second modification, the variety of photodetectors (for example, quantum well infrared photodetectors and quantum dot infrared photodetectors) arranged in the photodetector array 4 increases. Furthermore, according to the second modification, the variety of semiconductors (for example, InGaP) that can be used as stopper layers increases.

[0177] As described above, in the embodiment, an etching end point that provides an optimal processed shape is calculated based on an end point detector signal of elements released during etching from between the wide-gap hard masks arranged around the narrow-gap hard mask for the fine pixels. Therefore, according to the embodiment, it is possible to form fine pixels that can generate image signals with a high signal-to-noise ratio and little crosstalk. In other words, according to the embodiment, it is possible to provide an imaging device that can capture high-definition images with a high signal-to-noise ratio and little crosstalk.

[0178] Although the embodiments of the present invention have been described above, the embodiments are merely illustrative and not limiting. For example, in the above examples, each photodetector in the photodetector array 4 is a pin photodetector. However, each photodetector in the photodetector array 4 may be a photodetector other than a pin photodetector. For example, each photodetector in the photodetector array 4 may be an nBn infrared photodetector including, in this order, an n-type semiconductor layer, a wide bandgap barrier layer, and an n-type semiconductor layer.

[0179] Alternatively, each photodetector in the photodetector array 4 may be a pBp infrared photodetector including a p-type semiconductor layer, a wide bandgap barrier layer, and a p-type semiconductor layer in that order.

[0180] Alternatively, each photodetector in the photodetector array 4 may be a CBIRD (Complementary Barrier Infrared Detector) having an electron barrier in contact with one end of the light absorption layer and a hole barrier in contact with the other end of the light absorption layer. The electron barrier and hole barrier of the CBIRD are barriers for suppressing dark current, but each photodetector in the photodetector array 4 may be another photodetector having multiple barriers for suppressing dark current.

[0181] Alternatively, each photodetector in the photodetector array 4 may be a multi-band photodetector (for example, two-wavelength photodetector) that outputs a plurality of photocurrents corresponding to the light intensities of different wavelength bands.

[0182] In the above example, the semiconductor layers 102 are etched by reactive ion etching. However, the semiconductor layers 102 may be etched by a method other than reactive ion etching. For example, the semiconductor layers 102 may be etched by etching using high density plasma or sputter etching.

[0183] In the above example, the etching end point is calculated based on the QMS signal of the first constituent element (or the second constituent element) released from the plurality of semiconductor layers 102. However, the etching end point may also be calculated based on the output of an end point detector other than the QMS. For example, the etching end point may be calculated based on the output of an end point detector that detects elements released from the plurality of semiconductor layers 102 based on the color of plasma generated during etching.

[0184] In the above example, each photodetector in the photodetector array 4 is an element that detects infrared light. However, each photodetector in the photodetector array 4 may be a photodetector that detects light other than infrared light (for example, visible light).

[0185] In the above example, the contact layer 112 (see FIG. 2) is just-etched or over-etched between the second hard masks 22b (see FIG. 4(b)) to suppress crosstalk. However, even if the contact layer 112 is not just-etched or over-etched, crosstalk hardly occurs if the contact layer 112 remaining between the second mesas M2 is sufficiently thin. This is because photocarriers rarely diffuse through such a thin semiconductor layer.

[0186] Therefore, the contact layer 112 does not necessarily have to be just-etched or over-etched between the second mesas M2. In this case, the number of second contact layers 612b disposed between the tops T2 of the second mesas (see FIG. 23) and the slab lower surface 52 is one, not multiple.

[0187] The following additional notes are provided regarding the above-described embodiment.

[0188] (Appendix 1) a photodetector array having a plurality of semiconductor layers; a readout circuit connected to the photodetector array; the plurality of semiconductor layers are arranged to form a plurality of first mesas, a plurality of second mesas whose apex intervals are narrower than the apex intervals of the plurality of first mesas, and a slab in contact with the plurality of first mesas and the plurality of second mesas; the slab has a lower surface, an upper surface on which the plurality of first mesas are arranged, and another upper surface on which the plurality of second mesas are arranged, the upper surface being spaced apart from the lower surface more than the upper surface; the plurality of semiconductor layers include a plurality of contact layers arranged so that the distance from the lower surface of the slab is a constant value, and a stopper layer arranged between the plurality of contact layers and the lower surface so as to be in contact with the plurality of contact layers; the plurality of contact layers include a plurality of first contact layers disposed between tops of the plurality of first mesas and the upper surface of the slab so as to be spaced apart from the upper surface, and at least one second contact layer disposed between tops of the plurality of second mesas and the lower surface of the slab; the stopper layer lacks a first constituent element among the constituent elements of the plurality of contact layers, or contains a second constituent element different from any of the constituent elements of the plurality of contact layers; The readout circuit is configured to generate an image signal from photocarriers generated in the plurality of second mesas. Imaging device.

[0189] (Appendix 2) a first interval between a top of each of the plurality of first mesas and a top of another mesa that is closest to the each of the plurality of first mesas is constant; 2. An imaging device according to claim 1.

[0190] (Appendix 3) the plurality of first mesas surround the plurality of second mesas; the plurality of semiconductor layers are further arranged to form terraces surrounding the plurality of first mesas; a distance between a top of a third mesa among the plurality of first mesas that is closest to the other top surface and a top of a mesa among the plurality of second mesas that is closest to the third mesa is the first distance; The distance between the top of the terrace and the top of the mesa closest to the terrace among the plurality of first mesas is the first distance. 3. The imaging device according to claim 2.

[0191] (Appendix 4) the plurality of second mesas include a plurality of effective mesas and a plurality of dummy mesas surrounding the plurality of effective mesas, the readout circuit is configured to generate the image signal from the photocarriers generated in the plurality of effective mesas. The imaging device according to any one of Supplementary Notes 1 to 3 is characterized in that:

[0192] (Appendix 5) a common electrode connected to the top surface of the slab between the plurality of first mesas; a plurality of individual electrodes connected to the apex of each of the plurality of effective mesas; The readout circuit applies a voltage between the common electrode and the plurality of individual electrodes, thereby generating the image signal from the photocarriers. 5. The imaging device according to claim 4.

[0193] (Appendix 6) the second contact layer is a plurality of layers disposed between the tops of the second mesas and the other upper surface of the slab; The imaging device according to any one of Supplementary Notes 1 to 5 is characterized by the following.

[0194] (Appendix 7) The stopper layer is in contact with the lower surface of the slab. The imaging device according to any one of Supplementary Notes 1 to 6 is characterized by the following.

[0195] (Appendix 8) the area of ​​the portion of the upper surface of the slab that surrounds the plurality of first mesas is 1% or more of the area of ​​the portion of the other upper surface of the slab that surrounds the plurality of second mesas; The imaging device according to any one of Supplementary Notes 1 to 7 is characterized by the following.

[0196] (Appendix 9) the first constituent element is gallium, The second constituent element is indium. The imaging device according to any one of Supplementary Notes 1 to 8 is characterized by the following.

[0197] (Appendix 10) A method for manufacturing an imaging device having a photodetector array having a plurality of first mesas and a plurality of second mesas whose top intervals are narrower than the top intervals of the plurality of first mesas, and a readout circuit that generates an image signal from photocarriers generated in the plurality of second mesas, comprising: a first step of growing a plurality of unprocessed semiconductor layers including, in this order, a stopper layer, a contact layer in contact with the stopper layer, and a top layer; a second step of forming, after the first step, a plurality of first hard masks and a plurality of second hard masks spaced apart at intervals narrower than the intervals between the plurality of first hard masks on the surface of the uppermost layer; a third step of etching the semiconductor layers through the first hard masks and the second hard masks to form the first mesas and the second mesas; and a fourth step of monitoring, during the third step, a signal generated by a specific constituent element released from the plurality of semiconductor layers by the etching, the specific constituent element is an element contained in only one of the constituent elements of the stopper layer and the constituent elements of the contact layer, The etching is terminated based on the intensity of the signal so that each of the plurality of first mesas includes a portion of the stopper layer. A method for manufacturing an imaging device.

[0198] (Appendix 11) a first distance between each of the plurality of first hard masks and another hard mask among the first hard masks that is closest to the first hard mask is constant; The manufacturing method according to claim 10, characterized in that

[0199] (Appendix 12) the second step is a step of forming the plurality of second hard masks in a pixel region on the uppermost layer, further forming the plurality of first hard masks so as to surround the pixel region, and further forming a third hard mask so as to surround the plurality of first hard masks; the third step is a step of etching the semiconductor layers through the first hard masks, the second hard masks, and the third hard mask to form the first mesas, the second mesas, and terraces surrounding the first mesas; a distance between a fourth hard mask among the plurality of first hard masks that is closest to the pixel region and a hard mask among the plurality of second hard masks that is closest to the fourth hard mask is the first distance; The distance between the hard mask closest to the third hard mask among the plurality of first hard masks and the third hard mask is the first distance. The manufacturing method according to claim 11, characterized in that [Explanation of symbols]

[0200] 2: Imaging device 4: Photodetector array 6:Readout circuit 10,510: Stopper layer 22a: First hard mask 22b: Second hard mask 22c: Third hard mask 28: Common electrode 30: Individual electrode 48: Terrace 50: Slab 52: Underside of slab 54a: Top of the first slab 54b: Top of the second slab 102: Multiple semiconductor layers 108: Base 112,612: Contact layer 118: Top floor 502: Multiple semiconductor layers 612a: First contact layer 612b: Second contact layer

Claims

1. a photodetector array having a plurality of semiconductor layers; a readout circuit connected to the photodetector array; the plurality of semiconductor layers are arranged to form a plurality of first mesas, a plurality of second mesas whose apex intervals are narrower than the apex intervals of the plurality of first mesas, and a slab in contact with the plurality of first mesas and the plurality of second mesas; the slab has a lower surface, an upper surface on which the plurality of first mesas are arranged, and another upper surface on which the plurality of second mesas are arranged, the another upper surface being spaced apart from the lower surface more than the upper surface; the plurality of semiconductor layers include a plurality of contact layers arranged so that the distance from the lower surface of the slab is constant, and a stopper layer arranged between the plurality of contact layers and the lower surface so as to be in contact with the plurality of contact layers and the lower surface of the slab or to be in contact with the plurality of contact layers and spaced apart from the lower surface of the slab; the plurality of contact layers include a plurality of first contact layers disposed between tops of the plurality of first mesas and the upper surface of the slab so as to be spaced apart from the upper surface, and at least one second contact layer disposed between tops of the plurality of second mesas and the lower surface of the slab; the stopper layer lacks a first constituent element among the constituent elements of the plurality of contact layers, or contains a second constituent element different from any of the constituent elements of the plurality of contact layers; The readout circuit is configured to generate an image signal from photocarriers generated in the plurality of second mesas. Imaging device.

2. a first interval between a top of each of the plurality of first mesas and a top of another mesa that is closest to the each of the plurality of first mesas is constant; 2. The imaging device according to claim 1.

3. the plurality of first mesas surround the plurality of second mesas; the plurality of semiconductor layers are further arranged to form terraces surrounding the plurality of first mesas; a distance between a top of a third mesa among the plurality of first mesas that is closest to the other top surface and a top of a mesa among the plurality of second mesas that is closest to the third mesa is the first distance; the distance between the top of the terrace and the top of the mesa closest to the terrace among the plurality of first mesas is the first distance; 3. The imaging device according to claim 2.

4. the plurality of second mesas include a plurality of effective mesas and a plurality of dummy mesas surrounding the plurality of effective mesas, the readout circuit is configured to generate the image signal from the photocarriers generated in the plurality of effective mesas.

4. The imaging device according to claim 1, wherein the imaging device is a semiconductor laser.

5. a common electrode connected to the top surface of the slab between the plurality of first mesas; a plurality of individual electrodes connected to the apex of each of the plurality of effective mesas; The readout circuit applies a voltage between the common electrode and the plurality of individual electrodes, thereby generating the image signal from the photocarriers.

5. The imaging device according to claim 4.

6. the second contact layer is a plurality of layers disposed between the tops of the plurality of second mesas and the other upper surface of the slab; 6. The imaging device according to claim 1, wherein:

7. 1. A method for manufacturing an imaging device having a photodetector array having a plurality of first mesas and a plurality of second mesas whose top intervals are narrower than the top intervals of the plurality of first mesas, and a readout circuit that generates an image signal from photocarriers generated in the plurality of second mesas, a first step of growing a plurality of unprocessed semiconductor layers including, in this order, a stopper layer, a contact layer in contact with the stopper layer, and a top layer; a second step of forming, after the first step, a plurality of first hard masks and a plurality of second hard masks spaced apart at intervals narrower than the intervals between the plurality of first hard masks on the surface of the uppermost layer; a third step of etching the semiconductor layers through the first hard masks and the second hard masks to form the first mesas and the second mesas; and a fourth step of monitoring, during the third step, a signal generated by a specific constituent element released from the plurality of semiconductor layers by the etching, the specific constituent element is an element contained in only one of the constituent elements of the stopper layer and the constituent elements of the contact layer, The etching is terminated based on the intensity of the signal so that each of the plurality of first mesas includes a portion of the stopper layer. A method for manufacturing an imaging device.

Images