Semiconductor Devices

Abstract

To provide a pulse signal output circuit which can stably operate and a shift register including the pulse signal output circuit.SOLUTION: A pulse signal output circuit according to an embodiment comprises first through tenth transistors. A ratio W / L of a channel width W to a channel length L of each of the first transistor and the third transistor is set larger than W / L of the sixth transistor; W / L of the fifth transistor is set larger than W / L of the sixth transistor; W / L of the fifth transistor is set identical to W / L of the seventh transistor; and W / L of the third transistor is set larger than W / L of the fourth transistor. As a result, the pulse signal output circuit which can stably operate and a shift register including the pulse signal output circuit can be provided.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a pulse signal output circuit and a shift register. [Background technology]

[0002] Transistors formed on flat plates such as glass substrates, as used in liquid crystal display devices, The photodiodes are mainly made of semiconductor materials such as amorphous silicon or polycrystalline silicon. Although amorphous silicon transistors have low field-effect mobility, they are superior to glass transistors. On the other hand, transistors using polycrystalline silicon can be used Although it has high field-effect mobility, it requires a crystallization process such as laser annealing, and glass It has the characteristic that it is not necessarily suited to larger substrate areas.

[0003] In response to this, transistors that use oxide semiconductors as semiconductor materials have attracted attention. For example, zinc oxide or In-Ga-Zn-O oxide semiconductors are used as semiconductor materials. The technology for fabricating a transistor and using it as a switching element in an image display device is disclosed in Patent Document 1 and This is disclosed in Patent Document 2.

[0004] A transistor that uses an oxide semiconductor for the channel formation region is a transistor that uses amorphous silicon. In addition, the oxide semiconductor film has a higher field-effect mobility than the transistor. Film formation is possible at temperatures below 300°C using sputtering methods, and polycrystalline silicon is used. It is easier to fabricate than conventional transistors.

[0005] Transistors manufactured using such oxide semiconductors are widely used in liquid crystal displays, electronic devices, and Pixel parts and driving circuits of display devices such as electroluminescence displays or electronic paper For example, the above oxide semiconductor The pixel portion and driver circuit of a display device are constructed using transistors manufactured using conductors. The technique is disclosed in Non-Patent Document 1.

[0006] However, all of the above transistors manufactured using oxide semiconductors are n-channel transistors. Therefore, a driving circuit using a transistor manufactured using an oxide semiconductor is When a path is configured, the driver circuit is configured only with n-channel transistors. This will happen. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Non-patent literature]

[0008] [Non-Patent Document 1] T. Osada, and 8 others, "Development of Driver-Integrated Panel using Amorphous In-Ga-Zn-Oxide TFT", SID '09 DIGEST, pp. 184-187 (2009) Summary of the Invention [Problem to be solved by the invention]

[0009] The driving circuit used in a display device or the like is implemented by a shift register including a pulse signal output circuit. When the shift register is configured by transistors of the same conductivity type, Problems such as unstable operation may occur.

[0010] In view of the above-mentioned problems, one aspect of the present invention is to provide a pulse signal output circuit that can operate stably. It is an object of the present invention to provide a circuit and a shift register including the same. [Means for solving the problem]

[0011] One embodiment of the present invention includes first to tenth transistors, and the terminal, the first terminal of the second transistor, and the first output terminal are electrically connected; a first terminal of the third transistor, a first terminal of the fourth transistor, and a second output terminal; The first terminal of the fifth transistor and the second terminal of the sixth transistor are electrically connected to each other. The first terminal and the first terminal of the seventh transistor are electrically connected to each other. the gate terminal of the third transistor, the gate terminal of the seventh transistor, The terminals of the second transistor and the fourth transistor are electrically connected to each other. a gate terminal of the sixth transistor, a gate terminal of the eighth transistor, and a first terminal of the eighth transistor. The first terminal of the ninth transistor is electrically connected to the first terminal of the eighth transistor. The second terminal and the first terminal of the tenth transistor are electrically connected to each other, and the first transistor The ratio W / L of the channel width W to the channel length L of the first and third transistors is the ratio W / L of the channel width W to the channel length L of the sixth transistor is greater than the ratio W / L of the fifth transistor; The ratio W / L of the channel width W to the channel length L of the sixth transistor is the ratio W / L of the channel width W to the channel length L of the fifth transistor is larger than the ratio W / L of the fifth transistor. The ratio W / L of the channel width W to the channel length L of the seventh transistor is The ratio of the channel width W to the channel length L of the third transistor is equal to W / L. The ratio W / L of the channel width W to the channel length L of the fourth transistor is / L.

[0012] In the pulse signal output circuit, the second terminal of the first transistor and the third transistor The second terminal of the transistor receives the first clock signal, and the gate of the eighth transistor The second clock signal is input to the gate terminal of the tenth transistor. , a third clock signal is input, and the second terminal of the second transistor, the fourth transistor the second terminal of the sixth transistor, the second terminal of the ninth transistor, A first potential is applied to the terminals of the fifth transistor, the second terminal of the seventh transistor, A gate terminal of the tenth transistor and a second terminal of the tenth transistor are connected to a second potential higher than the first potential. 2 potential is applied to the gate terminal of the fifth transistor and the gate terminal of the ninth transistor. A first pulse signal is input to the output terminal, and a second pulse signal is output from the first output terminal or the second output terminal. A second pulse signal may be output.

[0013] The capacitor is connected to the gate terminal of the second transistor and the gate terminal of the fourth transistor. a gate terminal of the sixth transistor, a gate terminal of the eighth transistor, and a gate terminal of the eighth transistor. The first terminal of the ninth transistor may be electrically connected to the first terminal of the ninth transistor.

[0014] In the above, an eleventh transistor is provided, and a first terminal of the eleventh transistor is connected to the The gate terminal of the second transistor, the gate terminal of the fourth transistor, and the gate terminal of the sixth transistor the gate terminal of the eighth transistor, the first terminal of the ninth transistor, a second terminal of the eleventh transistor electrically connected to the eighth transistor; a second terminal of the ninth transistor, a first terminal of the ninth transistor, and a capacitance element; The channel width W of the eighth transistor and the tenth transistor is The width of the channel W of the saturation detector may be smaller than the width of the channel W of the saturation detector.

[0015] In the pulse signal output circuit, the second terminal of the eleventh transistor is connected to the third terminal of the eleventh transistor. The second potential is applied to the eleventh transistor, and the third pulse signal is input to the gate terminal of the eleventh transistor. This may be the case.

[0016] Furthermore, a shift register can be configured using a plurality of the above pulse signal output circuits. More specifically, for example, two pulse signal output circuits not including the eleventh transistor are used. and n (n: natural number) pulse signal output circuits each having the eleventh transistor. A pulse signal output circuit having n stages of a shift register and no eleventh transistor The channel width W of the eighth or tenth transistor is The eighth or tenth transistor of the pulse signal output circuit having the It may be configured to be larger than the panel width W.

[0017] Furthermore, the pulse signal output circuit or the shift register includes a plurality of transistors. It is preferable to use an oxide semiconductor for either of the above. A shift register can be formed by using multiple elements.

[0018] Note that in the above description, a transistor may be formed using an oxide semiconductor. The present invention is not limited to this. For example, wide-gap materials such as silicon carbide (more specifically, e.g., A semiconductor material having an energy gap Eg of greater than 3 eV may also be used.

[0019] In this specification, the terms "above" and "below" refer to the positional relationship of the components "directly above" and "below." For example, the term "gate insulating layer on a gate insulating layer" does not necessarily mean "directly under" the gate insulating layer. The expression "electrode" refers to a gate insulating layer and a gate electrode that includes other components between the gate insulating layer and the gate electrode. does not exclude.

[0020] In addition, in this specification, the terms "electrode" and "wiring" are used to refer to these components functionally. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wire" are used interchangeably to refer to the plural "electrodes." This also includes cases where "wires" and "circuits" are formed as a single unit.

[0021] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. It is assumed that this is possible.

[0022] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0023] For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as [Effects of the Invention]

[0024] To provide a pulse signal output circuit capable of stable operation and a shift register including the same. It is possible. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 2 is a diagram showing an example of the configuration of a pulse signal output circuit and a shift register. [Figure 2] 1 is a timing chart of a shift register. [Figure 3] FIG. 4 is a diagram illustrating the operation of a pulse signal output circuit. [Figure 4] FIG. 4 is a diagram illustrating the operation of a pulse signal output circuit. [Figure 5] FIG. 2 is a diagram showing an example of the configuration of a pulse signal output circuit and a shift register. [Figure 6] 1 is a timing chart of a shift register. [Figure 7] FIG. 4 is a diagram illustrating the operation of a pulse signal output circuit. [Figure 8] FIG. 4 is a diagram illustrating the operation of a pulse signal output circuit. [Figure 9] FIG. 2 is a diagram showing an example of the configuration of a pulse signal output circuit and a shift register. [Figure 10] 1A and 1B illustrate structural examples of transistors. [Figure 11] 1A to 1C illustrate an example of a method for manufacturing a transistor. [Figure 12]1A to 1C illustrate one embodiment of a semiconductor device. [Figure 13] 1A and 1B are diagrams illustrating electronic devices. [Figure 14] 1 is a timing chart of a shift register. DETAILED DESCRIPTION OF THE INVENTION

[0026] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and forms without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention is not to be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0027] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as those in the actual embodiment for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The position, size, range, etc. are not necessarily limited to those disclosed in the drawings, etc.

[0028] In this specification, ordinal numbers such as "first," "second," and "third" are used to indicate the composition of the elements. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0029] (Embodiment 1) In this embodiment, a pulse signal output circuit and a shift register including the pulse signal output circuit are provided. An example of the configuration and operation of the controller will be described with reference to FIGS.

[0030] <Circuit configuration> First, a pulse signal output circuit and a shift register circuit including the pulse signal output circuit An example of the configuration will be described with reference to FIG.

[0031] The shift register shown in this embodiment includes a first pulse signal output circuit 10 _1 ~nth Pal signal output circuit 10 _n (n is a natural number greater than or equal to 2) and a first signal that transmits a clock signal. The first signal line 11 has a first clock signal line 12 connected to a fourth clock signal line 14 (see FIG. 1(A)). A clock signal CLK1 is applied to the first signal line 11, and a second clock signal CLK2 is applied to the second signal line 12. A third clock signal CLK3 is applied to the third signal line 13, and a fourth signal line 1 4 is supplied with a fourth clock signal CLK4.

[0032] A clock signal is a signal that repeats an H signal (high potential) and an L signal (low potential) at regular intervals. Here, the first clock signal CLK1 to the fourth clock signal CLK4 are 1 / 4 cycles. In this embodiment, the clock signal is used to generate a pulse signal. Controls the signal output circuit, etc.

[0033] First pulse signal output circuit 10 _1 ~ nth pulse signal output circuit 10 _n are, respectively, First input terminal 21, second input terminal 22, third input terminal 23, fourth input terminal 24, It has a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 1(B)). see).

[0034] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first signal line 11. For example, the first pulse signal output circuit 13 is electrically connected to one of the first to fourth signal lines 14. road 10 _1 The first input terminal 21 is electrically connected to the first signal line 11, and the second input The terminal 22 is electrically connected to the second signal line 12, and the third input terminal 23 is electrically connected to the third signal line 1 3. The second pulse signal output circuit 10 _2 is the first input The terminal 21 is electrically connected to the second signal line 12, and the second input terminal 22 is electrically connected to the third signal line 1 3, and the third input terminal 23 is electrically connected to the fourth signal line 14. Here, the n-th pulse signal output circuit 10 _n The signal line connected to the second The figure shows the case of the signal line 12, the third signal line 13, and the fourth signal line 14. Pulse signal output circuit 10 _n The signal line connected to the digits will differ depending on the value of n. Therefore, it should be noted that the configuration shown here is merely an example.

[0035] In addition, the mth pulse signal output circuit (m is an arbitrary number of 2 or more) of the shift register shown in this embodiment In the (m-1)th pulse signal output circuit, the fourth input terminal 24 is connected to the first output terminal of the (m-1)th pulse signal output circuit. The fifth input terminal 25 is electrically connected to the (m+2)th pulse signal output circuit. The first output terminal 26 is electrically connected to the (m+1)th pulse The second output terminal 27 is electrically connected to the fourth input terminal 24 of the signal output circuit, and the second output terminal 27 is connected to the OUT( m).

[0036] For example, the third pulse signal output circuit 10 _3 Then, the fourth input terminal 24 receives the second pulse signal. No. output circuit 10 _2 The fifth input terminal 25 is electrically connected to the first output terminal 26 of the 5 pulse signal output circuit 10 _5 is electrically connected to the first output terminal 26 of the first output The terminal 26 is connected to the fourth pulse signal output circuit 10 _4 The fourth input terminal 24 and the first pulse signal No. output circuit 10 _1 The fifth input terminal 25 is electrically connected to the second input terminal 26.

[0037] In addition, the first pulse signal output circuit 10 _1 Now, let's connect the fourth input terminal 24 to the fifth wire 15. The first start pulse (SP1) is input from the kth pulse signal output circuit 1. 0 _k (k is a natural number between 2 and n), the output pulse of the previous stage is input to the fourth input terminal 24. In addition, the (n-1)th pulse signal output circuit 10 (n-1) Now, the fifth input A second start pulse (SP2) is input to the n-th pulse signal output circuit 25. road 10 _n In this case, a third start pulse (SP3) is input to the fifth input terminal 25. The second start pulse (SP2) and the third start pulse (SP3) are generated from the outside. The signal may be a signal input from a remote control or may be a signal generated within the circuit.

[0038] Next, the first pulse signal output circuit 10 _1 ~ nth pulse signal output circuit 10 _n Specific The configuration will be explained.

[0039] First pulse signal output circuit 10 _1 ~ nth pulse signal output circuit 10 _n Each of the first The pulse signal generating circuit 20 is configured with the first to fourth transistors 101 to 104. 0 and the first input signal composed of the fifth transistor 105 to the seventh transistor 107. The signal generating circuit 201 and the eighth to eleventh transistors 108 to 111 are included. and a second input signal generating circuit 202 (see FIG. 1(C)). In addition to the first input terminal 21 to the fifth input terminal 25, the first power supply line 31 and the second power supply line 32 A signal is supplied from the first transistor 101 to the eleventh transistor 111.

[0040] A specific example of the configuration of the pulse signal generating circuit is as follows.

[0041] A first terminal (either a source terminal or a drain terminal, the same applies below) of the first transistor 101 The first terminal of the second transistor 102 and the first output terminal 26 are electrically connected. Similarly, the first terminal of the third transistor 103 and the third terminal of the fourth transistor 104 are connected to each other. The terminal of the first transistor 1 is electrically connected to the second output terminal 27. The gate terminal of the third transistor 101, the gate terminal of the third transistor 103, and the first input signal generating circuit The output terminal of the second transistor 102 is electrically connected to the gate terminal of the second transistor 102. a gate terminal of the fourth transistor 104; an output terminal of the second input signal generating circuit; are electrically connected.

[0042] A second terminal (the other of the source terminal and the drain terminal, the same applies below) of the first transistor 101 and the second terminal of the third transistor are electrically connected to each other, and a first clock signal CLK is 1 is input to the node. The second terminal of the transistor also functions as a first input terminal 21 of the pulse signal output circuit. A first potential (e.g., For example, a low potential VSS is applied to the second terminal of the fourth transistor 104. A first potential is applied via a power supply line 31 .

[0043] A specific example of the configuration of the first input signal generating circuit is as follows.

[0044] a first terminal of the fifth transistor 105, a first terminal of the sixth transistor 106, The first terminal of the seventh transistor 107 is electrically connected to the first terminal of the seventh transistor 108. The second terminal of the register 107 functions as the output terminal of the first input signal generating circuit. The gate terminal of the fifth transistor 105 is connected to the first input terminal of the first input signal generating circuit. and also functions as the fourth input terminal 24 of the pulse signal output circuit.

[0045] A second potential is applied to a second terminal of the fifth transistor 105 via a second power supply line 32. The second terminal of the sixth transistor 106 is connected to the first power supply line 31. A potential is applied to the gate terminal of the fifth transistor 105, and a pulse signal ( The first pulse signal output circuit receives a start pulse signal. The output signal of the second input signal generating circuit is input to the gate terminal of 106. The gate terminal of the transistor 106 serves as the second input terminal of the first input signal generating circuit. The gate terminal of the seventh transistor 107 is connected to the second power supply line 32 via the second power supply line 33. A potential is applied.

[0046] In this embodiment, the seventh transistor 107 is provided. In the case where the seventh transistor 107 is provided, The potential of the first terminal of the fifth transistor 105 may be increased due to the load strap operation. That is, the voltage between the gate and source of the fifth transistor 105 (or between the gate and source) can be suppressed. This prevents a large voltage from being applied to the region between the fifth transistor and the drain. This can suppress deterioration of the star 105.

[0047] A specific example of the configuration of the second input signal generating circuit is as follows.

[0048] the second terminal of the tenth transistor 110 and the first terminal of the eighth transistor 108; The second terminal of the eighth transistor and the second terminal of the eleventh transistor are electrically connected. The second terminal of the ninth transistor is electrically connected to the first terminal of the ninth transistor to form a second input. It functions as the output terminal of the signal generating circuit.

[0049] a first terminal of the eleventh transistor 111 and a first terminal of the tenth transistor 110; The second potential is applied to the ninth transistor 109 through the second power supply line 32. The second terminal is supplied with a first potential via a first power supply line 31. The gate terminal of the 11th transistor 111 receives a pulse signal from the next stage. The gate terminal of the transistor 111 functions as a first input terminal of the second input signal generating circuit. At the same time, it also functions as the fifth input terminal 25 of the pulse signal output circuit. The second clock signal CLK2 is input to the gate terminal of the register 108. The gate terminal of the transistor 108 functions as a second input terminal of the second input signal generating circuit. The ninth transistor functions as a second input terminal 22 of the pulse signal output circuit. The gate terminal of the transistor 109 receives a pulse signal from the previous stage (in the first pulse signal output circuit, A start pulse signal is input to the gate terminal of the ninth transistor 109. It functions as the third input terminal of the second input signal generating circuit and also functions as the third input terminal of the pulse signal output circuit. The tenth transistor 110 also functions as the fourth input terminal 24. The gate terminal of the tenth transistor 110 is connected to the fourth input terminal 24. The third clock signal CLK3 is input to the gate terminal of the tenth transistor 110. The terminal functions as the fourth input terminal of the second input signal generating circuit and also serves as the pulse signal output terminal. It also serves as the third input terminal 23 of the circuit.

[0050] The components of the pulse signal output circuit described above (pulse signal generating circuit, first input signal generating circuit, The above examples (e.g., the configuration example of the first input signal generating circuit and the second input signal generating circuit) are merely examples, and the disclosed invention This is not limiting.

[0051] In the following description of this embodiment, the first transistor in the pulse signal output circuit shown in FIG. The gate terminal of the third transistor 101, the gate terminal of the third transistor 103, and the first input The node formed by the connection between the output terminal of the force signal generating circuit and is called node A. , the gate terminal of the second transistor 102, and the gate terminal of the fourth transistor 104. The node formed by connecting the output terminal of the second input signal generating circuit and the output terminal of the first input signal generating circuit is referred to as node B. do.

[0052] Between the node A and the first output terminal 26, a voltage is applied to suitably perform a bootstrap operation. In order to maintain the potential of the node B, a capacitor may be provided. An electrically connected capacitive element may be provided.

[0053] In FIG. 1C, the channel of the first transistor 101 and the third transistor 103 The ratio W / L of the channel width W to the channel length L of the sixth transistor 106 is It is preferable that the ratio of the channel width W to the surface area L is larger than W / L.

[0054] In FIG. 1C, the channel length L of the fifth transistor 105 is The ratio W / L of the width W is the ratio of the channel width W to the channel length L of the sixth transistor 106. It is preferable that the channel length L of the fifth transistor 105 is larger than W / L. The ratio W / L of the channel width W to the channel length L of the seventh transistor 107 is It is preferable that the ratio W / L of the channel width W of the fifth transistor 105 is equal to The ratio W / L of the channel width W to the channel length L of the seventh transistor 107 is It is preferable that the ratio of the channel width W to L is larger than W / L.

[0055] In addition, in FIG. 1C, the channel length L of the third transistor 103 is The ratio W / L of the width W is the ratio of the channel width W to the channel length L of the fourth transistor 104. It is preferably larger than W / L.

[0056] In addition, in FIG. 1C, the eighth transistor 108 and the tenth transistor 110 The channel width (W) of the eleventh transistor 111 is smaller than the channel width (W) of the eleventh transistor 112. It is preferable that:

[0057] Note that the first to eleventh transistors 101 to 111 are made of an oxide semiconductor. The use of an oxide semiconductor reduces the off-state current of a transistor. In addition, compared to amorphous silicon, the on-current and field-effect mobility are Furthermore, the deterioration of the transistor can be suppressed. This will lead to the realization of electronic circuits with low power consumption, high speed operation, and improved accuracy of operation. Note that a transistor including an oxide semiconductor will be described in detail in a later embodiment. Therefore, it will be omitted here.

[0058] <Operation> Next, the operation of the shift register shown in FIG. 1 will be described with reference to FIGS. 2 to 4 and 14. Specifically, in the timing chart shown in FIG. The operation in each period of 56 will be explained using FIG. 3 and FIG. 4. , CLK1 to CLK4 indicate clock signals, and SP1 indicates the first start pulse. OUT1 to OUT4 indicate the first pulse signal output circuit 10. _1 ~Fourth pulse signal output power circuit 10 _4 , and node A and node B are the outputs from the second output terminal of The potentials of the nodes A and B are shown, and SROUT1 to SROUT4 are the first pulse signals. No. output circuit 10 _1 -Fourth pulse signal output circuit 10 _4 The output from the first output terminal of show.

[0059] In the following description, the first transistor 101 to the eleventh transistor 111 are , all are n-channel transistors. When a transistor is represented by a solid line, the transistor is in a conductive state (on state). ), and when it is represented by a dashed line, it means that the transistor is in a non-conducting state ( This indicates that the power is in the ON state.

[0060] Typically, the first pulse signal output circuit 10 _1The operation of the first pulse signal is explained below. No. output circuit 10 _1 The configuration of the is as described above. The relationship between the potentials is as described above. In the following explanation, the potentials of the input terminals and power supply lines are All high potentials (also called H level or H signal) are VDD, and low potentials (L level) are All signals (also called L signals, L signals, etc.) are VSS.

[0061] During the first period 51, SP1 is at the H level, so the first pulse signal output circuit 10 _1 The gate terminal of the fifth transistor 105 serves as the fourth input terminal 24 of the ninth A high potential is applied to the gate terminal of the fifth transistor 105 and the second transistor 109. During the first period 51, the CLK3 is also at the H level. Since the seventh transistor 110 is turned on, the tenth transistor 110 is also turned on. Since a high potential is applied to the gate terminal of the seventh transistor 107, the seventh transistor 107 is also turned on. The state is switched on (see FIG. 3(A)).

[0062] When the fifth transistor 105 and the seventh transistor 107 are turned on, The potential of node A rises. The potential of the second terminal of the fifth transistor 105 is VDD. Therefore, the potential of the first terminal of the fifth transistor 105 is the fifth potential from the potential of the second terminal. The value (VDD-Vth) of the transistor 105 is 105 ) Since the potential of the gate terminal of the seventh transistor 107 is VDD, The threshold voltage Vth of the resistor 107107 Vth 105 In the above cases, the power of node A The order is (VDD-Vth 107 ), and the seventh transistor 107 is turned off. direction, Vth 107 Vth 105 If the voltage is less than 1 V, the seventh transistor 107 is in an on state. While maintaining this, the potential of node A is (VDD-Vth 105 ) below. The maximum potential of node A in period 51 is V AH Let's say.

[0063] The potential of node A is V AH , the first transistor 101 and the third transistor 103 is turned on. Here, since CLK1 is at the L level, the first output terminal 26 The second output terminal 27 outputs an L level signal.

[0064] In the second period 52, the potential of CLK1 switches from the L level to the H level. Since the first transistor 101 and the third transistor 103 are in an on state, The potential of the first output terminal 26 and the potential of the second output terminal 27 rise. There is a capacitance between the gate terminal and the source terminal (or drain terminal) of the transistor 101. This creates a capacitive coupling between the gate terminal and the source terminal (or drain terminal). Similarly, the gate terminal and the source terminal (or drain terminal) of the third transistor 103 are connected to each other. There is a capacitance between the gate terminal and the source terminal (or drain terminal), which Therefore, the potential of the first output terminal 26 and the potential of the second output terminal 27 are As the potential of the input terminal 27 rises, the potential of the floating node A also rises ( (Bootstrap operation). The potential of node A is finally VDD+Vth 101 Become higher The potential of the first output terminal 26 and the potential of the second output terminal 27 become VDD (H level). (See Figures 2 and 3(B)).

[0065] In the second period 52, the ninth transistor 109 is in an on state. Therefore, the first output terminal 26 changes from the L level to the H level. This suppresses the potential fluctuation at node B caused by capacitive coupling when the voltage changes to a This can prevent the occurrence of such a problem.

[0066] As described above, in the second period 52, the potential of the second output terminal 27 is set to the H level. In this case, in order to reliably raise the potential of the second output terminal 27 to VDD (H level), , the gate voltage of the third transistor 103 to turn it on. (Vgs) of the third transistor 103 is small. In this case, the drain current of the third transistor is small, so that In this case, the potential of the second output terminal 27 is increased to VDD (H level) during the second period. This means that it takes time for the waveform at the second output terminal 27 to rise. This can cause it to become dull and malfunction.

[0067] Incidentally, the magnitude of Vgs of the third transistor 103 in the second period 52 is The potential of the node A during the period 51 is determined by the potential of the third transistor 10. In order to increase Vgs of the node 3, the potential of the node A should be increased as much as possible during the first period 51. It is necessary to make it larger (in circuit design, the maximum is VDD-Vth 105or VDD-Vth 107 The same applies to the Vgs of the first output terminal 26 and the first transistor 101. This can be said.

[0068] Therefore, the ratio W / L of the channel width W to the channel length L of the fifth transistor 105 is , the ratio W / L of the channel width W to the channel length L of the sixth transistor 106 is larger than It is preferable that the ratio of the channel width W to the channel length L of the fifth transistor 105 is W / L is set to a value smaller than the ratio W / L of the channel width W to the channel length L of the sixth transistor 106. By increasing the potential of the node A in the first period 51 to V DD-Vth 105 or VDD-Vth 107 It can be increased to During the first period 51, the sixth transistor 106 is in an off state, but the fifth transistor The ratio W / L of the channel width W to the channel length L of the sixth transistor 105 is By making the ratio of the channel width W to the channel length L of the sixth transistor larger than W / L, Since the leakage current (Ioff) in the transistor 106 can be reduced, The potential of node A can be increased to VDD-Vth in a shorter time. 105 can be raised to.

[0069] In addition, as the channel length L decreases due to miniaturization of transistors, the threshold voltage shifts. In such a case, the sixth transistor 106 may be normally on. Also, the ratio W / L of the channel width W to the channel length L of the sixth transistor 106 is set to the fifth The ratio of the channel width W to the channel length L of the transistor 105 is set to be smaller than W / L. As a result, the on-resistance of the sixth transistor 106 is set to the on-resistance of the fifth transistor 105. This allows the potential of node A to be set to VDD-Vth 105 or VDD -Vth 107 can be brought closer to the potential.

[0070] The ratio W / L of the channel width W to the channel length L of the fifth transistor 105 is The ratio W / L of the channel width W to the channel length L of the transistor 107 in FIG. It is preferable that the values ​​are approximately equal. This is the case where they can be considered equal, assuming that there is a case where the fifth transistor The ratio W / L of the channel width W to the channel length L of the seventh transistor 105 and the seventh transistor 107 By making these equal, the fifth transistor 105 and the seventh transistor 107 Since the current supply capacity can be made equal, the potential of node A can be efficiently increased. The threshold voltages of the fifth transistor 105 and the seventh transistor 107 are It is desirable that the voltages Vth are approximately equal.

[0071] The ratio W / L of the channel width W to the channel length L of the fifth transistor 105 is Transistor characteristics, clock frequency, first transistor 101 and third transistor It can be determined by the gate capacitance of 103, the operating voltage of the shift register, and the like.

[0072] Furthermore, when the channel width W of the sixth transistor 106 is increased, the characteristics of the sixth transistor 106 are If the transistor becomes normally on, the leakage current increases, which leads to a drop in the potential of node A. Or, the fifth transistor 105 may be prevented from charging the node A. Furthermore, when high-speed operation is required, the potential of node B is decreased in a short time. In this case, the potential of the sixth transistor is It needs to be lowered in between.

[0073] Therefore, the channel width W of the sixth transistor is larger than the channel width W of the fifth transistor. By reducing the width W, it is possible to prevent the potential of the node A from changing. This reduces the load on the power supply B. In combination, the fifth transistor 105, the sixth transistor 106 and the seventh transistor By determining the size of the shift register 107, an efficient shift register can be realized. can.

[0074] During the third period 53, SP1 becomes L level, and the fifth transistor 105 and the ninth transistor The transistor 109 is turned off. Also, the CLK1 is maintained at the H level, and the node Since the potential of A does not change, the first output terminal 26 and the second output terminal 27 output VDD (H level) is output (see FIG. 3(C)). However, the potential of the first output terminal 26 does not change, so there is no problem due to capacitive coupling. It is negligible.

[0075] During the fourth period 54, CLK2 and CLK3 are at the H level, and therefore, The potential rises in a short time. Also, CLK1 becomes L level. As a result, the second transistor The first output terminal 26 and the fourth transistor 104 are turned on. The potential of the second output terminal 27 also drops in a short time (see FIG. 4(A)). Since the transistor 106 is turned on, the potential of the node A becomes L level. Since the first transistor 101 and the third transistor 103 are turned off, The potentials of the first output terminal 26 and the second output terminal 27 become L level.

[0076] During the fourth period 54, the potential of the node A is at the same level as before the sixth period when the CLK1 becomes H level. (i.e., during the fourth period 54 and the fifth period 55) If the potential at node A does not drop to VSS during the fifth period 55, the third transistor The potential at node A rises again due to the capacitive coupling between the gate and source of transistor 103, The first transistor 101 and the third transistor 103 are turned on, and the first output An electric charge may flow to the terminal 26 and the second output terminal 27, which may cause a malfunction.

[0077] Therefore, the first transistor 101, the third transistor 103 and the sixth transistor By determining the relationship of the saturation voltage Vcc and the saturation voltage Vs according to the equations (1) to (7), the operation caused by the load can be controlled. This reduces malfunctions and stabilizes operation.

[0078]

number

[0079]

number

[0080]

number

[0081]

number

[0082]

number

[0083]

number

[0084]

number

[0085] In the above equation, t CKH The period of the H level of CLK1, that is, the second period 52 and the third period corresponds to the period 53, and t CKL This means the period when CLK1 is at the L level, that is, the fourth period 54 and and the fifth period 55, off is the time it takes for node A to discharge to VSS. That is, t CKL Within the period t off The potential of node A is This will lower the voltage to VSS. off During the fourth period54 and the fifth period55 For example, in the fourth period 54_1 and in the fourth periods 54_1 to 54_3, The periods 54_1 to 54_5 may be used (see FIG. 14). Preferably, the fourth period 54 and the fifth period The fourth period 54_1 to 54_3 corresponds to half of the period 55. CKL to In contrast, t off If the time is set too short, the sixth The channel width W of the transistor 106 must be increased. off Long-term If this is set, the potential of node A will not be discharged to VSS before the next clock signal H is input, causing an error. This is because there is a possibility that t off Considering the frequency of the clock signal, It is necessary to decide taking into consideration the timing chart shown in Figure 14. For example, the fourth period 54_1 to 54_5 is exaggerated, but the timing shown in FIG. There is no big difference from the chart.

[0086] Also, C 101 and C 103 are the first transistor 101 and the third transistor indicates the gate capacitance of resistor 103, and V f indicates the potential of the node A in the third period 53.

[0087] i shown in equation (2) 106 indicates the drain current of the sixth transistor 106. From this, the size (for example, W / L) of the sixth transistor 106 can be determined. That is, the size of the sixth transistor 106 is determined based on the operating frequency of CLK1, the The size of the first transistor 101 and the third transistor 103, and the potential of the node A are used to determine the potential. This can be done.

[0088] For example, if the operating frequency of CLK1 is high, the potential of node A needs to fall more quickly. Therefore, from equation (1), t off It becomes necessary to reduce i 106 of Therefore, it is necessary to increase the 106 According to equation (2), W 106 Calculate The W size can be determined.

[0089] On the other hand, when the sizes of the first transistor 101 and the third transistor 103 are small, In 106 Since it is sufficient to have a small value, from equation (2), W 106 becomes smaller. The third transistor 103 is used to charge and discharge the output load. By increasing the size of the transistor, not only the fourth transistor 104 but also the Since the third transistor 103 can also be discharged, the drop in the output potential can be prevented. Therefore, if the potential of node A is gradually decreased, the third Since the first transistor 103 is in an on state, discharging occurs only through the fourth transistor 104. The output potential can be decreased in a shorter time than the conventional transistor. By determining the size of the sixth transistor 106 according to the characteristics and drive specifications, A shift register with high efficiency can be realized.

[0090] In the fourth period 54, the CLK1 goes from the H level to the L level, and at the same time, the fifth A pulse signal (SROUT3) is input to the input terminal 25 of the eleventh transistor 111 When the eleventh transistor 111 is turned on, the voltage of the node B is The digit is VDD-Vth 111 The second transistor 102 and the fourth transistor The second transistor 102 and the sixth transistor 106 are turned on. and the fourth transistor 104 is turned on, so that the first output terminal 26 and the The potential of the output terminal 27 of the second transistor is VSS. The transistor 103 is turned off.

[0091] At this time, the node B is charged through the eleventh transistor 111, and the first The signal is transmitted through the first transistor 110 and the eighth transistor 108. The gates of the eighth transistor 110 and the eighth transistor 108 are connected to the third input terminal 23. and the second input terminal 22, and the gate capacitance is directly connected to the third input terminal 23 and acts as a load on the second input terminal 22.

[0092] In the shift register shown in this embodiment, the transistors connected to the clock line The load of the third transistor 103 is calculated by dividing the total number of stages of the shift register by 4. Lov of the first transistor 101 + the gate capacitance of the tenth transistor 110 + the gate capacitance of the eighth transistor The gate capacitance is expressed as ε0×ε×( It is expressed as L × W) / tox. Lov is the source electrode layer or drain electrode of the transistor. It represents the length in the channel length direction of the region where the drain electrode layer and the semiconductor layer overlap.

[0093] In order to reduce the gate capacitance connected to the clock line, the eighth transistor 108 and the tenth transistor The channel width (W) of the eleventh transistor 111 is (W). This reduces the load on the clock line. In addition, the tenth transistor 110 and the eighth transistor By reducing the channel width (W) of the transistor 108, the layout area is reduced. It can be done.

[0094] During the fifth period 55, the potential of the fifth input terminal 25 (i.e., SROUT3) is at the H level. By maintaining the potential at node B, the potential at node B is maintained. 102, the fourth transistor 104 and the sixth transistor 106 are kept in the on state. As a result, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level (see FIG. 4(B)).

[0095] During the sixth period 56, the fifth input terminal 25 (i.e., SROUT3) becomes L level. As a result, the eleventh transistor 111 is turned off. At this time, the node B is at the above-mentioned potential As a result, the second transistor 102 and the fourth transistor The sixth transistor 104 and the sixth transistor 106 remain in the on state (see FIG. 4C). The potential of the node B usually drops due to the off-current of the transistor, etc. A transistor with a relatively low off-state current (for example, a transistor including an oxide semiconductor) is used. In addition, in order to mitigate the drop in the potential of the node B, For this purpose, a capacitive element may be provided.

[0096] In the subsequent period, if both CLK2 and CLK3 are at the H level, The eighth transistor 108 and the tenth transistor 110 are turned on, and the Therefore, when a transistor with a relatively large off-state current is used, Even if the pulse signal output circuit is turned off, malfunction of the pulse signal output circuit can be prevented.

[0097] Regarding the output from the shift register (OUT1 to OUT4, etc.), when the potential rises For example, when the potential rises, When determining data (for example, when writing data), In addition, when determining data by the fall of the potential, the time when the potential falls is It is given importance.

[0098] When determining data by increasing the potential, it is necessary to shorten the time required for the potential to increase. To achieve this, the channel width of the third transistor 103 relative to the channel length L is The ratio W / L of W is the ratio W of the channel width W to the channel length L of the fourth transistor 104. It is preferable to set the value to be larger than / L.

[0099] When determining data by decreasing the potential, it is necessary to shorten the time required for the potential to decrease. To achieve this, the channel width of the third transistor 103 relative to the channel length L is The ratio W / L of W is the ratio W of the channel width W to the channel length L of the fourth transistor 104. It is preferable to set the value to be larger than / L.

[0100] However, in one embodiment of the disclosed invention, the potential of the node A is connected to the gate of the third transistor 103. The voltage is raised to a predetermined level by the bootstrap operation using the capacitive coupling between the This turns on the third transistor 103, causing it to output an H-level signal. Therefore, the ratio W / L of the channel width W to the channel length L of the third transistor 103 is If it is not large enough, the H level potential output by the shift register will rise to VDD. Therefore, the channel length L of the third transistor 103 may be It is desirable that the ratio W / L of the channel width W be sufficiently large.

[0101] The shift register shown in this embodiment receives the m-th pulse signal from the m-th pulse signal output circuit. The pulse output from the (m+1)th pulse signal output circuit is half overlapped with the pulse output from the (m+1)th pulse signal output circuit. Therefore, compared to when this driving method is not adopted, the wiring is charged. In other words, this driving method can extend the time that can be used for charging. A pulse signal output circuit is provided that can withstand loads and operate at high frequencies.

[0102] (Embodiment 2) In this embodiment, the pulse signal output circuit and the shift register shown in the previous embodiment are A configuration example different from the register and its operation will be described with reference to FIGS. 5 to 8. .

[0103] <Circuit configuration> First, a pulse signal output circuit and a shift register circuit including the pulse signal output circuit An example of the configuration will be described with reference to FIG.

[0104] The configuration of the shift register shown in this embodiment is the same as that of the shift register shown in the previous embodiment. The first difference is that the first pulse signal output circuit 10 _1 ~nth Pulse signal output circuit 10 _n The difference is that it does not have the third input terminal 23 (see FIG. 5(A)). (See Figure 5(C)). In other words, two types of clock signals are input to one pulse signal output circuit. The other configurations are the same as those of the previous embodiment.

[0105] First pulse signal output circuit 10 _1 ~ nth pulse signal output circuit 10 _n is the third input Since it does not have the terminal 23, it does not have the tenth transistor connected thereto (FIG. 5(C) )). Accordingly, the second input signal generating circuit 202 shown in FIG. 1 and the The connections of the second input signal generating circuit 203 are partially different.

[0106] Specifically, the first pulse signal output circuit 10 _1 ~ nth pulse signal output circuit 10 _n of Each of the pulse signals is generated by the first transistor 101 to the fourth transistor 104. The generating circuit 200 and the fifth to seventh transistors 105 to 107 are included. The first input signal generating circuit 201, the eighth transistor 108, the ninth transistor 10 a second input signal generating circuit 203 configured with a ninth and eleventh transistor 111; In addition to the first input terminal 21 to the fifth input terminal 25, the first power supply line 3 The first and second power supply lines 32 are connected to the first transistor 101 to the eleventh transistor 11. A signal is supplied to 1.

[0107] A specific example of the configuration of the second input signal generating circuit 203 is as follows.

[0108] a second terminal of the eighth transistor 108; a second terminal of the eleventh transistor 111; The first terminal of the ninth transistor 109 is electrically connected to the second input signal generating circuit. It functions as the output terminal of the path.

[0109] A first terminal of the eleventh transistor 111 and a first terminal of the eighth transistor 108 are connected to each other. The second potential is applied to the ninth transistor 109 via the second power supply line 32. A first potential is applied to the second terminal via the first power supply line 31. A pulse signal is input to the gate terminal of the eleventh transistor 111. The gate terminal of the second input signal generating circuit functions as a first input terminal of the second input signal generating circuit and also functions as a pulse The gate of the eighth transistor 108 also functions as the fifth input terminal 25 of the signal output circuit. The second clock signal CLK2 is input to the output terminal of the eighth transistor 10. The gate terminal of 8 functions as the second input terminal of the second input signal generating circuit and also functions as the second input terminal of the second input signal generating circuit. The ninth transistor 109 also functions as the second input terminal 22 of the pulse signal output circuit. A pulse signal is input to the gate terminal of the ninth transistor 109. serves as the third input terminal of the second input signal generating circuit and also serves as the pulse signal output circuit. It also serves as the fourth input terminal 24 of the path.

[0110] The above-described configuration is merely an example, and the disclosed invention is not limited to this.

[0111] In the following description of this embodiment, as in the previous embodiment, the pulse signal output shown in FIG. In the output circuit, the gate terminal of the first transistor 101 and the gate terminal of the third transistor 103 are connected to each other. A node formed by connecting the gate terminal and the output terminal of the first input signal generating circuit is , a node A. The gate terminal of the second transistor 102 and the gate terminal of the fourth transistor 103 are connected to each other. the gate terminal of the eighth transistor 104, the second terminal of the eighth transistor 108, and the gate terminal of the eleventh transistor 109; The second terminal of the ninth transistor 111 is connected to the first terminal of the ninth transistor 109. The node formed is called node B.

[0112] Between the node A and the first output terminal 26, a voltage is applied to suitably perform a bootstrap operation. In order to maintain the potential of the node B, a capacitor may be provided. An electrically connected capacitive element may be provided.

[0113] The first transistor 101 to the ninth transistor 109 and the eleventh transistor 1 An oxide semiconductor is preferably used for the layer 11. The off-current of the transistor can be reduced. Also, compared to amorphous silicon, It can increase on-current and field effect mobility, and also suppress transistor degradation. This allows for low power consumption, high speed operation, and high accuracy of operation. It is possible to realize an electronic circuit with improved performance. The star will be described in detail in a later embodiment, so a description thereof will be omitted here.

[0114] <Operation> Next, the operation of the shift register shown in FIG. 5 will be described with reference to FIGS. 6 to 8. Specifically, each of the first period 51 to the fifth period 55 in the timing chart shown in FIG. The operation in this case will be described with reference to FIGS. 7 and 8. In the timing chart, CLK1 to CLK4 indicates a clock signal, SP1 indicates a first start pulse, and OUT 1 to OUT4 are the first pulse signal output circuits 10 _1 -Fourth pulse signal output circuit 10 _ 4, and node A and node B are the outputs from the second output terminal of and SROUT1 to SROUT4 indicate the potentials of the first pulse signal output circuit 1. 0 _1 -Fourth pulse signal output circuit 10 _4 1 shows the output from the first output terminal of the

[0115] In the following description, the first transistor 101 to the ninth transistor 109, All of the transistors 111 are n-channel transistors. 7 and 8, when a transistor is represented by a solid line, the transistor When a transistor is in a conducting state (ON state), it is indicated by a dashed line. This indicates that the transistor is in a non-conducting state (off state).

[0116] Typically, the first pulse signal output circuit 10 _1 The operation of the first pulse signal is explained below. No. output circuit 10 _1 The configuration of the is as described above. The relationship between the potentials is as described above. In the following explanation, the potentials of the input terminals and power supply lines are All high potentials (also called H level or H signal) are VDD, and low potentials (L level) are All signals (also called L signals, L signals, etc.) are VSS.

[0117] During the first period 51, SP1 is at the H level, so the first pulse signal output circuit 10 _1 The gate terminal of the fifth transistor 105 serves as the fourth input terminal 24 of the ninth A high potential is applied to the gate terminal of the fifth transistor 105 and the second transistor 109. The ninth transistor 109 is turned on. Since a high potential is applied to the seventh transistor 107, the seventh transistor 107 is also turned on (see FIG. 7). (See (A)).

[0118] When the fifth transistor 105 and the seventh transistor 107 are turned on, The potential of node A rises. When the potential of node A is V AH (V AH =VDD-Vth 105 -Vth 107 ), the fifth transistor 105 and the seventh transistor 107 is turned off, and node A is V AH It becomes floating while maintaining this state.

[0119] The potential of node A is V AH , the first transistor 101 and the third transistor 103 is turned on. Here, since CLK1 is at the L level, the first output terminal 26 The second output terminal 27 outputs an L level signal.

[0120] In the second period 52, the potential of CLK1 switches from the L level to the H level. Since the first transistor 101 and the third transistor 103 are in an on state, The potential of the first output terminal 26 and the potential of the second output terminal 27 rise. There is a capacitance between the gate terminal and the source terminal (or drain terminal) of the transistor 101. This creates a capacitive coupling between the gate terminal and the source terminal (or drain terminal). Similarly, the gate terminal and the source terminal (or drain terminal) of the third transistor 103 are connected to each other. There is a capacitance between the gate terminal and the source terminal (or drain terminal), which Therefore, the potential of the first output terminal 26 and the potential of the second output terminal 27 are As the potential of the input terminal 27 rises, the potential of the floating node A also rises ( (Bootstrap operation). The potential of node A is finally VDD+Vth 101 Become higher The potential of the first output terminal 26 and the potential of the second output terminal 27 become VDD (H level). (See FIG. 6 and FIG. 7(B)).

[0121] During the third period 53, the potential of CLK2 becomes H level, and the eighth transistor 10 8 is turned on. This causes the potential at node B to rise. Therefore, the second transistor 102, the fourth transistor 104, and the sixth transistor The first output terminal 26 is turned on, and the potential at the node A drops. The potential of the second output terminal 27 and the potential of the second output terminal 28 become L level (see FIG. 7C).

[0122] During the fourth period 54, the potential of CLK2 becomes L level, and the eighth transistor 10 8 is turned off, but the potential of the fifth input terminal 25 (i.e., SROUT3) is at H level. Therefore, the eleventh transistor 111 is turned on. The potential of the node B is maintained at the potential of the third period 53, and the potential of the first output terminal 26 and The potential of the second output terminal 27 is maintained at the L level (see FIG. 8A).

[0123] During the fifth period 55, the potential of the fifth input terminal 25 (i.e., SROUT3) is at the L level. Therefore, the potential of the node B is maintained. The transistor 104 and the sixth transistor 106 are kept on, and the first output The potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level (see FIG. 8B). .

[0124] The potential of the node B usually drops due to the off-current of the transistor, etc. Applying a transistor with low off-state current (for example, a transistor using an oxide semiconductor) to In addition, in order to reduce the drop in the potential of the node B, In this case, the capacitor provided may be a capacitor between the second transistor 1 and the the gate terminal of the fourth transistor 102, the gate terminal of the sixth transistor 103, the gate terminal of the eighth transistor 106, the first terminal of the eighth transistor 108, and the gate terminal of the ninth transistor 109; 09 and the first terminal thereof.

[0125] In the subsequent period, when the potential of CLK2 becomes H level, the eighth transistor The resistor 108 is turned on, and a potential is periodically applied to the node B. Even when using a transistor with a relatively large current, malfunction of the pulse signal output circuit This can prevent this.

[0126] As described above, the configurations, methods, etc. shown in this embodiment are applicable to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0127] (Embodiment 3) In this embodiment, the pulse signal output circuit and the shift register shown in the previous embodiment are An example of a configuration different from that of the register will be described with reference to FIG.

[0128] The configuration of the shift register shown in this embodiment is the same as that of the shift register shown in the previous embodiment. The configuration of the n-th pulse signal output circuit 10 is similar to that of the n-th pulse signal output circuit 10. _n At the end of , the first dummy pulse signal output circuit 10 _D1 and a second dummy pulse signal output circuit 1 0 _D2(See FIG. 9(A)). road 10 _D1 and the second dummy pulse signal output circuit 10 _D2 is the n-1th pulse signal output power circuit 10 _n-1 and the n-th pulse signal output circuit 10 _n The fifth input terminal 25 of It has the function of supplying a signal.

[0129] First dummy pulse signal output circuit 10 _D1 and the second dummy pulse signal output circuit 10 _D There is no pulse signal output circuit after the 2. Unlike the circuit, the first dummy pulse signal output circuit 10 _D1 and the second dummy pulse signal Output circuit 10 _D2 The pulse signal from the next stage (in this case, the second stage) is not input to this. Therefore, the terminals corresponding to the fifth input terminal 25 in the first to n-th pulse signal output circuits are (See FIG. 9B and FIG. 9C). The eleventh transistor 111 is also absent (see FIG. 9C).

[0130] The function of the dummy pulse signal output circuits (first and second dummy pulse signal output circuits) is (n-1th to nth pulse signal output circuits) Therefore, the dummy pulse signal output circuit needs to be able to fully charge the node B. Here, the first to n-th pulse signal output circuits are required to have the ability to receive the clock signal. In order to reduce the power consumption due to the input, the eighth transistor 108 and the tenth transistor By reducing the size of the transistor 110 (for example, the channel width W or the channel length L), The eleventh transistor 111 reduces the ratio W / L of the channel width W to the On the other hand, it is effective to use a configuration that ensures the 11th Since the transistor 111 does not exist, the charging capacity of the eleventh transistor 111 is not supplemented. The eighth transistor 108 and the tenth transistor 110 You will need to increase the size.

[0131] Specifically, for example, the eighth transistor of the first and second dummy pulse signal output circuits is the channel width W of the 10th transistor (or the ratio of channel width W to channel length L) W / L) is applied to the eighth transistor or the tenth transistor of the first to nth pulse signal output circuits. The channel width W of the transistor (or the ratio W / L of the channel width W to the channel length L) By adopting such a configuration, the pulse signal output circuit of the normal stage (the nth (1) to (n) pulse signal output circuits, while ensuring proper operation. A shift register is realized.

[0132] The basic configuration of the dummy pulse signal output circuit is the same as that of the previous embodiment, except for the above differences. Specifically, the first pulse signal output circuit is the same as the first pulse signal output circuit shown in road 10 _1 ~ nth pulse signal output circuit 10 _n Each of the first transistors 101 to A dummy pulse signal generating circuit 204 configured by a fourth transistor 104 and a fifth transistor A first input signal generating circuit 205 configured from the seventh transistor 105 to the seventh transistor 107 and a second input signal composed of the eighth transistor 108 to the tenth transistor 110. The first power supply line 31 and the second power supply line 32 are connected to a first power supply line 32 and a second power supply line 32. A signal is supplied to the first transistor 101 to the tenth transistor 110.

[0133] In addition, the operation of the dummy pulse signal output circuit is the same as that of the previous stage except that the output of the next stage is not input. Therefore, the pulse signal output circuit is the same as that shown in the previous embodiment. The above embodiments can be referred to for details. In addition, the dummy pulse signal output circuit has at least The output to the pulse signal output circuits of the normal stages (pulse signal output circuits n-1 to n) is ensured. Therefore, the number of output terminals is not limited to two systems, and one system is also acceptable. It is possible to omit the terminal 26 or the second output terminal 27. In this case, The transistor associated with the omitted output terminal (for example, when the second output terminal 27 is omitted) In this case, the third transistor 103 and the fourth transistor 104 may be omitted as appropriate. That's fine.

[0134] As described above, the configurations, methods, etc. shown in this embodiment are applicable to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0135] (Fourth embodiment) In this embodiment, the pulse signal output circuit and the shift register described in the above embodiment are applied. An example of a transistor that can be implemented will be described with reference to FIG. is not particularly limited, and may be, for example, a top gate structure or a bottom gate structure, a staggered type or The transistor can be of any suitable structure, such as a planar type. The single gate structure has one channel formation region, and the multi-gate structure has two or more channel formation regions. The gate structure may be a gate insulating layer disposed above and below the channel region. A structure having two gate electrode layers may also be used.

[0136] 10A to 10D show examples of cross-sectional structures of transistors. The transistors illustrated in FIGS. 10A to 10D each use an oxide semiconductor as a semiconductor. The advantages of using oxide semiconductors are that they can be easily processed at low temperatures and have high mobility. This means that high mobility and low off-state current can be achieved.

[0137] The transistor 410 illustrated in FIG. 10A is an example of a bottom-gate transistor. It is also called an inverted staggered transistor.

[0138] The transistor 410 includes a gate electrode layer 401, a gate The insulating layer 402, the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 40 In addition, an insulating layer 407 is provided in contact with the oxide semiconductor layer 403. A protective insulating layer 409 is further formed on the layer 407 .

[0139] The transistor 420 shown in FIG. 10B is a channel-protective transistor (also called a channel-stop transistor). It is an example of a bottom-gate transistor called an inverted staggered transistor. It is also called.

[0140] The transistor 420 includes a gate electrode layer 401, a gate An insulating layer 402, an oxide semiconductor layer 403, an insulating layer 427 functioning as a channel protective layer, The semiconductor device further includes a source electrode layer 405a and a drain electrode layer 405b. It is being used.

[0141] The transistor 430 illustrated in FIG. 10C is an example of a bottom-gate transistor. The transistor 430 includes a gate electrode layer 401, a gate the source electrode layer 405a, the drain electrode layer 405b, and the oxide semiconductor layer An insulating layer 407 is provided in contact with the oxide semiconductor layer 403. A protective insulating layer 409 is further formed on the edge layer 407 .

[0142] In transistor 430, gate insulating layer 402 is formed between substrate 400 and gate electrode layer 400. On the gate insulating layer 402, a source electrode layer 405a and a drain electrode layer 405b are provided. The gate insulating layer 402 and the source electrode layer 405b are provided in contact with each other. The oxide semiconductor layer 403 is provided over the electrode layer 405a and the drain electrode layer 405b.

[0143] The transistor 440 illustrated in FIG. 10D is an example of a top-gate transistor. The transistor 440 is formed on a substrate 400 having an insulating surface, an insulating layer 437, an oxide semiconductor A conductor layer 403, a source electrode layer 405a, a drain electrode layer 405b, a gate insulating layer 402, and a gate electrode layer 401. The source electrode layer 405a and the drain electrode layer 405 The wiring layers 436a and 436b are provided in contact with the wiring layers 436a and 436b, respectively.

[0144] In this embodiment, as described above, the oxide semiconductor layer 403 is used as the semiconductor layer. The oxide semiconductor used for the compound semiconductor layer 403 is a quaternary metal oxide, In-Sn- Ga-Zn-O system, ternary metal oxides In-Ga-Zn-O system, In-Sn-Z nO system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system , Sn-Al-Zn-O system, binary metal oxides In-Zn-O system, In-Ga- O series, Sn-Zn-O series, Al-Zn-O series, Zn-Mg-O series, Sn-Mg-O series, I n-Mg-O system, and single-component metal oxides such as In-O system, Sn-O system, and Zn-O system In addition, SiO2 may be added to the oxide semiconductor. The a-Zn-O oxide semiconductor is an oxide containing at least In, Ga, and Zn. There is no particular limitation on the composition ratio of In, Ga, and Zn. Elements other than In, Ga, and Zn may also be included.

[0145] The oxide semiconductor layer 403 contains a compound having the chemical formula InMO3(ZnO) m (m>0, m: non-natural Here, M is gallium (Ga), and , aluminum (Al), manganese (Mn) and cobalt (Co). indicates multiple metal elements. For example, M can be Ga, Ga and Al, Ga and Mn, or or Ga and Co.

[0146] A transistor 410, a transistor 420, and a transistor using the oxide semiconductor layer 403 The off-state current of the transistor 430 and the transistor 440 can be made extremely small. By using this in a pulse signal output circuit or a shift register, it becomes easier to maintain the potential of each node. This makes it easier to minimize the probability of malfunction of the pulse signal output circuit and shift register. can be done.

[0147] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. For example, A glass substrate or a quartz substrate used in a liquid crystal display device or the like can be used. Alternatively, a substrate having an insulating layer formed on a silicon wafer may be used.

[0148] In the bottom gate structure transistors 410, 420, and 430, In this case, an insulating layer serving as a base may be provided between the substrate and the gate electrode layer. It has the function of preventing the diffusion of impurity elements from silicon nitride film, silicon oxide film, nitride film. The insulating film may be formed of one or more films selected from a silicon oxide film and a silicon oxynitride film. This can be done.

[0149] The gate electrode layer 401 is made of molybdenum, titanium, chromium, tantalum, tungsten, or aluminum. Metallic materials such as tungsten, copper, neodymium, scandium, etc., or alloy materials containing these as the main components The structure may be a single layer structure or a laminated structure. It is also possible to do so.

[0150] The gate insulating layer 402 is formed by depositing a silicon oxide film using a plasma CVD method, a sputtering method, or the like. Silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, nitride Aluminum film, aluminum oxynitride film, aluminum nitride oxide film, hafnium oxide film For example, the first gate insulating film may be made of one or more films selected from the following: As an edge layer, a silicon nitride film ( SiN y (y>0)) and forming a sputtering layer as a second gate insulating layer on the first gate insulating layer. Silicon oxide film (SiO ) with a thickness of 5 nm to 300 nm was formed by the annealing method.x (x>0) The gate insulating layer can be formed to a total thickness of about 300 nm.

[0151] The source electrode layer 405a and the drain electrode layer 405b are made of molybdenum, titanium, chromium, or titanium. Metallic materials such as aluminum, tungsten, aluminum, copper, neodymium, scandium, etc. For example, the material may be an alloy containing aluminum or copper as its main component. and a layered structure of a high melting point metal layer such as titanium, molybdenum, or tungsten. It is possible to prevent the formation of hillocks and whiskers by using elements (silicon, neodymium, Even if heat resistance is improved by using aluminum materials containing added scandium, good.

[0152] In addition, the source electrode layer 405a, the drain electrode layer 405b (wiring formed in the same layer as this) A conductive metal oxide film may be used as the conductive film (including the layer). The oxides include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO ), indium oxide tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO) ), indium oxide zinc oxide alloy (In2O3-ZnO) or these metal oxide materials and the like containing silicon oxide.

[0153] The wiring layer 436a and the wiring layer 436 are in contact with the source electrode layer 405a and the drain electrode layer 405b. The electrode layer 405b is formed using the same material as the source electrode layer 405a and the drain electrode layer 405b. It can be achieved.

[0154] The insulating layer 407, the insulating layer 427, and the insulating layer 437 are typically made of a silicon oxide film, a silicon oxide film, or a silicon dioxide film. Inorganic insulating films such as silicon nitride films, aluminum oxide films, or aluminum oxynitride films can be used.

[0155] The protective insulating layer 409 may be a silicon nitride film, an aluminum nitride film, or a silicon nitride oxide film. An inorganic insulating film such as an aluminum nitride oxide film can be used.

[0156] In addition, a planarizing insulating layer is formed on the protective insulating layer 409 to reduce surface irregularities caused by the transistor. The planarization insulating film may be formed using a material such as polyimide, acrylic, or benzocyclobutene. In addition to the above organic materials, low dielectric constant materials (L It is possible to use insulating films made of these materials. A planarizing insulating film may be formed by stacking.

[0157] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0158] (Embodiment 5) In this embodiment, an example of a transistor including an oxide semiconductor layer and a manufacturing method thereof will be described. This will be explained in detail using FIG.

[0159] 11A to 11E are cross-sectional views showing a manufacturing process of a transistor. The transistor 510 shown in FIG. 10A has an inversely staggered structure similar to the transistor 410 shown in FIG. It is a type transistor.

[0160] The oxide semiconductor used in the semiconductor layer of this embodiment is an oxide semiconductor that does not contain hydrogen as an n-type impurity. and purify the oxide semiconductor to minimize the amount of impurities other than the main component. This results in an i-type (intrinsic) oxide semiconductor or an oxide semiconductor that is as close to i-type (intrinsic) as possible. This is what was done.

[0161] Note that the number of carriers in a highly purified oxide semiconductor is extremely small, and the carrier concentration is 1× 10 14 / cm 3 Less than 1 x 10 12 / cm 3 Less than 1×1 0 11 / cm 3 In addition, because of this small number of carriers, The current (off-state current) is sufficiently small.

[0162] Specifically, in the transistor including the above-described oxide semiconductor layer, The off-state current density per 1 μm of channel width is calculated as follows: When the voltage between the source and drain of the transistor is 3V, the current is 100zA / μm(1 x10 -19 A / μm) or less, and even 10zA / μm (1×10 -20 A / μm) or less It is possible to do this.

[0163] Furthermore, the transistor 510 including the highly purified oxide semiconductor layer has a temperature Almost no dependence is observed, and the off-current remains very small.

[0164] 11A to 11E, a process for manufacturing a transistor 510 on a substrate 505 will be described. Explain the process.

[0165] First, a conductive film is formed on a substrate 505 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 511 is formed by the photolithography process. The resist mask may be formed by an ink-jet method. When the film is formed by the photolithography method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0166] The substrate 505 having an insulating surface is the same as the substrate 400 in the above embodiment. In this embodiment mode, a glass substrate is used as the substrate 505.

[0167] Note that a base insulating layer may be provided between the substrate 505 and the gate electrode layer 511. The insulating layer has a function of preventing the diffusion of impurity elements from the substrate 505, and the silicon nitride film , a silicon oxide film, a silicon nitride oxide film, a silicon oxynitride film, or the like. It can be formed by multiple films.

[0168] The gate electrode layer 511 may be formed of molybdenum, titanium, chromium, tantalum, tungsten, or Metallic materials such as aluminum, copper, neodymium, scandium, etc., or alloys containing these as their main components The metal layer can be formed using a gold material. The metal layer can have a single layer structure or a laminated structure. A layer structure may also be used.

[0169] Next, a gate insulating layer 507 is formed on the gate electrode layer 511. The gate insulating layer 507 is The silicon oxide film can be formed by using a plasma CVD method, a sputtering method, or the like. silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film , aluminum nitride film, aluminum oxynitride film, aluminum nitride oxide film, hafnium oxide The insulating film may be formed of one or more films selected from the group consisting of silicon films and the like.

[0170] Note that the gate insulating layer 507 and the oxide semiconductor film 530 contain hydrogen, a hydroxyl group, and moisture as much as possible. In order to prevent the oxide semiconductor film 530 from being broken down, a sputtering apparatus was used as a pretreatment for forming the oxide semiconductor film 530. The substrate 505 on which the gate electrode layer 511 is formed in the preheating chamber or the gate insulating layer 507 The substrate 505 on which the above-mentioned structure is formed is preheated, and hydrogen, moisture, etc. adsorbed on the substrate 505 are removed. It is preferable to desorb impurities. In addition, the preheating is preferably performed by heating the source electrode layer 515a and the drain electrode layer 515b. This preheating process may be performed on the substrate 505 on which the electrode layer 515b has already been formed. The logic can be omitted.

[0171] Next, a film having a thickness of 2 nm to 200 nm, preferably 5 nm or more, is formed on the gate insulating layer 507. An oxide semiconductor film 530 having a thickness of 30 nm or less is formed (see FIG. 11A).

[0172] The oxide semiconductor film 530 may be formed of a quaternary metal oxide or a ternary metal oxide described in the above embodiment. Materials, binary metal oxides, In-O, Sn-O, Zn-O, etc. can be used. .

[0173] As a target for forming the oxide semiconductor film 530 by a sputtering method, in particular, In: A composition ratio of Ga:Zn=1:x:y (x is 0 or more, y is 0.5 or more and 5 or less) For example, In2O3:Ga2O3:ZnO=1:1:2 [mol A target having a composition ratio of In2O3:Ga can also be used. 2O3:ZnO=1:1:1 [molar ratio] and In2O3 :Ga2O3:ZnO=1:1:4 [molar ratio], A target having a composition ratio of 2O3:Ga2O3:ZnO=1:0:2 [molar ratio] was used. It can also be used.

[0174] In this embodiment, the amorphous oxide semiconductor layer is formed by using an In—Ga—Zn—O-based metal oxide. The film is formed by sputtering using a metal target.

[0175] The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more; More preferably, it is 99.9% or more. A metal oxide target with a high relative density is used. This makes it possible to form an oxide semiconductor layer with a dense structure.

[0176] The oxide semiconductor film 530 is formed in a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It is preferable to use a mixed atmosphere of oxygen or a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present at a concentration of 1 ppm or less. It is preferable to use a high-purity gas atmosphere in which the concentration has been reduced to 10 ppb or less. is.

[0177] When the oxide semiconductor film 530 is formed, for example, a processing chamber is maintained in a reduced pressure state. The object is held in a state where the temperature of the object to be treated is 100°C or higher but lower than 550°C, preferably 200°C or higher but lower than 40°C. The object to be processed is heated to 0° C. or lower. The temperature of the material to be treated may be room temperature (25°C ± 10°C (15°C or higher and 35°C or lower)). Then, the moisture in the processing chamber is removed, and sputtering gas from which hydrogen and water have been removed is introduced. The oxide semiconductor film 530 is formed using the target. By forming the conductive film 530, impurities contained in the oxide semiconductor layer can be reduced. It is also possible to reduce damage caused by sputtering. For this purpose, it is preferable to use an adsorption type vacuum pump. A pump, a titanium sublimation pump, etc. can be used. A cryopump or similar device may be used to evacuate the gas. By this, hydrogen, water, and the like can be removed from the treatment chamber. The impurity concentration in the

[0178] The oxide semiconductor film 530 is formed under the following conditions: The diameter was 170 mm, the pressure was 0.4 Pa, the direct current (DC) power was 0.5 kW, and the atmosphere was oxygen (oxygen 100%) atmosphere, or argon (100% argon) atmosphere, or oxygen and argon It is possible to apply conditions such as a mixed atmosphere of pulsed direct current (DC) power supply. When used, it is possible to reduce powdery substances (also called particles or dust) generated during film formation, and improve film thickness. The thickness of the oxide semiconductor film 530 is preferably greater than or equal to 1 nm and greater than or equal to 50 nm. Preferably, the thickness is 1 nm or more and 30 nm or less, and more preferably, the thickness is 1 nm or more and 10 nm or less. By using the oxide semiconductor film 530 having such a thickness, the short channel effect associated with miniaturization can be reduced. However, depending on the oxide semiconductor material used and the application of the semiconductor device, The appropriate thickness varies depending on the material and application. It is also possible to do so.

[0179] Note that before the oxide semiconductor film 530 is formed by a sputtering method, argon gas is introduced. Then, reverse sputtering is performed to generate plasma, and the surface to be formed (for example, the surface of the gate insulating layer 507) is Here, the reverse sputtering is the same as in the normal sputtering. In this method, instead of bombarding the sputtering target with ions, the ions are bombarded on the surface to be treated. This refers to a method of modifying a surface by bombarding it with ions. The method of applying the high frequency voltage to the surface to be treated in an argon atmosphere is There are methods for generating plasma in the near future. An atmosphere of oxygen or the like may be used.

[0180] Next, the oxide semiconductor film 530 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. The resist mask used in the photolithography process is an ink. If the resist mask is formed by the ink jet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0181] Note that when a contact hole is formed in the gate insulating layer 507, the process is performed using an oxide semiconductor This can be done simultaneously with the processing of the film 530 .

[0182] The oxide semiconductor film 530 may be etched by dry etching or wet etching. For example, the oxide semiconductor film 530 may be wet-etched using a The etching solution may be a mixture of phosphoric acid, acetic acid, and nitric acid. ITO07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0183] Then, the oxide semiconductor layer is subjected to heat treatment (first heat treatment) to form an oxide semiconductor layer 53 By the first heat treatment, excess water in the oxide semiconductor layer is removed. The oxide semiconductor layer is then structured to remove oxygen (including water and hydroxyl groups), and the energy gap is The temperature of the first heat treatment is, for example, 300° C. or higher and 55° C. or lower. The temperature must be below 0°C or between 400°C and 500°C.

[0184] The heat treatment is carried out by, for example, placing the object to be treated in an electric furnace using a resistance heating element, and heating the object in a nitrogen atmosphere. The process can be carried out under the conditions of 450°C for 1 hour. During this time, the oxide semiconductor layer is not exposed to the air. Ensure that water and hydrogen do not get mixed in.

[0185] Heat treatment equipment is not limited to electric furnaces, and may be heat conduction or heat radiation from a medium such as heated gas. For example, a device for heating the object to be treated may be used. pid Thermal Anneal equipment, GRTA (Gas Rapid The RTA (Rapid Thermal Anneal) equipment ) equipment can be used. The LRTA equipment is a device that uses halogen lamps, metal halide lamps, etc. lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a The GRTA device is a device that performs heat treatment using high-temperature gas. Inert gases such as rare gases like argon or nitrogen that do not react with the material to be treated by heat treatment. The body is used.

[0186] For example, in the first heat treatment, the workpiece is placed in a heated inert gas atmosphere and heated for several minutes. After the heating, the object to be treated may be taken out of the inert gas atmosphere and subjected to GRTA treatment. GRTA treatment allows high-temperature heat treatment in a short time. It is possible to apply this method even under temperature conditions exceeding 100°C. During the treatment, an inert gas is used instead of oxygen. By performing the first heat treatment in an atmosphere containing oxygen, This is because the defect level in the energy gap caused by oxygen vacancies can be reduced. .

[0187] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing ) as the main component and not containing water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into a heat treatment device Purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0188] In either case, the first heat treatment reduces impurities and produces an i-type (intrinsic semiconductor) or i-type By forming an oxide semiconductor layer that is as close to the original thickness as possible, a transistor with extremely excellent characteristics can be realized. It can be realized.

[0189] By the way, the above-mentioned heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc. This heat treatment can also be called a dehydration treatment or a dehydrogenation treatment. The dehydrogenation treatment is performed after the oxide semiconductor film 530 is formed and before the oxide semiconductor film 530 is processed into an island-shaped oxide semiconductor layer. In addition, such dehydration treatment and dehydrogenation treatment can be carried out in one step. It may be performed multiple times without limitation.

[0190] In addition to the above, the first heat treatment may be performed after forming the source electrode layer and the drain electrode layer. This is performed after forming an insulating layer on the source electrode layer and the drain electrode layer. It is possible to do so.

[0191] Next, a source electrode layer and a drain electrode layer are formed on the gate insulating layer 507 and the oxide semiconductor layer 531. A conductive film is formed to become the source electrode layer (including wiring formed in the same layer). The conductive film used for the drain electrode layer and the drain electrode layer may be formed using the materials described in the above embodiment modes. It can be used.

[0192] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 515a and the drain electrode layer 515b by etching, The mask is removed (see FIG. 11(C)).

[0193] The third photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. It is recommended to use laser light or ArF laser light. The channel length (L) is determined by the distance between the source electrode layer and the drain electrode layer. The exposure for forming a mask used in manufacturing transistors of less than 25 nm requires a size of several nm to several tens of nm. It is desirable to use extreme ultraviolet light with a short wavelength of 1000 m. Extreme ultraviolet light exposure has high resolution and a large depth of focus. The channel length (L) of the transistor is set to 10 nm or more and 1000 nm (1 μm) or less. This makes it possible to increase the operating speed of the circuit. It is also possible to reduce the power consumption of the semiconductor device.

[0194] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The etching step may be performed using a resist mask formed by a photomask. The resist mask formed using the gradation mask has areas of different thickness, allowing etching By repeating this process, the shape can be further deformed, allowing for multiple processes to be performed to create different patterns. Therefore, a single multi-tone mask can be used for a small number of etching processes. It is possible to form resist masks corresponding to at least two different patterns. This reduces the number of exposure masks and the corresponding photolithography steps. This allows for a reduction in the number of steps, thereby simplifying the process.

[0195] Note that when the conductive film is etched, the oxide semiconductor layer 531 is divided by etching. It is desirable to optimize the etching conditions so as not to cause the conductive The condition that only the film is etched and the oxide semiconductor layer 531 is not etched at all is obtained. It is difficult to form the oxide semiconductor layer 531 by etching the conductive film. A groove (recess) may also be formed.

[0196] The conductive film may be etched by either wet etching or dry etching. From the viewpoint of miniaturization of elements, it is preferable to use dry etching. The etching gas and etching solution can be selected appropriately depending on the material to be etched. In this embodiment, a titanium film is used as the conductive film, and an In film is used as the oxide semiconductor layer 531. -Because Ga-Zn-O based materials are used, when wet etching is applied, for example, The etchant used was ammonia hydrogen peroxide (31% by weight hydrogen peroxide solution: 28% by weight ammonia hydrogen peroxide solution). Niacin:water = 5:2:2) can be used.

[0197] Then, gases such as nitrous oxide (N2O), nitrogen (N2), or argon (Ar) are used. The exposed surface of the oxide semiconductor layer is then subjected to plasma treatment. When performing the plasma treatment, it is advisable to remove the An insulating layer 516 is formed to serve as a protective insulating film.

[0198] The insulating layer 516 has a thickness of at least 1 nm, and is formed by a method such as sputtering. It is preferable to form the insulating layer 516 by using a method that does not mix impurities such as silicon dioxide and hydrogen. When hydrogen is contained, the hydrogen penetrates into the oxide semiconductor layer and the hydrogen is released from the oxide semiconductor layer. This causes the back channel of the oxide semiconductor layer to become low-resistance (n-type). This is because there is a risk of a parasitic channel being formed due to the presence of oxide silicon in the insulating layer 516. silicon oxide film, silicon oxynitride film, aluminum oxide film, or aluminum oxynitride film It is preferable to use

[0199] In this embodiment, a silicon oxide film having a thickness of 200 nm is deposited as the insulating layer 516 by sputtering. The substrate temperature during film formation should be between room temperature (25°C) and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering. (typically argon) atmosphere, oxygen atmosphere, or a mixture of rare gas and oxygen atmosphere The target may be a silicon oxide target or a silicon target. A target can be used.

[0200] As in the case of forming the oxide semiconductor film 530, residual moisture in the deposition chamber for the insulating layer 516 is removed. To achieve this, it is preferable to use an adsorption type vacuum pump (such as a cryopump). By forming the film in a film formation chamber evacuated using an opto-pump, impurities contained in the insulating layer 516 can be reduced. In addition, the concentration of the insulating layer 516 can be reduced by using an exhaust method to remove residual moisture in the deposition chamber. The stage may be a turbo pump with a cold trap added.

[0201] The sputtering gas used to form the insulating layer 516 is a high-purity gas from which impurities such as hydrogen and water have been removed. Preferably it is a gas.

[0202] Next, a second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature is 200°C or higher and 450°C or lower, preferably 250°C or higher and 350°C or lower. For example, the second heat treatment may be performed at 250° C. for 1 hour in a nitrogen atmosphere. This can reduce variations in the electrical characteristics of the transistors. 516 to the oxide semiconductor layer 531, oxygen is supplied to the oxide semiconductor layer 531. The defects are filled to form an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is as close to i-type as possible. It is also possible to do so.

[0203] In this embodiment, the second heat treatment is performed after the insulating layer 516 is formed. The timing of the heat treatment is not limited to this. For example, the first heat treatment may be followed by the second heat treatment. Alternatively, the first heat treatment may also serve as the second heat treatment.

[0204] As described above, the oxide semiconductor layer 531 is formed by the first heat treatment and the second heat treatment. It is possible to purify it to the extent possible so that it contains as few impurities as possible other than the main component, and make it i-type (intrinsic). Cut.

[0205] Through the above steps, the transistor 510 is formed (see FIG. 11D).

[0206] It is desirable to further form a protective insulating layer 506 on the insulating layer 516 (see FIG. 11( The protective insulating layer 506 prevents the intrusion of hydrogen, water, and other substances from the outside. The edge layer 506 may be made of, for example, a silicon nitride film or an aluminum nitride film. Although there is no particular limitation on the film formation method, RF sputtering is suitable for mass production, so it is suitable for protective insulation. This is a suitable method for forming the layer 506.

[0207] After the protective insulating layer 506 is formed, the substrate is further heated in the atmosphere at 100° C. or higher and 200° C. or lower for 1 The heat treatment may be carried out under the conditions of 100 to 30 hours.

[0208] In this manner, the transistor including the highly purified oxide semiconductor layer manufactured according to this embodiment The off-state current of this transistor is extremely small. By using a resistor, it becomes easier to maintain the potential of the node. By using it in an output circuit or shift register, it can prevent malfunction of the pulse signal output circuit or shift register. The probability can be kept extremely low.

[0209] As described above, the configurations, methods, etc. shown in this embodiment are applicable to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0210] (Embodiment 6) The display function can be realized by using the shift registers shown as examples in the above-mentioned first to third embodiments. A semiconductor device (also called a display device) having the above structure can be manufactured. Alternatively, the entire display can be formed on the same substrate as the pixel section to form a system-on-panel. can.

[0211] Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements), light-emitting elements (light-emitting The light-emitting element can change its brightness depending on the current or voltage. This category includes elements that are controlled by the Also, electronic inks and other electronic devices that use electrical effects are included. Display media with more variable contrast can also be applied.

[0212] In FIG. 12A, a pixel portion 4002 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided, and the first substrate 4001 and the second substrate 4006 In FIG. 12A, a sealing material 4005 on a first substrate 4001 Therefore, in an area different from the enclosed area, a scanning line driving circuit 40 is provided on a separately prepared substrate. 4004, and a signal line driver circuit 4003 are mounted. 003, and various signals and potentials given to the scanning line driver circuit 4004 or the pixel portion 4002. is FPC (Flexible printed circuit)4018a, 401 It is supplied by 8b.

[0213] In FIG. 12B and FIG. 12C, the pixel portion 40 is provided on the first substrate 4001. A sealant 4005 is provided so as to surround the gate electrode 4002 and the scanning line driver circuit 4004. In addition, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driver circuit 4004. Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are connected to the first substrate 4001. The display element is sealed by a sealant 4005 and a second substrate 4006 . In FIG. 12(B) and FIG. 12(C), the sealing material 4005 on the first substrate 4001 Therefore, in an area different from the area surrounded by the signal line driver circuit 40, a signal line driver circuit 40 is provided on a separately prepared substrate. 03 is implemented. In Fig. 12(B) and Fig. 12(C), a separately formed signal A scanning line driver circuit 4003 and various signals provided to a scanning line driver circuit 4004 or a pixel portion 4002 Signals and potentials are supplied from FPC4018.

[0214] In addition, in FIG. 12(B) and FIG. 12(C), a signal line driver circuit 4003 is separately formed. Although an example in which the scanning line is mounted on the first substrate 4001 is shown, the present invention is not limited to this configuration. The driver circuit may be formed separately and mounted, or may be mounted as part of the signal line driver circuit or the scanning line driver circuit. Alternatively, only a part of the above may be formed separately and mounted.

[0215] The method of connecting the separately formed drive circuit is not particularly limited, and may be ip On Glass) method, wire bonding method, or TAB (Tape A A method such as a fused bonding method can be used. This is an example in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are implemented by the COG method. 12B shows an example in which a signal line driver circuit 4003 is mounted by the COG method. 2(C) is an example in which the signal line driver circuit 4003 is mounted by the TAB method.

[0216] The display device also includes a panel in which a display element is sealed, and a controller for the panel. and modules in which ICs, etc., including the above are mounted.

[0217] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. Also refers to connectors, such as FPC or TAB tape. Modules with TCP attached, TAB tape or TCP with a printed wiring board attached The IC (integrated circuit) is directly mounted on the module or display element using the COG method. All such modules are also included in the display device.

[0218] The pixel portion provided on the first substrate has a plurality of transistors. The transistors exemplified in the previous embodiments may be used as the transistors.

[0219] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, etc. These liquid crystal materials include ferroelectric liquid crystal, polymer dispersed liquid crystal, antiferroelectric liquid crystal, etc. Depending on the conditions, cholesteric phase, smectic phase, cubic phase, chiral nematic phase, etc. It shows the crystalline phase, isotropic phase, etc.

[0220] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. To achieve this, it is advisable to use a liquid crystal composition containing 5% by weight or more of a chiral agent in the liquid crystal layer. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a short response time of 1 msec or less. Since the liquid crystal display is optically isotropic, no alignment treatment is required and the viewing angle dependency is small. Therefore, the rubbing process is not required. This can prevent electrostatic damage caused by the electrostatic discharge, and can prevent defects and damage to the liquid crystal display device during the manufacturing process. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0221] The specific resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The resistivity values ​​in this document are those measured at 20°C.

[0222] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. It is set so that the charge can be held for a predetermined period, taking into consideration the current and other factors. The magnitude may be set in consideration of the off-state current of the transistor and the like.

[0223] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, FFS (Fringe Field Switching) mode ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. Use uid Crystal mode, etc.

[0224] Furthermore, normally black type liquid crystal display devices, for example, those employing vertical alignment (VA) mode A VA type liquid crystal display device is a liquid crystal display device in which the liquid crystal of the liquid crystal display panel is It is a type of method that controls the arrangement of molecules. VA type LCD displays When the liquid crystal molecules are not aligned, they are oriented vertically relative to the panel surface. There are several examples of this, such as MVA (Multi-Domain Verification). cal Alignment) mode, PVA(Patterned Vertical) mode Alignment mode, ASV mode, etc. can be used. The pixel is divided into several regions (subpixels), and the molecules are tilted in different directions in each region. We use a method called multi-domain or multi-domain design, which is designed to It is possible.

[0225] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflecting members, For example, a polarizing substrate and a retardation substrate are provided. Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0226] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may be different for each dot of the color element. The present invention is not limited to color display devices, but can also be applied to monochrome display devices. It is also possible to do so.

[0227] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element using electroluminescence can be applied to a light-emitting material They are distinguished by whether they are organic or inorganic compounds, and generally, the former are organic E The latter is called an inorganic EL element.

[0228] In an organic EL element, when a voltage is applied to the light-emitting element, electrons and positive charges are released from a pair of electrodes. The holes are then injected into a layer containing a light-emitting organic compound, allowing a current to flow. The recombination of carriers (electrons and holes) causes light-emitting organic compounds to form excited states. The excited state is formed, and light is emitted when the excited state returns to the ground state. The optical element is called a current-excited light-emitting element.

[0229] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. It is a localized emission that uses

[0230] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display), and is a paper It is possible to make it as easy to read as a digital camera, consume less power than other display devices, and have a thinner and lighter form factor. This has the advantage that

[0231] The electrophoretic display device may have various forms, but it has a structure in which first particles having a positive charge and and a second particle having a negative charge. By applying an electric field to the microcapsules, The particles in the cell are moved in opposite directions to each other, and only the color of the particles that gather on one side is displayed. The first particles or the second particles contain a dye, and when there is no electric field, they move. The color of the first particle and the color of the second particle are different (including colorless). )

[0232] In this way, the electrophoretic display device moves materials with high dielectric constants to areas with high electric fields, so-called This is a display that utilizes the dielectrophoretic effect.

[0233] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0234] The first particles and the second particles in the microcapsules may be made of a conductive material or an insulating material. , semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of electrochromic materials, magnetophoretic materials, and composite materials of these. Just use

[0235] In addition, a display device using a twist ball display method can also be applied as electronic paper. The twist ball display method uses spherical particles painted in black and white as the display element. The first electrode layer and the second electrode layer are disposed between the first electrode layer and the second electrode layer. This is a display method that controls the orientation of spherical particles by creating a potential difference between the electrode layers. be.

[0236] The display device exemplified above may be provided with the pulse signal output circuit shown in the first or second embodiment. By applying the circuit, it is possible to provide a display device having various functions.

[0237] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0238] (Embodiment 7) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also known as mobile phones or mobile phone devices), (c), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples include:

[0239] FIG. 13(A) shows a semiconductor device manufactured by mounting the semiconductor device disclosed in this specification as at least one component. The notebook-type personal computer is a computer having a main body 3001, a housing 3002, a display unit 3003, and a 003, keyboard 3004, etc.

[0240] FIG. 13B shows a semiconductor device manufactured by mounting the semiconductor device disclosed in this specification as at least one component. The main body 3021 is a personal digital assistant (PDA) with a display unit 3023 and an external interface. A face 3025 and operation buttons 3024 are provided. There is a stylus 3022.

[0241] The semiconductor device disclosed in this specification can also be used as electronic paper. 13(C) is an electronic book created by mounting the electronic paper as a component. C) shows an example of an electronic book. For example, an electronic book 2700 includes a housing 2701 and The housing 2701 and the housing 2703 are made up of two housings. The opening and closing operation can be performed with the shaft portion 2711 as an axis. This configuration allows the device to function like a paper book.

[0242] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 13C), and An image can be displayed on the display portion (the display portion 2707 in FIG. 13C).

[0243] FIG. 13C shows an example in which an operation unit and the like are provided in the housing 2701. For example, The housing 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The surface may be provided with a keyboard, a pointing device, etc. On the back and sides, there are external connection terminals (earphone terminal, USB terminal, etc.), storage media insertion port, etc. Furthermore, the electronic book 2700 may have a function as an electronic dictionary. A similar configuration may also be used.

[0244] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0245] FIG. 13(D) shows a semiconductor device manufactured by mounting the semiconductor device disclosed in this specification as at least one component. It is a mobile phone that is made up of two housings, housing 2800 and housing 2801. The body 2801 includes a display panel 2802, a speaker 2803, a microphone 2804, Pointing device 2806, camera lens 2807, external connection terminal 2808, etc. The housing 2800 also includes a solar cell 28 for charging the portable information terminal. 10, an external memory slot 2811, etc. The antenna is located inside the housing 2801. It is built into the part.

[0246] The display panel 2802 is equipped with a touch panel, and the image displayed on the display panel 2802 is shown in FIG. The multiple operation keys 2805 are indicated by dotted lines. It also has a boost circuit to boost the voltage required for each circuit.

[0247] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the camera lens 2802, so video calls are possible. The speaker 2803 and microphone 2804 are not limited to voice calls, but also to video calls, Recording and playback are possible. Furthermore, the housing 2800 and the housing 2801 can be slid apart. As shown in 13(D), it can be folded from the unfolded state to the overlapped state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0248] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the memory slot 2811, it is possible to store and transfer a larger amount of data. We can handle it.

[0249] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0250] FIG. 13(E) shows a semiconductor device manufactured by mounting the semiconductor device disclosed in this specification as at least one component. It is a digital video camera, and it has a main body 3051, a first display unit 3057, an eyepiece unit 3053 , an operation switch 3054, a second display unit 3055, a battery 3056, etc. It has been done.

[0251] FIG. 13(F) shows a television in which the semiconductor device disclosed in this specification is mounted as at least one component. The television device 9600 has a display unit mounted on a housing 9601. The display unit 9603 is capable of displaying images. In addition, the configuration shown here is such that the housing 9601 is supported by a stand 9605. .

[0252] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by a remote control operator. A display unit for displaying the output information may be provided.

[0253] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0254] As described above, the configurations, methods, etc. shown in this embodiment are applicable to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination. [Explanation of symbols]

[0255] 11 Signal line 12 Signal line 13 Signal line 14 Signal line 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 input terminals 25 Input terminals 26 Output terminal 27 Output terminal 31 Power line 32 Power line 51 period 52 period 53 period 54 period 55 period 56 period 101 Transistor 102 transistor 103 Transistor 104 transistors 105 transistors 106 transistors 107 Transistor 108 transistors 109 Transistor 110 Transistor 111 Transistor 200 Pulse signal generation circuit 201 first input signal generating circuit 202 second input signal generating circuit 203 Second input signal generating circuit 204 Dummy pulse signal generating circuit 205 First input signal generating circuit 206 Second input signal generating circuit 400 boards 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Insulating Layer 409 Protective Insulation Layer 410 Transistor 420 transistors 427 Insulating Layer 430 transistors 436a Wiring layer 436b wiring layer 437 Insulating Layer 440 transistors 505 board 506 Protective insulation layer 507 Gate insulating layer 510 Transistor 511 Gate electrode layer 515a Source electrode layer 515b Drain electrode layer 516 Insulating Layer 530 Oxide semiconductor film 531 Oxide semiconductor layer 2700 e-books 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 2800 chassis 2801 Case 2802 Display panel 2803 Speaker 2804 Microphone 2805 Operation Key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 solar cell 2811 external memory slot 3001 main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main Unit 3022 stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main Unit 3053 Eyepiece 3054 Operation switch 3055 Display section 3056 Battery 3057 Display section 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4018 FPC 4018a FPC 4018b FPC 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand

Claims

1. A shift register is included. the shift register includes first to eighth transistors; one of the source and the drain of the first transistor is always electrically connected to an output signal line; the other of the source and the drain of the first transistor is always electrically connected to a first clock signal line; one of the source and the drain of the second transistor is always electrically connected to the first power supply line; the other of the source and the drain of the second transistor is always electrically connected to the output signal wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the one of the source and the drain of the fourth transistor; the gate of the third transistor is always electrically connected to the second power supply line; the other of the source and the drain of the fourth transistor is always electrically connected to the second power supply line; a gate of the fourth transistor is always electrically connected to a first signal line; one of the source and the drain of the fifth transistor is always electrically connected to the first power supply line; the other of the source and the drain of the fifth transistor is always electrically connected to the other of the source and the drain of the third transistor; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the first power supply line; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; a gate of the sixth transistor is always electrically connected to the first signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the second power supply line; the gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to a second clock signal line; When the other of the source or drain of the eighth transistor is in a state of conduction with the gate of the second transistor and the gate of the fifth transistor via at least a channel formation region of the eighth transistor, a potential at which at least the second transistor is turned on and a potential at which the fifth transistor is turned on are input to the gate of the second transistor and the gate of the fifth transistor via at least a channel formation region of the eighth transistor.

2. A shift register is included. the shift register includes first to eighth transistors; one of the source and the drain of the first transistor is always electrically connected to an output signal line; the other of the source and the drain of the first transistor is always electrically connected to a first clock signal line; one of the source and the drain of the second transistor is always electrically connected to the first power supply line; the other of the source and the drain of the second transistor is always electrically connected to the output signal wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the one of the source and the drain of the fourth transistor; the gate of the third transistor is always electrically connected to the second power supply line; the other of the source and the drain of the fourth transistor is always electrically connected to the second power supply line; a gate of the fourth transistor is always electrically connected to a first signal line; one of the source and the drain of the fifth transistor is always electrically connected to the first power supply line; the other of the source and the drain of the fifth transistor is always electrically connected to the other of the source and the drain of the third transistor; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the first power supply line; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; a gate of the sixth transistor is always electrically connected to the first signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the second power supply line; the gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the second transistor; the gate of the eighth transistor is always electrically connected to a second clock signal line; when the other of the source or the drain of the eighth transistor is in a state of conduction with the gate of the second transistor and the gate of the fifth transistor via at least a channel formation region of the eighth transistor, a potential at which at least the second transistor is turned on and a potential at which the fifth transistor is turned on are input to the gate of the second transistor and the gate of the fifth transistor via at least a channel formation region of the eighth transistor, a W / L (W is a channel width, L is a channel length) of the first transistor is larger than a W / L of the fifth transistor; The semiconductor device wherein the W / L of the fourth transistor is larger than the W / L of the fifth transistor.

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