Thin film transistor and display device including the same

Abstract

To provide a thin film transistor and a display device including the same, in which the channel length can be reduced or minimized.SOLUTION: A thin film transistor and a display device including the same are disclosed. The transistor includes a first gate electrode on a substrate, a gate insulating film on the first gate electrode, a first active layer on the gate insulating film, a drain electrode on one side of the first active layer, a side wall spacer on a side wall of the drain electrode, and a first source electrode provided on the other side of the first active layer and on a side wall of the side wall spacer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a thin film transistor and a display device including the same. [Background technology]

[0002] Generally, thin film transistors (TFTs) that make up display pixels and circuits are composed of three terminals: gate, source, and drain, and can be driven by turning on and / or off an electron channel between the source and drain electrodes depending on the gate electric field of a semiconductor active layer interposed between the gate insulating film. Due to limitations in the exposure process for large-area displays set up for mass production, the current driving capability of such TFTs is significantly reduced compared to CMOS Si backplane FETs, with channel lengths at the level of several microns. Furthermore, the area of ​​the TFT is large, roughly equivalent to the channel length, which has been a constraint on the realization of ultra-high resolution displays for meta-buses, which have recently emerged. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor capable of reducing or minimizing a channel length and a display device including the same. [Means for solving the problem]

[0004] The present invention discloses a thin film transistor including a first gate electrode on a substrate, a gate insulating film on the first gate electrode, a first active layer on the gate insulating film, a drain electrode on one side of the first active layer, sidewall spacers on sidewalls of the drain electrode, and a first source electrode provided on the other side of the first active layer and on sidewalls of the sidewall spacers.

[0005] According to one example, the first active layer may have a first channel length corresponding to a bottom thickness of the sidewall spacer.

[0006] According to an example, the semiconductor device may further include a blocking insulating layer on the drain electrode.

[0007] According to one example, the first source electrode may be provided on the blocking insulating layer.

[0008] According to an example, the semiconductor device may further include an upper electrode between the blocking insulating layer and the first source electrode.

[0009] According to an example, the semiconductor device may further include a second active layer between the drain electrode and the blocking insulating layer.

[0010] According to an example, the semiconductor device may further include a second source electrode between the second active layer and the blocking insulating layer.

[0011] According to one example, the semiconductor device may further include a second gate electrode on the sidewall spacer layer.

[0012] According to one example, the second gate electrode may be connected to the first source electrode.

[0013] According to one example, the second active layer may have a second channel length corresponding to its thickness.

[0014] A thin film transistor according to an embodiment of the present invention includes a first gate electrode on a substrate, a gate insulating film on the first gate electrode, a first active layer on the gate insulating film, a drain electrode on one side of the first active layer, a second active layer on the drain electrode, a first source electrode on the second active layer, sidewall spacers on sidewalls of the drain electrode, the second active layer, and the first source electrode, a second source electrode provided on the other side of the first active layer, and a second gate electrode on a sidewall of the sidewall spacer.

[0015] According to one example, the second gate electrode may be connected to the second source electrode.

[0016] According to an example, the semiconductor device may further include a blocking insulating layer provided on the first source electrode.

[0017] According to one example, the second gate electrode may extend to the blocking insulating layer.

[0018] According to one example, the first active layer may have a first channel length corresponding to a bottom thickness of the sidewall spacer, and the second active layer may have a second channel length corresponding to the thickness thereof.

[0019] A display device according to an embodiment of the present invention includes scan lines extending in a first direction, data lines intersecting the first direction in a second direction, and thin film transistors provided at intersections of the data lines and the scan lines, wherein the thin film transistors include a first gate electrode on a lower substrate, a gate insulating film on the first gate electrode, a first active layer on the gate insulating film, a drain electrode on one side of the first active layer, sidewall spacers on sidewalls of the drain electrode, and first source electrodes provided on the other side of the first active layer and on sidewalls of the sidewall spacers.

[0020] According to one example, the first active layer may overlap the data line.

[0021] According to one example, the first gate electrode may extend in the first direction, and the first source electrode may extend in the second direction.

[0022] According to an example, the first active layer may have the same width as the first gate electrode and the scan line.

[0023] According to one example, the scan lines are wider or thicker than the data lines. [Effects of the Invention]

[0024] As described above, the thin film transistor of the present invention can reduce or minimize the channel length to correspond to the bottom thickness of the sidewall spacer by using the source electrode and the drain electrode on both sides of the gate electrode and the sidewall spacer on the active layer. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a plan view showing an example of a display device according to the concept of the present invention; [Figure 2] FIG. 2 is a cross-sectional view taken along line II' in FIG. [Figure 3] 1 is a plan view showing an example of a display device according to the concept of the present invention; [Figure 4] FIG. 4 is a cross-sectional view taken along line II-II' in FIG. [Figure 5] FIG. 2 is a plan view illustrating an example of the thin film transistor of FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line III-III' in FIG. 5. [Figure 7] FIG. 2 is a plan view illustrating an example of the thin film transistor of FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line IV-IV′ in FIG. 7. [Figure 9] FIG. 2 is a plan view illustrating an example of the thin film transistor of FIG. [Figure 10] 10 is a cross-sectional view taken along line VV' in FIG. 9. FIG. [Figure 11] FIG. 3 is a cross-sectional view showing an example of the thin film transistor of FIG. 2. [Figure 12] FIG. 3 is a cross-sectional view showing an example of the thin film transistor of FIG. 2. DETAILED DESCRIPTION OF THE INVENTION

[0026] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The advantages and / or features of the present invention, as well as methods for achieving the same, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the invention is not limited to the embodiments described herein, and may be embodied in different forms. Rather, the embodiments described herein are provided so that the disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art. The invention is defined only by the scope of the claims. The same reference numerals refer to the same elements throughout the specification.

[0027] The terms used in this specification are intended to describe the embodiments and are not intended to limit the present invention. In this specification, the singular form includes the plural form unless otherwise specified in the phrase. When used in this specification, the terms 'comprises' and / or 'comprising' do not exclude the presence or addition of one or more other components, operations, and / or elements to a referenced component, operation, and / or element. Furthermore, since this specification is based on preferred embodiments, reference numerals presented according to the order of description are not necessarily limited to that order.

[0028] Furthermore, the embodiments described herein will be described with reference to cross-sectional views and / or plan views that are ideal exemplary views of the present invention. In the drawings, thicknesses of films and regions are exaggerated for efficient explanation of the technical content. Therefore, the shapes of the exemplary views may vary depending on manufacturing techniques and / or tolerances. Therefore, the embodiments of the present invention are not limited to the specific shapes shown in the drawings, but also include changes in shapes that occur depending on the manufacturing process.

[0029] 1 shows an example of a display device 100 according to the concepts of the present invention. FIG. 2 shows a cross section taken along line II' of FIG.

[0030] 1 and 2, the display device 100 of the present invention may include a liquid crystal display device. Alternatively, the display device 100 of the present invention may include an organic light emitting display device, but the present invention is not limited thereto. According to one example, the display device 100 may include a lower substrate 10, scan lines 12, data lines 14, pixel electrodes 80, thin film transistors 20, a protective film 30, a liquid crystal layer 40, a common electrode 50, a color filter layer 60, and an upper substrate 70.

[0031] The lower substrate 10 may be a transparent substrate. For example, the lower substrate 10 may include a glass substrate or a plastic substrate.

[0032] The scan lines 12 may be provided on the lower substrate 10. The scan lines 12 may extend in a first direction D1. For example, the scan lines 12 may include a metal such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), or tantalum (Ta). Alternatively, the scan lines 12 may include indium tin oxide (ITO), although the present invention is not limited thereto.

[0033] The data lines 14 may be provided on the scan lines 12. The data lines 14 may extend in a second direction D2. The second direction D2 may intersect with the first direction D1. The data lines 14 may have the same material as the scan lines 12. For example, the data lines 14 may include a metal such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), or tantalum (Ta). Alternatively, the data lines 14 may include indium tin oxide (ITO), although the present invention is not limited thereto.

[0034] The thin film transistor 20 may be provided at the intersection of the scan line 12 and the data line 14 in a plan view. The thin film transistor 20 may overlap the data line 14. Although not shown, the thin film transistor 20 may be provided between the data line 14 and the scan line 12 in a vertical view. The thin film transistor 20 may drive the pixel electrode 80. That is, the thin film transistor 20 may control the data voltage or data signal provided to the pixel electrode 80. The thin film transistor 20 may include a bottom gate thin film transistor (TFT) or a back channel etched thin film transistor (BCE TFT).

[0035] Referring to FIG. 2, the thin film transistor 20 may include a first gate electrode 21, a gate insulating layer 22, a first active layer 23, a drain electrode 24, a blocking insulating layer 25, a sidewall spacer 26, an upper electrode 27, and a first source electrode 28.

[0036] The first gate electrode 21 may be provided on the substrate 10. The first gate electrode 21 may be the scan line 12 of FIG. 1 or may be connected to the scan line 12. That is, the first gate electrode 21 may extend in a first direction D1. The first gate electrode 21 may include a metal such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), or tantalum (Ta). Alternatively, the first gate electrode 21 may include indium tin oxide (ITO), although the present invention is not limited thereto.

[0037] A gate insulating film 22 may be provided on the first gate electrode 21. For example, the gate insulating film 22 may include silicon oxide. Alternatively, the gate insulating film 22 may include silicon nitride, although the present invention is not limited thereto.

[0038] The first active layer 23 may be provided on the gate insulating layer 22. The first active layer 23 may overlap the first gate electrode 21 and the data line 14. For example, the first active layer 23 may include polysilicon or amorphous silicon. Alternatively, the first active layer 23 may include crystalline silicon, although the present invention is not limited thereto.

[0039] The drain electrode 24 may be provided on one side of the first active layer 23. Although not shown, the drain electrode 24 may be connected to the pixel electrode 80. For example, the drain electrode 24 may include indium tin oxide (ITO). Alternatively, the drain electrode 24 may include a metal such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), or tantalum (Ta), although the present invention is not limited thereto.

[0040] A blocking insulating layer 25 may be provided on the drain electrode 24. The blocking insulating layer 25 may include a silicon oxide or silicon nitride dielectric.

[0041] The upper electrode 27 may be provided on the blocking insulating film 25. The upper electrode 27 may include a metal such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), or tantalum (Ta), but the present invention is not limited thereto.

[0042] The sidewall spacer 26 may be provided on one sidewall of the drain electrode 24, the blocking insulating film 25, and the upper electrode 27. The sidewall spacer 26 may include silicon oxide or silicon nitride formed by a PECVD (plasma enhanced chemical vapor deposition) method. The sidewall spacer 26 may be formed by a self-aligned method.

[0043] The first source electrode 28 may be provided on the other side of the first active layer 23. The first source electrode 28 may be provided on the sidewall spacer 26 and the top electrode 27. The first source electrode 28 may be the data line 14 of FIG. 1. That is, the first source electrode 28 may extend in the second direction D2. The first source electrode 28 may be provided on the blocking insulating film 25 and the top electrode 27. Alternatively, the first source electrode 28 may be connected to the data line 14. For example, the first source electrode 28 may include a metal such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), or tantalum (Ta). Alternatively, the first source electrode 28 may include indium tin oxide (ITO), although the present invention is not limited thereto.

[0044] When a gate voltage or a scan signal is applied to the first gate electrode 21, a first channel may be generated in the first active layer 23 between the first source electrode 28 and the drain electrode 24. The first active layer 23 has a first channel length L CH1 For example, the first channel length L CH1 The first channel may have a width of about 15 μm. According to one example, the first channel length L CH1 may correspond to the bottom thickness of the sidewall spacer 26.

[0045] Therefore, the thin film transistor 20 of the present invention has a first channel length L using the first gate electrode 21 and the first source electrode 28 and the drain electrode 24 on both sides of the sidewall spacer 26 on the first active layer 23. CH1 can be reduced or minimized to correspond to the bottom thickness of the sidewall spacer 26.

[0046] When a first channel is formed in the first active layer 23, a data voltage or a data signal can be provided through the first channel from the first source electrode 28 to the drain electrode 24. The data voltage or the data signal can induce an electric field between the pixel electrode 80 and the common electrode 50, thereby changing the optical properties or polarization direction of the liquid crystal layer 40.

[0047] The protective layer 30 may be provided on the first source electrode 28. The protective layer 30 may have a flat upper surface. The protective layer 30 may include silicon oxide.

[0048] The pixel electrode 80 may be provided in a pixel defined by the scan line 12 and the data line 14. Although not shown, the pixel electrode 80 may be provided on the passivation layer 30. The pixel electrode 80 may be connected to one side of the drain electrode 24 of the thin film transistor 20 through a contact electrode that penetrates the passivation layer 30.

[0049] The liquid crystal layer 40 may be provided on the protective film 30 and the pixel electrode 80. The liquid crystal layer 40 may change its optical properties or polarization direction in response to an electric field induced between the pixel electrode 80 and the common electrode 50. For example, the liquid crystal layer 40 may include smectic liquid crystal, nematic liquid crystal, or cholesteric liquid crystal.

[0050] The common electrode 50 may be provided on the liquid crystal layer 40. The common electrode 50 may include ITO (Indium Tin Oxide). The common electrode 50 may be grounded.

[0051] A color filter layer 60 may be provided on the common electrode 50. The color filter layer 60 may include polymers or pigments having red, green, and blue colors.

[0052] The upper substrate 70 may be provided on the color filter layer 60. The upper substrate 70 may be transparent. The upper substrate 70 may include a glass substrate or a plastic substrate.

[0053] 3 shows an example of a display device 100 according to the concepts of the present invention. FIG. 4 shows a cross section taken along line II-II' of FIG.

[0054] 3 and 4, sidewall spacers 26 of the thin film transistor 20 of the present invention may be provided on both sidewalls of the drain electrode 24, the blocking insulating film 25, and the top electrode 27, respectively. That is, each thin film transistor 20 may have a plurality of first channels. The width of the first active layer 23 of the thin film transistor 20 may be the same as the width of the scan line 12 and the first gate electrode 21. The scan line 12 may be wider or thicker than the data line 14.

[0055] The lower substrate 10, the first gate electrode 21, the gate insulating film 22, the first active layer 23, the drain electrode 24, the blocking insulating film 25, the upper electrode 27, the first source electrode 28, the passivation film 30, the liquid crystal layer 40, the common electrode 50, the color filter layer 60, the upper substrate 70, and the pixel electrode 80 may be configured in the same manner as in FIGS. 1 and 2.

[0056] Fig. 5 shows an example of the thin film transistor 20 of Fig. 1. Fig. 6 shows a cross section taken along line III-III' of Fig. 5.

[0057] 5 and 6, the first gate electrode 21, the drain electrode 24, and the first source electrode 28 of the thin film transistor 20 may be connected to a gate pad 21a, a drain pad 24a, and a source pad 28a, respectively.

[0058] The lower substrate 10, the first gate electrode 21, the gate insulating film 22, the first active layer 23, the drain electrode 24, the blocking insulating film 25, the upper electrode 27, and the first source electrode 28 may be configured in the same manner as in FIG.

[0059] Fig. 7 shows an example of the thin film transistor 20 of Fig. 1. Fig. 8 shows a cross section taken along line IV-IV' of Fig. 7.

[0060] 7 and 8, the drain electrodes 24 of the thin film transistors 20 may be connected in parallel by a connection line 24b. The first source electrodes 28 may be contacted to the first active layers 23 between the sidewall spacers 26.

[0061] The lower substrate 10, the first gate electrode 21, the gate insulating film 22, the first active layer 23, the drain electrode 24, the blocking insulating film 25, the upper electrode 27, and the first source electrode 28 may be configured in the same manner as in FIG.

[0062] Figure 9 shows an example of the thin film transistor 20 of Figure 1. Figure 10 shows a cross section taken along line VV' of Figure 9. Figure 10 may be the same as Figure 8.

[0063] 9 and 10, the thin film transistors 20 may be connected in series, and at least one of the drain electrodes 24 may be connected to or function as a source electrode or gate electrode of another thin film transistor, but the present invention is not limited thereto.

[0064] The lower substrate 10, the first gate electrode 21, the gate insulating film 22, the first active layer 23, the drain electrode 24, the blocking insulating film 25, the upper electrode 27, and the first source electrode 28 may be configured in the same manner as in FIG.

[0065] FIG. 11 shows an example of the thin film transistor 20 of FIG.

[0066] 11, the first source electrode 28 of the thin film transistor 20 may be in contact with the blocking insulating layer 25 without the top electrode 27 of FIG. 2. The top surface of the blocking insulating layer 25 may be coplanar with the top surface of the sidewall spacer 26.

[0067] The lower substrate 10, the first gate electrode 21, the gate insulating film 22, the first active layer 23, the drain electrode 24, the blocking insulating film 25, and the first source electrode 28 may be configured in the same manner as in FIG.

[0068] FIG. 12 shows an example of the thin film transistor 20 of FIG.

[0069] Referring to FIG. 12, the thin film transistor 20 may further include a second active layer 29, a second source electrode 32, and a second gate electrode .

[0070] The second active layer 29 may be provided between the drain electrode 24 and the blocking insulating layer 25. The second active layer 29 may be thinner than the sidewall spacer 26. For example, the second active layer 29 may include amorphous silicon, polysilicon, or crystalline silicon, but the present invention is not limited thereto.

[0071] The second source electrode 32 may be provided between the second active layer 29 and the blocking insulating film 25. The blocking insulating film 25 may be provided between the second source electrode 32 and the second gate electrode 34. The blocking insulating film 25 may also be provided between the first source electrode 28 and the second source electrode 32. That is, the second source electrode 32 may be insulated from the first source electrode 28 and the second gate electrode 34 by the blocking insulating film 25.

[0072] The second gate electrode 34 may be provided on a sidewall of the sidewall spacer 26. The second gate electrode 34 may be connected to the first source electrode 28. The second gate electrode 34 may include the same material as the first source electrode 28. When a data voltage or a data signal is provided to the first source electrode 28 and the second gate electrode 34, a second channel may be induced in the second active layer 29. The second active layer 29 has a second channel length L CH2 The second channel length L CH2 may correspond to the thickness of the second active layer 29.

[0073] As a result, the thin film transistor 20 of the present invention has a first channel length L using the first gate electrode 21, the drain electrode 24, the first source electrode 28, the second source electrode 32, and the second gate electrode 34. CH1 and the second channel length L CH2 can be reduced or minimized.

[0074] The lower substrate 10, the first gate electrode 21, the gate insulating film 22, the first active layer 23, and the drain electrode 24 may be configured in the same manner as in FIG.

[0075] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0076] 10 Substrate 12 scan lines 14 Data Lines 20 Thin-film transistor 21 First gate electrode 22 Gate insulating film 23 1st active layer 24 Drain electrode 26 Sidewall spacer 28 First source electrode 25 Blocking insulating film 27 Upper electrode 29 2nd active layer 32 second source electrode 34 Second gate electrode

Claims

1. a first gate electrode overlying a substrate; a gate insulating film on the first gate electrode; a first active layer on the gate insulating film; a drain electrode on one side of the first active layer; a sidewall spacer on a sidewall of the drain electrode; a first source electrode provided on the other side of the first active layer and on a sidewall of the sidewall spacer; a blocking insulating film on the drain electrode; a blocking insulating layer and an upper electrode between the blocking insulating layer and the first source electrode.

2. The thin film transistor of claim 1 , wherein the first active layer has a first channel length corresponding to a bottom thickness of the sidewall spacer.

3. A first gate electrode on a substrate; a gate insulating film on the first gate electrode; a first active layer on the gate insulating film; a drain electrode on one side of the first active layer; a sidewall spacer on a sidewall of the drain electrode; a first source electrode provided on the other side of the first active layer and on a sidewall of the sidewall spacer; a blocking insulating film on the drain electrode; a second active layer between the drain electrode and the blocking insulating layer;

4. The thin film transistor of claim 3 , further comprising a second source electrode between the second active layer and the blocking insulating layer.

5. The thin film transistor of claim 4 , further comprising a second gate electrode on the sidewall spacer layer.

6. The thin film transistor of claim 5 , wherein the second gate electrode is connected to the first source electrode.

7. The thin film transistor of claim 3 , wherein the second active layer has a second channel length corresponding to the thickness of the second active layer.

8. a first gate electrode overlying a substrate; a gate insulating film on the first gate electrode; a first active layer on the gate insulating film; a drain electrode on one side of the first active layer; a second active layer on the drain electrode; a first source electrode on the second active layer; sidewall spacers on sidewalls of the drain electrode, the second active layer, and the first source electrode; a second source electrode provided on the other side of the first active layer; a second gate electrode on a sidewall of the sidewall spacer.

9. The thin film transistor of claim 8 , wherein the second gate electrode is connected to the second source electrode.

10. The thin film transistor of claim 8 , further comprising a blocking insulating film provided on the first source electrode.

11. The thin film transistor of claim 10 , wherein the second gate electrode extends to the blocking insulating layer.

12. the first active layer has a first channel length corresponding to a bottom thickness of the sidewall spacer; The thin film transistor of claim 8 , wherein the second active layer has a second channel length corresponding to the thickness of the second active layer.

13. a scan line extending in a first direction; data lines intersecting in a second direction intersecting the first direction; a thin film transistor provided at an intersection of the data line and the scan line; The thin film transistor is a first gate electrode on the lower substrate; a gate insulating film on the first gate electrode; a first active layer on the gate insulating film; a drain electrode on one side of the first active layer; a sidewall spacer on a sidewall of the drain electrode; a first source electrode provided on the other side of the first active layer and on a sidewall of the sidewall spacer; a blocking insulating film on the drain electrode; an upper electrode between the blocking insulating film and the first source electrode.

14. A scan line extending in a first direction; data lines intersecting in a second direction intersecting the first direction; a thin film transistor provided at an intersection of the data line and the scan line; The thin film transistor is a first gate electrode on the lower substrate; a gate insulating film on the first gate electrode; a first active layer on the gate insulating film; a drain electrode on one side of the first active layer; a sidewall spacer on a sidewall of the drain electrode; a first source electrode provided on the other side of the first active layer and on a sidewall of the sidewall spacer; a blocking insulating film on the drain electrode; a second active layer between the drain electrode and the blocking insulating layer.

15. The display device according to claim 13 or 14, wherein the first active layer overlaps the data line.

16. the first gate electrode extends in the first direction; The display device of claim 13 or 14, wherein the first source electrode extends in the second direction.

17. The display device of claim 13 or 14, wherein the first active layer has the same width as the first gate electrode and the scan line.

18. 15. The display device according to claim 13, wherein the scan lines are wider or thicker than the data lines.

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