Semiconductor device, semiconductor device manufacturing method, inverter circuit, drive device, vehicle, and elevator

Abstract

To provide a semiconductor device capable of reducing an on-resistance.SOLUTION: A semiconductor device of an embodiment includes: a silicon carbide layer including a first face parallel to a first direction and a second direction perpendicular to the first direction and a second face parallel to the first face; a first trench and a second trench extending in the first direction on the first face; a first gate electrode in the first trench; a second gate electrode in the second trench; an n-type first silicon carbide region; a p-type second silicon carbide region between the first silicon carbide region and the first face; an n-type third silicon carbide region between the second silicon carbide region and the first face; a p-type fourth silicon carbide region at a bottom of the first trench; and a fifth silicon carbide region at a bottom of the second trench. A width of the fourth silicon carbide region in the second direction is less than a width of the first trench in the second direction, and a length of the fourth silicon carbide region in a third direction from the first face toward the second face is more than the width of the fourth silicon carbide region in the second direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device, a method for manufacturing a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap approximately three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. Utilizing these physical properties will enable the realization of semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) using silicon carbide are required to have low on-resistance. To reduce the on-resistance of MOSFETs, trench-gate vertical MOSFETs are used, in which the gate electrode is provided inside a trench.

[0004] In vertical MOSFETs, a structure that achieves both high breakdown voltage and low on-resistance is the superjunction structure (hereinafter also referred to as the "SJ structure"), in which p-type and n-type regions are arranged alternately in the horizontal direction. The SJ structure achieves high breakdown voltage in MOSFETs by alleviating the electric field strength in the semiconductor through depletion layers that extend horizontally in the p-type and n-type regions. At the same time, low on-resistance in MOSFETs can be achieved by increasing the concentration of impurity regions.

[0005] By combining a trench gate vertical MOSFET with an SJ structure and further miniaturizing it, it is possible to further reduce the on-resistance. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 2021-27138 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a semiconductor device capable of reducing the on-resistance. [Means for solving the problem]

[0008] A semiconductor device according to an embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface, a first trench present in the silicon carbide layer and extending in the first direction in the first surface, a first gate electrode located in the first trench, a first gate insulating layer located between the first gate electrode and the silicon carbide layer, a second trench present in the silicon carbide layer and extending in the first direction in the first surface and positioned in the second direction relative to the first trench, a second gate electrode located in the second trench, a second gate insulating layer located between the second gate electrode and the silicon carbide layer, an n-type first silicon carbide region located in the silicon carbide layer, and a second gate insulating layer located in the silicon carbide layer between the first silicon carbide region and the first surface, a p-type second silicon carbide region located between the first surface and the first trench; an n-type third silicon carbide region located in the silicon carbide layer and between the second silicon carbide region and the first trench; a p-type fourth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the first trench; a p-type fifth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the second trench; a first electrode located on the first surface side and electrically connected to the second silicon carbide region and the third silicon carbide region; and a second electrode located on the second surface side of the silicon carbide layer, wherein a width of the fourth silicon carbide region in the second direction is smaller than a width of the first trench in the second direction, and a length of the fourth silicon carbide region in a third direction from the first surface toward the second surface is longer than a width of the fourth silicon carbide region in the second direction. the fourth silicon carbide region includes a first region and a second region located between the first region and the first trench, in contact with the first trench, and having a p-type impurity concentration higher than a p-type impurity concentration of the first region, and the p-type impurity concentration of the first region is 1×10 17 cm -3 The p-type impurity concentration of the second region is higher than 1×10 20 cm -3 Higher . [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 1 is a diagram showing the crystal structure of a silicon carbide semiconductor. [Figure 4] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 3A to 3C are explanatory views of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] FIG. 10 is a schematic cross-sectional view of a semiconductor device of a comparative example. [Figure 13] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 14] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 15] FIG. 10 is a schematic plan view of a semiconductor device according to a second embodiment. [Figure 16] FIG. 10 is a schematic diagram of a drive device according to a third embodiment. [Figure 17] FIG. 10 is a schematic diagram of a vehicle according to a fourth embodiment. [Figure 18] FIG. 10 is a schematic diagram of a vehicle according to a fifth embodiment. [Figure 19] FIG. 10 is a schematic diagram of an elevator according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0011] In the following description, n ++ , n + , n, n - and p ++ , p, p - When the notation is used, these notations represent the relative level of impurity concentration in each conductivity type. ++ is n + The n-type impurity concentration is relatively higher than that of + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. ++ HAp + The p-type impurity concentration is relatively higher than that of p + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. ++ type, n + type, n - The type is simply n-type, p ++ type, p + type, p - The type is sometimes simply referred to as p-type.

[0012] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM). The distances, such as the width and depth, of the impurity region can be determined by, for example, SIMS. The distances, such as the width and depth, of the impurity region can also be determined from, for example, an SCM image.

[0013] The trench width, trench spacing, trench depth, insulating layer thickness, etc. can be measured on an image obtained by, for example, SIMS or a Transmission Electron Microscope (TEM).

[0014] (First embodiment) The semiconductor device of the first embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface, a first trench present in the silicon carbide layer and extending in the first direction in the first surface, a first gate electrode located in the first trench, a first gate insulating layer located between the first gate electrode and the silicon carbide layer, a second trench present in the silicon carbide layer and extending in the first direction in the first surface and positioned in a second direction relative to the first trench, a second gate electrode located in the second trench, a second gate insulating layer located between the second gate electrode and the silicon carbide layer, an n-type first silicon carbide region located in the silicon carbide layer, and a gate insulating layer located in the silicon carbide layer between the first silicon carbide region and the first surface, and a gate insulating layer between the first trench and the second trench. a p-type second silicon carbide region located between the first silicon carbide region and the first trench; an n-type third silicon carbide region located in the silicon carbide layer and between the second silicon carbide region and the first surface; a p-type fourth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the first trench; a p-type fifth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the second trench; a first electrode located on the first surface side of the silicon carbide layer and electrically connected to the second silicon carbide region and the third silicon carbide region, and a second electrode located on the second surface side of the silicon carbide layer, wherein the width of the fourth silicon carbide region in the second direction is smaller than the width of the first trench in the second direction, and the length of the fourth silicon carbide region in the third direction from the first surface to the second surface is longer than the width of the fourth silicon carbide region in the second direction.

[0015] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment is a trench-gate vertical MOSFET 100 made of silicon carbide. The MOSFET 100 is an n-channel MOSFET that uses electrons as carriers. The MOSFET 100 has an SJ structure.

[0016] 2 is a schematic plan view of the semiconductor device of the first embodiment. FIG. 2 is a plan view of the first plane (F1 in FIG. 1) of FIG. 1. The first direction and the second direction are parallel to the first plane F1. The second direction is perpendicular to the first direction. FIG. 1 is a cross section taken along line AA' of FIG. 2.

[0017] The MOSFET 100 includes a silicon carbide layer 10, a first trench 11a, a second trench 11b, a third trench 11c, a first gate electrode 12a, a second gate electrode 12b, a third gate electrode 12c, a first gate insulating layer 14a, a second gate insulating layer 14b, a third gate insulating layer 14c, a source electrode 16 (first electrode), a drain electrode 18 (second electrode), and an interlayer insulating layer 20.

[0018] Hereinafter, the first trench 11a, the second trench 11b, and the third trench 11c may be collectively referred to as trench 11. Hereinafter, the first gate electrode 12a, the second gate electrode 12b, and the third gate electrode 12c may be collectively referred to as gate electrode 12. Hereinafter, the first gate insulating layer 14a, the second gate insulating layer 14b, and the third gate insulating layer 14c may be collectively referred to as gate insulating layer 14.

[0019] In the silicon carbide layer 10, n + a drain region 22 of n-type, a drift region 24 (first silicon carbide region), a body region 26 of p-type (second silicon carbide region), + a source region 28 (third silicon carbide region), p + A p-type contact region 30, a p-type first pillar region 32a (fourth silicon carbide region), a p-type second pillar region 32b (fifth silicon carbide region), and a p-type third pillar region 32c are provided.

[0020] Each of the first pillar region 32a, the second pillar region 32b, and the third pillar region 32c includes a low concentration region 32x (first region) and a high concentration region 32y (second region).

[0021] Hereinafter, the first pillar region 32a, the second pillar region 32b, and the third pillar region 32c may be collectively referred to as the pillar region 32.

[0022] The silicon carbide layer 10 is made of single-crystal SiC, for example, 4H—SiC.

[0023] Silicon carbide layer 10 has a first surface ("F1" in FIG. 1) and a second surface ("F2" in FIG. 1). First surface F1 and second surface F2 face each other. Hereinafter, first surface F1 will also be referred to as the front surface, and second surface F2 will also be referred to as the back surface. Note that, hereinafter, "depth" refers to the depth in the direction toward second surface F2, with first surface F1 as the reference.

[0024] 1 and 2, the first direction and the second direction are parallel to the first plane F1 and the second plane F2, and the third direction is perpendicular to the first plane F1 and the second plane F2.

[0025] Figure 3 shows the crystal structure of a silicon carbide semiconductor. A typical crystal structure of a silicon carbide semiconductor is a hexagonal system such as 4H-SiC. One of the faces (top faces of the hexagonal prism) whose normal is the c-axis along the axial direction of the hexagonal prism is the (0001) face. A face equivalent to the (0001) face is called the silicon face and is expressed as the {0001} face. Silicon (Si) is arranged on the silicon face.

[0026] The other surface (top surface of the hexagonal prism) normal to the c-axis along the axial direction of the hexagonal prism is the (000-1) surface. The surface equivalent to the (000-1) surface is called the carbon surface and is written as the {000-1} surface. Carbon (C) is arranged on the carbon surface.

[0027] On the other hand, the side surfaces of the hexagonal prism (cylindrical surfaces) are m-planes, i.e., {1-100} planes, which are equivalent to the (1-100) plane. Furthermore, the planes passing through pairs of non-adjacent ridges are a-planes, i.e., {11-20} planes, which are equivalent to the (11-20) plane. Both silicon (Si) and carbon (C) are arranged on the m-plane and a-plane.

[0028] The first plane F1 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (0001) plane. That is, the normal is a plane inclined at an angle of 0 to 8 degrees with respect to the c-axis in the

[0001] direction. In other words, the off-angle with respect to the (0001) plane is 0 to 8 degrees. The second plane F2 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (000-1) plane.

[0029] The (0001) plane is called the silicon plane, and the (000-1) plane is called the carbon plane.

[0030] The tilt direction of the first plane F1 and the second plane F2 is, for example, the <11-20> direction. The <11-20> direction is the a-axis direction. In FIG. 2, for example, the first direction shown in FIG. 2 is in the same plane as the a-axis direction.

[0031] The trench 11 exists in the silicon carbide layer 10. The trench 11 is a recess provided in the silicon carbide layer 10. The trench 11 extends in a first direction as shown in FIG.

[0032] The width of trench 11 in the second direction (Wt in FIGS. 1 and 2) is, for example, equal to or less than the distance between two adjacent trenches 11 (St in FIGS. 1 and 2).

[0033] The width of trench 11 in the second direction (Wt in FIGS. 1 and 2) is, for example, not less than 0.2 μm and not more than 1.0 μm.

[0034] The distance St between two adjacent trenches 11 is 1.0 μm or less. The distance St between two adjacent trenches 11 is, for example, 0.2 μm or more and 1.0 μm or less. For example, the distance St between the first trench 11a and the second trench 11b is 0.2 μm or more and 1.0 μm or less.

[0035] The trenches 11 are repeatedly arranged in the second direction. The repeat pitch of the trenches 11 in the second direction is, for example, not less than 0.4 μm and not more than 2.0 μm.

[0036] The depth of the trench 11 is, for example, not less than 0.5 μm and not more than 2.0 μm.

[0037] The inclination angle of the side surface of trench 11 with respect to the m-plane or the a-plane is, for example, not less than 0 degrees and not more than 5 degrees.

[0038] The gate electrode 12 is provided in the trench 11. The first gate electrode 12a is provided in the first trench 11a. The second gate electrode 12b is provided in the second trench 11b. The third gate electrode 12c is provided in the third trench 11c.

[0039] The gate electrode 12 is provided between the source electrode 16 and the drain electrode 18. The gate electrode 12 extends in a first direction.

[0040] The gate insulating layer 14 is provided between the gate electrode 12 and the silicon carbide layer 10. The first gate insulating layer 14a is provided between the first gate electrode 12a and the silicon carbide layer 10. The second gate insulating layer 14b is provided between the second gate electrode 12b and the silicon carbide layer 10. The third gate insulating layer 14c is provided between the third gate electrode 12c and the silicon carbide layer 10.

[0041] The gate insulating layer 14 is provided between the gate electrode 12 and each of the source region 28 , the body region 26 , the drain region 22 , and the pillar region 32 .

[0042] The gate electrode 12 is a conductive layer, and is, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0043] The gate insulating layer 14 is, for example, a silicon oxide film. For example, a high-k insulating film (a high-dielectric-constant insulating film such as HfSiON, ZrSiON, or AlON) can be used as the gate insulating layer 14. Alternatively, for example, a stacked film of a silicon oxide film (SiO2) and a high-k insulating film can also be used as the gate insulating layer 14.

[0044] The interlayer insulating layer 20 is provided on the gate electrode 12. The interlayer insulating layer 20 is, for example, a silicon oxide film.

[0045] The source electrode 16 is provided on the front surface side of the silicon carbide layer 10. The source electrode 16 is provided on the front surface of the silicon carbide layer 10.

[0046] The source electrode 16 is electrically connected to the source region 28. The source electrode 16 contacts the source region 28.

[0047] The source electrode 16 is electrically connected to the contact region 30. The source electrode 16 is in contact with the contact region 30.

[0048] The source electrode 16 includes a metal. The metal forming the source electrode 16 has a laminated structure of titanium (Ti) and aluminum (Al), for example.

[0049] The drain electrode 18 is provided on the back surface side of the silicon carbide layer 10. The drain electrode 18 is provided on the back surface of the silicon carbide layer 10. The drain electrode 18 is in contact with the drain region 22.

[0050] The drain electrode 18 is, for example, a metal or a metal-semiconductor compound, and includes a material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0051] n+ The n-type drain region 22 is provided on the back surface side of the silicon carbide layer 10. The drain region 22 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 22 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0052] The n-type drift region 24 is provided on the drain region 22. The drift region 24 is provided between the drain region 22 and the surface of the silicon carbide layer 10.

[0053] The drift region 24 functions as a current path when the MOSFET 100 is in an on-state, and also has the function of maintaining the breakdown voltage of the MOSFET 100 by forming a depletion layer in the drift region 24 when the MOSFET 100 is in an off-state.

[0054] The drift region 24 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 24 is, for example, 1×10 16 cm -3 More than 1×10 19 cm -3 The thickness of the drift region 24 in the third direction is, for example, not less than 5 μm and not more than 150 μm.

[0055] The p-type body region 26 is provided between the drift region 24 and the surface of the silicon carbide layer 10. The body region 26 is provided between two adjacent trenches 11. The body region 26 is provided between the first trench 11a and the second trench 11b.

[0056] The body region 26 is in contact with the gate insulating layer 14. The body region 26 functions as a channel region of the MOSFET 100. For example, when the MOSFET 100 is in an on-state, a channel through which electrons flow is formed in the region of the body region 26 in contact with the gate insulating layer 14.

[0057] The body region 26 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the body region 26 is, for example, 5×10 16 cm -3 5x10 or more 17 cm -3 The depth of the body region 26 is, for example, not less than 0.5 μm and not more than 1.0 μm.

[0058] n + The source region 28 is provided between the body region 26 and the surface of the silicon carbide layer 10. The source region 28 is in contact with the source electrode 16. The source region 28 is in contact with the trench 11. The source region 28 is the gate insulating layer 14.

[0059] The n-type impurity concentration of the source region 28 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The depth of the source region 28 is shallower than the depth of the body region 26. The depth of the source region 28 is, for example, not less than 0.1 μm and not more than 0.6 μm. The distance between the drift region 24 and the source region 28 is, for example, not less than 0.1 μm and not more than 0.6 μm.

[0060] p + The contact region 30 is provided between the body region 26 and the surface of the silicon carbide layer 10. The contact region 30 is in contact with the source electrode 16. The contact region 30 is adjacent to the source region 28. The contact region 30 is in contact with the source region 28.

[0061] The contact region 30 has the function of reducing the electrical resistance between the source electrode 16 and the body region 26 .

[0062] The contact region 30 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the contact region 30 is higher than the p-type impurity concentration of the body region 26. The p-type impurity concentration of the contact region 30 is, for example, 1×10 19 cm -3 More than 1×10 22 cm-3 The following is the result.

[0063] The p-type pillar regions 32 are provided between the drift region 24 and the trench 11. The pillar regions 32 are repeatedly arranged in the second direction. An n-type drift region 24 is provided between two adjacent pillar regions 32.

[0064] The p-type pillar regions 32 and the n-type drift regions 24 are alternately arranged in the second direction. The alternately arranged p-type pillar regions 32 and n-type drift regions 24 form an SJ structure. The depletion layers extending laterally in the p-type pillar regions 32 and the n-type drift regions 24 reduce the electric field strength in the silicon carbide layer 10, thereby achieving a high breakdown voltage for the MOSFET 100. At the same time, the high impurity concentration in the n-type drift regions 24 can achieve a low on-resistance for the MOSFET 100.

[0065] The p-type pillar regions 32 are connected to the source electrode 16 at connection portions (not shown). The potential of the pillar regions 32 is fixed to the source potential. The connection portions are arranged, for example, at predetermined intervals in the first direction.

[0066] The p-type first pillar region 32a is provided between the drift region 24 and the first trench 11a. The first pillar region 32a is provided between the drift region 24 and the bottom surface of the first trench 11a. The first pillar region 32a contacts the bottom surface of the first trench 11a.

[0067] The p-type second pillar region 32b is provided between the drift region 24 and the second trench 11b. The second pillar region 32b is provided between the drift region 24 and the bottom surface of the second trench. The second pillar region 32b contacts the bottom surface of the second trench.

[0068] The p-type third pillar region 32c is provided between the drift region 24 and the third trench 11c. The third pillar region 32c is provided between the drift region 24 and the bottom surface of the third trench 11c. The third pillar region 32c contacts the bottom surface of the third trench 11c.

[0069] The width in the second direction of the pillar region 32 (Wp in FIG. 1) is smaller than the width in the second direction of the trench 11 (Wt in FIG. 1). The width in the second direction of the pillar region 32 Wp is, for example, 90% or less of the width in the second direction Wt of the trench 11.

[0070] For example, the width in the second direction of the first pillar region 32a (Wp in FIG. 1) is smaller than the width in the second direction of the first trench 11a (Wt in FIG. 1). The width in the second direction Wp of the first pillar region 32a is, for example, 50% to 90% of the width in the second direction Wt of the first trench 11a.

[0071] The width in the second direction of the pillar region 32 (Wp in FIG. 1) is smaller than, for example, the width in the second direction of the gate electrode 12 (Wg in FIG. 1). For example, the width in the second direction of the first pillar region 32a (Wp in FIG. 1) is smaller than the width in the second direction of the first gate electrode 12a (Wg in FIG. 1).

[0072] The width of the pillar region 32 in the second direction (Wp in FIG. 1) is smaller than the width of the drift region 24 between two adjacent pillar regions 32 (Wn in FIG. 1). In other words, the width of the pillar region 32 in the second direction (Wp in FIG. 1) is smaller than the interval Wn between two adjacent pillar regions 32.

[0073] For example, the width of the first pillar region 32a in the second direction (Wp in FIG. 1) is smaller than the width of the drift region 24 between the first pillar region 32a and the second pillar region 32b (Wn in FIG. 1). In other words, the width of the first pillar region 32a in the second direction (Wp in FIG. 1) is smaller than the distance Wn between the first pillar region 32a and the second pillar region 32b.

[0074] The length (d2 in FIG. 1) of the pillar region 32 in the third direction from the first face F1 to the second face F2 is longer than the width (Wp in FIG. 1) of the pillar region 32 in the second direction. The length d2 of the pillar region 32 in the third direction from the first face F1 to the second face F2 is, for example, 5 to 200 times the width Wp of the pillar region 32 in the second direction. Preferably, it is 10 to 100 times the width Wp.

[0075] For example, the length (d2 in FIG. 1) of the first pillar region 32a in the third direction from the first face F1 toward the second face F2 is longer than the width (Wp in FIG. 1) of the first pillar region 32a in the second direction. The length d2 of the first pillar region 32a in the third direction from the first face F1 toward the second face F2 is, for example, 5 to 200 times the width Wp of the first pillar region 32a in the second direction. Preferably, it is 10 to 100 times the width Wp.

[0076] The length in the third direction of the pillar region 32 (d2 in FIG. 1) is, for example, longer than the length in the third direction of the trench 11 (d1 in FIG. 1). The length in the third direction of the pillar region 32 (d2) is, for example, 1.5 times or more the length in the third direction of the trench 11 (d1).

[0077] For example, the length in the third direction of the first pillar region 32a (d2 in FIG. 1) is longer than the length in the third direction of the first trench 11a (d1 in FIG. 1). The length in the third direction of the first pillar region 32a (d2) is, for example, 1.5 times or more the length in the third direction of the first trench 11a (d1).

[0078] The pillar region 32 includes a low concentration region 32x and a high concentration region 32y. The high concentration region 32y is provided between the trench 11 and the low concentration region 32x. The high concentration region 32y contacts the bottom surface of the trench 11.

[0079] For example, the first pillar region 32a includes a low-concentration region 32x and a high-concentration region 32y. The high-concentration region 32y is provided between the first trench 11a and the low-concentration region 32x. The high-concentration region 32y contacts the bottom surface of the first trench 11a.

[0080] The length of the high-concentration region 32y in the third direction (d4 in FIG. 1) is shorter than the length of the low-concentration region 32x in the third direction (d3 in FIG. 1).

[0081] The p-type impurity concentration of the high-concentration region 32y is higher than the p-type impurity concentration of the low-concentration region 32x, and is, for example, 10 times or more the p-type impurity concentration of the low-concentration region 32x.

[0082] The pillar region 32 contains, for example, aluminum (Al) as a p-type impurity. The low-concentration region 32x and the high-concentration region 32y contain, for example, aluminum (Al) as a p-type impurity.

[0083] The p-type impurity concentration of the low concentration region 32x is, for example, 1×10 17 cm -3 The p-type impurity concentration of the low concentration region 32x is, for example, 1×10 18 cm -3 5x10 or more 19 cm -3 The following is the result.

[0084] The p-type impurity concentration of the high concentration region 32y is, for example, 1×10 20 cm -3 The p-type impurity concentration of the high concentration region 32y is, for example, 1×10 21 cm -3 5x10 or more 22 cm -3 The following is the result.

[0085] For example, when the width of the pillar region 32 in the second direction is Wp, the p-type impurity concentration of the low concentration region 32x of the pillar region 32 is N1, the width of the drift region 24 between two adjacent pillar regions 32 is Wn, and the n-type impurity concentration of the drift region 24 between two adjacent pillar regions 32 is N2, the relationship of the following equation is satisfied. 0.8≦(Wp×N1) / (Wn×N2)≦1.2

[0086] Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described.

[0087] The method for manufacturing a semiconductor device of the first embodiment includes forming a mask material having an opening on the surface of a silicon carbide layer, forming a trench in the silicon carbide layer using the mask material as a mask, performing a first ion implantation to implant carbon (C) into the bottom of the trench to a region from the bottom that is deeper than the depth of the trench using the mask material as a mask, forming a sidewall material on the side of the trench, and using the sidewall material as a mask, performing a second ion implantation to implant a first p-type impurity into the bottom of the trench to a region from the bottom that is deeper than the depth of the trench, and then performing a heat treatment at 1600°C or higher.

[0088] 4, 5, 6, 7, 8, 9, 10, and 11 are explanatory views of the method for manufacturing the semiconductor device of the first embodiment. Figures 4 to 11 are schematic cross-sectional views showing the semiconductor device in the middle of manufacturing. Figures 4 to 11 show cross sections corresponding to Figure 1.

[0089] First, a silicon carbide layer 10 is prepared, which has a first face F1 (front face) that is a silicon face and a second face F2 (back face) that is a carbon face (FIG. 4). + a drain region 22, an n-type drift region 24, a p-type body region 26, and + type source region 28, and p + A mold contact region 30 is formed.

[0090] The drift region 24 is formed by, for example, epitaxial growth on the drain region 22. The body region 26, the source region 28, and the contact region 30 are formed in the surface of the drift region 24 by, for example, ion implantation.

[0091] Next, a mask material 40 having openings 40a is formed on the surface of the silicon carbide layer 10 (FIG. 5). The mask material 40 is, for example, an insulator. The mask material 40 is, for example, silicon oxide.

[0092] The mask material 40 is formed by, for example, depositing an insulating film and patterning the insulating film by photolithography and etching.

[0093] Next, using the mask material 40 as an etching mask, trenches 11 are formed in the silicon carbide layer 10 (FIG. 6). The trenches 11 are formed by, for example, reactive ion etching (RIE).

[0094] Next, using mask material 40 as an ion implantation mask, a first ion implantation is performed to implant carbon (C) into the bottom surface of trench 11 (FIG. 7). Carbon regions 42 are formed in silicon carbide layer 10 by the first ion implantation.

[0095] In the first ion implantation, carbon (C) is implanted to a region whose depth from the bottom surface of trench 11 is deeper than the depth of trench 11. The depth of carbon region 42 from first face F1 is at least twice the depth of trench 11 from first face F1.

[0096] The first ion implantation is performed multiple times, for example, with different acceleration energies.

[0097] The first ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The first ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0098] Next, a sidewall material 44 is formed on the side surface of the trench 11. The sidewall material 44 is, for example, an insulator. The sidewall material 44 is, for example, silicon oxide.

[0099] The bottom surface of the trench 11 is exposed at the bottom of the sidewall material 44. The sidewall material 44 is formed by, for example, depositing an insulating film and etching using the RIE method.

[0100] Next, using the mask material 40 and the sidewall material 44 as an ion implantation mask, a second ion implantation is performed to implant aluminum (Al) into the bottom surface of the trench 11 (FIG. 8). The second ion implantation forms low-concentration regions 32x of the p-type pillar regions 32. The aluminum (Al) implanted in the second ion implantation is an example of a first impurity.

[0101] In the second ion implantation, aluminum (Al) is implanted to a region whose depth from the bottom surface of trench 11 is deeper than the depth of trench 11. The depth of low concentration region 32x from first face F1 is at least twice the depth of trench 11 from first face F1.

[0102] The second ion implantation is performed multiple times, for example, with different acceleration energies.

[0103] The second ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The second ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0104] The maximum concentration of carbon implanted in the silicon carbide layer 10 by the first ion implantation is higher than, for example, the maximum concentration of aluminum implanted in the silicon carbide layer 10 by the second ion implantation.

[0105] The carbon dose in the first ion implantation is, for example, 10 times or more the aluminum dose in the second ion implantation. To prevent diffusion of impurities into the outer regions of the pillar regions 32, the carbon dose in the first ion implantation implanted into the carbon region 42 is more than 10 times the carbon vacancy in the drift region 24, preferably 100 times or more, and more preferably 1000 times or more. The carbon vacancy in the drift region 24 formed by epitaxial growth is 1×10 14 cm -3 Therefore, the carbon dose of the first ion implantation is estimated to be 1×10 15 cm -3 That's 1 x 10 16 cm -3 More than 1×10 is preferable.17 cm -3 The above is more preferable.

[0106] For example, the distribution of carbon implanted into silicon carbide layer 10 by the first ion implantation in silicon carbide layer 10 before heat treatment covers the distribution of aluminum implanted into silicon carbide layer 10 by the second ion implantation in silicon carbide layer 10 before heat treatment. For example, the distribution of aluminum (Al) implanted in silicon carbide layer 10 by the second ion implantation is included in carbon region 42, as shown in FIG.

[0107] Next, using the mask material 40 and the sidewall material 44 as an ion implantation mask, a third ion implantation is performed to implant aluminum (Al) into the bottom surface of the trench 11 (FIG. 9). The third ion implantation forms a high-concentration region 32y in the p-type pillar region 32. The aluminum (Al) implanted in the third ion implantation is an example of a second impurity.

[0108] In the third ion implantation, aluminum (Al) is implanted to a region whose depth from the bottom surface of trench 11 is shallower than the depth of trench 11. The depth of high concentration region 32y from first face F1 is equal to or less than twice the depth of trench 11 from first face F1.

[0109] The third ion implantation is performed, for example, at a temperature of not less than 1000° C. and not more than 1300° C. The third ion implantation is performed, for example, when the temperature of the silicon carbide layer 10 is not less than 1000° C. and not more than 1300° C.

[0110] The maximum concentration of carbon implanted in the silicon carbide layer 10 in the first ion implantation is higher than, for example, the maximum concentration of aluminum implanted in the silicon carbide layer 10 in the third ion implantation.

[0111] For example, the distribution of carbon implanted into silicon carbide layer 10 by the first ion implantation in silicon carbide layer 10 before the heat treatment covers the distribution of aluminum implanted into silicon carbide layer 10 by the third ion implantation in silicon carbide layer 10 before the heat treatment. For example, the distribution of aluminum (Al) implanted in silicon carbide layer 10 by the third ion implantation is included in carbon region 42, for example, as shown in FIG.

[0112] Next, the mask material 40 and the sidewall material 44 are removed by etching using, for example, a wet etching method.

[0113] Next, a carbon film 46 is formed on the surface of the silicon carbide layer 10 .

[0114] Next, heat treatment is performed (FIG. 10). The heat treatment is performed, for example, at a temperature of 1600° C. or higher and 2000° C. or lower. The heat treatment is performed in a non-oxidizing atmosphere. For example, the heat treatment is performed in an inert gas atmosphere. For example, the heat treatment is performed in an argon gas atmosphere.

[0115] The heat treatment activates the aluminum ions implanted into the silicon carbide layer 10. The heat treatment is an activation annealing of the aluminum. Furthermore, the heat treatment causes interstitial carbon formed by the carbon ion implantation into the silicon carbide layer 10 to fill carbon vacancies in the silicon carbide layer 10.

[0116] Carbon film 46 prevents silicon and carbon from being desorbed into the atmosphere from silicon carbide layer 10 during heat treatment. Carbon film 46 also absorbs excess interstitial carbon in silicon carbide layer 10 during heat treatment.

[0117] Next, the carbon film 46 is removed (FIG. 11). Thereafter, a gate insulating layer 14 and a gate electrode 12 are formed inside the trench 11 using a known process technology. Furthermore, an interlayer insulating layer 20 and a source electrode 16 are formed on the surface of the silicon carbide layer 10. Furthermore, a drain electrode 18 is formed on the back surface of the silicon carbide layer 10.

[0118] By the above manufacturing method, the MOSFET 100 shown in FIGS. 1 and 2 is manufactured.

[0119] Next, the operation and effects of the semiconductor device and the semiconductor device manufacturing method of the first embodiment will be described.

[0120] The MOSFET 100 of the first embodiment can achieve a reduced on-resistance and improved reliability, as will be described in detail below.

[0121] A trench gate structure in which a gate electrode is provided in a trench is applied to the MOSFET 100. By applying the trench gate structure, the channel area per unit area increases, and the on-resistance of the MOSFET 100 is reduced.

[0122] Furthermore, in the MOSFET 100, the p-type pillar regions 32 and the n-type drift regions 24 are alternately arranged in the second direction. The alternately arranged p-type pillar regions 32 and n-type drift regions 24 form an SJ structure. The depletion layers extending laterally in the p-type pillar regions 32 and the n-type drift regions 24 mitigate the electric field strength in the silicon carbide layer 10, thereby achieving a high breakdown voltage for the MOSFET 100. At the same time, the on-resistance of the MOSFET 100 is reduced by increasing the n-type impurity concentration in the n-type drift regions 24.

[0123] The MOSFET 100 also has p-type pillar regions 32 at the bottom of the trench 11. The presence of the p-type pillar regions 32 reduces the electric field applied to the gate insulating layer 14 at the bottom of the trench 11 when the MOSFET 100 is in an off state. This improves the reliability of the gate insulating layer 14.

[0124] Furthermore, in the MOSFET 100, the pillar regions 32 contact the bottom surface of the trench 11 and include a high-concentration region 32y having a high p-type impurity concentration. The inclusion of the high-concentration region 32y having a high p-type impurity concentration further reduces the electric field applied to the gate insulating layer 14 at the bottom of the trench 11. This further improves the reliability of the gate insulating layer 14.

[0125] Furthermore, in the MOSFET 100, the pillar regions 32 include high-concentration regions 32y having a high concentration of p-type impurities, thereby reducing the electrical resistance of the pillar regions 32 in the first direction. For example, the p-type pillar regions 32 are connected to the source electrode 16 at connection portions (not shown). The connection portions are arranged, for example, at predetermined intervals in the first direction. By reducing the electrical resistance of the pillar regions 32 in the first direction, for example, it is possible to increase the intervals between the connection portions and reduce the area of ​​the connection portions per unit area. Therefore, the channel area per unit area of ​​the MOSFET 100 increases, and the on-resistance of the MOSFET 100 can be reduced.

[0126] In the MOSFET 100, the width in the second direction of the pillar region 32 (Wp in FIG. 1) is smaller than the width in the second direction of the trench 11 (Wt in FIG. 1). Because the width in the second direction of the pillar region 32 (Wp in FIG. 1) is smaller than the width in the second direction of the trench 11 (Wt in FIG. 1), it is possible to reduce, for example, the distance between two adjacent trenches 11 (St in FIGS. 1 and 2). This increases the channel area per unit area, and further reduces the on-resistance of the MOSFET 100.

[0127] From the viewpoint of reducing the on-resistance of the MOSFET 100, the width Wp of the pillar region 32 in the second direction is preferably 90% or less, and more preferably 80% or less, of the width Wt of the trench 11 in the second direction.

[0128] From the viewpoint of reducing the on-resistance of the MOSFET 100, the width of the pillar regions 32 in the second direction (Wp in FIG. 1) is preferably smaller than the width of the gate electrode 12 in the second direction (Wg in FIG. 1).

[0129] From the viewpoint of improving the breakdown voltage of the MOSFET 100, the length d2 of the pillar region 32 in the third direction from the first face F1 to the second face F2 is preferably at least five times, and more preferably at least ten times, the width Wp of the pillar region 32 in the second direction.

[0130] From the viewpoint of improving the breakdown voltage of MOSFET 100, the length in the third direction of pillar region 32 (d2 in FIG. 1) is preferably longer than the length in the third direction of trench 11 (d1 in FIG. 1), more preferably 1.5 times or more the length in the third direction d1 of trench 11, and even more preferably 2 times or more the length in the third direction d1 of trench 11.

[0131] From the viewpoint of ensuring that the SJ structure of the MOSFET 100 functions effectively, it is preferable to satisfy the following relationship, where Wp is the width of the pillar region 32 in the second direction, N1 is the p-type impurity concentration of the low-concentration region 32x of the pillar region 32, Wn is the width of the drift region 24 between two adjacent pillar regions 32, and N2 is the n-type impurity concentration of the drift region 24 between two adjacent pillar regions 32. 0.8≦(Wp×N1) / (Wn×N2)≦1.2

[0132] 12 is a schematic cross-sectional view of a semiconductor device of a comparative example, and corresponds to FIG.

[0133] The semiconductor device of the comparative example is a trench-gate vertical MOSFET 901 using silicon carbide. The MOSFET 901 is an n-channel MOSFET that uses electrons as carriers.

[0134] The MOSFET 901 of the comparative example is a MOSFET manufactured by a manufacturing method different from that of the semiconductor device of the first embodiment. The MOSFET 901 of the comparative example is manufactured without performing the first ion implantation included in the semiconductor manufacturing method of the first embodiment. The first ion implantation implants carbon (C) into the bottom surface of the trench.

[0135] In the MOSFET 901 of the comparative example, the width of the pillar regions 32 in the second direction (Wp in FIG. 12) is larger than the width of the trench 11 in the second direction. In the MOSFET 901 of the comparative example, the distance in the second direction between adjacent pillar regions 32 (Wn in FIG. 12) is smaller than that in the MOSFET 100 of the first embodiment. Furthermore, in the MOSFET 901 of the comparative example, the distance in the third direction between the pillar regions 32 and the body region 26 is smaller than that in the MOSFET 100 of the first embodiment.

[0136] When the distance Wn between adjacent pillar regions 32 in the second direction becomes small, the current path through the drift region 24 is narrowed during the on-state of the MOSFET. Furthermore, when the distance in the third direction between the pillar regions 32 and the body region 26 becomes small, the current path through the drift region 24 is narrowed during the on-state of the MOSFET. Therefore, the on-resistance of the MOSFET increases. Furthermore, when Al in the pillar regions 32 diffuses and reaches the body region 26, that is, when the distance in the third direction between the pillar regions 32 and the body region 26 becomes zero, the operation of the MOSFET becomes difficult.

[0137] Furthermore, if the distance in the third direction between the pillar region 32 and the body region 26 becomes small, the threshold voltage of the MOSFET may vary due to variations in the third distance.

[0138] For example, if the diffusion of aluminum in the pillar regions 32 can be suppressed, the distance Wn between adjacent pillar regions 32 in the second direction and the distance Wn between the pillar regions 32 and the body region 26 in the third direction can be increased, thereby reducing the on-resistance of the MOSFET.

[0139] In the method for manufacturing a semiconductor device according to the first embodiment, carbon (C) is introduced by ion implantation into a range wider than the range into which impurities are ion-implanted. This method reduces the carbon vacancy density in the silicon carbide layer 10, and can suppress diffusion of the impurities ion-implanted into the silicon carbide layer 10 due to heat treatment.

[0140] The diffusion of impurities in the silicon carbide layer 10 is promoted by carbon vacancies in the silicon carbide layer 10. In the method for manufacturing a semiconductor device according to the first embodiment, carbon regions 42 are formed by carbon ion implantation, thereby reducing the carbon vacancy density in the silicon carbide layer 10. This suppresses the diffusion of impurities, and also the diffusion of aluminum in the pillar regions 32.

[0141] In particular, in the method for manufacturing a semiconductor device according to the first embodiment, carbon is ion-implanted into the bottom surface of trench 11 by a first ion implantation to form carbon region 42, and then aluminum is ion-implanted into the bottom surface of trench 11 by a second ion implantation using sidewall material 44 as a mask. As a result, the distribution of aluminum is covered by carbon region 42 at least in the second direction.

[0142] In the method for manufacturing a semiconductor device according to the first embodiment, carbon regions 42 are formed in regions where lateral diffusion of aluminum is expected before the heat treatment for diffusing aluminum, thereby effectively suppressing the lateral diffusion of aluminum.

[0143] Therefore, according to the manufacturing method of the semiconductor device of the first embodiment, it is possible to manufacture a MOSFET 100 in which the interval Wn between adjacent pillar regions 32 in the second direction and the distance in the third direction between the pillar regions 32 and the body region 26 are larger than those of the MOSFET 901 of the comparative example. This makes it possible to manufacture a MOSFET 100 that can reduce the on-resistance. Furthermore, in the MOSFET 100, the increase in the distance in the third direction between the pillar regions 32 and the body region 26 suppresses fluctuations in the threshold voltage.

[0144] Furthermore, since the diffusion of aluminum in the pillar region 32 can be suppressed, the concentration of p-type impurities in the pillar region 32 can be increased. This reduces the electrical resistance of the pillar region 32. Therefore, for example, when the MOSFET 100 is turned off, the discharge of holes from the pillar region 32 is promoted. This reduces the switching loss of the MOSFET 100.

[0145] In the MOSFET 100, the pillar region 32 is connected to the source electrode 16 at a position somewhere in the first direction. For example, the pillar region 32 is connected to the source electrode 16 by providing a connection portion. In the MOSFET 100, the p-type impurity concentration of the pillar region 32 can be increased, which reduces the electrical resistance of the pillar region 32 in the first direction and allows for a wider spacing between the connection portions.

[0146] Furthermore, by increasing the p-type impurity concentration in the high-concentration region 32y of the pillar region 32, the electric field applied to the gate insulating layer 14 at the bottom of the trench 11 is further relaxed during the off operation of the MOSFET 100. This further improves the reliability of the gate insulating layer 14 of the MOSFET 100.

[0147] The first ion implantation for implanting carbon is preferably performed at a temperature of 1000° C. or higher. By introducing carbon into silicon carbide layer 10 at a temperature of 1000° C. or higher, interstitial carbon enters carbon vacancies during ion implantation, thereby reducing the carbon vacancy density. Therefore, for example, diffusion of impurities can be suppressed when subsequent ion implantation of impurities is performed at a high temperature.

[0148] Furthermore, by implanting carbon ions at a temperature of 1000° C. or higher, damage caused by the carbon ion implantation can be reduced, thereby improving the characteristics of the MOSFET 100.

[0149] The second ion implantation of aluminum (Al) is preferably performed at a temperature of 1000°C or higher. By implanting impurity ions at a temperature of 1000°C or higher, damage caused by the ion implantation of impurities can be reduced. This can suppress amorphization of the silicon carbide layer 10 due to damage, and maintain high crystallinity, thereby increasing the activation efficiency after activation annealing. Since the higher the ion implantation temperature, the higher the crystallinity of the silicon carbide layer 10 can be maintained, the more preferable ion implantation temperature is 1100°C or higher.

[0150] From the viewpoint of suppressing thermal deterioration of the mask material 40 and the sidewall material 44, the temperature of the first ion implantation and the second ion implantation is preferably 1300°C or less, and more preferably 1200°C.

[0151] It should be noted that prior to the second ion implantation of aluminum, the carbon region 42 is formed by the first ion implantation of carbon, so that diffusion of impurities due to high-temperature ion implantation can be suppressed.

[0152] From the viewpoint of suppressing aluminum diffusion, it is preferable that the maximum concentration of carbon implanted in silicon carbide layer 10 by the first ion implantation be higher than the maximum concentration of aluminum implanted in silicon carbide layer 10 by the second ion implantation.

[0153] From the viewpoint of suppressing aluminum diffusion, the carbon dose in the first ion implantation is preferably 10 times or more, and more preferably 100 times or more, the aluminum dose in the second ion implantation.

[0154] From the viewpoint of suppressing the diffusion of aluminum, it is preferable that the distribution of carbon implanted into silicon carbide layer 10 by the first ion implantation in silicon carbide layer 10 before heat treatment covers the distribution of aluminum implanted into silicon carbide layer 10 by the second ion implantation in silicon carbide layer 10 before heat treatment.

[0155] The temperature of the heat treatment is preferably 1850°C or higher. By performing the heat treatment at 1850°C or higher, the activation rate of the impurities is improved. Note that, because the carbon region 42 is formed by the first ion implantation of carbon prior to the second ion implantation of aluminum, the diffusion of aluminum can be suppressed even when the heat treatment is performed at 1850°C or higher.

[0156] In the third ion implantation, it is preferable to adopt the same conditions as those in the second ion implantation.

[0157] As described above, according to the semiconductor device and the method for manufacturing the semiconductor device of the first embodiment, it is possible to achieve a reduction in on-resistance.

[0158] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that it further includes a plurality of p-type sixth silicon carbide regions located in the silicon carbide layer, in contact with the fourth silicon carbide region, between the first silicon carbide region and the first trench, between the second silicon carbide region and the first trench, and between the third silicon carbide region and the first trench, and repeatedly arranged in the first direction. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0159] 13 and 14 are schematic cross-sectional views of a semiconductor device according to a second embodiment. The semiconductor device according to the second embodiment is a trench-gate vertical MOSFET 200 made of silicon carbide. The MOSFET 200 is an n-channel MOSFET that uses electrons as carriers. The MOSFET 200 has an SJ structure.

[0160] Fig. 15 is a schematic plan view of a semiconductor device of the second embodiment. Fig. 15 is a plan view of the first plane (F1 in Figs. 13 and 14) of Figs. 13 and 14. The first direction and the second direction are parallel to the first plane F1. The second direction is perpendicular to the first direction. Fig. 13 is a BB' cross section of Fig. 15. Fig. 14 is a CC' cross section of Fig. 15.

[0161] The MOSFET 200 includes a silicon carbide layer 10, a first trench 11a, a second trench 11b, a third trench 11c, a first gate electrode 12a, a second gate electrode 12b, a third gate electrode 12c, a first gate insulating layer 14a, a second gate insulating layer 14b, a third gate insulating layer 14c, a source electrode 16 (first electrode), a drain electrode 18 (second electrode), and an interlayer insulating layer 20.

[0162] In the silicon carbide layer 10, n + a drain region 22 of n-type, a drift region 24 (first silicon carbide region), a body region 26 of p-type (second silicon carbide region), +a p-type source region 28 (third silicon carbide region), a p-type first pillar region 32a (fourth silicon carbide region), a p-type second pillar region 32b (fifth silicon carbide region), and a p-type + A mold connection region 34 (sixth silicon carbide region) is provided.

[0163] p + A connecting region 34 of the type contacts the pillar region 32. The connecting region 34 is provided between the drift region 24 and the trench 11. The connecting region 34 is provided between the body region 26 and the trench 11. The connecting region 34 is provided between the source region 28 and the trench 11.

[0164] p + A connection region 34 of the type contacts the first pillar region 32a. The connection region 34 is provided between the drift region 24 and the first trench 11a. The connection region 34 is provided between the body region 26 and the first trench 11a. The connection region 34 is provided between the source region 28 and the first trench 11a.

[0165] The connection region 34 contacts the side surface of the trench 11. The connection region 34 contacts, for example, the bottom surface of the trench 11. The connection region 34 contacts, for example, the first face F1.

[0166] The connection region 34 contacts the side surface of the first trench 11a. The connection region 34 contacts, for example, the bottom surface of the first trench 11a.

[0167] The connection region 34 contacts the gate insulating layer 14. The connection region 34 contacts the source electrode 16 on the first face F1, for example.

[0168] As shown in FIG. 15, the plurality of connection regions 34 are repeatedly arranged at intervals Sp in the first direction.

[0169] The connection region 34 has the function of electrically connecting the pillar region 32 and the source electrode 16. The connection region 34 is a connecting portion that connects the pillar region 32 and the source electrode 16. The connection region 34 fixes the pillar region 32 to the potential of the source electrode 16. The connection region 34 fixes the pillar region 32 to the source potential.

[0170] The connection region 34 also serves to reduce the electrical resistance between the source electrode 16 and the body region 26 .

[0171] The semiconductor device of the second embodiment can be formed, for example, by using the manufacturing method of the first embodiment, after forming the trench 11 and before forming the sidewall material 44, by injecting carbon (C) and aluminum (Al) from the side of the trench 11 using an oblique ion implantation method.

[0172] The MOSFET 200 has a connection region 34 that electrically connects the pillar region 32 and the source electrode 16. Therefore, when the MOSFET 200 is turned off, the discharge of holes from the pillar region 32 is promoted, thereby reducing the switching loss of the MOSFET 200.

[0173] Furthermore, the MOSFET 200 has the connection region 34, and thus has a p-type MOSFET on the first face F1, as in the MOSFET 100. + This eliminates the need to provide a contact region of the type shown in FIG. 15. Therefore, for example, the distance St between two adjacent trenches can be reduced, thereby reducing the on-resistance of the MOSFET 200. This is possible because the impurity concentration in the connection region 34 is not spread by diffusion even if the impurity concentration is increased. Furthermore, compared to the case where diffusion is not suppressed, Sp in FIG. 15 can be made longer. The channel area per unit area is increased, thereby further reducing the on-resistance of the MOSFET 200. This is possible because the impurity concentration in the connection region 34 is not spread by diffusion even if the impurity concentration is increased.

[0174] As described above, according to the semiconductor device and the method for manufacturing the semiconductor device of the second embodiment, it is possible to reduce the on-resistance.

[0175] (Third embodiment) The inverter circuit and the drive device of the third embodiment are an inverter circuit and a drive device that include the semiconductor device of the first embodiment.

[0176] 16 is a schematic diagram of a driving device according to the third embodiment. The driving device 700 includes a motor 140 and an inverter circuit 150.

[0177] The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c, each of which uses the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140.

[0178] According to the fourth embodiment, the inverter circuit 150 and the driving device 700 are provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the inverter circuit 150 and the driving device 700.

[0179] (Fourth embodiment) The vehicle of the fourth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0180] 17 is a schematic diagram of a vehicle according to the fourth embodiment. The vehicle 800 according to the fourth embodiment is a railway vehicle. The vehicle 800 includes a motor 140 and an inverter circuit 150.

[0181] The inverter circuit 150 is composed of three semiconductor modules that use the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The wheels 90 of the vehicle 800 are rotated by the motor 140.

[0182] According to the fourth embodiment, the vehicle 800 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 800.

[0183] (Fifth embodiment) The vehicle of the fifth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0184] 18 is a schematic diagram of a vehicle according to the fifth embodiment. The vehicle 900 according to the fifth embodiment is an automobile. The vehicle 900 includes a motor 140 and an inverter circuit 150.

[0185] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0186] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the wheels 90 of the vehicle 900.

[0187] According to the fifth embodiment, the vehicle 900 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 900.

[0188] (Sixth embodiment) The elevator of the sixth embodiment is an elevator equipped with the semiconductor device of the first embodiment.

[0189] 19 is a schematic diagram of an elevator according to the sixth embodiment. The elevator 1000 according to the sixth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoist 616, a motor 140, and an inverter circuit 150.

[0190] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0191] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the hoisting machine 616, causing the car 610 to rise and fall.

[0192] According to the sixth embodiment, the elevator 1000 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the elevator 1000.

[0193] In the above, in the first and second embodiments, aluminum (Al) has been used as an example of a p-type impurity, but boron (B) can also be used as a p-type impurity.

[0194] In the first embodiment, an example has been described in which the first ion implantation is performed before the second ion implantation, but it is also possible to perform the first ion implantation after the second ion implantation.

[0195] In the above, the first and second embodiments have been described using an example in which the silicon carbide has a crystal structure of 4H—SiC, but the present invention can also be applied to silicon carbide with other crystal structures, such as 6H—SiC and 3C—SiC.

[0196] In the first and second embodiments, a MOSFET is used as an example of a semiconductor device, but the present invention can also be applied to an insulated gate bipolar transistor (IGBT). For example, an IGBT can be realized by replacing the region corresponding to the drain region 22 of the MOSFET 100 from n-type to p-type.

[0197] Furthermore, in the third to sixth embodiments, the semiconductor device of the present invention has been described as being applied to vehicles and elevators, but the semiconductor device of the present invention can also be applied to, for example, a power conditioner of a solar power generation system.

[0198] Furthermore, in the third to sixth embodiments, the semiconductor device of the first embodiment is applied, but it is also possible to apply, for example, the semiconductor device of the second embodiment.

[0199] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0200] 10 Silicon carbide layer 11 Trench 11a First Trench 11b Second trench 12a First gate electrode 12b Second gate electrode 14a First gate insulating layer 14b Second gate insulating layer 16 Source electrode (first electrode) 18 Drain electrode (second electrode) 24 drift region (first silicon carbide region) 26 Body region (second silicon carbide region) 28 source region (third silicon carbide region) 32a First pillar region (fourth silicon carbide region) 32b Second pillar region (fifth silicon carbide region) 32x low density area (first area) 32y High concentration region (second region) 34 Connection region (sixth silicon carbide region) 40 Masking material 40a opening 44 Sidewall material 100 MOSFET (semiconductor device) 150 Inverter circuit 200 MOSFET (semiconductor device) 700 Drive Unit 800 vehicles 900 vehicles 1000 elevators F1 First Side F2 Second side

Claims

1. a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench in the silicon carbide layer, the first trench extending in the first direction at the first surface; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; a second trench in the silicon carbide layer, extending in the first direction at the first surface and positioned in the second direction relative to the first trench; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, between the first silicon carbide region and the first surface, and between the first trench and the second trench; an n-type third silicon carbide region located in the silicon carbide layer and between the second silicon carbide region and the first surface; a p-type fourth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the first trench; a p-type fifth silicon carbide region located in the silicon carbide layer and between the first silicon carbide region and the second trench; a first electrode located on the first surface side of the silicon carbide layer and electrically connected to the second silicon carbide region and the third silicon carbide region; a second electrode located on the second surface side of the silicon carbide layer; Equipped with a width of the fourth silicon carbide region in the second direction is smaller than a width of the first trench in the second direction; a length of the fourth silicon carbide region in a third direction from the first surface toward the second surface is longer than a width of the fourth silicon carbide region in the second direction; the fourth silicon carbide region includes a first region and a second region located between the first region and the first trench, in contact with the first trench, and having a p-type impurity concentration higher than a p-type impurity concentration of the first region; the p-type impurity concentration of the first region is higher than 1×10 17 cm −3 ; A semiconductor device, wherein the p-type impurity concentration of the second region is higher than 1×10 20 cm −3 .

2. 2 . The semiconductor device according to claim 1 , wherein a width of said fourth silicon carbide region in said second direction is 90% or less of a width of said first trench in said second direction.

3. 2 . The semiconductor device according to claim 1 , wherein a width of said fourth silicon carbide region in said second direction is smaller than a width of said first gate electrode in said second direction.

4. The semiconductor device according to claim 1 , wherein a length of said fourth silicon carbide region in said third direction is longer than a length of said first trench in said third direction.

5. 2. The semiconductor device according to claim 1, wherein the length of said second region in said third direction is shorter than the length of said first region in said third direction.

6. 2 . The semiconductor device according to claim 1 , wherein a width in said second direction of said fourth silicon carbide region is smaller than a width in said second direction of said first silicon carbide region between said fourth silicon carbide region and said fifth silicon carbide region.

7. 2. The semiconductor device according to claim 1, further comprising: a plurality of p-type sixth silicon carbide regions located in the silicon carbide layer, in contact with the fourth silicon carbide region, between the first silicon carbide region and the first trench, between the second silicon carbide region and the first trench, and between the third silicon carbide region and the first trench, and repeatedly arranged in the first direction.

8. 8. An inverter circuit comprising the semiconductor device according to claim 1.

9. A driving device comprising the semiconductor device according to any one of claims 1 to 7.

10. A vehicle comprising the semiconductor device according to any one of claims 1 to 7.

11. An elevator comprising the semiconductor device according to any one of claims 1 to 7.

12. forming a mask material having an opening on the surface of the silicon carbide layer; forming a trench in the silicon carbide layer using the mask material as a mask; performing a first ion implantation to implant carbon (C) into the bottom surface of the trench to a region whose depth from the bottom surface is deeper than the depth of the trench, using the mask material as a mask; forming a sidewall material on a side surface of the trench; performing a second ion implantation using the sidewall material as a mask to implant a p-type first impurity into the bottom surface of the trench to a region whose depth from the bottom surface is deeper than the depth of the trench; A method for manufacturing a semiconductor device, which involves heat treatment at 1600°C or higher.

13. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the first ion implantation is performed at a temperature of 1000[deg.] C. or higher.

14. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the second ion implantation is performed at a temperature of 1000[deg.] C. or higher.

15. 13. The method for manufacturing a semiconductor device according to claim 12, wherein a dose of carbon (C) implanted in the first ion implantation is 10 times or more a dose of the first impurity implanted in the second ion implantation.

16. 13. The method for manufacturing a semiconductor device according to claim 12, further comprising, after forming the sidewall material and before the heat treatment, performing a third ion implantation using the sidewall material as a mask to implant a second p-type impurity into the bottom surface of the trench to a region whose depth from the bottom surface is shallower than the depth of the trench.

17. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the first impurity is aluminum (Al).

Images