Signal processing device, signal processing method, and receiving device

Abstract

The present technology relates to a signal processing device, a signal processing method, and a receiver that enable gain control to be appropriately performed on various interfering signals. An amplifier amplifies a signal by controlling the gain according to a count value, and a comparator compares the signal outputted by the amplifier and the count value. A counter counts the count value according to the output of the comparator. The present technology can be applied, for example, to a receiver, or the like, that receives an RF signal for a television broadcast.

Description

[Technical Field]

[0001] The present technology relates to a signal processing device, a signal processing method, and a receiving device, and in particular to a signal processing device, a signal processing method, and a receiving device that enable appropriate gain control to be performed for various interference signals, for example. [Background technology]

[0002] BACKGROUND ART A receiving device has been proposed that controls the gain of an amplifier that amplifies an RF (radio frequency) signal to prevent degradation of communication quality (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-157394 Summary of the Invention [Problem to be solved by the invention]

[0004] However, depending on the interfering signal (its profile), it may be difficult to appropriately control the gain of an amplifier that amplifies an RF signal containing the interfering signal.

[0005] The present technology has been made in view of such circumstances, and is intended to enable appropriate gain control to be performed against various interference signals. [Means for solving the problem]

[0006] The signal processing device of the present technology is a signal processing device that includes an amplifier that controls gain according to a count value and amplifies a signal, a comparator that compares the signal output by the amplifier with the count value, and an integrator that counts the count value according to the output of the comparator.

[0007] The signal processing method of the present technology is a signal processing method that includes: an amplifier controlling a gain according to a count value and amplifying a signal; a comparator comparing a signal output by the amplifier with the count value; and an integrator counting the count value according to the output of the comparator.

[0008] The receiving device of the present technology is a receiving device that includes an amplifier that controls gain according to a count value and amplifies a signal, a comparator that compares the signal output by the amplifier with the count value, an integrator that counts the count value according to the output of the comparator, and a demodulation circuit that demodulates the signal output by the amplifier.

[0009] In the signal processing device, signal processing method, and receiving device according to the present technology, an amplifier controls a gain according to a count value to amplify a signal, a comparator compares a signal output by the amplifier with the count value, and an integrator counts the count value according to the output of the comparator.

[0010] The signal processing device and the receiving device may be independent devices, or may be internal blocks constituting a single device. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram illustrating a configuration example of an embodiment of a receiving device to which the present technology is applied. [Figure 2] FIG. 2 is a diagram illustrating a first configuration example of the OVLD avoidance circuit 11. [Figure 3] 10 is a diagram illustrating an example of gain control of the RF amplifier 21. FIG. [Figure 4] 10 is a diagram showing an example of the level (MIXOUT level) of the envelope of the IF signal and the RFGC voltage when the SW type OVLD avoidance circuit 11 starts operating. FIG. [Figure 5] 10A and 10B are diagrams illustrating examples of a detection voltage and an RFGC voltage corresponding to an RF signal as a disturbance signal. [Figure 6]FIG. 10 is a diagram illustrating a second configuration example of the OVLD avoidance circuit 11. [Figure 7] FIG. 2 is a block diagram showing an example of the configuration of a DTC generating unit 61. [Figure 8] FIG. 10 is a block diagram showing another example of the configuration of the amplitude detection section 25. [Figure 9] 10 is a timing chart illustrating an example of the operation of the OVLD avoidance circuit 11. [Figure 10] FIG. 10 is a diagram illustrating a third configuration example of the OVLD avoidance circuit 11. [Figure 11] 10A and 10B are diagrams illustrating examples of frequency distributions of a desired signal and an interference signal. [Figure 12] FIG. 10 is a diagram illustrating a fourth configuration example of the OVLD avoidance circuit 11. [Figure 13] FIG. 10 is a diagram illustrating a fifth configuration example of the OVLD avoidance circuit 11. [Figure 14] 10A and 10B are diagrams illustrating examples of frequency distributions of a desired signal and an interference signal. [Figure 15] FIG. 10 is a diagram illustrating a sixth configuration example of the OVLD avoidance circuit 11. [Figure 16] FIG. 10 is a diagram illustrating a seventh configuration example of the OVLD avoidance circuit 11. [Figure 17] 10 is a timing chart illustrating an example of the operation of the OVLD avoidance circuit 11. [Figure 18] FIG. 10 is a diagram illustrating an eighth configuration example of the OVLD avoidance circuit 11. [Figure 19] 10A and 10B are diagrams illustrating examples of a detection voltage and an RFGC voltage corresponding to an RF signal as a disturbance signal. DETAILED DESCRIPTION OF THE INVENTION

[0012] <One embodiment of a receiving device to which the present technology is applied>

[0013] FIG. 1 is a block diagram showing an example of the configuration of an embodiment of a receiving device to which the present technology is applied.

[0014] In FIG. 1, the receiving device 10 includes an OVLD (overload) avoidance circuit 11, an ADC (analog to digital converter) 12, and a demodulation circuit 13.

[0015] The receiving device 10 receives, for example, an RF signal such as a television broadcast, demodulates it, and outputs the result.

[0016] The OVLD avoidance circuit 11 is supplied with an RF signal.

[0017] The OVLD avoidance circuit 11 controls the gain so that the level can be processed by the subsequent block, amplifies the RF signal, frequency-converts it to an IF (intermediate frequency) signal, and outputs the result.

[0018] The ADC 12 performs AD conversion on the IF signal output by the OVLD avoidance circuit 11 and supplies it to the demodulation circuit 13.

[0019] The demodulation circuit 13 demodulates the IF signal from the ADC 12 and outputs the demodulated signal obtained by the demodulation.

[0020] <First Configuration Example of the OVLD Avoidance Circuit 11>

[0021] FIG. 2 is a diagram showing a first configuration example of the OVLD avoidance circuit 11 in FIG. 1.

[0022] In FIG. 2, the OVLD avoidance circuit 11 includes an RF amplifier 21, a mixer 22, a BPF (band pass filter) 23, an IF amplifier 24, an amplitude detection unit 25, and a gain control unit 26.

[0023] The RF amplifier 21 is supplied with an RF signal.

[0024] The RF amplifier 21 controls the gain in accordance with an RFGC (RF gain control) voltage as a gain control signal (for the RF amplifier 21) from the gain control unit 26, and amplifies and outputs the RF signal with that gain. By controlling the gain in accordance with the RFGC voltage, the RF amplifier 21 amplifies the RF signal so that good reception characteristics can be adaptively obtained in the receiving device 10 while avoiding saturation.

[0025] The mixer 22 multiplies the RF signal output by the RF amplifier 21 by a signal of a predetermined frequency, thereby frequency-converting the RF signal into an IF signal and outputting the IF signal.

[0026] Here, the IF signal output by mixer 22 is a signal obtained by frequency converting the RF signal output by RF amplifier 21, and is therefore also a signal output by RF amplifier 21, and is a signal proportional to the signal output by RF amplifier 21.

[0027] The BPF 23 filters the IF signal output by the mixer 22 and outputs an IF signal in a predetermined frequency band.

[0028] The IF amplifier 24 amplifies and outputs the IF signal output by the BPF 23. The IF signal output by the IF amplifier 24 is supplied to the ADC 12 (FIG. 1).

[0029] Here, the gain of the IF amplifier 24 is controlled in response to a gain control signal (for the IF amplifier 24) supplied from a circuit not shown.

[0030] The amplitude detection unit 25 detects the amplitude (level) of the IF signal output by the mixer 22 (which, as described above, is also the signal output by the RF amplifier 21 and is a signal proportional to the signal output by the RF amplifier 21), and outputs a detection voltage obtained as a result of the detection.

[0031] The amplitude detection unit 25 includes a peak hold unit 31, for example.

[0032] The peak hold unit 31 detects the envelope of the IF signal by holding the peak of the IF signal output by the mixer 22, and outputs the level of the envelope as a detected voltage.

[0033] The gain control unit 26 generates and outputs an RFGC voltage as a gain control signal in accordance with the detected voltage from the amplitude detection unit 25. The RFGC voltage output by the gain control unit 26 is supplied to the RF amplifier 21, and the RF amplifier 21 controls the gain in accordance with the RFGC voltage.

[0034] The gain control section 26 includes, for example, a comparator 32, a DC power supply 33, a switch SW, a resistor R1, a capacitor C, and a resistor R2.

[0035] The detection voltage from the amplitude detection unit 25 (peak hold unit 31) is supplied to the non-inverting input terminal of the comparator 32. The voltage of the capacitor C, which becomes the RFGC voltage, is supplied to the inverting input terminal of the comparator 32.

[0036] The comparator 32 compares the detection voltage supplied to the non-inverting input terminal with the RFGC voltage supplied to the inverting input terminal, and outputs the comparison result.

[0037] For example, the comparator 32 outputs an H (high) level when the detection voltage is greater than (equal to or greater than) the RFGC voltage, and outputs an L (low) level when the detection voltage is not greater than (less than) the RFGC voltage.

[0038] Here, the state in which the detection voltage is greater than the RFGC voltage is also called an attack state, and the state in which the detection voltage is not greater than the RFGC voltage is also called a recovery state.

[0039] The positive electrode of the DC power supply 33 is connected to one end of the resistor R1 via the switch SW, and the negative electrode of the DC power supply 33 is connected to the ground (GND).

[0040] The switch SW turns on / off in accordance with the output of the comparator 32, thereby turning on / off the connection between the DC power supply 33 and the resistor R1.

[0041] The other end of the resistor R1 is connected to one end of the capacitor C and the resistor R2, and the other ends of the capacitor C and the resistor R2 are connected to ground. Therefore, the capacitor C and the resistor R2 are connected in parallel.

[0042] The other end of the resistor R1 and the connection point of the capacitor C and one end of the resistor R2 are connected to an output terminal, and the voltage at this connection point is output as an RFGC voltage from the output terminal of the gain control unit 26. Therefore, the voltage of the capacitor C is output as an RFGC voltage from the output terminal.

[0043] In the gain control section 26, for example, when the output of the comparator 32 is at H level and in an attack state, the switch SW is turned on, and the connection between the DC power supply 33 and the resistor R1 is turned on. This turns on the application of the (DC) voltage from the DC power supply 33 to the capacitor C, and the capacitor C is charged.

[0044] On the other hand, when the output of the comparator 32 is at L level and in the recovery state, the switch SW is turned off, and the connection between the DC power supply 33 and the resistor R1 is cut off. This cuts off the application of the voltage from the DC power supply 33 to the capacitor C, and the charge stored in the capacitor C is discharged via the resistor R2.

[0045] Therefore, the application of voltage from the DC power supply 33 to the capacitor C is turned on or off depending on the output of the comparator 32.

[0046] FIG. 3 is a diagram illustrating an example of control of the gain of the RF amplifier 21. In FIG.

[0047] In FIG. 3, the horizontal axis represents the RFGC voltage, and the vertical axis represents the gain of the RF amplifier 21.

[0048] As shown in FIG. 3, the RF amplifier 21 is controlled so that the gain decreases as the RFGC voltage increases (so that the gain increases as the RFGC voltage decreases).

[0049] The gain of the RF amplifier 21 can also be controlled (gain control) so that the gain increases as the RFGC voltage increases. When the gain of the RF amplifier 21 is controlled so that the gain increases as the RFGC voltage increases, the logic of the comparator 32 needs to be inverted.

[0050] 2, in an attack state in which the detection voltage is higher than the RFGC voltage, the switch SW turns on and charges the capacitor C. Therefore, in an attack state, the voltage of the capacitor C, i.e., the RFGC voltage, rises and the gain of the RF amplifier 21 falls.

[0051] When the gain of the RF amplifier 21 decreases, the level (voltage) of the IF signal output by the mixer 22, and therefore the detection voltage, decreases.

[0052] When the detection voltage decreases and enters a recovery state where the detection voltage is not larger than the RFGC voltage, the switch SW turns off and discharges the capacitor C. Therefore, in the recovery state, the voltage of the capacitor C, i.e., the RFGC voltage, decreases and the gain of the RF amplifier 21 increases.

[0053] When the gain of the RF amplifier 21 increases, the level of the IF signal output by the mixer 22, and therefore the detection voltage, also increases.

[0054] Then, when the detection voltage and the RFGC voltage are balanced, the OVLD avoidance circuit 11 becomes stable. That is, the RFGC voltage, and furthermore, the gain of the RF amplifier 21, becomes (almost) constant.

[0055] As described above, in the OVLD avoidance circuit 11, the gain control of the RF amplifier 21 is performed by charging and discharging the capacitor C using the switch SW inserted in the charging path through which the DC power supply 33 charges the capacitor C, i.e., the connection line between the DC power supply 33 and the capacitor C.

[0056] The above-described gain control method, which is performed by charging and discharging the capacitor C using the switch SW, is hereinafter also referred to as the SW method.

[0057] FIG. 4 is a diagram showing an example of the level (MIXOUT level) of the envelope of the IF signal and the RFGC voltage when the SW type OVLD avoidance circuit 11 starts to operate.

[0058] The OVLD avoidance circuit 11 is reset at the start of operation, and the reset causes the gain control unit 26 to output an RFGC voltage of, for example, 0 V. The OVLD avoidance circuit 11 is reset, for example, at the start of operation, and also when an interference signal occurs after the start of operation, and then the interference signal disappears and the RFGC voltage returns to its original value (here, 0 V).

[0059] Thereafter, when an RF signal occurs as a disturbance signal, the RF signal is amplified by the gain immediately after the RF amplifier 21 is reset, and as a result, the level of the IF signal (MIXOUT) output by the mixer 22, and therefore the detection voltage, increases.

[0060] When the detection voltage is greater than the RFGC voltage (attack state), the switch SW turns on and the voltage of the capacitor C, which is the RFGC voltage, rises.

[0061] The increase in the RFGC voltage reduces the gain of the RF amplifier 21, and as a result, the level of the IF signal output by the mixer 22, and therefore the detection voltage, decreases.

[0062] When the detection voltage decreases and enters a recovery state where the detection voltage is not larger than the RFGC voltage, the switch SW turns off and discharges the capacitor C. Therefore, in the recovery state, the voltage of the capacitor C, i.e., the RFGC voltage, decreases and the gain of the RF amplifier 21 increases.

[0063] When the gain of the RF amplifier 21 increases, the level of the IF signal output by the mixer 22, and therefore the detection voltage, also increases.

[0064] Then, when the detection voltage and the RFGC voltage are balanced, the OVLD avoidance circuit 11 becomes stable. That is, the RFGC voltage, and therefore the gain of the RF amplifier 21, become constant.

[0065] FIG. 5 is a diagram showing an example of a detection voltage and an RFGC voltage corresponding to an RF signal as a disturbance signal.

[0066] FIG. 5A shows the detected voltage and RFGC voltage corresponding to a continuous jamming signal.

[0067] For a continuous interference signal, the attack state and the recovery state are repeated in a short cycle, and an RFGC voltage that is close to a stable state, that is, an RFGC voltage with small fluctuations, is generated.

[0068] FIG. 5B shows the detected voltage and RFGC voltage corresponding to an intermittent interference signal.

[0069] For an intermittent interference signal, the state is an attack state during the period when the interference signal is present, and the state is a recovery state during the period when the interference signal is not present.

[0070] Therefore, for an intermittent interference signal, the attack state and the recovery state are repeated depending on the length of the period of time during which the interference signal is present or absent.

[0071] In the attack state, the voltage of the capacitor C, which is the RFGC voltage, rises, and in the recovery state, the voltage of the capacitor C, which is the RFGC voltage, drops according to a time constant determined by the capacitor C and the resistor R2.

[0072] Therefore, the RFGC voltage has a sawtooth waveform.

[0073] Here, the time from when the OVLD avoidance circuit 11 receives an RF signal as a disturbance signal until the RFGC voltage starts to stabilize is referred to as the attack time.

[0074] Furthermore, the time from when the RF signal as a disturbance signal is received by the OVLD avoidance circuit 11 until the RFGC voltage returns to the voltage at the time of reset after the disturbance signal disappears is referred to as recovery time.

[0075] In both A and B of FIG. 5, the RFGC voltage is not stable, and therefore the RFGC voltage is in the attack time.

[0076] To quickly stabilize the RFGC voltage, a short attack time is desirable. To shorten the attack time, the time constant during charging and discharging of capacitor C must be reduced.

[0077] Furthermore, from the viewpoint of stabilizing the RFGC voltage over a long period of time, a long recovery time is desirable. To achieve a long recovery time, the time constant of the capacitor C when it is discharged must be increased.

[0078] If the recovery time is short, the amount of drop in the RFGC voltage during periods when no intermittent interference signal is present increases, and the sawtooth-shaped change in the RFGC voltage increases, making it difficult to generate a stable RFGC voltage.

[0079] In order to generate a stable RFGC voltage for an intermittent interference signal, it is necessary to shorten the attack time and lengthen the recovery time.

[0080] However, in the SW type OVLD avoidance circuit 11, the attack time and recovery time are restricted due to the circuit configuration, making it difficult to generate a stable RFGC voltage for an intermittent interference signal.

[0081] That is, in the SW type OVLD avoidance circuit 11, the attack time and recovery time are determined by a time constant determined by the product of the capacitance value and the resistance value, but the circuit constants that can be adopted in the time constant circuit that provides that time constant are restricted.

[0082] The maximum capacitance value of capacitors available as general-purpose chip components is around 0.1 uF. Capacitors with values ​​exceeding this value are difficult to adopt for consumer applications due to their high cost, large temperature and voltage dependency of capacitance, and large size.

[0083] In addition, by increasing the capacitance value of the capacitor C, the recovery time can be lengthened, but at the same time, the attack time also becomes longer.

[0084] For this reason, the capacitance value of the capacitor C is set to a value that strikes a balance between shortening the attack time and lengthening the recovery time.

[0085] Methods for lengthening the recovery time include increasing the capacitance value of capacitor C and increasing the resistance value of resistor R2.

[0086] However, in the OVLD avoidance circuit 11, various leaks exist in devices such as the substrate, components, and ICs, so the resistance value that can be adopted for the resistor R2 is approximately 10 MΩ at most, and the recovery time is limited by this resistance value.

[0087] As described above, in the SW method OVLD avoidance circuit 11, in order to increase the recovery time, a large-capacity capacitor is required as the capacitor C, which increases the BOM (bill of materials) cost. Furthermore, it is difficult to provide a large-capacity capacitor C inside the chip, and since the capacitor C needs to be externally attached, the substrate area increases. In addition, when providing a resistor R2 with a large resistance value of about 10 MΩ in order to increase the recovery time, as with a large-capacity capacitor C, it also needs to be externally attached, and again, the substrate area increases.

[0088] Also, in the SW method OVLD avoidance circuit 11, particularly for intermittent interference signals, due to the time constant, the attack time becomes longer.

[0089] Furthermore, in the SW method OVLD avoidance circuit 11, due to the capacitance value of the capacitor C, component unit price, and leakage of the device, the length of the recovery time is restricted, and due to this restriction, there are intermittent interference signals (profiles) that make it difficult to generate a stable RFGC voltage.

[0090] Also, in the SW method OVLD avoidance circuit 11, variations in operation may occur due to deviations in the capacitance value of the capacitor C, temperature dependence, and voltage dependence.

[0091] <Second Configuration Example of OVLD Avoidance Circuit 11>

[0092] FIG. 6 is a diagram showing a second configuration example of the OVLD avoidance circuit 11 of FIG. 1. <0​​​​​​​​​​2 in that it includes the RF amplifier 21 through the amplitude detection unit 25. In other words, the OVLD avoidance circuit 11 in FIG.

[0096] However, the OVLD avoidance circuit 11 in FIG. 6 differs from that in FIG. 2 in that it has a gain control section 51 instead of the gain control section 26.

[0097] The gain control unit 51 generates and outputs an RFGC voltage as a gain control signal in accordance with the detected voltage from the amplitude detection unit 25. The RFGC voltage output by the gain control unit 51 is supplied to the RF amplifier 21, and the RF amplifier 21 controls the gain in accordance with the RFGC voltage.

[0098] The gain control unit 51 includes a comparator 32, a DTC (digital time constant) generation unit 61, and a DAC (digital to analog converter) 62.

[0099] The DTC generating unit 61 counts in synchronization with an externally supplied clock in response to the output of the comparator 32, and generates and outputs a count value that changes with a predetermined time constant based on the count.

[0100] The DAC 62 converts the count value output by the DTC generating unit 61 into an analog signal by digital-to-analog conversion, and outputs the analog signal as an RFGC voltage.

[0101] The RFGC voltage output by the DAC 62 is supplied to the RF amplifier 21 via the output terminal (of the gain control unit 51), and is also supplied to the inverting input terminal of the comparator 32.

[0102] Therefore, the comparator 32 compares the detected voltage output by the amplitude detection unit 25 (peak hold unit 31) with the RFGC voltage output by the DAC 62.

[0103] If the gain control of the RF amplifier 21 can be performed by a digital signal, the gain control unit 51 can be configured without the DAC 62. In this case, the count value output by the DTC generation unit 61 is provided to the RF amplifier 21 as a gain control signal.

[0104] 6, the RFGC voltage is a signal (voltage) obtained by converting the count value output by the DTC generation unit 61 into an analog signal. Therefore, the RF amplifier 21 that performs gain control in accordance with the RFGC voltage can be said to be an amplifier that performs gain control in accordance with the count value output by the DTC generation unit 61.

[0105] Similarly, the comparator 32 can be said to be a comparator that compares the signal output by the RF amplifier 21 with the count value output by the DTC generation unit 61.

[0106] FIG. 7 is a block diagram showing an example of the configuration of the DTC generating unit 61 shown in FIG.

[0107] The DTC generation unit 61 includes an accumulator 71 and a timer 72 .

[0108] The accumulator 71 counts the count value in accordance with the output of the comparator 32 .

[0109] That is, the accumulator 71 counts (accumulates) the count value with an accumulating polarity according to the output of the comparator 32 and at the timing of the timing signal output by the timer 72.

[0110] The accumulator 71 either counts up or counts down the count value in the attack state where the output of the comparator 32 is at H level, or counts up or counts down the count value in the recovery state where the output of the comparator 32 is at L level.

[0111] For example, the accumulator 71 counts (counts up) the count value with an accumulating polarity of count up in the attack state, and counts (counts down) the count value with an accumulating polarity of count down in the recovery state.

[0112] The timer 72 generates and outputs a timing signal (for example, a pulse) synchronized with the clock supplied to the DTC generation unit 61.

[0113] The timer 72 sets the timer mode, which is the operation mode of the timer 72, according to the output of the comparator 32, and generates timing signals at intervals (cycles) that vary depending on the timer mode.

[0114] Here, the timer mode in the attack state where the output of the comparator 32 is at H level is also called attack mode, and the timer mode in the recovery state where the output of the comparator 32 is at L level is also called recovery mode.

[0115] In attack mode, the timer 72 generates a timing signal with a period (first interval) obtained by dividing the clock frequency by a factor of N. In recovery mode, the timer 72 generates a timing signal with a period (second interval) obtained by dividing the clock frequency by a factor of M, which is greater than N.

[0116] Therefore, the period of the timing signal in the recovery mode is longer than the period of the timing signal in the attack mode.

[0117] Here, the period of the timing signal in the attack mode is also called the attack period, and the period of the timing signal in the recovery mode is also called the recovery period.

[0118] The timer 72 is configured so that the attack period and recovery period (division ratios N and M) can be set externally.

[0119] Therefore, the attack period and recovery period are programmable.

[0120] The accumulator 71 counts the count value at the timing of the timing signal output by the timer 72, that is, at the attack period or recovery period. Therefore, the count interval of the count value of the accumulator 71 is also programmable.

[0121] In the OVLD avoidance circuit 11 configured as above, when the detection voltage is in an attack state higher than the RFGC voltage (when the output of the comparator 32 is at H level), the timer 72 enters attack mode and generates and outputs a timing signal of an attack period.

[0122] In the attack state, the accumulator 71 counts up the count value, for example, by one digit at a time, at the timing of a timing signal output by the timer 72. The DAC 62 performs digital-to-analog conversion on the count value of the accumulator 71 and outputs it as an RFGC voltage.

[0123] Therefore, in the attack state, the RFGC voltage increases by a voltage corresponding to one digit of the count value in an attack period.

[0124] As the RFGC voltage increases, the gain of the RF amplifier 21 decreases.

[0125] When the gain of the RF amplifier 21 decreases, the level of the IF signal output by the mixer 22, and therefore the detection voltage, decreases.

[0126] When the detection voltage drops and enters a recovery state where the detection voltage is not higher than the RFGC voltage (the output of the comparator 32 becomes L level), the timer 72 enters recovery mode and generates and outputs a timing signal of a recovery period.

[0127] In the recovery state, the integrator 71 counts down the count value, for example, by one digit at a time, at the timing of a timing signal output by the timer 72. The DAC 62 performs digital-to-analog conversion on the count value of the integrator 71 and outputs it as an RFGC voltage.

[0128] Therefore, in the recovery state, the RFGC voltage decreases by a voltage corresponding to one digit of the count value in each recovery period.

[0129] As the RFGC voltage decreases, the gain of the RF amplifier 21 increases.

[0130] When the gain of the RF amplifier 21 increases, the level of the IF signal output by the mixer 22, and therefore the detection voltage, also increases.

[0131] In this way, in the OVLD avoidance circuit 11, the detection voltage and the RFGC voltage are balanced so that the IF signal output from the mixer 22 falls within a level that provides a good reception state while avoiding saturation of the IF signal.

[0132] Then, when the detection voltage and the RFGC voltage are balanced, the OVLD avoidance circuit 11 becomes stable. That is, the RFGC voltage, and furthermore, the gain of the RF amplifier 21, becomes (almost) constant.

[0133] As described above, in the OVLD avoidance circuit 11, the gain control of the RF amplifier 21 is performed by counting up the count value in the attack period and counting down the count value in the recovery period.

[0134] Hereinafter, the gain control method in which the count value is counted up in the attack period and counted down in the recovery period as described above will also be referred to as the count method.

[0135] FIG. 8 is a block diagram showing another example of the configuration of the amplitude detection section 25. In FIG.

[0136] In the figure, parts corresponding to those in FIG. 2 or FIG. 6 are given the same reference numerals, and the description thereof will be omitted below as appropriate.

[0137] 8, the amplitude detection unit 25 includes a peak hold unit 31 and an amplitude scaler 81.

[0138] 8 is common to the cases of Fig. 2 or 6 in that it has a peak hold unit 31. However, the amplitude detection unit 25 of Fig. 8 differs from the cases of Fig. 2 or 6 in that it is newly provided with an amplitude scaler 81.

[0139] The amplitude scaler 81 is supplied with the IF signal output by the mixer 22 .

[0140] The amplitude scaler 81 scales the IF signal output by the mixer 22 , that is, multiplies the IF signal by a predetermined amplitude scaler coefficient, and supplies the resulting signal to the peak hold unit 31 .

[0141] 8, the peak hold unit 31 detects the envelope of the scaled IF signal from the amplitude scaler 81, and outputs the level of the envelope as a detected voltage. As a result, the comparator 32 compares the detected voltage of the scaled IF signal (the signal output by the amplitude scaler 81) with the RFGC voltage (the output of the DAC 62).

[0142] The amplitude scaler coefficient of the amplitude scaler 81 is configured to be externally settable and is programmable.

[0143] FIG. 9 is a timing chart illustrating an example of the operation of the OVLD avoidance circuit 11 of FIG.

[0144] Figure 9 shows, from top to bottom, the output of comparator 32 (comparator output), the integration polarity of integrator 71, the count value of integrator 71, the timer mode of timer 72, the timing signal output by timer 72, the detection voltage output by amplitude detection unit 25, the RFGC voltage output by DAC 62, the envelope of the IF signal output by mixer 22, and the envelope of the RF signal output by RF amplifier 21.

[0145] The OVLD avoidance circuit 11 is reset at the start of operation, and after the reset, a predetermined initial value is set as the count value in the integrator 71. The initial value of the count value can be set externally.

[0146] The DAC 62 converts the initial count value into digital and outputs it as an RFGC voltage.

[0147] On the other hand, in the RF amplifier 21, for example, the RF signal including the interference signal is amplified by a gain according to the RFGC voltage and output to the mixer 22. The mixer 22 converts the RF signal from the RF amplifier 21 into an IF signal and outputs the IF signal.

[0148] In the amplitude detection section 25, the IF signal output from the mixer 22 is scaled, and the envelope of the scaled IF signal is detected, and the level of the envelope of the IF signal is output as a detection voltage.

[0149] When the detected voltage is greater than the RFGC voltage, ie, when the output of the comparator 32 is at H level, the timer 72 sets the timer mode to attack mode and generates and outputs a timing signal with an attack period Tattack.

[0150] In the attack state, the accumulator 71 sets the integration polarity to count up (+) and counts the count value at the timing of the timing signal output by the timer 72. Therefore, the count value is incremented by 1 at the attack period Tattack.

[0151] The DAC 62 converts the count value of the integrator 71 into a digital signal and outputs it as an RFGC voltage.

[0152] Therefore, in the attack state, the RFGC voltage increases by a voltage corresponding to one digit of the count value at an attack period Tattack.

[0153] As the RFGC voltage increases, the gain of the RF amplifier 21 decreases.

[0154] When the gain of the RF amplifier 21 decreases, the level of the IF signal output from the mixer 22 decreases, and the detection voltage output from the peak hold unit 31 also decreases.

[0155] When the detection voltage drops and enters a recovery state where the detection voltage is not higher than the RFGC voltage, the timer 72 sets the timer mode to the recovery mode, and generates and outputs a timing signal of the recovery period Trecovery.

[0156] In the recovery state, the integrator 71 sets the integration polarity to count down (-) and counts the count value at the timing of the timing signal output by the timer 72. Therefore, the count value is decremented by 1 at the recovery period Trecovery.

[0157] The DAC 62 converts the count value of the integrator 71 into a digital signal and outputs it as an RFGC voltage.

[0158] Therefore, in the recovery state, the RFGC voltage decreases by a voltage (hereinafter also referred to as a unit voltage) corresponding to one digit of the count value in a recovery period Trecovery.

[0159] As the RFGC voltage decreases, the gain of the RF amplifier 21 increases.

[0160] When the gain of the RF amplifier 21 increases, the level of the IF signal output by the mixer 22 increases, and thus the detection voltage increases.

[0161] 9, at time t1 in the recovery state, the RFGC voltage drops by a unit voltage, causing the detection voltage to enter an attack state where it is higher than the RFGC voltage, and immediately after that, the RF signal increases, causing the detection voltage to further increase in response to the RF signal.

[0162] Thereafter, the OVLD avoidance circuit 11 repeats the same operation, and the detection voltage and the RFGC voltage become balanced.

[0163] Then, when the detection voltage and the RFGC voltage are balanced, the RFGC voltage and hence the gain of the RF amplifier 21 become constant, and the OVLD avoidance circuit 11 becomes stable.

[0164] The slope of the count value counted up in the attack state, and therefore the slope (V / sec) of the RFGC voltage rise, can be adjusted by the attack period Tattack. That is, as shown in Fig. 9, by setting the attack period Tattack to a short time (small), the slope of the RFGC voltage rise can be made steeper, and by setting the attack period Tattack to a long time (large), the slope of the RFGC voltage rise can be made gentler.

[0165] Similarly, the slope of the count value counted down in the recovery state, and therefore the slope of the RFGC voltage decrease, can be adjusted by the recovery period Trecovery. That is, by setting the recovery period Trecovery to a short time, the slope of the RFGC voltage decrease can be made steeper, and by setting the recovery period Trecovery to a long time, the slope of the RFGC voltage decrease can be made gentler.

[0166] Therefore, by setting the attack period Tattack to a short time, the slope of the rise in the RFGC voltage can be made steeper, and the convergence time until the RFGC voltage (and the IF signal) converges can be shortened.

[0167] Furthermore, by setting the recovery period Trecovery to be longer than the attack period Tattack, the slope of the decline of the RFGC voltage can be made gentler, and the time for which the RFGC voltage remains in the converged state after convergence can be made longer.

[0168] By shortening the convergence time of the RFGC voltage and lengthening the duration of the RFGC voltage after convergence, it is possible to shorten the attack time and lengthen the recovery time.

[0169] Therefore, according to the counting method, without being restricted by the component constants of the external capacitor C and resistor R2 like the SW method, nor by the characteristics of actual devices such as leakage, it is possible to achieve a short attack time and a long recovery time. As a result, gain control is appropriately performed for various interference signals.

[0170] In addition, as shown in FIG. 8, the amplitude detection unit 25 is configured to include an amplitude scaler 81, and by adjusting the amplitude scaler coefficient, the level of the IF signal when the RFGC voltage (and the IF signal) converges can be adjusted to an appropriate level for the receiving device 10.

[0171] <The third configuration example of the OVLD avoidance circuit 11>

[0172] FIG. 10 is a diagram showing a third configuration example of the OVLD avoidance circuit 11 in FIG. 1.

[0173] In the figure, parts corresponding to those in FIG. 6 are labeled with the same reference numerals, and the description thereof will be omitted as appropriate below

[0174] In FIG. 10, the OVLD avoidance circuit 11 includes an RF amplifier 21, a mixer 22, a BPF 23, an IF amplifier 24, an amplitude detection unit 25, and a gain control unit 51.

[0175] Therefore, the OVLD avoidance circuit 11 in FIG. 10 is configured in the same manner as in the case of FIG. 6.

[0176] However, the OVLD avoidance circuit 11 in FIG. 10 is different from the case of FIG. 6 in that the RF signal immediately after the RF amplifier 21 outputs is supplied to the amplitude detection unit 25, while the IF signal immediately after the mixer 22 outputs is supplied to the amplitude detection unit 25.

[0177] 10, the amplitude detection unit 25 does not detect the envelope of the IF signal immediately after it is output by the mixer 22, but detects the envelope of the RF signal immediately after it is output by the RF amplifier 21. Then, the amplitude detection unit 25 supplies the level of the envelope of the RF signal to the gain control unit 51 as a detection voltage.

[0178] In the OVLD avoidance circuit 11 of FIG. 6, the gain of the RF amplifier 21 is controlled according to the result of comparison between the RFGC voltage and a detection voltage obtained by detecting the envelope of the IF signal output by the mixer 22.

[0179] On the other hand, in the OVLD avoidance circuit 11 of FIG. 10, the gain of the RF amplifier 21 is controlled according to the result of comparison between the detection voltage obtained by detecting the envelope of the RF signal output by the RF amplifier 21 and the RFGC voltage.

[0180] The IF signal output from the mixer 22 may be band-limited by an LPF (low pass filter).

[0181] When the IF signal is band-limited, the interference signals whose detection voltage is detected are only interference signals (nearby interference signals) within a predetermined frequency band centered on the desired signal that the receiving device 10 is attempting to receive.

[0182] Therefore, interference signals that are far away from the desired signal on the frequency axis (distant interference signals), that is, distant interference signals that are outside the range of a predetermined frequency band centered on the desired signal, are not subject to detection.

[0183] Therefore, it may not be possible to reduce reception interference caused by distant interfering signals.

[0184] FIG. 11 is a diagram showing an example of the frequency distribution of a desired signal and an interference signal.

[0185] When the IF signal output by the mixer 22 is band-limited, the interfering signal whose detection voltage is detected is only the nearby interfering signal (nearby interfering wave) within a frequency band of, for example, about ±100 MHz centered on the desired signal (desired wave) that the receiving device 10 is trying to receive.

[0186] Therefore, distant interfering signals (distant interfering waves) outside the range of the frequency band of about ±100 MHz centered on the desired signal are not subject to detection.

[0187] Therefore, if the IF signal (envelope) output by the mixer 22 is detected, the distant interfering signal may not be reflected in the detection voltage, and the reception failure caused by the distant interfering signal may not be reduced.

[0188] On the other hand, as shown in FIG. 10, by detecting the RF signal output by the RF amplifier 21, a detection voltage reflecting the distant interfering signal as well as the nearby interfering signal can be obtained. By performing gain control of the RF amplifier 21 according to the comparison result between such a detection voltage and the RFGC voltage, it is possible to reduce reception failures caused not only by nearby interfering signals but also by distant interfering signals.

[0189] <The Fourth Configuration Example of the OVLD Avoidance Circuit 11>

[0190] FIG. 12 is a diagram showing the fourth configuration example of the OVLD avoidance circuit 11 in FIG. 1.

[0191] In the figure, parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate below.

[0192] In FIG. 12, the OVLD avoidance circuit 11 includes an RF amplifier 21, a mixer 22, a BPF 23, an IF amplifier 24, and a gain control unit 51.

[0193] Furthermore, in FIG. 12, the OVLD avoidance circuit 11 includes amplitude detection units 91 and 92, and an adder 93.

[0194] 6 in that it includes an RF amplifier 21, a mixer 22, a BPF 23, an IF amplifier 24, and a gain control section 51.

[0195] 6 in that the OVLD avoidance circuit 11 in FIG. 12 includes amplitude detectors 91 and 92 and an adder 93 instead of the amplitude detector 25.

[0196] 6, amplitude detection section 91 detects the IF signal output by mixer 22 (the signal immediately after being output by mixer 22), and outputs the level of the envelope of the IF signal as a detection voltage.

[0197] Similar to amplitude detector 25 in FIG. 10, amplitude detector 92 detects the RF signal output by RF amplifier 21 (the signal immediately after being output by RF amplifier 21), and outputs the level of the envelope of the RF signal as a detection voltage.

[0198] Here, the detection voltage obtained by detecting the IF signal output by the amplitude detection unit 91 is also referred to as the IF detection voltage, and the detection voltage obtained by detecting the RF signal output by the amplitude detection unit 92 is also referred to as the RF detection voltage.

[0199] The adder 93 adds the IF detection voltage output by the amplitude detection section 91 and the RF detection voltage output by the amplitude detection section 92 together, and supplies the added detection voltage (addition signal) that is the result of the addition to the gain control section 51.

[0200] Therefore, in the OVLD avoidance circuit 11 of FIG. 12, the gain of the RF amplifier 21 is controlled according to the result of comparison between the added detection voltage and the RFGC voltage.

[0201] In the receiving device 10, when the sensitivity to reception interference caused by nearby interference signals and distant interference signals is different, the reception interference caused by nearby interference signals and distant interference signals can be sufficiently reduced by controlling the gain of the RF amplifier 21 according to the comparison result between the added detection voltage and the RFGC voltage.

[0202] <The Fifth Configuration Example of the OVLD Avoidance Circuit 11>

[0203] FIG. 13 is a diagram showing the fifth configuration example of the OVLD avoidance circuit 11 in FIG. 1.

[0204] In the figure, parts corresponding to those in the case of FIG. 12 are denoted by the same reference numerals, and their descriptions will be omitted as appropriate below.

[0205] In FIG. 13, the OVLD avoidance circuit 11 includes a mixer 22, a BPF 23, an IF amplifier 24, a gain control unit 51, amplitude detection units 91 and 92, and an adder 93.

[0206] Furthermore, in FIG. 13, the OVLD avoidance circuit 11 includes RF amplifiers 111 and 112, a BPF 113, and an LPF 114.

[0207] <00​​​​​​​​​​​​​​​​The RF amplifiers 111 and 112 are RF amplifiers having the same gain control characteristics and control the gain in accordance with the same RFGC voltage, so that the RF signals output by the RF amplifiers 111 and 112 are (almost) the same RF signals.

[0212] The RF signal output from the RF amplifier 111 is supplied to the BPF 113 , and the RF signal output from the RF amplifier 112 is supplied to the amplitude detection unit 92 .

[0213] The BPF 113 filters the signal immediately after being output by the RF amplifier 111, that is, the RF signal output by the RF amplifier 111, and outputs an RF signal in a predetermined frequency band obtained as a result of the filtering.

[0214] The RF signal output from the BPF 113 is supplied to the mixer 22. The mixer 22 frequency-converts the RF signal from the BPF 113 into an IF signal and outputs the IF signal.

[0215] The IF signal output by the mixer 22 is supplied to the LPF 114. The LPF 114 filters the IF signal from the mixer 22 and outputs an IF signal in a predetermined low frequency band obtained as a result of the filtering.

[0216] The IF signal output from the LPF 114 is supplied to the BPF 23 and the amplitude detection unit 91.

[0217] Therefore, in FIG. 13, the amplitude detection section 91 detects the IF signal obtained by filtering the IF signal output by the mixer 22 with the LPF 114, and outputs the IF detection voltage obtained by this detection.

[0218] Furthermore, the amplitude detection section 92 detects the RF signal output by the RF amplifier 112, and outputs an RF detection voltage obtained by the detection.

[0219] Then, the gains of the RF amplifiers 111 and 112 are controlled according to the result of comparison between the RFGC voltage and the summed detection voltage obtained by adding the IF detection voltage and the RF detection voltage as described above.

[0220] In the OVLD avoidance circuit 11 of FIG. 13, a BPF 113 is provided that filters the signal immediately after being output by the RF amplifier 111, that is, the RF signal output by the RF amplifier 111, in order to improve reception quality.

[0221] BPF 113 is a BPF that has, for example, the frequency band of the desired signal as its passband. Therefore, if amplitude detection unit 92 detects the RF signal output by BPF 113, the RF detection voltage obtained by the detection will fluctuate depending on the frequency detuning of the interference signal included in the RF signal from the desired signal due to the influence of filtering by BPF 113.

[0222] FIG. 14 is a diagram showing an example of the frequency distribution of a desired signal and an interference signal.

[0223] In FIG. 14, the dotted line indicates the frequency characteristic of the BPF 113 (band selection filter characteristic).

[0224] The influence of filtering by the BPF 113 on nearby interfering signals (nearby interfering waves) having frequencies close to those of the desired signal is small.

[0225] On the other hand, for a distant interfering signal (distant interfering wave) whose frequency is far from that of the desired signal, the influence of filtering by the BPF 113 becomes greater as the detuned frequency of the distant interfering signal becomes greater.

[0226] That is, the level of the distant interfering signal indicated by the dotted arrow in the figure decreases as indicated by the solid arrow in the figure as the detuning frequency of the distant interfering signal increases.

[0227] Therefore, as shown in FIG. 13, in the OVLD avoidance circuit 11, an RF amplifier 112 having the same gain control characteristics as the RF amplifier 111 is provided, and instead of the RF signal output from the BPF 113, the RF signal output from the RF amplifier 112 is detected. Thereby, it is possible to prevent the RF detection voltage obtained by the detection from varying according to the offset frequency of the remote interference signal.

[0228] <The sixth configuration example of the OVLD avoidance circuit 11>

[0229] FIG. 15 is a diagram showing a sixth configuration example of the OVLD avoidance circuit 11 in FIG. 1.

[0230] In the figure, parts corresponding to those in FIG. 12 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate below.

[0231] In FIG. 15, the OVLD avoidance circuit 11 includes an RF amplifier 21, a mixer 22, a BPF 23, an IF amplifier 24, a gain control unit 51, amplitude detection units 91 and 92, and an adder 93.

[0232] Furthermore, in FIG. 15, the OVLD avoidance circuit 11 includes an ADC 121.

[0233] Therefore, the OVLD avoidance circuit 11 in FIG. 15 is common to the case of FIG. 12 in that it includes an RF amplifier 21, a mixer 22, a BPF 23, an IF amplifier 24, a gain control unit 51, amplitude detection units 91 and 92, and an adder 93.

[0234] However, the OVLD avoidance circuit 11 in FIG. 15 is different from the case of FIG. 12 in that an ADC 121 is newly provided.

[0235] The addition detection voltage is supplied from the adder 93 to the ADC 121.

[0236] The ADC 121 performs AD conversion of the addition detection voltage from the adder 93 into a digital signal and supplies it to the DTC generation unit 61.

[0237] In the DTC generation unit 61 (Fig. 7), after reset, when it first enters the attack state, the integrator 71 sets the value corresponding to the digital signal's addition detection voltage, which is the output of the ADC 121, as the initial value of the count value as a predicted value of the convergence value of the RFGC voltage (addition detection voltage).

[0238] For example, the integrator 71 obtains a value obtained by multiplying the addition detection voltage of the digital signal from the ADC 121 by a predetermined coefficient as a predicted value of the convergence value of the RFGC voltage, and sets that predicted value as the initial value of the count value.

[0239] Therefore, in Fig. 15, with the predicted value of the convergence value of the RFGC voltage as the initial value, the counting of the count value starts, so the convergence time until the RFGC voltage converges can be made shorter.

[0240] Note that the ADC 121 starts operating at reset and stops operating after the initial value of the count value is set. The ADC 121 then starts (restarts) operating when the OVLD avoidance circuit 11 is reset and enters the attack state.

[0241] <The Seventh Configuration Example of the OVLD Avoidance Circuit 11>

[0242] <0​​​​​​​​​​​​​​​​16 has the RF amplifier 21, mixer 22, BPF 23, IF amplifier 24, gain control section 51, amplitude detection sections 91 and 92, and adder 93 in common with the case of FIG.

[0247] However, the OVLD avoidance circuit 11 in FIG. 16 differs from that in FIG. 15 in that the ADC 121 is not provided and that a comparator 131 is newly provided.

[0248] The comparator 131 compares the RFGC voltage output by the DAC 62 with the added detection voltage that is the output of the adder 93, and outputs an H level or an L level that indicates the comparison result.

[0249] Here, the accumulator 71 constituting the DTC generating unit 61 (FIG. 7) stores a count value. Register (not shown) It has.

[0250] 16 has an SAR sequencer (not shown) that controls (the value of) the register of the accumulator 71 in accordance with the output of the comparator 131. The SAR sequencer and the register of the accumulator 71 form an SAR (successive approximation register).

[0251] In FIG. 16, the SAR configured in the DTC generating unit 61, the DAC 62, and the comparator 131 configure a successive approximation type ADC.

[0252] In such a successive approximation ADC, the summed detection voltage, which is the output of the adder 93 and is supplied to the comparator 131, is AD converted. In the successive approximation ADC, the result of the AD conversion, i.e., the digital summed detection voltage, is set in the register of the integrator 71.

[0253] In the DTC generating unit 61, as in the case of FIG. 15, the integrator 71 sets a value corresponding to the added detection voltage of the digital signal as the predicted value of the convergence value of the RFGC voltage to the initial value of the count value.

[0254] Therefore, in FIG. 16, as in FIG. 15, counting of the count value is started using the predicted value of the convergence value of the RFGC voltage as the initial value, so the convergence time until the RFGC voltage is converged can be made shorter.

[0255] Furthermore, in FIG. 16, a successive approximation type ADC is configured using the integrator 71 of the DTC generation unit 61 and the DAC 62, so the circuit can be simplified compared to when a single ADC 121 is provided, as in FIG. 15.

[0256] 16, the successive approximation type ADC starts operation at reset, and stops operation (as a successive approximation type ADC) after the initial value of the count value is set, similar to the ADC 121 in FIG. 15. Thereafter, the successive approximation type ADC starts operation when the OVLD avoidance circuit 11 is reset and enters an attack state.

[0257] FIG. 17 is a timing chart for explaining an example of the operation of the OVLD avoidance circuit 11 of FIGS.

[0258] 17, similarly to FIG. 9, shows the output of comparator 32 (comparator output), the integration polarity of integrator 71, the count value of integrator 71, the timer mode of timer 72, the timing signal output by timer 72, the detection voltage output by amplitude detection unit 25, the RFGC voltage output by DAC 62, the envelope of the IF signal output by mixer 22, and the envelope of the RF signal output by RF amplifier 21.

[0259] 17 further shows the timing at which the ADC 121 in FIG. 15 and the successive approximation ADC in FIG. 16 perform ADC operation (ADC operation on the detected voltage) to AD convert the detected voltage (added detected voltage).

[0260] The operation of the OVLD avoidance circuit 11 will be described below with reference to the OVLD avoidance circuit 11 in Fig. 15. The operation of the OVLD avoidance circuit 11 in Fig. 16 will be described with "ADC121" in the following description replaced with "successive approximation type ADC".

[0261] The OVLD avoidance circuit 11 is reset at the start of operation, and after the reset, when an attack state occurs, the ADC 121 starts AD conversion of the detection voltage (added detection voltage) from the adder 93.

[0262] Thereafter, the integrator 71 obtains a predicted value of the convergence value of the RFGC voltage from the output of the ADC 121, and sets the predicted value as the initial value of the count value.

[0263] The subsequent operations are the same as those in FIG. 9, and therefore will not be described further.

[0264] As described above, in the integrator 71, by setting the predicted value of the convergence value of the RFGC voltage as the initial value of the count value and starting to count the count value, the convergence time until the RFGC voltage converges can be shortened.

[0265] That is, by obtaining a predicted value of the convergence value of the RFGC voltage from the value obtained by AD converting the detection voltage, it is possible to obtain a predicted value that is relatively close to the true convergence value. Then, by setting such a predicted value as the initial value of the count value of the integrator 71, the RFGC voltage output by the DAC 62 that performs DA conversion of the count value becomes a voltage that is close to the true convergence value. As a result, the RFGC voltage converges in a shorter time than when the initial value of the count value is set without using the value obtained by AD converting the detection voltage.

[0266] Figure 17 shows examples of count values ​​when the initial value of the count value is set to the predicted convergence value of the RFGC voltage obtained using the value obtained by AD converting the detected voltage, and when the initial value of the count value is set without using the value obtained by AD converting the detected voltage.

[0267] In FIG. 17, when the initial value of the count value is set to the predicted convergence value of the RFGC voltage obtained using the value obtained by AD converting the detected voltage, the RFGC voltage converges at the second count.

[0268] On the other hand, in FIG. 17, when the initial value of the count value is set without using the value obtained by AD-converting the detection voltage, it takes 9 counts for the RFGC voltage to converge.

[0269] <The eighth configuration example of the OVLD avoidance circuit 11>

[0270] FIG. 18 is a diagram showing the eighth configuration example of the OVLD avoidance circuit 11 in FIG. 1.

[0271] In the figure, parts corresponding to the cases of FIG. 2, or FIGS. 6 and 8 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate below.

[0272] In FIG. 18, the OVLD avoidance circuit 11 includes an RF amplifier 21, a mixer 22, a BPF 23, an IF amplifier 24, an amplitude detection unit 25, a comparator 32, a DAC 62, an integrator 71, and a timer 72.

[0273] The OVLD avoidance circuit 11 further includes a DC power supply 33, a switch SW, a resistor R1, a capacitor C, and a resistor R2.

[0274] In addition, the OVLD avoidance circuit 11 has switches 151 and 152.

[0275] Therefore, the OVLD avoidance circuit 11 in FIG. 18 is common with the cases of FIGS. 6 and 8 in that it includes an RF amplifier 21, a mixer 22, a BPF 23, an IF amplifier 24, an amplitude detection unit 25, a comparator 32, a DAC 62, an integrator 71, and a timer 72.

[0276] Furthermore, the OVLD avoidance circuit 11 in FIG. 18 is common with the case of FIG. 2 in that it includes an RF amplifier 21, a mixer 22, a BPF 23, an IF amplifier 24, an amplitude detection unit 25, a comparator 32, a DC power supply 33, a switch SW, a resistor R1, a capacitor C, and a resistor R2.

[0277] However, the OVLD avoidance circuit 11 in FIG. 18 differs from those in FIG. 2, FIG. 6 and FIG. 8 in that switches 151 and 152 are newly provided.

[0278] The OVLD avoidance circuit 11 in FIG. 18 is configured to be able to selectively perform SW-type gain control and count-type gain control as the gain control of the RF amplifier 21.

[0279] The switch 151 selects one of the connection point between the capacitor C and the resistor R1 and the output terminal of the DAC 62, and connects the selected one to a gain control terminal for controlling the gain of the RF amplifier .

[0280] The switch 152 selects one of an on / off control terminal for controlling the on / off of the switch SW, the integrator 71 and the timer 72, and connects the selected one to the output terminal of the comparator 32.

[0281] The switches 151 and 152 operate in conjunction with each other in response to, for example, an external operation.

[0282] That is, when the switch 151 selects the connection point of the capacitor C and the resistor R1, the switch 152 selects the on / off control terminal of the switch SW.

[0283] Furthermore, when the switch 151 selects the output terminal of the DAC 62 , the switch 152 selects the integrator 71 and the timer 72 .

[0284] When the switch 151 selects the connection point of the capacitor C and the resistor R1 and the switch 152 selects the on / off control terminal of the switch SW, the OVLD avoidance circuit 11 is configured substantially the same as in FIG. 2 and performs SW type gain control.

[0285] That is, in this case, the voltage of the capacitor C is selected by the switch 151 as the RFGC voltage and is supplied to the RF amplifier 21.

[0286] On the other hand, when the switch 151 selects the output terminal of the DAC 62 and the switch 152 selects the accumulator 71 and the timer 72, the OVLD avoidance circuit 11 is configured substantially the same as in the cases of FIGS. 6 and 8, and performs count-type gain control.

[0287] That is, in this case, the output of the DAC 62 is selected by the switch 151 as the RFGC voltage and is provided to the RF amplifier 21 .

[0288] According to the OVLD avoidance circuit 11 of FIG. 18, it is possible to select an appropriate method from the SW method and the count method depending on the characteristics and use of the receiving device 10, and perform gain control of that method.

[0289] For example, if the receiving device 10 is a system that is highly sensitive to deterioration in reception quality due to stepwise changes in gain, the SW method may be able to maintain better reception quality than the count method.

[0290] Therefore, in the OVLD avoidance circuit 11 of Fig. 18, if the receiving device 10 is a system that is highly sensitive to reception quality degradation due to stepwise changes in gain, gain control can be performed using the SW method. On the other hand, if the receiving device 10 is not a system that is highly sensitive to reception quality degradation due to stepwise changes in gain, gain control can be performed using the count method.

[0291] Moreover, the OVLD avoidance circuit 11 in FIG. 18 has a circuit configuration in which the amplitude detection unit 25 and the comparator 32, which are blocks necessary for gain control, are shared between the SW method and the count method.

[0292] Therefore, the OVLD avoidance circuit 11 in FIG. 18 can be configured by adding a small number of circuits to the OVLD avoidance circuit 11 in FIG. 2 or FIG. 6 and FIG.

[0293] FIG. 19 is a diagram showing an example of a detection voltage and an RFGC voltage corresponding to an RF signal as a disturbance signal.

[0294] FIG. 19A shows the detection voltage corresponding to an intermittent interference signal and the RFGC voltage when gain control is performed by the SW method, and is the same as FIG. 5B.

[0295] When gain control is performed using the SW method, for an intermittent interference signal, the RFGC voltage has a sawtooth waveform and is unstable, as explained in FIG. 5B.

[0296] FIG. 19B shows the detection voltage corresponding to an intermittent interference signal and the RFGC voltage when gain control is performed using the counting method.

[0297] When gain control is performed using the counting method, for an intermittent interference signal, the RFGC voltage converges quickly during the period when the interference signal is present by setting the attack period Tattack to a short time.

[0298] Furthermore, by setting the recovery period Trecovery to a time that is sufficiently longer than the attack period Tattack, for example, a time that is approximately the same as the period when no interference signal is present, the RFGC voltage hardly drops during the period when no interference signal is present.

[0299] Therefore, for an intermittent interference signal, the RFGC voltage converges early in the initial period in which the interference signal is present and then becomes almost stable, thereby shortening the attack time and lengthening the recovery time.

[0300] As described above, in the counting method, the comparator 32 compares the signal (detection voltage of the RF signal and IF signal) output by the RF amplifier 21 with the count value (RFGC voltage obtained by DA conversion) output by the integrator 71, the integrator 71 counts the count value according to the output of the comparator 32, and the RF amplifier 21 controls the gain according to the count value (RFGC voltage obtained by DA conversion) and amplifies the RF signal, so that gain control can be performed appropriately for various interference signals without providing an external capacitor C and resistor R2.

[0301] For example, by setting the attack period Tattack, which is the timing for counting up the count value, to a short time, the RFGC voltage can be quickly (in a short time) converged, thereby shortening the attack time.

[0302] The attack time can be made shorter by setting the initial value of the count value to an appropriate initial value (for example, an empirically obtained predicted value of the convergence value of the RFGC voltage) depending on the circuit configuration of the OVLD avoidance circuit 11, etc.

[0303] 15 and 16, by predicting the convergence value of the RFGC voltage from the AD conversion result of the detection voltage, a highly accurate predicted convergence value is obtained and set as the initial value of the count value, thereby making it possible to extremely shorten the attack time. In other words, it is possible to stabilize the OVLD avoidance circuit 11 in an extremely short time.

[0304] By setting the recovery period Trecovery, which is the timing for counting down the count value, to a time that is sufficiently longer than the attack period Tattack, for example, it is possible to make the recovery time extremely long.

[0305] By increasing the recovery time, it is possible to suppress the drop in the RFGC voltage during periods when no intermittent interference signals are present, and to prevent the RFGC voltage from taking on a sawtooth waveform with a large amplitude, as shown in Figure 5B.

[0306] Therefore, it can handle interference signals (profiles) that the SW method cannot handle. In other words, for intermittent interference signals that are difficult to generate a stable RFGC voltage with the SW method, the fluctuations in the RFGC voltage are reduced, a stable RFGC voltage is generated, and stable reception is possible.

[0307] Furthermore, the counting method makes it possible to realize a robust OVLD avoidance circuit 11 that is not affected by variations in parts.

[0308] The OVLD avoidance circuit 11 can be configured by combining any of the first to eighth configuration examples with components of other configuration examples to the extent possible.

[0309] For example, the OVLD avoidance circuit 11 can be configured by combining the ADC 121 of the sixth configuration example in FIG. 15 with the eighth configuration example in FIG.

[0310] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present technology.

[0311] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0312] The present technology can have the following configurations.

[0313] <1> an amplifier that controls the gain according to the count value and amplifies the signal; a comparator that compares the signal output by the amplifier with the count value; an accumulator that counts the count value in response to an output of the comparator; A signal processing device comprising: <2> The accumulator counts up or down the count value depending on the output of the comparator. <1> The signal processing device according to claim 1. <3> The accumulator counts the count value at a first interval or at a second interval different from the first interval, depending on the output of the comparator. <1> or <2> The signal processing device according to claim 1. <4> further comprising a DAC that performs digital-to-analog conversion of the count value; The amplifier controls a gain in accordance with an output of the DAC; The comparator compares the signal output by the amplifier with the output of the DAC. <1> Or <3> 10. The signal processing device according to claim 9, <5> further comprising a mixer for converting the frequency of the signal output by the amplifier; The comparator compares the signal output by the mixer with the output of the DAC. <4> The signal processing device according to claim 1. <6> a scaler that scales the signal output by the mixer; The comparator compares the signal output by the scaler with the output of the DAC. <5> The signal processing device according to claim 1. <7> A state in which the signal output by the amplifier is larger than the output of the DAC is defined as an attack state, and a state in which the signal output by the amplifier is not larger than the output of the DAC is defined as a recovery state. The accumulator performs one of counting up and counting down the count value in the attack state and the other in the recovery state. <4> Or <6> 10. The signal processing device according to claim 9, <8> The accumulator counts the count value at a first interval in the attack state, and counts the count value at a second interval longer than the first interval in the recovery state. <7> The signal processing device according to claim 1. <9> The first interval and the second interval are configured to be externally settable. <8> The signal processing device according to claim 1. <10> The comparator compares the output of the DAC with an added signal obtained by adding the signal immediately after the amplifier outputs and the signal immediately after the mixer outputs. <5> or <6> The signal processing device according to claim 1. <11> A BPF that filters the signal immediately after the amplifier outputs; another amplifier having the same gain control characteristics as the amplifier, which controls the gain according to the output of the DAC and amplifies the signal; Furthermore, The comparator compares the output of the DAC with an added signal obtained by adding the signal output by the mixer and the signal output by the other amplifier. <5> The signal processing device according to claim 1. <12> further comprising an ADC that performs AD conversion of the signal output by the amplifier; The accumulator sets a value corresponding to the output of the ADC as the initial value of the count value. <4> Or <11> 10. The signal processing device according to claim 9, <13> The ADC is a successive approximation type ADC including the integrator, the DAC, and another comparator that compares the output of the DAC with the signal output by the amplifier. <12> The signal processing device according to claim 1. <14> a capacitor to which voltage application is turned on or off depending on the output of the comparator; a resistor connected in parallel with the capacitor; a switch for selecting the output of the DAC or the voltage of the capacitor and providing it to the amplifier as a gain control signal; Further equipped <4> Or <13> 10. The signal processing device according to claim 9, <15> an amplifier controlling a gain according to the count value and amplifying the signal; a comparator comparing the signal output by the amplifier with the count value; an accumulator counting the count value in response to an output of the comparator; A signal processing method comprising: <16> an amplifier that controls the gain according to the count value and amplifies the signal; a comparator that compares the signal output by the amplifier with the count value; an accumulator that counts the count value in response to an output of the comparator; a demodulation circuit that demodulates the signal output by the amplifier; A receiving device comprising: [Explanation of symbols]

[0314] 10 receiver, 11 OVLD avoidance circuit, 12 ADC, 13 demodulation circuit, 21 RF amplifier, 22 mixer, 23 BPF, 24 IF amplifier, 25 amplitude detection unit, 26 gain control unit, 31 peak hold unit, 32 comparator, 33 DC power supply, 51 gain control unit, 61 DTC generation unit, 62 DAC, 71 integrator, 72 timer, 81 amplitude scaler, 91, 92 amplitude detection unit, 93 adder, 111, 112 RF amplifier, 113 BPF, 114 LPF, 121 ADC, 131 comparator, 151, 152 switch

Claims

1. an amplifier that controls the gain according to the count value and amplifies the signal; a mixer that converts the frequency of the signal output by the amplifier; a comparator that compares the signal output by the mixer with the count value; an accumulator that counts the count value in response to an output of the comparator; A signal processing device comprising:

2. The accumulator counts up or down the count value depending on the output of the comparator. The signal processing device according to claim 1 .

3. The accumulator counts the count value at a first interval or at a second interval different from the first interval, depending on the output of the comparator.

3. The signal processing device according to claim 1 or 2.

4. The apparatus further comprises a timer that generates and outputs a timing signal of the first interval or the second interval according to the output of the comparator; The accumulator counts the count value in accordance with the timing signal output by the timer. The signal processing device according to claim 3 .

5. further comprising a DAC that performs digital-to-analog conversion of the count value; The amplifier controls a gain in accordance with an output of the DAC; The comparator compares the signal output by the amplifier with the output of the DAC.

5. A signal processing device according to claim 1.

6. a scaler that scales the signal output by the mixer; The comparator uses the signal output by the scaler as the signal output by the mixer, and compares the signal output by the scaler with the output of the DAC; The accumulator counts the count value in response to the output of the comparator, which compares the signal output by the scaler with the output of the DAC. The signal processing device according to claim 5 .

7. A state in which the signal output from the mixer is larger than the output from the DAC is defined as an attack state, and a state in which the signal output from the mixer is not larger than the output from the DAC is defined as a recovery state, The accumulator performs one of counting up and counting down the count value in the attack state and the other in the recovery state.

7. The signal processing device according to claim 5 or 6.

8. The accumulator counts the count value at a first interval in the attack state, and counts the count value at a second interval longer than the first interval in the recovery state. The signal processing device according to claim 7 .

9. The first interval and the second interval are configured to be externally settable. The signal processing device according to claim 8 .

10. the comparator outputs a sum signal obtained by adding the signal immediately after the amplifier has output and the signal immediately after the mixer has output, and compares the sum signal with the output of the DAC; The integrator counts the count value in response to the output of the comparator, which compares the sum signal with the output of the DAC.

7. The signal processing device according to claim 5 or 6.

11. A BPF that filters the signal immediately after the amplifier outputs; another amplifier having the same gain control characteristics as the amplifier, which controls the gain according to the output of the DAC and amplifies the signal; Furthermore, the mixer performs frequency conversion of the signal output from the BPF; The comparator outputs a sum signal obtained by adding the signal output by the BPF and the signal output by the other amplifier as a signal output by the mixer, and compares the sum signal with the output of the DAC; The integrator counts the count value in response to the output of the comparator, which compares the sum signal with the output of the DAC. The signal processing device according to claim 5 .

12. further comprising an ADC that performs AD conversion of the signal output by the amplifier; The accumulator sets a value corresponding to the result of AD conversion by the ADC as the initial value of the count value.

12. A signal processing device according to claim 5.

13. the ADC is a successive approximation type ADC including the integrator, the DAC, and another comparator that compares the output of the DAC with the signal output by the amplifier, In the successive approximation type ADC, the result of AD conversion is stored in the accumulator. The signal processing device according to claim 12.

14. a capacitor to which application of a power supply voltage is turned on or off in accordance with an output of the comparator; a resistor connected in parallel with the capacitor; a switch for selecting the output of the DAC or the voltage of the capacitor and providing it to the amplifier as a gain control signal; Further equipped 14. A signal processing device according to claim 5.

15. an amplifier controlling a gain according to the count value and amplifying the signal; a mixer for converting the frequency of the signal output by the amplifier; a comparator comparing the signal output by the mixer with the count value; an accumulator counting the count value in response to an output of the comparator; A signal processing method comprising:

16. an amplifier that controls the gain according to the count value and amplifies the signal; a mixer that converts the frequency of the signal output by the amplifier; a comparator that compares the signal output by the mixer with the count value; an accumulator that counts the count value in response to an output of the comparator; a demodulation circuit that demodulates the signal output by the amplifier; A receiving device comprising:

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