DEVICE AND METHOD FOR MULTILINK WIRELESS TRANSMISSION - Patent application

Abstract

To provide a device and method for reducing latency in a wireless network.SOLUTION: A first entity 100 is configured to: transmit a first indication 101 to a second entity 200, the first indication indicating a first set of packets transmitted from the first entity to a first link receiver 110; and transmit a first transmit status indication 102 to the second entity, the first transmit status indication indicating which packets of the first set of packets were successfully received by the first link receiver, or indicating which packets of the first set of packets were not received by the first link receiver. Each packet indicated in the first indication and the first transmit status indication is associated with a global multi-link sequence number.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates generally to wireless communications, and more particularly to multi-link aggregation in wireless transmissions. The present disclosure proposes devices and methods for low latency and tight delay wireless transmissions. [Background technology]

[0002] The IEEE 802.11 standard / protocol family, or 802.11 for short, specifies a set of medium access control (MAC) layer protocols and physical layer (PHY) protocols for implementing wireless local area network (WLAN) Wi-Fi computer communications at various frequencies.

[0003] The 802.11 protocol family uses Carrier Sense Multiple Access with Collision Avoidance (CSMA / CA). CSMA is a MAC protocol in which nodes verify the absence of other traffic before transmitting on a shared transmission medium, such as an electrical bus or a band in the electromagnetic spectrum. CSMA / CA in computer networking is a network multiple access method in which carrier sensing is used, but nodes attempt to avoid collisions by beginning transmission only after the channel is sensed to be "idle." Wi-Fi transmissions based on CSMA / CA include random backoff, so transmit opportunity (TxOP) timing cannot be guaranteed.

[0004] IEEE 802.11e, 802.11e or 11e for short, introduces Enhanced Distributed Channel Access (EDCA) with four access categories, each differing from the others by a random backoff window, which provides statistically higher priority for low-latency traffic over other traffic.

[0005] A typical residential Wi-Fi environment contains several access points (APs) sharing the same channel. However, overlapping basic service set (OBSS) transmissions are not coordinated and there is no protocol for cooperation between APs. Therefore, latency cannot be bounded or guaranteed.

[0006] It has been proposed to implement multi-link devices that operate on two different channels in parallel. However, one of the biggest challenges in such multi-link implementations is how to mitigate the simultaneous transmit-receive (STR) problem between two different channels on the same Wi-Fi chip. Summary of the Invention [Means for solving the problem]

[0007] Considering the above limitations, embodiments of the present disclosure aim to introduce a solution for mitigating OBSS time division interference. In particular, one objective is to optimize air capture opportunities. One objective is to achieve lower latency in wireless transmissions.

[0008] This object is achieved by the embodiments provided in the attached independent claims, advantageous implementations of which are further defined in the dependent claims.

[0009] Embodiments of the present disclosure provide a software-based approach for STR multi-link implementation. In particular, software-based low-latency messages (e.g., a first indication and a first transmission status indication) are exchanged between a first entity and a second entity to keep all links of the multi-link implementation synchronized.

[0010] A first aspect of the present disclosure provides a first entity for multilink implementation in a wireless network, the first entity being configured to: send a first indication to a second entity, the first indication indicating a first set of packets transmitted from the first entity to a first link receiver; and send a first transmission status indication to the second entity, the first transmission status indication indicating which packets of the first set of packets were successfully received by the first link receiver and / or which packets of the first set of packets were not received by the first link receiver, wherein each packet indicated in the first indication and the first transmission status indication is associated with a global multilink sequence number.

[0011] In one implementation of the first aspect, the first entity is further configured to: obtain a sequence of packets to be transmitted to the first link receiver, each packet being associated with a global multilink sequence number; maintain a first transmission queue of the sequence of packets; and transmit the packets in the first transmission queue to the first link receiver.

[0012] Global multilink sequence numbers are designed to identify packets in a multilink implementation. In particular, a sequence of packets that needs to be transmitted on different links / channels of a multilink is identical. Each global multilink sequence number identifies the same packet in different links. That is, identical packets in different links share the same global multilink sequence number. In particular, global multilink sequence numbers are different from conventional sequence numbers in wireless transmissions. In particular, a global multilink sequence number can be set for each packet before the first entity acquires the packet.

[0013] In one implementation of the first aspect, the first entity is further configured to: transmit a first set of packets to a first link receiver, the first set of packets being included in a sequence of packets; receive a first block acknowledgement (BA) from the first link receiver, the first BA indicating which packets of the first set of packets were successfully received by the first link receiver and / or which packets of the first set of packets were not received by the first link receiver; and generate a first transmission status indication based on the first BA and a global multilink sequence number associated with the packets indicated in the first BA.

[0014] In response to receiving the packet, the receiver, e.g., the first link receiver, may transmit an acknowledgement message to the transmitter, e.g., the first entity. In this embodiment, the first link receiver may transmit a BA (to acknowledge multiple packets together using a single frame) to the first entity. In response, the first entity may generate a first transmission status indication by appending a global multilink sequence number to the packet indicated by the first BA. In particular, the BA may indicate the packet by indicating the packet's Wi-Fi sequence number.

[0015] In one implementation of the first aspect, each packet of the first packet set includes a radio sequence number, and the first BA indicates which packets of the first packet set were successfully received by the first link receiver and / or which packets of the first packet set were not received by the first link receiver by indicating the radio sequence number of each packet.

[0016] Typically, each packet in a wireless transmission includes a sequence number field that indicates the sequence number of the packet, which the BA can use to indicate received or missing packets.

[0017] In one implementation of the first aspect, the first entity is further configured to receive a second instruction from the second entity, the second instruction indicating a second set of packets transmitted from the second entity to the second link receiver, each packet indicated in the second instruction being associated with a global multilink sequence number, the second set of packets being included in a sequence of packets, and in response to the second instruction, move the second set of packets from the first transmit queue to a first hold queue, and the packets in the first hold queue are put on hold.

[0018] The link between the second entity and the second link receiver is another link of multiple channels / radios in a multi-link implementation. The second set of packets is included in a sequence of packets, i.e., the second set of packets indicated by the second entity is also in the first transmit queue of the first entity. To avoid sending redundant packets, when a set of packets is sent on one link, the other link(s) are notified and move this set of packets out of their transmit queues and into a hold queue accordingly.

[0019] In one implementation of the first aspect, the first entity is further configured to receive a second transmission status indication from the second entity, the second transmission status indication indicating which packets of the second set of packets were successfully received by the second link receiver and / or which packets of the second set of packets were not received by the second link receiver, and in response to the second transmission status indication, release the packets successfully received by the second link receiver from the first holding queue and / or return the packets not received by the second link receiver to the head of the first transmission queue.

[0020] For packets that are successfully received by a receiver, e.g., a second link receiver, there is no need for the first entity to transmit these packets again. Therefore, these packets can be released from the first holding queue. In particular, missing packets or packets that cannot be successfully decoded by the receiver need to be retransmitted. Therefore, these packets can be returned to the first transmission queue. Preferably, these packets can be transmitted in the next TxOP.

[0021] In one implementation of the first aspect, the first entity is implemented in a first chipset, and the second entity is implemented in a second chipset different from the first chipset.

[0022] As mentioned above, implementing STR Multilink on the same chipset is a major challenge.

[0023] Thus, this embodiment proposes an alternative implementation that is done at the software level. This solution is based on current multi-band products, which include external on-board high radio frequency (RF) isolation between the two radios, but each radio uses an independent chipset and RF chain.

[0024] In an implementation of the first aspect, the first chipset and the second chipset are located on the same wireless device.

[0025] For example, a Wi-Fi device may have two Wi-Fi chips connected to the same host (e.g., via PCIe), or the first and second chipsets may be located on two wireless devices.

[0026] In one implementation of the first aspect, the first chipset and the second chipset are located on different wireless devices and communicate with each other via a wired or wireless network backhaul connection.

[0027] If the two wireless chipsets are not located on the same device, there may be a network backhaul connection between the two wireless chipsets, which may be wired or wireless.

[0028] In one implementation of the first aspect, the first chipset operates at a different frequency than the second chipset.

[0029] Preferably, one of the two chipsets may operate at a higher frequency (e.g., 5 GHz high band) and the other chipset operates at a lower frequency (e.g., 5 GHz low band), which can achieve better RF isolation.

[0030] A second aspect of the present disclosure provides a second entity for multilink implementation in a wireless network, the second entity being configured to: receive a first indication from a first entity, the first indication indicating a first set of packets transmitted from the first entity to a first link receiver; receive a first transmission status indication from the first entity, the first transmission status indication indicating which packets of the first set of packets were successfully received by the first link receiver and / or which packets of the first set of packets were not received by the first link receiver; and each packet indicated in the first indication and the first transmission status indication is associated with a global multilink sequence number.

[0031] As mentioned above, embodiments of the present disclosure propose exchanging software-based low-latency messages (e.g., a first indication and a first transmission status indication) between a first entity and a second entity to keep all links of a multilink implementation synchronized. In addition, a global multilink sequence number is designed to identify packets in a multilink implementation.

[0032] In one implementation of the second aspect, the second entity is further configured to: obtain a sequence of packets that need to be transmitted to the second link receiver, each packet being associated with a global multilink sequence number; maintain a second transmission queue of the sequence of packets; and transmit the packets in the second transmission queue to the second link receiver.

[0033] In particular, a global multilink sequence number may be set in each packet before the second entity obtains the packet.

[0034] In one implementation of the second aspect, the first set of packets is included in a sequence of packets, and the second entity is further configured to, in response to the first instruction, move the first set of packets from the second transmit queue to a second hold queue, and the packets in the second hold queue are put on hold.

[0035] That is, the first set of packets indicated by the first entity is also in a second transmit queue of the second entity. When the set of packets is transmitted on one link (as indicated by the first indication), the other(s) link(s) (i.e., the second entity) is informed and accordingly moves this set of packets (i.e., the first set of packets) out of its transmit queue, in order to avoid transmitting redundant packets.

[0036] In one implementation of the second aspect, in response to the first transmission status indication, the second entity is further configured to release packets that were successfully received by the first link receiver from the second holding queue and / or return packets that were not received by the first link receiver to the head of the second transmission queue.

[0037] In some cases, over-the-air packet errors may occur during reception, so packets that were not received may be returned to the transmit queue to await retransmission, and preferably these packets may be transmitted in the next TxOP.

[0038] In one implementation of the second aspect, the second entity is further configured to: transmit a second set of packets to a second link receiver, the second set of packets being included in a sequence of packets; receive a second BA from the second link receiver, the second BA indicating which packets of the second set of packets were successfully received by the second link receiver and / or which packets of the second set of packets were not received by the second link receiver; and generate a second transmission status indication based on the second BA and a global multilink sequence number associated with the packets indicated in the second BA.

[0039] In particular, the link between the second entity and the second link receiver is another link of multiple channels / radios in a multilink implementation. When the second entity transmits a second set of packets, the first entity needs to be informed accordingly. Optionally, the second entity may generate a second transmission status indication by appending a global multilink sequence number to packets indicated by the second BA. This synchronization message (i.e., the second transmission status indication) is used to inform the first entity as to which packets were successfully transmitted and which packets should be retransmitted.

[0040] In one implementation of the second aspect, each packet of the second packet set includes a radio sequence number, and the second BA indicates which packets of the second packet set were successfully received by the second link receiver and / or which packets of the second packet set were not received by the second link receiver by indicating the radio sequence number of each packet.

[0041] Typically, each packet in a wireless transmission includes a sequence number field that indicates the sequence number of the packet. The second BA can use the sequence number to indicate received or missing packets.

[0042] In one implementation of the second aspect, the second entity is further configured to: send a second indication to the first entity, the second indication indicating a second set of packets transmitted from the second entity to the second link receiver; and send a second transmission status indication to the first entity, the second transmission status indication indicating which packets of the second set of packets were successfully received by the second link receiver and / or which packets of the second set of packets were not received by the second link receiver.

[0043] Optionally, the second set of packets may also be in a first transmit queue of the first entity. To avoid transmitting redundant packets, when a set of packets (e.g., the second set of packets transmitted from the second entity) is transmitted on one link, the other(s) link(s) (e.g., the first entity) are notified.

[0044] A third aspect of the present disclosure provides a wireless transmission device, particularly an access point in a wireless network, the wireless transmission device comprising: at least one first entity according to the first aspect or any implementation form of the first aspect; and at least one second entity according to the second aspect or any implementation form of the second aspect; the wireless transmission device is configured to: obtain an original sequence of packets; generate a sequence of packets by appending a global multilink sequence number to each packet of the original sequence of packets; replicate the sequence of packets; and provide the sequence of packets to each of the at least one first entity and the at least one second entity.

[0045] A multi-link implementation may include multiple links. An embodiment of the present disclosure proposes a wireless transmission device with at least two chipsets. In particular, when a packet is transmitted on one channel, traffic information is synchronized across all channels. In this way, the wireless transmission device optimizes the air capture opportunities of all chipsets. Furthermore, latency can be dramatically reduced.

[0046] An implementation form of the wireless transmitting device of the third aspect may correspond to the implementation form of the first entity of the first aspect and the implementation form of the second entity of the second aspect described above. The wireless transmitting device of the third aspect and its implementation form achieves the same advantages and effects as those described above for the first entity of the first aspect and its implementation form, and the second entity of the second aspect and its implementation form.

[0047] A fourth aspect of the present disclosure provides a wireless receiving device, particularly a station in a wireless network, the wireless receiving device comprising at least one first link receiver and at least one second link receiver, wherein the at least one first link receiver is configured to receive packets from at least one first entity according to the first aspect and any implementation form of the first aspect, and the at least one second link receiver is configured to receive packets from at least one second entity according to the second aspect and any implementation form of the second aspect, and the wireless receiving device is configured to obtain a received stream by combining packets received by the at least one first link receiver and packets received by the at least one second link receiver.

[0048] Therefore, the embodiment of the present disclosure further proposes a wireless receiving device including at least two link receivers. The wireless receiving device combines all links received by all link receivers into a signal receiving stream, and each receiver receives packets from a corresponding chipset. In particular, the wireless receiving device can further transmit the combined stream to a device in a next layer in sequence.

[0049] An implementation form of the wireless receiving device of the fourth aspect may correspond to the implementation form of the first entity of the first aspect described above and the implementation form of the second entity of the second aspect described above. The wireless receiving device of the fourth aspect and its implementation form achieves the same advantages and effects as those described above for the first entity of the first aspect and its implementation form, and the second entity of the second aspect and its implementation form.

[0050] A fifth aspect of the present disclosure provides a method, performed by a first entity, for multilink implementation in a wireless network, the method including: sending a first indication to a second entity, the first indication indicating a first set of packets transmitted from the first entity to a first link receiver; and sending a first transmission status indication to the second entity, the first transmission status indication indicating which packets of the first set of packets were successfully received by the first link receiver and / or which packets of the first set of packets were not received by the first link receiver, wherein each packet indicated in the first indication and the first transmission status indication is associated with a global multilink sequence number.

[0051] An implementation of the method of the fifth aspect may correspond to the implementation of the first entity of the first aspect described above. The method of the fifth aspect and its implementation achieves the same advantages and effects as those described above for the first entity of the first aspect and its implementation.

[0052] A sixth aspect of the present disclosure provides a method, performed by a second entity, for multilink implementation in a wireless network, the method including: receiving a first indication from a first entity, the first indication indicating a first set of packets transmitted from the first entity to a first link receiver; and receiving a first transmission status indication from the first entity, the first transmission status indication indicating which packets of the first set of packets were successfully received by the first link receiver and / or which packets of the first set of packets were not received by the first link receiver, wherein each packet indicated in the first indication and the first transmission status indication is associated with a global multilink sequence number.

[0053] An implementation of the method of the sixth aspect may correspond to the implementation of the second entity of the second aspect described above. The method of the sixth aspect and its implementations achieve the same advantages and effects as those described above for the second entity of the second aspect and its implementations.

[0054] A seventh aspect of the present disclosure provides a computer program product comprising program code for, when implemented on a processor, performing a method according to the fifth aspect and any implementation of the fifth aspect, or the sixth aspect and any implementation of the sixth aspect.

[0055] It should be noted that all devices, elements, units, and means described in this application can be implemented with software elements or hardware elements, or any kind of combination thereof. All steps performed by various entities described in this application, and functions described as being performed by various entities, are intended to mean that the respective entities are adapted or configured to perform the respective steps and functions. Even if, in the following description of specific embodiments, a specific function or step to be performed by an external entity is not reflected in the description of the specific detailed element of the entity that performs the specific step or function, it should be apparent to those skilled in the art that these methods and functions can be implemented with respective software elements or hardware elements, or any kind of combination thereof.

[0056] The above aspects and implementations of the present disclosure are explained in the following description of specific embodiments in connection with the accompanying drawings. [Brief explanation of the drawings]

[0057] [Figure 1] 1 illustrates a first entity according to one embodiment of the present disclosure. [Figure 2] 1 illustrates a second entity according to an embodiment of the present disclosure. [Figure 3] 1 illustrates a multi-link implementation according to one embodiment of the present disclosure. [Figure 4] 1 illustrates a multi-link implementation according to one embodiment of the present disclosure. [Figure 5] FIG. 1 illustrates a block diagram of a multi-link implementation according to one embodiment of the present disclosure. [Figure 6] FIG. 1 illustrates a high-level flow diagram according to one embodiment of the present disclosure. [Figure 7] 1 illustrates delay modeling according to one embodiment of the present disclosure. [Figure 8]1 illustrates a topology of a network simulator (NS-3) according to one embodiment of the present disclosure. [Figure 9] 1 illustrates simulation results according to one embodiment of the present disclosure. [Figure 10] 1 illustrates a method according to one embodiment of the present disclosure. [Figure 11] 1 illustrates a method according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0058] Exemplary embodiments of methods, devices, and program products for efficient packet transmission in a communication system are described with reference to the figures. While this description provides detailed examples of possible implementations, it should be noted that these details are intended to be illustrative and not limiting of the scope of the present application in any way.

[0059] Furthermore, embodiments / examples may refer to other embodiments / examples, for example, any description, including but not limited to, terms, elements, processes, descriptions and / or technical advantages, referred to in one embodiment / example may be applicable to the other embodiments / examples.

[0060] Multilink / Multi-Radio MAC (MRM) addresses OBSS time-division interference on the same primary channel (e.g., 20 / 40 / 80 / 160 / 320 MHz). By using at least one additional channel in parallel, an AP can transmit to a station while the first channel is occupied by an uplink from the OBSS or its own BSS. Similarly, the AP transmits on a first channel while the other channel is occupied by an uplink from the OBSS / its own BSS. In this way, the AP optimizes air capture opportunities and dramatically reduces latency in wireless transmissions.

[0061] Known solutions propose hardware-based STR techniques implemented at the baseband level. However, implementing a multi-link (or multi-radio) baseband within a single die (chip) faces significant technical implementation challenges for STR. In such a flow while one radio is in receive (Rx), the transmit (Tx) signal of the other radio may be captured by the first radio's receiver, leading to Rx errors. To overcome such Rx errors, high isolation between the radios is required. In addition to the technical implementation challenges of such isolation, high isolation also leads to additional costs that most vendors want to avoid. Therefore, implementing STR multi-link on the same chipset is a significant challenge.

[0062] The embodiments of the present disclosure propose an alternative implementation that takes place at the software level. This software-based multi-link can be implemented based on current multi-band products that include external on-board high-frequency radio frequency (RF) isolation between the two radios. Each radio uses an independent chipset and RF chain. For example, a simultaneous multi-radio device including 2*5 GHz operating in "STR" mode can be used.

[0063] FIG. 1 illustrates a first entity 100 according to one embodiment of the present disclosure. The first entity 100 may include a processing circuit (not shown) configured to perform, implement, or initiate various operations of the first entity 100 described herein. The processing circuit may include hardware and software. The hardware may include analog or digital circuits, or both analog and digital circuits. The digital circuit may include components such as an application-specific integrated circuit (ASIC), a field-programmable array (FPGA), a digital signal processor (DSP), or a general-purpose processor. The first entity 100 may further include a memory circuit that stores one or more instructions that can be executed by a processor or processing circuit, particularly under software control. For example, the memory circuit may include a non-transitory storage medium that stores executable software code that, when executed by the processor or processing circuit, causes various operations of the first entity 100 to be performed. In one embodiment, the processing circuit includes one or more processors and a non-transitory memory coupled to the one or more processors. The non-transitory memory may carry executable program code that, when executed by one or more processors, causes the first entity 100 to perform, implement, or initiate the operations or methods described herein.

[0064] In particular, a first entity 100 is designed for multilink implementation in a wireless network. The first entity 100 is configured to send a first indication 101 to a second entity 200. The second entity 200 is also designed for multilink implementation in a wireless network. In particular, the first indication 101 indicates a first set of packets to be transmitted from the first entity 100 to a first link receiver 110 in the wireless network. The first entity 100 is further configured to send a first transmission status indication 102 to the second entity 200, the first transmission status indication 200 indicating which packets of the first set of packets were successfully received by the first link receiver 110 and / or which packets of the first set of packets were not received by the first link receiver 110. In particular, each packet indicated in the first indication 101 and the first transmission status indication 102 is associated with a global multilink sequence number.

[0065] To address the aforementioned challenges, embodiments of the present disclosure provide a software-based approach for STR multilink to achieve lower latency. In particular, software-based low-latency messages (e.g., first indication 101 and first transmission status indication 102) are exchanged between the first entity 100 and the second entity 200 to keep all links of the multilink implementation synchronized.

[0066] The present disclosure designs a new layer to manage link traffic to multiple independent MAC / PHYs (i.e., multiple entities, such as the first entity 100 and the second entity 200). Exchanged messages enable synchronization between the MAC queues of the multiple entities. In particular, when a set of packets is transmitted on one link (e.g., the link between the first entity 100 and the first link receiver 110), the other(s) link(s) (e.g., the second entity 200) are informed. These messages (e.g., the first indication 101 and the first transmission status indication 102) enable the second entity 200 to avoid transmitting redundant packets.

[0067] In particular, the global multilink sequence number is designed to identify packets in the multilink and is independent of the Wi-Fi Tx sequence number, and may be set for each packet before the first entity 100 obtains the packet.

[0068] Optionally, according to one embodiment of the present disclosure, the first entity 100 may be configured to obtain a sequence of packets to be transmitted to the first link receiver 110, each packet being associated with a global multilink sequence number. The first entity 100 may be further configured to maintain a first transmit queue of the sequence of packets, and to transmit the packets in the first transmit queue to the first link receiver 110. In particular, the link between the first entity 100 and the first link receiver 110 is one of multiple channels / radios in a multilink implementation.

[0069] In a multilink implementation, the first entity 100 may obtain a packet to be transmitted from a host device. In particular, the host device may duplicate the packet to be transmitted and provide a copy to the first entity 100. In particular, packets to be transmitted on different links / channels of the multilink are identical to each other. That is, the host device may provide other copies of the packet to be transmitted to transmitters of other links, such as the second entity 200. Each global multilink sequence number identifies the same packet in different links. That is, identical packets in different links (e.g., the link between the first entity 100 and the first link receiver 110, or the link between the second entity 200 and the second link receiver 210) share the same global multilink sequence number.

[0070] According to one embodiment of the present disclosure, after obtaining the sequence of packets, the first entity 100 may be further configured to transmit a first set of packets to the first link receiver 110. The first set of packets is included in the sequence of packets. Typically, in response to receiving the first set of packets, the first link receiver 110 may transmit an acknowledgement message, in particular a BA (for acknowledging multiple packets together using a single frame), to the first entity 100. Thus, the first entity 100 may be configured to receive a first BA from the first link receiver 110, the first BA indicating which packets of the first set of packets were successfully received by the first link receiver 110 and / or which packets of the first set of packets were not received by the first link receiver 110.

[0071] Note that in a wireless transmission, each packet includes a sequence number field indicating the sequence number of the packet. Typically, a BA may indicate received or missing packets using the sequence number. Thus, according to one embodiment of the present disclosure, each packet of the first packet set may include a wireless sequence number, and the first BA indicates which packets of the first packet set were successfully received by the first link receiver 110 and / or which packets of the first packet set were not received by the first link receiver 110 by indicating the wireless sequence number of each packet.

[0072] Optionally, the first entity 100 may be further configured to generate the first transmission status indication 102 based on the first BA and a global multilink sequence number associated with the packet indicated by the first BA. That is, the global multilink sequence number is built on top of the over-the-air sequence number. For example, a host device providing the sequence of packets to the first entity 100 may append the global multilink sequence number to each packet during the aforementioned duplication process.

[0073] The global multilink sequence number is different from the radio sequence number. This disclosure proposes a solution where each radio link operates independently. Each link manages its own radio sequence number. Therefore, a new higher-level sequence number, the global multilink sequence number, is provided to synchronize the transmission status of the same packet in different links.

[0074] Furthermore, according to one embodiment of the present disclosure, the first entity 100 may be further configured to receive a second indication from the second entity 200. The second indication may indicate a second set of packets transmitted from the second entity 200 to the second link receiver 210. It should be understood that the link between the second entity 200 and the second link receiver 210 may be other links of multiple channels / radios in a multilink implementation. Similar to the previous embodiment, each packet indicated in the second indication may also be associated with a global multilink sequence number.

[0075] According to this embodiment, the second set of packets is included in the sequence of packets. That is, the second set of packets indicated by the second entity is also in the first transmit queue of the first entity 100. The first entity 100 may be further configured to, in response to the second instruction, move the second set of packets from the first transmit queue to the first pending queue, and the packets in the first pending queue are put on hold. Generally speaking, packets in the transmit queue of the transmitter are transmitted sequentially to the receiver. According to an embodiment of the present disclosure, when the set of packets is transmitted on one link, the other link(s) are informed and accordingly move the set of packets out of their transmit queues to avoid transmitting redundant packets.

[0076] In particular, packet errors may occur during transmission. Failed packets (packets that cannot be successfully decoded by the receiver) need to be retransmitted. According to an embodiment of the present disclosure, the first entity 100 may be further configured to receive a second transmission status indication from the second entity 200, the second transmission status indication indicating which packets of the second set of packets were successfully received by the second link receiver 210 and / or which packets of the second set of packets were not received by the second link receiver 210.

[0077] For packets that are successfully received by a receiver, for example, the second link receiver 210, the first entity 100 does not need to transmit these packets. Optionally, the first entity 100 may be further configured to release the packets that are successfully received by the second link receiver 210 from the first pending queue in response to the second transmission status indication. On the other hand, packets that are not received by the receiver need to be retransmitted. Optionally, the first entity 100 may be further configured to return the packets that are not received by the second link receiver 210 to the head of the first transmission queue. Preferably, these packets may be transmitted in the next TxOP.

[0078] FIG. 2 illustrates a second entity 200 according to one embodiment of the present disclosure. The second entity 200 may include a processing circuit (not shown) configured to perform, implement, or initiate various operations of the second entity 200 described herein. The processing circuit may include hardware and software. The hardware may include analog or digital circuits, or both analog and digital circuits. The digital circuit may include components such as an application-specific integrated circuit (ASIC), a field-programmable array (FPGA), a digital signal processor (DSP), or a general-purpose processor. The second entity 200 may further include a memory circuit that stores one or more instructions that can be executed by a processor or processing circuit, particularly under software control. For example, the memory circuit may include a non-transitory storage medium that stores executable software code that, when executed by the processor or processing circuit, causes the second entity 200 to perform various operations. In one embodiment, the processing circuit includes one or more processors and a non-transitory memory coupled to the one or more processors. The non-transitory memory may carry executable program code that, when executed by one or more processors, causes the second entity 200 to perform, implement, or initiate the operations or methods described herein.

[0079] In particular, the second entity 200 shown in Fig. 2 is designed for multilink implementation in a wireless network. The second entity 200 is configured to receive a first indication 101 from the first entity 100. The first entity 100 shown in Fig. 2 may be the first entity shown in Fig. 1. In particular, the first indication 101 indicates a first set of packets transmitted from the first entity 100 to the first link receiver 110. The second entity 200 is further configured to receive a first transmission status indication 102 from the first entity 100, the first transmission status indication 101 indicating which packets of the first set of packets were successfully received by the first link receiver 110 and / or which packets of the first set of packets were not received by the first link receiver 110. In particular, each packet indicated in the first indication 101 and the first transmission status indication 102 is associated with a global multilink sequence number.

[0080] According to one embodiment of the present disclosure, the second entity 200 may be further configured to obtain a sequence of packets that need to be transmitted to the second link receiver 210, each packet being associated with a global multilink sequence number, maintain a second transmission queue of the sequence of packets, and transmit the packets in the second transmission queue to the second link receiver 210.

[0081] As discussed in the previous embodiment, the host device may duplicate the packet to be transmitted and provide a copy to the first entity 100. Because the second entity needs to transmit the same packet, the host device may also provide a copy of the packet to be transmitted to the second entity 200.

[0082] Using knowledge of the packets to be transmitted, i.e., the sequence of packets, and knowledge of the first set of packets indicated in the first instruction 101, the second entity 200 may be further configured to move the first set of packets from the second transmit queue to a second hold queue. In particular, the first set of packets is included in the sequence of packets. Since the first set of packets was transmitted (by the first entity 100) on one link, the second entity 200 needs to hold the first set of packets to avoid transmitting redundant packets.

[0083] For packets of the first packet set that are successfully received by a receiver, e.g., the first link receiver 110, there is no need for the second entity to transmit these packets again. Therefore, these packets may be released from the second pending queue. In particular, packets that cannot be successfully decoded by the receiver need to be retransmitted. Therefore, the second entity 200 may return these packets to the second transmit queue. Preferably, these packets may be transmitted in the next TxOP.

[0084] Optionally, according to an embodiment of the present disclosure, in response to the first transmission status indication 102, the second entity 200 may be further configured to release packets that were successfully received by the first link receiver 110 from the second holding queue. Optionally, the second entity 200 may be further configured to return packets that were not received by the first link receiver 110 to the head of the second transmission queue.

[0085] Further, according to one embodiment of the present disclosure, the second entity 200 may be configured to transmit a second set of packets to the second link receiver 210. In particular, the second set of packets is included in a sequence of packets. In response, the second entity 200 may be further configured to receive a second BA from the second link receiver 210, the second BA indicating which packets of the second set of packets were successfully received by the second link receiver 210 and / or which packets of the second set of packets were not received by the second link receiver 210. To inform the first entity 100 about a transmission status on the link between the second entity 200 and the second link receiver 210, a second transmission status indication may be generated by the second entity 200 based on the second BA and a global multilink sequence number associated with the packets indicated in the second BA.

[0086] It should be understood that each packet of the second packet set includes a radio sequence number, and the second BA indicates which packets of the second packet set were successfully received by the second link receiver 210 and / or which packets of the second packet set were not received by the second link receiver 210 by indicating the radio sequence number of each packet.

[0087] Optionally, the second entity 200 may be further configured to send a second indication to the first entity 100. The second indication indicates a second set of packets transmitted from the second entity 200 to the second link receiver 210. The second entity 200 may be further configured to send a second transmission status indication to the first entity 100, the second transmission status indication indicating which packets of the second set of packets were successfully received by the second link receiver 210 and / or which packets of the second set of packets were not received by the second link receiver 210.

[0088] FIG. 3 illustrates a multilink implementation according to an embodiment of the present disclosure. The embodiment of the present disclosure defines an MRM Tx device including a first entity 100 and a second entity 200. In particular, the first entity 100 may be the first entity shown in FIG. 1 or FIG. 2, and the second entity 200 may be the second entity shown in FIG. 1 or FIG. 2. The MRM Tx device may obtain traffic from a cloud (e.g., a cloud virtual reality (VR) server) and provide packets to be transmitted to both the first entity 100 and the second entity 200. In this embodiment, the first entity 100 is an AP operating at a high 80 MHz frequency, and the second entity 200 is an AP operating at a low 80 MHz frequency. Each of the first entity 100 and the second entity 200 transmits to a respective station (STA). According to one embodiment of the present disclosure, the MRM Rx device may combine traffic from two STAs to obtain an Rx stream, which may then be further supplied to a terminal (e.g., a VR headset) in turn.

[0089] For simplicity, Fig. 3 depicts two Wi-Fi chipsets located in the same housing, but there is no constraint to implement this design between two independent Wi-Fi products (different boxes). In addition, it is worth mentioning that although Fig. 3 shows only two Wi-Fi chipsets in the host, the present disclosure does not limit the number of chipsets in a multi-link implementation. That is, an embodiment of the present disclosure provides a wireless transmission device that may include at least one first entity 100 as illustrated in Fig. 1 and at least one second entity 200 as illustrated in Fig. 2.

[0090] According to one embodiment of the present disclosure, a wireless transmitting device may be configured to obtain an original sequence of packets (packets to be transmitted). Further, the wireless transmitting device may be configured to generate a sequence of packets by appending a global multilink sequence number to each packet of the original sequence of packets. The wireless transmitting device may then be configured to replicate the sequence of packets and provide the sequence of packets to each of the at least one first entity 100 and the at least one second entity 200.

[0091] Similarly, embodiments of the present disclosure also provide a wireless receiving device that may include at least one first link receiver 110 that receives packets from at least one first entity 100, as illustrated in Figure 1, and at least one second link receiver 210 that receives packets from at least one second entity 200, as illustrated in Figure 2. According to an embodiment of the present disclosure, the wireless receiving device may be configured to obtain a received stream by combining packets received by the at least one first link receiver 110 and packets received by the at least one second link receiver 210.

[0092] 4 illustrates a VR multi-link implementation according to one embodiment of the present disclosure. In particular, VR requires high throughput (e.g., 80 Mbps at the entry level and 260 Mbps at the comfort level) and also requires strict and bounded latency. Therefore, VR over wireless transmission faces significant challenges. These challenges include guaranteeing throughput while operating in a real deployment, facing air sharing in a real deployment with other devices in the home, and facing interference from other Wi-Fi systems operating on the same frequency or adjacent / alternate frequencies.

[0093] In an ideal clean and isolated environment, Wi-Fi can meet the latency requirements of VR. However, in residential deployments, it is highly likely that during some access attempts, the VR AP will encounter long Txs or multiple Txs with OBSSs exceeding 10 ms, making it unable to continue Tx.

[0094] In the software-level solution proposed in the embodiments of the present disclosure, each radio uses an independent chipset and RF chain. High RF isolation between the two radios can be achieved based on current multi-band products. For example, a simultaneous multi-radio device including 2*5 GHz operating in "STR" mode can be used.

[0095] In this embodiment, the VR Wi-Fi device has two Wi-Fi chips connected to the same host (e.g., via PCIe). In particular, Wi-Fi chip A may be the first entity 100 as shown in FIG. 1 or FIG. 2, and Wi-Fi chip B may be the second entity 200 as shown in FIG. 1 or FIG. 2. Wi-Fi chip A operates in the 5 GHz high band, and Wi-Fi chip B operates in the 5 GHz low band. The host operating system (OS) may be Linux or any other OS (not a strict real-time OS). Traffic can be replicated internally for each Wi-Fi driver by using zero-copy operations (e.g., using sk_buff_clone, etc.).

[0096] Figure 5 shows a block diagram of a Software-Defined Multilink (SDML) architecture according to one embodiment of the present disclosure, and Figure 6 shows a high-level flow diagram of this architecture. For simplicity, the block diagram of Figure 5 depicts two Wi-Fi chipsets located in the same housing, but there is no constraint to implementing SDML between two independent Wi-Fi products (different boxes), with the SDML bridging logic implemented in a third traffic manager / controller device. In particular, one of the Wi-Fi chipsets may be the first entity 100 as shown in Figure 1 or Figure 2, and the other of the Wi-Fi chipsets may be the second entity 200 as shown in Figure 1 or Figure 2.

[0097] An efficient messaging infrastructure (e.g., message (Msg) queues) must be implemented between the two Wi-Fi chips. Due to software-based implementation requirements, messages must be passed through the host. When multilink traffic is received by the bridge-level SDML logic, the SDML logic obtains a global multilink sequence number (independent of the Wi-Fi Tx sequence number) and replicates it across all SDML Tx links.

[0098] The SDML architecture is based on two main messages that keep all links synchronized: Data Sent (i.e., the first indication 101 as shown in Figure 1, Figure 2, or Figure 5), which indicates which packets have been sent by the link transmitter, and BA Received (i.e., the first transmission status indication 102 as shown in Figure 1, Figure 2, or Figure 5), which indicates which packets have been successfully received by the link receiver. When an SDML device receives an SDML Data Sent Msg from another SDML link transmitter, such as "Data Msg SDML SN#100-120" as shown in Figure 6, the SDML device must find the indicated packets and remove them from the transmit queue to the SDML pending queue, as shown in Figure 6. When an SDML device receives an SDML BA Msg from another SDML link transmitter, such as "BA Msg SDML SN#100-120" as shown in Figure 6, the SDML device must find the indicated successfully received packets in the SDML pending queue and remove them. All indicated failed packets must be returned to the head of the transmit queue to be transmitted at the next TxOP. For example, if the SDML device receives "Data Msg SDML SN#121-140" and then receives "BA Msg NACK SDML SN#130-135" as shown in Figure 6, the SDML device knows that packets with SDML SN#130-135 need to be retransmitted. In response, the SDML device releases packets with SDML SN#121-129 and 136-140 and pushes packets with SDML SN#130-135 back to the head of the transmit queue.

[0099] Figure 7 further illustrates delay modeling according to this embodiment of the present disclosure. In particular, NS-3 randomly picks each message event. Exponential distribution modeling is a common approach in the industry for software interrupt latency modeling. The arguments of the NS-3 exponential distribution are the mean and bounds. A bound of 10 ms with different mean values ​​from 0.5 to 3 ms are simulated.

[0100] 8 shows an NS-3 topology according to one embodiment of the present disclosure, where SDML is simulated in the open source NS-3 system level simulation. SDML AP 250Mbps Constant Bit Rate (CBR) User Datagram Protocol (UDP) traffic Modulation coding method (MCS-4) (16-QAM 3 / 4), 3SS, 80MHz → PHY rate 526.5Mbps ·Tx power 25dBm Msg queue delay exponential distribution Limit 10ms (max tail) ·Average {0.5,1.0,1.5,2.0,2.5,3.0}ms Simulation run duration: 5 seconds (5 seconds was used so that NS-3 could have enough events for the spread over the exponential distribution) ·interference {50,100,125,150,175,200}Mbps Variable Bit Rate (VBR) UDP VR traffic MCS-5 (64-QAM 2 / 3), 2SS, 40 / 80MHz → PHY rate 216 / 468Mbps ·Tx power 25dBm

[0101] Figure 9 shows the simulation results of this SWML implementation. It can be easily observed that SWML can be as efficient as hardware-based multilink. Even a 3 ms Msg queue delay from the exponential distribution can service both entry and comfort levels at 90%, which should provide sufficient margin for the required implementation. As shown in Figure 9, to meet the 99% requirement, the Msg queue delay should not exceed the Exp distribution with an average of 1.5 ms.

[0102] 10 illustrates a method 1000 according to one embodiment of the present disclosure. In a particular embodiment of the present disclosure, the method 1000 is performed by the first entity 100 illustrated in FIG. 1. The method 1000 includes the steps of: transmitting 1001 a first indication 101 to the second entity 200, where the first indication 101 indicates a first set of packets transmitted from the first entity 100 to the first link receiver 110; and transmitting 1002 a first transmission status indication 102 to the second entity 200, where the first transmission status indication 102 indicates which packets of the first set of packets were successfully received by the first link receiver 110 and / or which packets of the first set of packets were not received by the first link receiver 110. In particular, each packet indicated in the first indication 101 and the first transmission status indication 102 is associated with a global multilink sequence number. In some cases, the second entity 200 is the second entity shown in FIG. 1 or FIG.

[0103] 11 illustrates a method 1100 according to one embodiment of the present disclosure. In a particular embodiment of the present disclosure, the method 1100 is performed by the second entity 200 illustrated in FIG. 2. The method 1100 includes receiving 1101 a first indication 101 from the first entity 100, the first indication 101 indicating a first set of packets transmitted from the first entity 100 to the first link receiver 110, and receiving 1102 a first transmission status indication 102 from the first entity 100, the first transmission status indication 102 indicating which packets of the first set of packets were successfully received by the first link receiver 110 and / or which packets of the first set of packets were not received by the first link receiver 110. In particular, each packet indicated in the first indication 101 and the first transmission status indication 102 is associated with a global multilink sequence number. In some cases, the first entity 100 is the first entity shown in FIG. 1 or FIG.

[0104] The present disclosure has been described with reference to various exemplary embodiments and implementations. However, other variations can be understood and effected by those skilled in the art by practicing the claimed disclosure, upon studying the drawings, the disclosure, and the independent claims. In the claims and the description, the word "comprising" does not exclude other elements or steps, and the indefinite articles "a" or "an" do not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used in advantageous implementations.

[0105] Furthermore, any method according to the embodiments of the present disclosure may be implemented in a computer program having code means, which, when executed by a processing means, causes the processing means to perform the steps of the method. The computer program is included in a computer-readable medium of a computer program product. The computer-readable medium may essentially include any memory, such as a ROM (Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM (Erasable PROM), a flash memory, an EEPROM (Electrically Erasable PROM), or a hard disk drive.

[0106] Furthermore, it will be understood by those skilled in the art that embodiments of the first entity 100 and the second entity 200 each comprise the necessary communication capabilities, e.g. in the form of functions, means, units, elements, etc., for performing the solution. Examples of other such means, units, elements and functions are processors, memories, buffers, control logic, encoders, decoders, rate matchers, de-rate matchers, mapping units, multipliers, decision units, selection units, switches, interleavers, de-interleavers, modulators, demodulators, inputs, outputs, antennas, amplifiers, receiver units, transmitter units, DSPs, trellis coded modulation (TCM) encoders, TCM decoders, power supply units, power feeders, communication interfaces, communication protocols, etc., suitably arranged with respect to one another for performing the solution.

[0107] In particular, the processor(s) of the first entity 100 and the second entity 200 may each comprise, for example, one or more instances of a central processing unit (CPU), processing unit, processing circuit, processor, application specific integrated circuit (ASIC), microprocessor, or other processing logic capable of interpreting and executing instructions. Thus, the term "processor" may refer to a processing circuit comprising multiple processing circuits, such as, for example, any, some, or all of the above. The processing circuit may further perform data processing functions for input, output, and processing of data, including data buffers, as well as device control functions such as call processing control, user interface control, etc. [Explanation of symbols]

[0108] 100 First Entity 101 First Instruction 102 First transmission status indication 110 first link receiver 200 Second Entity 210 Second Link Receiver 1000 ways 1100 methods

Claims

1. A first entity (100) for multi-link implementation in a wireless network, comprising a processing circuit and a memory circuit, the memory circuit storing one or more instructions that, when executed by the processing circuit, cause the first entity (100) to: transmitting a first instruction (101) to a second entity (200), the first instruction (101) indicating a first set of packets to be transmitted from the first entity (100) to a first link receiver (110), the first entity (100) being mounted on a first chipset located on a wireless device, and the second entity (200) being mounted on a second chipset located on the wireless device and different from the first chipset; transmitting a first transmission status indication (102) to the second entity (200), the first transmission status indication (102) indicating which packets of the first set of packets were successfully received by the first link receiver (110) and / or which packets of the first set of packets were not received by the first link receiver (110); Let them do this, Each packet indicated in the first indication (101) and the first transmission status indication (102) is associated with a global multilink sequence number; the global multilink sequence number is set in each packet before the first entity (100) retrieves the packet; First entity (100).

2. The one or more instructions, when executed by the processing circuit, cause the first entity (100) to: obtaining a sequence of packets to be transmitted to the first link receiver (110), each packet being associated with a global multilink sequence number; maintaining a first transmission queue of the sequence of packets, the packets in the first transmission queue being to be transmitted to the first link receiver (110); Further The first entity (100) of claim 1.

3. The one or more instructions, when executed by the processing circuit, cause the first entity (100) to: transmitting the first set of packets to the first link receiver (110), the first set of packets being included in the sequence of packets; receiving a first block acknowledgement (BA) from the first link receiver (110), the first BA indicating which packets of the first set of packets were successfully received by the first link receiver (110) and / or which packets of the first set of packets were not received by the first link receiver (110); generating the first transmission status indication (102) based on the first BA and a global multilink sequence number associated with a packet indicated by the first BA; Further The first entity (100) of claim 2.

4. Each packet of the first packet set includes a radio sequence number, and the first BA indicates which packets of the first packet set were successfully received by the first link receiver (110) and / or which packets of the first packet set were not received by the first link receiver (110) by indicating the radio sequence number of each packet. The first entity (100) according to claim 3.

5. The one or more instructions, when executed by the processing circuit, cause the first entity (100) to: receiving a second indication from the second entity (200), the second indication indicating a second set of packets transmitted from the second entity (200) to a second link receiver (210), each packet indicated in the second indication being associated with a global multilink sequence number, the second set of packets being included in the sequence of packets; in response to the second instruction, moving the second set of packets from a first transmit queue to a first hold queue, where packets in the first hold queue are put on hold; Further A first entity (100) according to any one of claims 2 to 4.

6. The one or more instructions, when executed by the processing circuit, cause the first entity (100) to: receiving a second transmission status indication from the second entity (200), the second transmission status indication indicating which packets of a second set of packets were successfully received by a second link receiver (210) and / or which packets of the second set of packets were not received by the second link receiver (210); in response to the second transmission status indication; Releasing packets successfully received by said second link receiver (210) from the first holding queue; and / or returning packets not received by said second link receiver (210) to the head of a first transmission queue; Further The first entity (100) of claim 1.

7. 7. The first entity (100) of any one of claims 1 to 6, wherein the first entity (100) operates at a different frequency than the second entity (200).

8. A second entity (200) for multi-link implementation in a wireless network, comprising a processing circuit and a memory circuit, the memory circuit storing one or more instructions that, when executed by the processing circuit, cause the second entity (200) to: receiving a first instruction (101) from a first entity (100), the first instruction (101) indicating a first set of packets transmitted from the first entity (100) to a first link receiver (110), the second entity (200) being mounted on a second chipset located on a wireless device, the first entity (100) being mounted on a first chipset located on the wireless device and different from the second chipset; receiving a first transmission status indication (102) from the first entity (100), the first transmission status indication (102) indicating which packets of the first set of packets were successfully received by the first link receiver (110) and / or indicating which packets of the first set of packets were not received by the first link receiver (110); Let them do this, Each packet indicated in the first indication (101) and the first transmission status indication (102) is associated with a global multilink sequence number; the global multilink sequence number is set in each packet before the first entity (100) retrieves the packet; The second entity (200).

9. The one or more instructions, when executed by the processing circuit, cause the second entity (200) to: Obtaining a sequence of packets that need to be transmitted to a second link receiver (210), each packet being associated with a global multilink sequence number; maintaining a second transmit queue of the sequence of packets, the packets in the second transmit queue to be transmitted to the second link receiver (210); Further The second entity (200) according to claim 8.

10. The first set of packets is included in the sequence of packets, and the one or more instructions, when executed by the processing circuit, cause the second entity (200) to: in response to the first instruction (101), moving the first set of packets from the second transmit queue to a second hold queue, where packets in the second hold queue are put on hold; Further The second entity (200) according to claim 9.

11. The one or more instructions, when executed by the processing circuit, cause the second entity (200) to: In response to the first transmission status indication (102), Releasing packets successfully received by the first link receiver (110) from the second holding queue; and / or returning packets not received by the first link receiver (110) to the head of the second transmit queue; Further The second entity (200) according to claim 10.

12. The one or more instructions, when executed by the processing circuit, cause the second entity (200) to: transmitting a second set of packets to the second link receiver (210), the second set of packets being included in the sequence of packets; receiving a second block acknowledgement (BA) from the second link receiver (210), the second BA indicating which packets of the second set of packets were successfully received by the second link receiver (210) and / or which packets of the second set of packets were not received by the second link receiver (210); generating a second transmission status indication based on the second BA and a global multilink sequence number associated with a packet indicated by the second BA; Further A second entity (200) according to any one of claims 9 to 11.

13. Each packet of the second packet set includes a radio sequence number, and the second BA indicates which packets of the second packet set were successfully received by the second link receiver (210) and / or which packets of the second packet set were not received by the second link receiver (210) by indicating the radio sequence number of each packet. The second entity (200) according to claim 12.

14. The one or more instructions, when executed by the processing circuit, cause the second entity (200) to: sending a second instruction to the first entity (100), the second instruction indicating the second set of packets transmitted from the second entity (200) to the second link receiver (210); transmitting the second transmission status indication to the first entity (100), the second transmission status indication indicating which packets of the second set of packets were successfully received by the second link receiver (210) and / or which packets of the second set of packets were not received by the second link receiver (210); Further A second entity (200) according to claim 12 or 13.

15. 15. The second entity (200) of any one of claims 8 to 14, wherein the second entity (200) operates at a different frequency than the first entity (100).

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