Efficiently transmittable bit sequences with limited disparity

Abstract

The invention relates to a method for generating efficiently transmittable bit sequences with limited disparity and limited run length. The proposed method allows particularly efficient transmission of data. Optimized disparity is a quality feature for data transmittability. Unfavourable disparity cannot be interpreted properly at the receiver side, which may result in improper transmission of data over the data channel. It allows particularly efficient reading and allows the generation of a data stream that is also very efficient in terms of overhead data. The conversion of data segments into sub-symbols is performed in parallel, which allows the conversion to be performed efficiently. The invention further relates to a correspondingly configured system device, as well as a computer program product and a memory-readable medium with control instructions for carrying out the method.

Description

[Technical Field]

[0001] The present invention relates to a method for generating efficiently transmittable bit sequences with limited disparity and limited run length. The proposed method allows for efficient data transmission over a transmission channel. Optimized disparity is a quality characteristic for data transmissibility. Unfavorable disparity may not be properly interpreted at the receiving end, resulting in improper data transmission over the data channel. Another quality characteristic is data efficiency, which refers to the ratio between transmitted user data and other data not directly related to the content of the user data. This includes so-called header data. The proposed invention allows for particularly efficient readout and allows for the generation of a data stream that is highly efficient, even with regard to overhead data. This minimizes the so-called overhead of the user data, resulting in highly efficient processing. Furthermore, unambiguous interpretation at the receiving end eliminates the need for repeated data transmission, allowing for highly error-resilient readout at the receiving end. Furthermore, the proposed method is highly efficient, since it allows for parallel conversion of data segments into subsymbols or symbols composed of subsymbols, and this parallel design requires only technically simple units to manufacture. Therefore, the efficiency gains here also relate to the hardware or runtime used. The invention also relates to a correspondingly configured system apparatus, as well as a computer program product and a memory-readable medium with control instructions for carrying out the method. [Background technology]

[0002] Non-Patent Document 1 presents a fault-tolerant DC-balanced line encoding scheme for use in AC-coupled channel link transceivers with 7-bit frame alignment as opposed to the more common 8-bit alignment.

[0003] Patent Document 1 discloses a method and apparatus for encoding input data at a higher speed, which enables error detection and clock recovery as well as reduction of spectral components near DC, and can encode data while embedding error detection information.

[0004] Patent Document 2shows a method that makes it possible, among other things, to read an analog data stream over a data line in an error-free manner. In particular, the amplitude of the signal is monitored, and more preferably, the signal is measured at the point where the amplitude is at a maximum. This converts the analog data stream into a digital data set, ensuring that the maximum amplitude safely undercuts or exceeds the threshold between 0 and 1 on the line.

[0005] Although various encoding and data transmission methods are known in the current technology, they all relate to applications that can only be used in a disadvantageous manner in automobiles. For example, current technology often assumes that high computing power is available and that high real-time requirements are not required. Also, current technology often assumes that the weight or reliability of the components used plays a secondary role. Current technology often refers to traditional computer networks, where reliability and low technical complexity are not as important.

[0006] Based on this current technology, it is necessary to create a method or system that allows data for safety requirements in automobiles to be processed as quickly as possible, requires little technical effort, and minimizes the error rate during transmission by eliminating the need for retransmission if an error is detected. Low technical complexity requires the introduction of components that are as simple as possible, lightweight, and can be efficiently manufactured in large quantities. Because lightweight and real-time operation are not critical for standalone PCs or servers, known methods and system devices based on computer network technology generally cannot be used here. While dissipated heat is generally a challenge for computer configurations, energy efficiency in automobiles is even more important; for example, in electromobility, power consumption even affects the vehicle's range.

[0007] Further prior art relates to the transmission of data in a serial data stream. For example, current technology provides extensive descriptive data that is transmitted along with the user data and indicates where the user data is located and how it should be interpreted. Current technology is also known to discard individual data packets if they are not transmitted correctly. Current technology is also known to retransmit data packets if they do not arrive at the sender on time or in an unexpected format.

[0008] When transmitting data serially, it is necessary to keep the number of 1s and 0s in the serial data stream as equal as possible. This is called disparity. A disparity of zero is desirable on average and in the short term to avoid baseline drift during transmission. Baseline drift (DC voltage fluctuations) in a serial signal can lead to bit errors. In extreme cases, transmission may become impossible.

[0009] A minimum number of 0->1 or 1->0 transitions are required to ensure that the serial bits in a serial data stream can be reliably recovered at the receiver without transmitting a clock. This means that the clock for recovering the serial data is generated locally from the serial data stream at the receiver. The so-called run length specifies how many times the same bit (1 or 0) occurs consecutively without changing. A long run length makes it impossible to reliably recover the clock from the serial data stream, so a short run length is always desirable.

[0010] The challenge of line codes (block codes in this case) is to generate symbols with guaranteed disparity and guaranteed run length from arbitrary data words with arbitrary disparity and infinite run length. This leads to overhead during transmission. This means that more bits (in the form of symbols) must be transmitted than are contained in the net data word being transmitted. This means that the required transmission speed (bandwidth) must be greater than the data rate of the data being transmitted. This results in a higher error rate or requires more effort, power, etc., for the system than would be required to transmit the raw data.

[0011] Current technologies either have high overhead (8B10B) or the quality of the coded signal in terms of disparity and run length is very poor, so additional (complex) measures such as scramblers are often required to improve the quality in terms of disparity or run length. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] U.S. Patent No. 6,691,275 [Patent Document 2] European Patent Application Publication No. 3323219 [Non-patent literature]

[0013] [Non-Patent Document 1] Boye Jeffrey et al, “11b / 14b Encoding - A Fault Tolerant, DC-Balanced Line Code for AC-Coupled Channel Link Transceivers”, 2019 IEEE Aerospace Conference, IEEE, 2 March 2019 Summary of the Invention

[0014] It is an object of the present invention to provide a method for generating a bit stream that can be transmitted particularly efficiently. In this context, efficient may refer to hardware efficiency, efficient decoding at the receiver, no need for redundant data transmission due to uninterpretable signals, and / or a low ratio of user data to overhead data. Furthermore, the present invention should enable the creation or use of particularly efficient hardware that allows runtime optimization through parallel processing. It is also an object of the present invention to provide a correspondingly configured system apparatus, as well as a computer program product and a computer-readable storage medium with control instructions for performing the method or operating the system apparatus.

[0015] This problem is solved by the features of claim 1. Further advantageous embodiments are described in the dependent claims. Thus, there is provided a method in a motor vehicle for generating an efficiently transmittable bit sequence with constrained disparity and constrained run length, comprising: providing an arbitrary bit sequence; segmenting the provided bit sequence into a sequence of predetermined segments according to a predetermined bit length; and encoding each segment into a respective sub-symbol using one coding unit per segment from among a plurality of coding units, wherein a first subset of coding units actively controls the signs of the disparities of the generated sub-symbols by inverting the disparities of the sub-symbols to compensate for the disparity of a subset of a second coding unit, and wherein juxtaposition of the sub-symbols results in the efficiently transmittable bit sequence.

[0016] In the preparatory processing step, a potentially unlimited bit sequence can be provided, including any bit sequence. Depending on the application, the data stream can be of any length and can be divided into multiple words or any bit sequence. This provides an output data stream with a bit sequence of potentially any length. However, this arbitrary length can be specified in the preparatory processing step, preferably as 112 bits. Once the length or bit length of the arbitrary bit sequence is specified, it is fixed according to one aspect of the present invention. In this respect, the length of a bit sequence in the sense of the present invention cannot be understood as arbitrary. Rather, a synonym for an arbitrary bit sequence according to the present invention can be a bit sequence whose length can be freely selected in advance and / or a bit sequence whose content corresponds to the transmitted data or at least part of the transmitted data.

[0017] It is therefore possible to provide an output data stream containing an arbitrary sequence of bits in a preparatory processing step, which is then read from the output data stream and provided in the first processing step.

[0018] In general, since the output data stream or output bit string may have a large number of bits, the process is performed iteratively so that several arbitrary bit strings are generated from the output bit string, segmented, converted into sub-symbols, optimized for disparity, and then transmitted, which means that the output bit string can be of any length and ultimately transmitted across multiple symbols.

[0019] There are multiple coding units, one for each segment corresponding to an arbitrary or freely selectable portion of the bit string. The coding units convert the segments into sub-symbols, and the concatenated set of sub-symbols corresponds to a symbol or whole symbols of the bit string to be efficiently transmitted. Thus, according to one aspect of the invention, the coding units are arranged in a logical path in the processing chain or structural arrangement between the segments and the sub-symbols.

[0020] The proposed method is particularly efficient because the transmittable bit streams have a particularly high level of user data compared to current technology. For example, 128 bits with 112 bits of user data can be transmitted. The proposed method is therefore superior to current technology in this respect. Furthermore, the generation of the transmittable bit streams can be performed in parallel, and a particularly simple-designed coding unit can be used for this purpose. Simple in this context means, for example, that the coding unit requires very little circuitry. The coding unit does not need to have extensive logic and can be optimized for a certain number of bits. Therefore, according to the present invention, the input and output of each coding unit can be fixed in terms of the number of bits.

[0021] The optimized disparity of the transmitted bit sequence makes it possible to avoid errors when interpreting it over a serial channel. Efficient therefore also refers, among other things, to the fact that the bit sequence is error-tolerant and can be reliably transmitted exactly once. Redundant transmissions are avoided by the high probability of detection and by the optimized disparity.

[0022] When transmitting data serially, it is advantageous to maintain as equal a number of ones and zeros as possible in the serial data stream. This is commonly referred to as disparity. For reliable clock recovery at the receiver, a run-length limit can be imposed on the generated channel sequence, limiting the maximum number of consecutive ones and zeros. Therefore, the proposed method can also be considered a method for efficient encoding of bit strings. According to the present invention, disparity is optimized by skillfully setting partial disparities. This can be used particularly advantageously when the bit string has a limited run length. Furthermore, the limited disparity and limited run length can relate to any bit string provided. This means that the bit string does not necessarily have to be efficiently transmittable. Overall, any bit string provided can be efficiently transmittable, or the transmitted bit string can be generated or created from this bit string to be efficiently transmittable.

[0023] In a preparatory processing step, an arbitrary bit string for encoding user data is provided. Problems can arise in this arbitrary bit string if, for example, there is an undesirable disparity. For example, too many zeros can cause problems during transmission. This should be avoided, so the arbitrary bit string is optimized in further processing steps for efficient transmission. The provided arbitrary bit string represents arbitrary user data to be transmitted from a transmitter to a receiver via a serial data channel. The arbitrary bit string can be, for example, control data in an automobile.

[0024] According to the present invention, a given bit sequence is segmented into a sequence of predetermined segments according to a predetermined bit length. Thus, an input data stream, i.e., an arbitrary bit sequence, is divided according to a predetermined procedure so that individual data segments are generated. The segments thus cumulatively result in an arbitrary bit sequence. The predetermined bit length has the advantage that the coding unit can be optimized in the same way as each bit length is taken into account. This allows highly specialized and very efficient circuits to be created. The predetermined bit lengths are explained below, but these are merely examples.

[0025] Each segment is coded into subsymbols using one coding unit per segment from among multiple coding units. The coding itself is performed by one coding unit, which detects a segment at the input side and converts this segment into subsymbols. Subsymbols are also bit strings. Therefore, any bit string is divided into multiple segments, and these segments are converted into subsymbols by the respective coding units, thereby coding any bit string to be transmitted in terms of the entire set of subsymbols. Overall, it is advantageous that the number of segments corresponds to the number of coding units, and therefore the number of subsymbols. For this reason, it is possible to have exactly one coding unit for each segment, and the coding unit generates exactly one subsymbol from the segment. The number of coding units represents all the coding units used, which corresponds to the number of segments. The number of segments is predetermined because a certain bit length is specified. Therefore, the method is overall deterministic.

[0026] To achieve a preferred overall disparity, a subset of first coding units are present that actively control the signs of the disparities of the sub-symbols by inverting the disparities of the generated sub-symbols to compensate for the disparities of the subset of second coding units. This means that some subsets of coding units control the signs of the disparities and some do not. A subset of the first coding units controls the signs, and a subset of the second coding units does not control the signs. Thus, a subset of the first coding units can be said to be active and a subset of the second coding units can be said to be passive. Because the subsets or types of coding units are different, it is possible to serially connect the coding units such that a subset of the first coding units advantageously shapes the overall disparity of the sub-symbols in the subset of the second coding units.

[0027] Thus, according to the present invention, any coding unit can be used with respect to the disparity of its subsymbols. A subset of first coding units can be connected in parallel and control the disparity of its preceding coding unit and its own coding unit, or the sign of its subsymbol disparity, depending on the disparity of a subset of second coding units. This means that a certain number of subsets of second coding units are used, followed by another certain number of subsets of first coding units. Thus, the type or subset of coding units changes so that the next parallel-connected coding unit adapts the disparity of its preceding subsymbols and / or its own subsymbols. This avoids undesirable disparity caused by connecting non-controllable coding units in parallel one after another. That is, each subset of first coding units corrects the sign of the preceding parallel-connected coding unit or its subsymbols. This parallel connection of coding units will be described in more detail below with reference to FIG. 4.

[0028] In summary, it can be concluded that a subset of the first coding unit optimizes a subset of the second coding unit in terms of disparity. Optimizing the disparity means that the disparity is 0. How to calculate the disparity or how to set the disparity (for example, by changing the sign) is well known to those skilled in the art.

[0029] Therefore, the proposed method generates sub-symbols whose sequences are optimized with respect to disparity. Each segment is converted into a sub-symbol, so that the transmitted (whole) symbol can be generated by concatenating the sub-symbols. This allows for efficient or error-resilient transmission due to the optimized disparity or partial disparity. This results in a preferred bit sequence being transmitted.

[0030] According to one aspect of the present invention, any bit sequence is not limited in its disparity and run length. This has the advantage that any amount of user data can be transmitted or any amount of user data can be converted into a bit sequence whose disparity and run length are limited. This means that any bit sequence can be encoded and transmitted into a bit sequence optimized with respect to its disparity and run length.

[0031] According to a further aspect of the present invention, the disparity of the subset of second coding units is not controllable. This has the advantage that any sub-symbols can be generated using the subset of second coding units, and simple coding units are used. These can be designed to be particularly simple, since the generated sub-symbols of this coding unit are not subject to any restrictions regarding disparity or run length.

[0032] According to a further aspect of the invention, active control of the code is performed by conditional inversion of sub-symbols. This has the advantage that the corresponding sub-symbols of a subset of the first coding unit can be controlled in a simple manner. Only the disparity of a sub-symbol or individual bits needs to be inverted. The code refers to the disparity of a sub-symbol, which can be positive or negative.

[0033] According to a further aspect of the invention, the conditional inversion is performed depending on the disparity of the entire symbol formed from all sub-symbols. This has the advantage that not only are the sub-symbols optimized, but the entire, i.e. combined, sub-symbols, and thus the entire symbol, are optimized in terms of disparity, thereby resulting in a preferred overall symbol.

[0034] According to a further aspect of the invention, the dependencies are influenced so that the value of the disparity magnitude is minimized. This has the advantage that the lowest possible disparity is achieved, preferably 0. Thus, the disparities are related to each other in such a way that the amount of disparity is as close to 0 as possible or as low as possible.

[0035] According to a further aspect of the invention, the magnitude value is minimized so that positive disparity of the entire symbol is cancelled by negative parity of the sub-symbols, which has the advantage that positive disparity of the entire symbol is minimized or eliminated.

[0036] According to a further aspect of the invention, the magnitude value is minimized so that the negative disparity of the entire symbol is cancelled by the positive parity of the sub-symbols, which has the advantage that the disparity of the entire symbol is minimized or eliminated.

[0037] According to a further aspect of the invention, an active control is provided that depends on the entire set of symbols already transmitted, so that the disparity of the entire set of symbols is minimized, which has the advantage that some entire symbols are minimized or disparity-removed with respect to their disparity, whereby some columns of the entire set of symbols are also optimized with respect to their transmittability.

[0038] According to a further aspect of the present invention, a subset of the first coding units encodes 11-bit segments into 13-bit sub-symbols. This has the advantage that the 11 bits are coded particularly efficiently, resulting in only an additional 2 bits. This is particularly advantageous when a total of 128-bit symbols are to be created. Generally, the specific values ​​of the proposed technical teachings mentioned herein have been empirically determined and can be demonstrated by the fact that only an additional 128-112 bits, i.e., an additional 14% effort, is required. Therefore, the values ​​listed herein have proven advantageous for the transmission of 112 bits.

[0039] According to a further aspect of the invention, a subset of the first coding units have disparities between +3 and +9, which are inverted to -3 and -9 by inversion. This has the advantage that, for example, a disparity of +3 is offset by a disparity of -3, and the same is true when adjusting a disparity of +9 with a disparity of -9. This is particularly advantageous for any bit string of 112 bits that is coded as 128 bits.

[0040] According to a further aspect of the invention, the run length in the sub-symbols is at most 7. This has the advantage that at most 7 identical instances of 0 and 1 are generated, which is particularly advantageous in the proposed cases of 112 or 128 bits.

[0041] According to a further aspect of the invention, the run length of the sub-symbols in the subset of the first coding unit is at most 5, starting from the most significant bit and / or the least significant bit. This has the advantage that there can be at most 5 identical bits at the beginning or end of a sub-symbol. This has proven to be particularly advantageous in the described case.

[0042] According to a further aspect of the invention, the second subset of coding units encodes 11-bit segments into 12-bit sub-symbols, or 7-bit segments into 8-bit sub-symbols, or 6-bit segments into 8-bit sub-symbols, which has the advantage that this coding produces particularly advantageous values ​​in the case of 112 bits transmitted in a 128-bit symbol, with a minimized overhead of only 14%.

[0043] According to a further aspect of the invention, disparities between -2 and +2 are generated in a subset of the second coding units, which has the advantage that preferred disparities are generated as well.

[0044] According to a further aspect of the invention, in the subset of second coding units the run length of the generated sub-symbols is 6. This has the advantage that optimized sub-symbols are generated.

[0045] According to a further aspect of the invention, the subset of second coding units generates sub-symbols with a maximum run length at the edges of 3. This has the advantage that the sub-symbols created by the subset of second coding units have a maximum run length of 3 at the beginning or end, which is an advantageous value.

[0046] According to a further aspect of the invention, multiple coding units are addressed in parallel, each coding one segment into one sub-symbol. This has the advantage that a segment is converted into exactly one sub-symbol by exactly one coding unit. Thus, by addressing multiple coding units in parallel, multiple segments can be formed from any bit sequence and then converted into sub-symbols in parallel.

[0047] According to a further aspect of the invention, the coding units are addressed in a sequence of 212122221212, where 1 represents a subset of the first coding unit and 2 represents a subset of the second coding unit. This has the advantage that a coding unit that is not actively controlled is always followed by a single coding unit that can be actively controlled. The proposed coding units have been empirically shown to result in good overall symbol quality.

[0048] According to a further aspect of the present invention, when a data stream with positive and negative disparity is applied, the data stream that contributes to minimizing the overall disparity of the entire symbol is selected by a multiplexer. This has the advantage of being able to select an appropriate data stream with a code that minimizes or eliminates disparity. For example, if the disparity to be optimized is negative, a data stream with positive disparity is selected, and then this data stream is minimized or compensated for with respect to its disparity.

[0049] One aspect of the present invention is bundling several data streams (video, audio, and data) into one transport frame and transmitting them serially. Different data formats not only have different bandwidth requirements, but also different latency, reassembly sublayer, and bit error rate requirements. In particular, the transmission of today's video data formats requires not only the transmission of pure video data and its frame information, but also the support of encryption methods such as HDCP. All of this requires many different data channels with a wide range of requirements in terms of bandwidth, latency, reassembly sublayer, etc. In addition, much more complex network architectures are desired than simple transmitter and receiver architectures provide. An architecture with multiple repeaters and branches (Y) where data paths can originate and terminate is advantageous because it also provides the possibility to reintegrate data paths into links.

[0050] According to one aspect of the invention, this technology follows the basic idea of ​​consistent bundling of services, but offers completely new possibilities in terms of network architecture and enables new approaches in the implementation of today's video interfaces. This technology can also be used as a generic data transport layer, for example for Ethernet or for the transmission of camera data or any type of sensor data.

[0051] In contrast to IP, where a packet may reach its destination via a different route than previous and subsequent packets, in a virtual path, all packets / cells follow the same path, so latency and reassembly sublayers across the virtual path are constant.

[0052] Also, the characteristics of the virtual paths can be configured differently so that different virtual paths do not interfere with each other, which has the advantage that the virtual paths can be used as multiplexing branches for different services (video, audio, Ethernet).

[0053] A virtual path consumes bandwidth only when data is actually being transferred. The virtual path concept also makes it possible to implement complex and extensive diagnostic and network configuration functions at run time using separate (virtual) data channels.

[0054] According to one aspect of the present invention, a virtual path layer is provided between the physical layer (serializer and framer) and the various application data interfaces. In accordance with one aspect of the present invention, this is used to multiplex various data paths and to support more complex architectures with repeaters and branches, which is primarily done at the cell layer.

[0055] According to one aspect of the invention, a further part of the virtual path layer is an application adaptation layer which performs the conversion of video (stream) or e.g. Ethernet (packet) data into cells, and which also includes OAM functions for network diagnostics and management.

[0056] In accordance with one aspect of the present invention, this technology can be the basis for transmitting a variety of data formats over serial connections within the vehicle (and elsewhere), thus forming the basis for a new generation of devices.

[0057] High serial bandwidth requires defining architectures, cell formats and interfaces that allow flexible internal data bus widths to match the speed of the internal clock system with the capabilities of the chip technology.

[0058] According to one aspect of the present invention, the virtual path layer is a physical layer including a transmission sublayer and a physical media sublayer, and the cell layer and application adaptation layer include a segmentation sublayer and a reassembly sublayer and a function for adapting data formats to corresponding applications.

[0059] The main task is to establish a physical connection with other physical layers. This connection is essentially bidirectional. In theory, this connection can be realized over a wide variety of media. In practice, two serial differential Gbps connections are used. This layer handles line coding, inserting empty cells to separate the cell rate from the connection rate, and assembling the cell stream into a serial frame.

[0060] In the cell layer, the segmentation data (cell payload data) from the above segmentation and reassembly sublayer is assembled into a complete cell with a header, VP identifier and CRC, or the cell is CRC checked and the payload is passed to the segmentation and reassembly sublayer. This is also the location where the multiplexing of different cell streams for application adaptation functions and the distribution of cell payloads to application adaptation functions according to VP identifiers (feed-in / feed-out) take place.

[0061] According to one aspect of the present invention, the multiplexing and demultiplexing (forwarding) of cell streams in repeaters and splitters also occurs at the cell layer. According to one aspect of the invention, the task of the application adaptation function is to adapt the data of the application interface to the format of the user data field of the cell and to transmit control information to the other side or to the other side for the adaptation used (time occurrence, framing).

[0062] According to one aspect of the present invention, all virtual data paths are unidirectional, i.e., they start at an initiator and terminate at one or more targets. When virtual data paths logically join together, such as HDCP for video channels, thus forming a bidirectional data path, these paths must have the same VP identifier.

[0063] A virtual data path begins at an initiator and terminates at one or more targets. This is realized by the Cell Sublayer, which allows the following on the virtual path: Add / remove multiplexing VP conversion Perform the function of.

[0064] <Stream data (continuous data stream)> The stream data function combines clock domain crossing and bit-width conversion of data from the application interface to the N bits of the cell row. The cell row payload is pre-formatted so that the self-addressing and header fit into the first and last cell row.

[0065] Streaming data is (usually) source synchronous. Clock domain crossings of data paths from the application clock domain to the clock domain of the virtual routing layer are performed here.

[0066] In the transmit direction, a data buffer is provided into which source synchronized data is written along with the source clock. The segmentation layer extracts data from this buffer as needed to perform data format conversion into N-bit wide cell rows. Frame data (e.g., Hsync, Vsync, DE) is encoded with payload information bits so that the frame can be reconstructed at the receiver.

[0067] In the receive direction, cell data from the reassembly sublayer is written into a data buffer (cell row bit width). Frame information is reconstructed based on the payload information bits. The source clock is regenerated, for example, using buffer fill levels and clock synthesis.

[0068] If data encryption is required (HDCP), cell data is encrypted or decrypted with this function. There can be different implementations of this basic function (e.g., V-stream-in / out, A-stream-in / out, EncV-stream-in / out) due to different types of streaming data: audio, encrypted video, unencrypted video, etc. The interface to the segmentation and reassembly sublayer is the same for all functions.

[0069] <Burst data (discontinuous data stream)> The burst data function combines clock domain crossing and data bit width conversion of data from the application interface to the N bits of the cell row. The cell row payload is pre-formatted so that the self-addressing and header fit into the first and last cell row.

[0070] The burst data is (usually) synchronized to an external time and has different identification signals for direction and data type (address / data / byte enable). This data is usually accompanied by control lines to implement a particular protocol.

[0071] In the transmit direction, a data buffer is provided, into which burst data is written along with the interface clock, and the segmentation layer retrieves data from this buffer as needed to perform data format conversion into N-bit wide row cells.

[0072] In the receive direction, cell data from the reassembly sublayer is written into data buffers, which make the cell rows bit-wide. Interface control signals are reconstructed based on the payload information bits.

[0073] The payload information bits are used to generate control signals for the application specific interface or to synchronize protocol state machines in the application specific interface.

[0074] Due to the different interfaces that provide burst-like data (SPI, I2C, MII), there can be different implementations of this basic function (e.g., SPI burst, I2C burst, MII burst).

[0075] Therefore, their structure should be the same, but they will also have (slightly) different stream in / out interfaces. The problem is solved by a system device in a motor vehicle for generating an efficiently transmittable bit sequence with a constrained disparity and a constrained run length, the system device comprising: an interface unit configured to provide an arbitrary bit sequence; a segmentation unit configured to segment the provided bit sequence into a sequence of predetermined segments according to a predetermined bit length; and a coding device configured to code each segment into a respective sub-symbol using one coding unit per segment from among a plurality of coding units, wherein a subset of a first coding unit actively controls the signs of the disparities of the sub-symbols by inverting the disparities of the generated sub-symbols to compensate for the disparity of a subset of a second coding unit, and the juxtaposition of the sub-symbols results in an efficiently transmittable bit sequence.

[0076] The problem is also solved by a computer program product comprising control instructions for carrying out the proposed method or for operating the proposed apparatus. Advantageously, according to the present invention, the proposed devices and units can be operated using the present methods. Furthermore, the proposed devices and units are suitable for implementing the methods according to the present invention. The devices therefore implement structural features that are suitable for carrying out the corresponding methods. However, the structural features can also be designed as process steps. The proposed methods also provide steps for implementing the functions of the structural features. Also, physical components can be virtually provided or virtualized.

[0077] Further advantages, features, and details of the present invention will become apparent from the following description in which aspects of the present invention are described in detail with reference to the drawings. The features described in the claims and the specification may be important to the present invention individually or in any combination. Similarly, the features described above and further described herein may be used individually or in any combination. Functionally similar or identical parts or components may be designated by the same reference numerals. The terms "left," "right," "top," and "bottom" used in describing the embodiments refer to normally readable figure names or drawings with normally readable reference numerals in their orientation. The illustrated and described embodiments should not be understood as definitive, but are of an exemplary nature for describing the present invention. The detailed description is for the information of those skilled in the art; therefore, known circuits, structures, and methods are not shown or described in detail in the description so as not to complicate the understanding of the description. [Brief explanation of the drawings]

[0078] [Figure 1] FIG. 1 is a schematic flow chart of a method for generating an efficiently transmittable bit sequence with limited disparity and limited run length according to one embodiment of the present invention. [Figure 2] FIG. 2 shows a basic frame format and the application of a so-called block code according to one embodiment of the present invention. [Figure 3] FIG. 3 is a schematic diagram of the assembly and structure of a so-called block code according to a further embodiment of the present invention. [Figure 4] FIG. 4 is a schematic block diagram of a system apparatus for generating efficiently transmittable bit sequences having limited disparity and limited run length in accordance with a further embodiment of the present invention. [Figure 5] FIG. 5 is a schematic diagram of a frame format that may be used in accordance with the present invention. [Figures 6A-6D]6A, 6B, 6C, and 6D are exemplary encodings of data segments to symbols to optimize disparity in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0079] Some of the figures show parameters in English notation that are well known to those skilled in the art and that can be used as parameters and cannot be converted. FIG. 1 shows a schematic flow chart of an in-vehicle method for generating an efficiently transmittable bit sequence with constrained disparity and constrained run length, comprising: providing (100) an arbitrary bit sequence; segmenting (101) the provided bit sequence into a sequence of predetermined segments according to a predetermined bit length; and encoding (102) each segment into a respective sub-symbol using one encoding unit per segment from among a plurality of encoding units, wherein a subset of a first encoding unit actively controls the signs of the disparities of the generated sub-symbols by inverting the disparity of the generated sub-symbols to compensate for the disparity of a subset of a second encoding unit, and wherein juxtaposition of the sub-symbols results in an efficiently transmittable bit sequence.

[0080] Figure 2 shows a data format with an arbitrary bit string on the left and sub-symbols on the right. The data to be encoded has 112 bits, and each sub-symbol has 128 bits. In this way, an arbitrary bit string of 112 bits is encoded into a symbol with a total of 128 bits. The encoded 128 bits are optimized for disparity. The arrow in the center indicates that the encoding unit converts the data segment on the left into the sub-symbol on the right. The diagram also shows that this method can be used multiple times, meaning that any number of bit strings can be converted into any number of entire symbols. The data can also be divided into different data cells or data frames.

[0081] Even if the data on the left has the same semantic content as the data on the right, the data on the right is coded so that its disparity is optimized. In general, this method can be applied to any data, and therefore any bit string, and can transfer both user data and header data.

[0082] The data fields entered should be understood as merely examples and form an example of the application of the present invention. Figure 3 shows the central coding unit along with its input and output. The output data consists of 112 bits, here with indices 0 to 111. These are divided into segments with lengths of 11, 6, 7, or other lengths. In this example, these segments are converted into subsymbols with lengths of 12, 13, 8, or other lengths. The proposed example is advantageous because it encodes 112 bits into 128 bits, thereby achieving particularly high efficiency. The 128 bits have the same content as the bit string being encoded, but are 16 bits longer.

[0083] The diagram on the left shows that an arbitrary bit string of 112 bits is segmented into 11-bit data segments and then coded into 12 bits by coding units 11B12B.

[0084] Figure 4 shows an arbitrary bit string of 112 bits segmented into 11, 6, or 7 bits. Multiple encoding units are then addressed in parallel, converting the bits into subsymbols that are optimized for disparity. For example, 12 bits are coded and then 11 bits are encoded, or 13 bits are coded and then 11 bits are encoded.

[0085] In Figure 4, the coding unit from the second subset is shown at the center left and labeled 11B12B. It provides subsymbols with any code, i.e., any disparity. To compensate for this disparity, a coding unit 11B13B is connected downstream in parallel to the bit string. This means that a data stream is formed that converts the most significant bit of the 2 x 11 into two subsymbols. That is, 11B12B forms an 11-bit data segment, which is then converted into a 12-bit subsymbol with any code, i.e., any disparity, and the coding unit 11B13B encodes the data segment from 11 bits to 13 bits. In this figure, the second coding unit from the left, 11B13B, is the coding unit of the first subset. It includes an inverter and a multiplexer. The first 13 bits are available as a data stream, which is split so that one part is inverted with respect to code, i.e., disparity, and the other part is left unchanged. The leftmost encoding unit uses either a positive or negative (i.e., original or inverted) data stream with disparity feedback to compensate for the sign. Thus, the first multiplexer on the left has two data streams, each representing a subsymbol: one with the original sign (i.e., output from the 11B13B encoding unit) and one with the inverted sign or disparity.

[0086] Therefore, based on feedback from the upper unit, the disparity resulting from the leftmost encoder 11B12B is determined, and the lower left multiplexer compensates for or minimizes the disparity of the sub-symbols of the leftmost encoder 11B12B. This is done in parallel, with the encoding units from the second subset followed by the encoding units from the first subset that minimize or eliminate disparity. Finally, the entire symbol is output at the lower right. This entire symbol has 128 bits and is composed of multiple sub-symbols, as indicated by the bold lines below using diagonal arrows. This output line therefore contains multiple sub-symbols optimized or minimized in terms of disparity, forming the entire symbol, which can then be output and transmitted.

[0087] According to one aspect of the present invention, the present invention encodes 112-bit wide data words with any disparity (maximum disparity: 112) and any run length (maximum run length: 112) into 128-bit wide symbols, thus resulting in an overhead of 14.2%.

[0088] The maximum run length occurring within a symbol, as well as any sequence of any symbol, is 8 identical bits. The maximum disparity over the length average is 0. The disparity within a symbol is less than 9.

[0089] The logic complexity is minimal and comparable to ten 8B / 10B encoders (which have the well-known drawback of large overhead). This is achieved by the use or parallel use of multiple "mini" encoders that are optimally matched to each other in terms of disparity and run-length characteristics.

[0090] Encoders 11B12B, 7B8B, 6B8B generate all symbols with a guaranteed maximum run length of 6 in any (partial) symbol order. According to one aspect of the invention, the encoder (11B13B) generates symbols with a guaranteed maximum run length of 7, or at the beginning or end of a symbol, generates symbols with a maximum run length of 5. Due to the ordering of the encoder (11B13B) with other encoders (FIG. 2), a maximum run length of 8 can be generated in the symbol.

[0091] The encoder has the following characteristics: [11B13B] 11-bit data is mapped to 2048 symbols using 13 bits. · Symbols can be transmitted in inverted or non-inverted format. Disparity: +3 to +9 or variable -3 to -9 Run length in words: 7 Edge run length: 5 [11B13B] 11-bit data is mapped to 2048 symbols using 13 bits. · Symbols can be transmitted in inverted or non-inverted format. Disparity: +3 to +9 or variable -3 to -9 Run length in words: 7 Edge run length: 5 [11B12B] - 11-bit data is mapped to 2048 symbols using 12 bits. · Symbols are transmitted only non-inverted. Disparity: -2, -1, 0, 1, 2 Run length in words: 6 Edge run length: 3 [7B8B] - 7-bit data is mapped to 128 symbols using 8 bits. ·Transmit symbols only non-inverted. Disparity: -2, -1, 0, 1, 2 Run length in words: 6 Edge run length: 3 [6B8B] 6-bit data is mapped to 64 symbols with 8 bits. ·Transmit symbols only non-inverted. Disparity: 0 Run length in words: 6 Edge run length: 3 To compensate for the uncontrollable disparity of up to ±12 (6 × ±2) in the 11B12B and 7B8B encoders, four 11B13B encoders can be used to generate a controllable disparity of at least ±12, thereby reliably achieving balanced disparity regardless of the data being transmitted.

[0092] To further reduce the hardware complexity, according to one aspect of the present invention, four small encoders (11B13B) with controllable disparity with respect to sign (+-) are used.

[0093] According to one aspect of the invention, the disparity of a symbol is controlled so that each encoder calculates the parity of "its" sub-symbol, which is done with little effort since the sub-symbols only have a few bits.

[0094] Four of the eleven encoders can be used to actively control the sign of the disparity of the subsymbols by inverting the generated subsymbols. For this purpose, the encoders (11B13B) are characterized in that they generate symbols with positive disparity (+3 to +9) for all input data. By inverting the subsymbols, symbols with negative disparity (-3 to -9) are obtained.

[0095] This makes it possible to compensate for the disparity (-2, -1, 0, 1, 2) of the sub-symbols of the other encoders (11B12B and 7B8B). Encoder 6B8B generates symbols whose disparity is always 0. All (partial) parities of encoders (11B12B and 7B8B) are then added together and the result determines how many inverted and non-inverted symbols of encoder (11B13B) are used.

[0096] The minimum (smallest) disparity of encoder 11B13B is ±3. In total, a disparity of ±12 (4 × ±3) per symbol can be compensated with these four encoders.

[0097] Additionally, five (11B12B) encoders and one (7B8B) encoder are used, with a maximum disparity of ±2. Therefore, in the extreme case, these six encoders produce a disparity of exactly ±12 (2 × ±6), which can be easily compensated for by the 11B13B encoder.

[0098] According to one aspect of the invention, the method achieves the same quality as the 8B10B code, but with half the overhead (coding loss). The encoding and decoding hardware implementation requires minimal resources (logic) because it uses several small encoders instead of one large one.

[0099] Encoding can typically be done entirely in one cycle in a parallel data path (no pipelining is required). Controlling the disparity of a 128-bit symbol can be achieved with (very) little logic and can be achieved entirely within one clock (slow) of the data path, instead of calculating the disparity by counting 1 and 0 bits in the serial data stream using a very fast serial clock.

[0100] Due to the deterministic disparity and run length, no further scrambling is required, thus allowing fast synchronization to the data stream at the receiver (no scrambler synchronization is required).

[0101] Among other things, this is very useful for power-saving modes, where the link can be turned off to save energy and then turned back on when needed, for which fast synchronization between transmitter and receiver is essential.

[0102] According to one aspect of the present invention, the present invention encodes 112-bit wide data words with any disparity (maximum disparity: 112) and any run length (maximum run length: 112) into 128-bit wide symbols, thus resulting in an overhead of 14.2%.

[0103] The maximum run length occurring within a symbol, as well as any sequence of any symbol, is 8 identical bits. The maximum disparity over the length average is 0. The disparity within a symbol is less than 9.

[0104] The logic complexity is minimal and comparable to ten 8B / 10B encoders (which have the well-known drawback of large overhead). This is achieved by the use or parallel use of multiple "mini" encoders that are optimally matched to each other in terms of disparity and run-length characteristics.

[0105] Encoders 11B12B, 7B8B, 6B8B generate all symbols with a guaranteed maximum run length of 6 in any (partial) symbol order. According to one aspect of the invention, the encoder (11B13B) generates symbols with a guaranteed maximum run length of 7, or at the beginning or end of a symbol, generates symbols with a maximum run length of 5. Due to the ordering of the encoder (11B13B) with other encoders (FIG. 2), a maximum run length of 8 can be generated in the symbol.

[0106] The encoder has the following characteristics: To further reduce the hardware complexity, four small encoders (11B13B) with controllable disparity with respect to sign (+-) are used.

[0107] According to one aspect of the invention, the disparity of a symbol is controlled so that each encoder calculates the parity of "its" sub-symbol, which is done with little effort since the sub-symbols only have a few bits.

[0108] Four of the eleven encoders can be used to actively control the sign of the disparity of the subsymbols by inverting the generated subsymbols. For this purpose, the encoders (11B13B) are characterized in that they generate symbols with positive disparity (+3 to +9) for all input data. By inverting the subsymbols, symbols with negative disparity (-3 to -9) are obtained.

[0109] This makes it possible to compensate for the disparity (-2, -1, 0, 1, 2) of the sub-symbols of the other encoders (11B12B and 7B8B). Encoder 6B8B generates symbols whose disparity is always 0. All (partial) parities of encoders (11B12B and 7B8B) are then added together and the result determines how many inverted and non-inverted symbols of encoder (11B13B) are used.

[0110] The minimum (smallest) disparity of encoder 11B13B is ±3. In total, a disparity of ±12 (4 × ±3) per symbol can be compensated with these four encoders.

[0111] Additionally, five (11B12B) encoders and one (7B8B) encoder are used, with a maximum disparity of ±2. Therefore, in the extreme case, these six encoders produce a disparity of exactly ±12 (2 × ±6), which can be easily compensated for by the 11B13B encoder.

[0112] This method achieves the same quality as the 8B10B code, but with half the overhead (coding loss). The encoding and decoding hardware implementation requires minimal resources (logic) because it uses several small encoders instead of one large one.

[0113] Encoding can typically be done entirely in one cycle in a parallel data path (no pipelining is required). Controlling the disparity of a 128-bit symbol can be achieved with (very) little logic and can be achieved entirely within one clock (slow) of the data path, instead of calculating the disparity by counting 1 and 0 bits in the serial data stream using a very fast serial clock.

[0114] Due to the deterministic disparity and run length, no further scrambling is required, thus allowing fast synchronization to the data stream at the receiver (no scrambler synchronization is required).

[0115] Among other things, this is very useful for power-saving modes, where the link can be turned off to save energy and then turned back on when needed, for which fast synchronization between transmitter and receiver is essential.

[0116] Figure 5 shows a data format that may be used, for example, in Figures 2, 3, and / or 4. Similarly, a 128-bit full symbol and a 112-bit arbitrary data string are shown. Overall, the arbitrary bit string and full symbol may have different header or frame data.

[0117] The following describes several specific possibilities for converting segments of any bit string into subsymbols to minimize or eliminate disparity. The first table shows a 6-bit to 8-bit conversion, the second table shows a 7-bit to 8-bit conversion, the third table shows an 11-bit to 12-bit conversion, and the fourth table shows an 11-bit to 13-bit conversion. Thus, 6-, 7-, or 11-bit segments are converted into 8-, 12-, or 13-bit subsymbols. The illustrated encoding is illustrative and demonstrates the technical effect achieved in this case. Using the proposed encoding, empirically evaluated, the present invention achieves that 112 bits are optimized with respect to their disparity, so that only 128 bits are required. This corresponds to a so-called overhead of only 14%. In this case, cell is used as a synonym for frame. These may also be packages.

[0118] <Cell format / frame format> According to one aspect of the invention, a cell includes a header having a fixed bit length, a payload area having four selectable bit lengths, and a footer also having a fixed bit length.

[0119] The cell structure is a string of bits as follows: · A 7-bit virtual path identifier (VP) that represents the unique address of the virtual path. A 3-bit column number (SN) that numbers cells consecutively in their column. A 2-bit wide cell type (CT) identifier that specifies the length of the user data. Payload Information (PI), a 3-bit wide string containing additional information about the payload. This may also be used to synchronize payload data with frame or control data. A 10-bit wide CRC polynomial (HCRC) for error protection of the header information. This polynomial has a Hamming distance of 5 to a 21-bit (P=0x2B9) bit string. The payload (PL) ranges from 187 bits, 411 bits, 635 bits, or 859 bits in length depending on the CT value. The shortest payload is chosen to be even larger than the maximum supported (video) streaming bus width (which should simplify the mapping of streaming data to cell payloads). Finally, a 12-bit wide CRC polynomial (PCRC) for error protection of user data. This polynomial has a Hamming distance of 4 up to a bit string of 2035 bits (P=0x8F3).

[0120] <Transmission frame format> According to one aspect of the present invention, a transmission frame includes a sequence of M-bit wide words. The frame starts with an M-bit wide "comma" word from a sequence of comma words defined for frame alignment. This is followed by K cells. A cell consists of 2, 4, 6, or 8 N-bit wide words that carry a header, payload, and footer. These N-bit wide words are encoded into M-bit wide symbols (line encoding).

[0121] This format is chosen to allow the cell data to be processed at the appropriate time frequency, provided that the serializer / deserializer always processes blocks of M bits.

[0122] 6A shows a portion of an exemplary encoding of a data segment into symbols, where 6 bits are encoded into 8 bits to optimize disparity in accordance with one aspect of the present invention. For example, the segment 000000 is encoded into the sub-symbol 00101011, i.e., a 6B8B encoder.

[0123] Furthermore, FIG. 6B shows a 7B8B encoder, FIG. 6C shows a 11B12B encoder, and FIG. 6D shows a 11B13B encoder.

Claims

1. 1. A method in a motor vehicle for generating an efficiently transmittable bit sequence having limited disparity and limited run length, comprising: providing (100) an arbitrary bit string; Segmenting (101) the provided bit string into a sequence of predetermined segments according to a predetermined bit length; encoding (102) each segment into a respective subsymbol using one coding unit per segment from among a plurality of coding units; wherein a subset of first coding units actively controls the signs of the generated sub-symbol disparities by inverting the disparities of the sub-symbols to compensate for the disparity of a subset of second coding units that is not controllable depending on the entire symbols already transmitted, thereby minimizing the disparity of the entire symbols, and the juxtaposition of the sub-symbols results in the efficiently transmittable bit sequence.

2. 2. The method of claim 1, wherein the arbitrary bit string is not restricted in disparity and run length of the bit string.

3. 2. The method of claim 1, wherein the active control of the code is performed by bitwise conditional inversion of symbols.

4. 4. A method according to claim 1, wherein the inversion is performed conditionally depending on the disparity of the entire symbol formed from all sub-symbols.

5. 5. The method of claim 4, wherein the dependence is affected such that the disparity magnitude value is minimized.

6. 6. The method of claim 5, wherein the magnitude value is minimized so that the positive disparity of the entire symbol is cancelled by the negative parity of the sub-symbol.

7. 6. The method of claim 5, wherein the magnitude value is minimized so that negative disparity of an entire symbol is cancelled by positive parity of the sub-symbol.

8. 4. The method according to claim 1, wherein the first subset of coding units encodes 11-bit segments into 13-bit sub-symbols.

9. 4. The method of claim 1, wherein the subset of first coding units has a disparity between +3 and +9, which is inverted to -3 to -9 by bit reversal of the sub-symbols.

10. 4. The method according to claim 1, wherein the run length in the sub-symbols is a maximum of 7.

11. 4. The method according to claim 1, wherein the run length of the sub-symbols in the subset of the first coding unit is at most 5, starting from the most significant bit and / or the least significant bit.

12. 4. The method according to claim 1, wherein the second subset of coding units encodes 11-bit segments into 12-bit sub-symbols, or 7-bit segments into 8-bit sub-symbols, or 6-bit segments into 8-bit sub-symbols.

13. 4. The method according to claim 1, wherein a disparity between -2 and +2 is generated in the second subset of coding units.

14. 4. The method according to claim 1, wherein the generated sub-symbols in the subset of second coding units have a run length of six.

15. 4. The method according to claim 1, wherein the second subset of coding units generates sub-symbols with a maximum run length of 3 at the edges.

16. 4. The method according to claim 1, wherein the coding units are addressed in parallel, each coding unit coding a segment into sub-symbols.

17. 4. The method according to claim 1, wherein the plurality of coding units are addressed in a sequence of 212122221212, where 1 represents a subset of the first coding unit and 2 represents a subset of the second coding unit.

18. 4. The method according to claim 1, wherein, when there are positive and negative data streams with respect to the disparity, a data stream that contributes to minimizing all disparities of the entire symbol is selected by a multiplexer.

19. 1. A system apparatus in a motor vehicle for generating an efficiently transmittable bit sequence having limited disparity and limited run length, comprising: an interface unit configured to provide (100) an arbitrary bit sequence; a segmentation unit configured to segment (101) the provided bit sequence into a sequence of predetermined segments according to a predetermined bit length; a coding device configured to encode (102) each segment into a respective subsymbol using one coding unit per segment from among a plurality of coding units; a subset of first coding units actively controls the signs of the generated sub-symbol disparities by inverting the disparities of the sub-symbols to compensate for the disparities of the non-controllable subset of second coding units depending on the entire symbols already transmitted, thereby minimizing the disparity of the entire symbols, and the juxtaposition of the sub-symbols results in the efficiently transmittable bit sequence.

20. A computer program comprising instructions which, when executed by at least one computer, cause said computer to carry out the steps of the method according to any one of claims 1 to 3.

21. 4. A computer readable storage medium comprising instructions which, when executed by at least one computer, cause said computer to perform the steps of the method of any one of claims 1 to 3.

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