Vertical Bipolar Junction Transistor

Abstract

The vertical bipolar junction transistor includes an intrinsic base epitaxially grown on a first emitter or collector, the intrinsic base being compositionally graded, a second collector or emitter formed on the intrinsic base, and an extrinsic base formed all around the intrinsic base. The extrinsic base is separated from the first emitter or collector by a first spacer. The extrinsic base is separated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base is doped with a p-type dopant, and the first emitter or collector and the second collector or emitter are doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter are fabricated from III-V semiconductor materials.

Description

[Technical Field]

[0001] The present invention relates generally to semiconductor structures and methods of forming the same, and more particularly to semiconductor structures including vertical bipolar junction transistors (BJTs) with an all-around extrinsic base and an epitaxially grown compositionally graded intrinsic base. [Background technology]

[0002] Bipolar transistors constructed from compound semiconductors can enable a wide range of applications. Bipolar transistors can be used as high-speed devices based on narrow-bandgap semiconductor materials. Bipolar transistors can also be used as high-voltage devices based on wide-bandgap semiconductor materials. Summary of the Invention

[0003] According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a vertical bipolar junction transistor. The vertical bipolar junction transistor may include an intrinsic base epitaxially grown and compositionally graded on a first emitter or collector, a second collector or emitter formed on the intrinsic base, and an extrinsic base formed around the entire periphery of the intrinsic base. The extrinsic base may be separated from the first emitter or collector by a first spacer. The extrinsic base may be separated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector and the second collector or emitter may be doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter may be fabricated from III-V semiconductor materials.

[0004] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a vertical bipolar junction transistor. The vertical bipolar junction transistor may include an intrinsic base epitaxially grown on a first emitter or collector, which may be compositionally graded; an isolation layer isolating the first emitter or collector from the substrate; a second collector or emitter formed on the intrinsic base; and an extrinsic base formed around the entire periphery of the intrinsic base. The extrinsic base may be separated from the first emitter or collector by a first spacer, and the extrinsic base may be separated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector and the second collector or emitter may be doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter may be fabricated from III-V semiconductor materials.

[0005] According to another embodiment of the present invention, a method is provided. The method may include epitaxially growing an intrinsic base on a first emitter or collector, epitaxially growing a second collector or emitter on the intrinsic base, and epitaxially growing an extrinsic base around the entire periphery of the intrinsic base to form a vertical bipolar junction transistor. The extrinsic base may be separated from the first emitter or collector by a first spacer. The extrinsic base may be separated from the second collector or emitter by a second spacer. The intrinsic base may be compositionally graded. The compositionally graded intrinsic base may be fabricated from indium aluminum gallium arsenide. Compositionally grading the intrinsic base may include increasing the aluminum content and decreasing the gallium content in the intrinsic base. Increasing the aluminum content and decreasing the gallium content in the intrinsic base may widen the bandgap of the intrinsic base. The bandgap of the intrinsic base may be smaller in the gallium-rich, aluminum-poor portion of the intrinsic base. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector and second collector or emitter may be doped with an n-type dopant.

[0006] The following detailed description is given by way of example and is not intended to be limiting of the invention solely thereto and will be best understood in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view illustrating an emitter, a sacrificial layer, and a first dielectric layer disposed on a substrate according to an exemplary embodiment. [Figure 2] 1 is a cross-sectional view illustrating a trench formed to expose an emitter according to an illustrative embodiment. [Figure 3] FIG. 10 is a cross-sectional view of an intrinsic base in accordance with an illustrative embodiment. [Figure 4]FIG. 4 is a cross-sectional view illustrating a first mask formed on top of a second dielectric layer according to an exemplary embodiment. [Figure 5] 1 is a cross-sectional view illustrating a first dielectric layer, a second dielectric layer, a second spacer, and a portion of a sacrificial layer removed according to an illustrative embodiment. [Figure 6] FIG. 10 is a cross-sectional view illustrating the exposed sidewalls of the intrinsic base after the sacrificial layer has been removed in accordance with an illustrative embodiment. [Figure 7] FIG. 1 is a cross-sectional view illustrating an extrinsic base surrounding an intrinsic base according to an illustrative embodiment. [Figure 8] 10A-10C are cross-sectional views illustrating etching a portion of the extrinsic base and depositing an interlayer dielectric in accordance with an illustrative embodiment. [Figure 9] FIG. 10 is a cross-sectional view illustrating removing the first mask to expose the top surface of the second dielectric layer according to an illustrative embodiment. [Figure 10] 5A-5C are cross-sectional views illustrating forming openings in first and second dielectric layers according to an illustrative embodiment. [Figure 11] 10A-10C are cross-sectional views illustrating forming a collector according to an exemplary embodiment. [Figure 12] FIG. 10 is a cross-sectional view illustrating depositing a second interlayer dielectric on top of the collector according to an illustrative embodiment. [Figure 13a] 10A-10C are cross-sectional views illustrating forming contacts according to an illustrative embodiment. [Figure 13b] FIG. 10 is a top view of a contact according to an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to depict specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbers represent like elements.

[0009] Although detailed embodiments of the claimed structures and methods are disclosed herein, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In this specification, detailed descriptions of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0010] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof, refer to the disclosed structures and methods as oriented in the drawings. The terms "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is on a second element, such as a second structure, although there may be an intervening element, such as an interfacial structure, between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intervening conductive, insulating, or semiconducting layer at the interface between the two elements.

[0011] In the following detailed description, some process steps or operations known in the art may be combined together for purposes of illustration and description, and in some instances may not be described in detail, so as not to obscure the presentation of embodiments of the present invention. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description will focus heavily on the distinctive features or elements of various embodiments of the present invention.

[0012] FIELD OF THE INVENTION Embodiments of the present invention generally relate to semiconductor structures and methods of forming the same. More particularly, the present invention relates to a semiconductor structure including a vertical bipolar junction transistor (BJT) with an all-around extrinsic base and an epitaxially grown compositionally graded intrinsic base.

[0013] A bipolar junction transistor (BJT) is a type of transistor that uses both electrons and holes as charge carriers, allowing a small current injected into one of its terminals to control a much larger current flowing between the other two terminals, resulting in the device being capable of amplification or switching.

[0014] A conventional vertical BJT may include a compound semiconductor stack composed of various semiconductor layers with different bandgaps. Once the semiconductor stack is formed, it may be patterned in a step-like fashion using a selective etchant to create the necessary contacts. As a result, the top stack has a tapered structure, with the top being narrower than the middle, which is narrower than the bottom. This can result in area being consumed by the contacts, reducing device density. Furthermore, the etching process used to form the contacts can damage the sidewalls of the stack. Furthermore, the lateral separation between the contacts and the active region of a vertical BJT increases contact resistance. Therefore, there is a need to form a dense vertical BJT with low contact resistance and substantially undamaged sidewalls.

[0015] Embodiments of the present invention propose a vertical BJT with a full-periphery extrinsic base associated with the intrinsic base. More specifically, embodiments of the present invention propose an extrinsic base surrounding the intrinsic base, the extrinsic base having a wider bandgap than the bandgap of the intrinsic base. Placing the full-periphery extrinsic base surrounding the intrinsic base reduces base leakage, lowers contact resistance, and improves electrical control of the intrinsic base. Furthermore, embodiments of the present invention allow contacts to be formed without damaging the sidewalls of the intrinsic and extrinsic bases.

[0016] 1-13 illustrate an exemplary structure of a vertical BJT with a full-circumference extrinsic base and an epitaxially grown compositionally graded intrinsic base, as well as a method of fabricating the same, according to one embodiment. It will be understood that, as is known in the art, the designations of the emitter and collector terminals depend on the polarity of the voltages applied to the bipolar transistor during operation. For example, in an npn transistor, the collector is biased with a positive voltage polarity relative to the emitter, and in a pnp transistor, the collector is biased with a negative voltage polarity relative to the emitter. Thus, depending on the polarity of the voltages applied to the bipolar transistor, the emitter (e.g., 106 in FIGS. 1-13) can function as the collector, and the collector (e.g., 134 in FIGS. 11-13) can function as the emitter. Therefore, the designations of the regions and terminals as emitter or collector (e.g., 106 and 134) are interchangeable.

[0017] Referring now to FIG. 1 , a structure 100 is shown according to one embodiment. The structure 100 may include a substrate 102, an isolation layer 104, an emitter 106, a first spacer 108, a sacrificial layer 110, a second spacer 112, and a first dielectric layer 114. The substrate 102 may include one or more semiconductor materials. For example, in one embodiment, the substrate 102 may be an indium phosphide wafer. In another embodiment, the substrate 102 may be fabricated from a III-V material, such as gallium arsenide, indium arsenide, or aluminum arsenide, with a top surface fabricated from indium phosphide. In a further embodiment, the substrate 102 may be a silicon wafer with a buffer layer of a III-V material and a top surface of indium phosphide. In yet another embodiment, the substrate 102 is a semiconductor material that allows for the lattice-matched formation of the described device structures. BJTs can also be formed using combinations of silicon, silicon-germanium (SiGe), and / or germanium. Additionally, gallium arsenide and germanium or other lattice-matched semiconductor equivalents can be used.

[0018] Isolation layer 104 is grown on the top surface of substrate 102 and, in some embodiments, may have a thickness between 50 and 100 nm. Isolation layer 104 is composed of a semi-insulating semiconductor with a wide bandgap and a low doping concentration. In one exemplary embodiment in which the top surface of substrate 102 is composed of indium phosphide, isolation layer 104 is made of indium aluminum arsenide (InAu), which is lattice matched to indium phosphide and has a wider bandgap than indium phosphide. 0.52 Al 0.48 In a preferred embodiment, the isolation layer 104 is substantially undoped and has a wider bandgap than the substrate 102.

[0019] Once the isolation layer 104 is grown to a desired thickness, the emitter 106 is then grown on top of the isolation layer 104. The emitter 106 may be referred to as the first emitter or collector 106. In some embodiments, the emitter 106 may have a thickness in the range of 10-50 nm, although thinner or thicker layers may also be used. The emitter 106 is heavily doped in-situ with an n-type dopant, such as tellurium. In an exemplary embodiment where the isolation layer 104 is fabricated from indium aluminum arsenide, the emitter 106 is fabricated from indium gallium aluminum arsenide by epitaxial growth. The bandgap is determined by the indium gallium aluminum arsenide (In 0.53 Ga 0.47 A composition is chosen that is slightly larger than the bandgap of indium gallium aluminum arsenide, but sufficiently conductive. One exemplary composition of indium gallium aluminum arsenide is In 0.53 Al 0.02 Ga 0.45 Other lattice-matched InGaAlAs compositions that meet the above application requirements can be selected. The aluminum content can be from 1 to a maximum of 10%.

[0020] To form the InGaAlAs, indium, gallium, and aluminum epitaxial precursors are co-flowed into a process reactor along with an arsenic source. The ratios of the In, Ga, and Al sources, as well as the process conditions, define the growth composition. The indium source can be trimethylindium (TMIn), the gallium source can be trimethylgallium (TMGa), and the aluminum source can be trimethylaluminum (TMAl). The arsenic source can be an organo-arsenic metal compound such as arsine (AsH) or tertiarybutylarsine (TBAs). In some embodiments, the emitter 106 has a bottom portion heavily doped with an n-type dopant (to reduce series resistance) and a top portion moderately doped with, for example, an n-type dopant, along with a relatively light doping of the same type (to suppress Auger recombination). In another exemplary embodiment in which the substrate is composed of semi-insulating gallium arsenide, the emitter 106 is composed of epitaxially grown heavily doped n-type gallium arsenide or indium gallium arsenide.

[0021] Next, a sacrificial layer 110 is deposited on the emitter 106 between the first spacer 108 and the second spacer 112. The first spacer 108 is deposited on the emitter 106, the sacrificial layer 110 is deposited on the first spacer 108, and the second spacer 112 is deposited on the sacrificial layer 110. The first spacer 108 may also be referred to as a bottom spacer. The second spacer 112 may also be referred to as a top spacer.

[0022] The first spacer 108 and the second spacer 112 may include an insulating material such as, for example, silicon dioxide, silicon nitride, SiOCN, or SiBCN. Other non-limiting examples of the material of the first spacer 108 and the second spacer 112 may include a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The material of the first spacer 108 and the second spacer 112 is deposited by a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The first spacer 108 and the second spacer 112 may each have a thickness of about 3 to about 15 nm, or about 5 to about 10 nm.

[0023] The sacrificial layer 110 may include a sacrificial gate material, such as amorphous silicon (α-Si) or polycrystalline silicon (polysilicon). The sacrificial material may be deposited by a deposition process, including, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof. The sacrificial material forming the sacrificial layer 110 may have a thickness of about 8 nm to about 100 nm, or about 10 nm to about 30 nm.

[0024] The first dielectric layer 114 is deposited on the top surface of the second spacer 112, which is on the sacrificial layer 110. The first dielectric layer 114 may also be referred to as an oxide layer. Non-limiting examples of materials for the first dielectric layer 114 may include silicon dioxide, tetraethyl orthosilicate (TEOS) oxide, high aspect ratio plasma (HARP) oxide, high temperature oxide (HTO), high density plasma (HDP) oxide, oxide formed by an atomic layer deposition (ALD) process (e.g., silicon oxide), or any combination thereof. The first dielectric layer 114 may have a thickness ranging from about 30 nm to about 200 nm, or from about 50 nm to about 100 nm. After the first dielectric layer 114 is deposited, the structure 100 may be treated with a planarization process, such as a chemical mechanical polishing (CMP) process, to smooth the top surface of the first dielectric layer 114.

[0025] Referring now to FIG. 2 , a structure 100 is shown having a trench 116, according to one embodiment. The trench 116 extends from the top surface of the first dielectric layer 114 to the emitter 106, exposing the top surface of the emitter 106. The trench 116 is formed by performing one or more etching processes that are selective to (do not substantially remove) and stop at the material of the emitter 106. The etching process may be, for example, reactive ion etching. For example, a first etching process that is selective to the material of the first spacer 108 may be performed to remove the first dielectric layer 114, the second spacer 112, and a portion of the sacrificial layer 110.

[0026] Once the top surface of the first spacer 108 is exposed, the exposed sidewall portions of the second spacer 112 and the exposed sidewall portions of the sacrificial layer 110 are oxidized. This oxidation allows a layer of oxide 118 to form along the exposed sidewalls of the sacrificial layer 110 and the second spacer 112. This oxidation may be performed by a plasma oxidation process or other oxidation process to form the layer of oxide 118. A second etching process is performed to remove the exposed portions of the first spacer 108 and expose the top surface of the emitter 106. The resulting trench 116 may extend through the top surface of the first dielectric layer 114 to the top surface of the exposed portion of the emitter 106.

[0027] 3, a structure 100 having an intrinsic base 120 is shown, according to one embodiment. Once the first spacers 108 are removed from the bottom of the trench 116, an epitaxial layer is grown on the exposed top surface of the emitter 106 to form the intrinsic base 120. The intrinsic base 120 may be grown using any suitable growth process, such as chemical vapor deposition (CVD) (liquid phase (LP) or reduced pressure chemical vapor deposition (RPCVD)), vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), metalorganic chemical vapor deposition (MOCVD), or other suitable process.

[0028] The intrinsic base 120 has a lattice constant that is the same or substantially the same as the lattice constant of the emitter 106. Furthermore, the composition of the intrinsic base 120 is varied (i.e., graded) during epitaxial growth to achieve a graded bandgap. In one example, the intrinsic base 120 may comprise indium aluminum gallium arsenide, and as known in the art and described herein with respect to FIG. 1 , the bandgap of the intrinsic base 120 may be gradually widened during epitaxial growth by gradually increasing the aluminum content and gradually decreasing the gallium content while maintaining substantially the same lattice constant. Thus, the bottom portion of the intrinsic base 120 closest to the emitter 106 contains more gallium and less aluminum than the top portion of the intrinsic base 120 closest to the top surface of the first dielectric layer 114. Because the bottom of the intrinsic base 120 contains more gallium and less aluminum than the top of the intrinsic base 120, the bottom of the intrinsic base 120 has a smaller bandgap than the top of the intrinsic base 120. The aluminum and gallium composition varies within the intrinsic base 120, creating a compositional gradient within the intrinsic base 120. As known in the art, a gradually varying (i.e., graded) bandgap profile can be beneficial for promoting carrier transport efficiency in the base compared to an abruptly varying bandgap profile. In another embodiment, when the emitter 106 functions as a collector, the top of the intrinsic base 120 can contain more gallium and less aluminum than the bottom of the intrinsic base 120. As a result, the top of the intrinsic base 120 can have a smaller bandgap than the bottom of the intrinsic base 120.

[0029] The intrinsic base 120 is doped in-situ with a p-type dopant, such as magnesium. The dopant of the intrinsic base 120 is different from the dopant of the emitter 106. For example, if the emitter 106 is doped with an n-type dopant, the intrinsic base 120 is doped with a p-type dopant. Furthermore, the doping levels are also different. For example, the emitter 106 may be heavily doped with an n-type dopant, while the intrinsic base 120 may be moderately or lightly doped with a p-type dopant. The doping of the intrinsic base 120 may be kept at a substantially constant level during epitaxial growth or may be varied (graded) as desired.

[0030] During the growth process, the epitaxial growth of the intrinsic base 120 may extend vertically beyond the top of the first dielectric layer 114 (not shown). A planarization process, such as a chemical-mechanical polishing (CMP) process, may be used to remove the epitaxial overgrowth above the first dielectric layer 114. As a result, the top surface of the intrinsic base 120 is substantially coplanar with the top surface of the first dielectric layer 114.

[0031] 4, structure 100 is shown with a second dielectric layer 122 and a first mask 124, according to one embodiment. Second dielectric layer 122 is deposited on the top surface of first dielectric layer 114 and intrinsic base 120 using known deposition techniques, such as atomic layer deposition. Second dielectric layer 122 may be fabricated from the same or substantially the same material as that of first dielectric layer 114. A planarization process, such as CMP, may be used after deposition of second dielectric layer 122 to remove excess second dielectric layer 122 from the top surface of structure 100.

[0032] The first mask 124 is deposited on the top surface of the second dielectric layer 122 such that a portion of the first mask 124 overlaps and extends beyond the intrinsic base 120, such that the first mask 124 covers more of the intrinsic base 120 than the intrinsic base 120. The first mask 124 is deposited using known deposition techniques, such as atomic layer deposition. The first mask 124 may be fabricated from a material that is resistant to various etching processes, thereby protecting the portions of the structure 100 covered by the first mask 124 during subsequent etching processes.

[0033] 5, structure 100 is shown with portions of first dielectric layer 114, second dielectric layer 122, second spacer 112, and sacrificial layer 110 removed, according to one embodiment. After first mask 124 is formed, an etching process, such as a reactive ion etch process, is used to recess portions of second dielectric layer 122, first dielectric layer 114, second spacer 112, and sacrificial layer 110. Sacrificial layer 110 is recessed sufficiently to not expose the top surfaces of first spacers 108. As a result, portions of sacrificial layer 110 remain along the top surfaces of first spacers 108.

[0034] 6, structure 100 is shown with the sidewalls of intrinsic base 120 exposed, according to one embodiment. Substantially all of sacrificial layer 110 and oxide layer 118 are removed. A first etching process, such as a wet etching process, may be used to remove sacrificial layer 110, thereby exposing the top surfaces of first spacers 108, the bottom surfaces of second spacers 112, and oxide layer 118 (shown in FIGS. 2-5). Another etching process, such as a buffered oxide etch or another form of isotropic etch, may be used to remove oxide layer 118, thereby exposing the sidewalls of intrinsic base 120.

[0035] 7, a structure 100 with an extrinsic base 126 is shown, according to one embodiment. A large-grain polycrystalline epitaxial layer is grown on the exposed top surface of the first spacer 108 and along the exposed sidewalls of the intrinsic base 120 to form the extrinsic base 126. The extrinsic base 126 may be grown using any suitable growth process, such as chemical vapor deposition (CVD) (liquid phase (LP) or reduced-pressure chemical vapor deposition (RPCVD)), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), metalorganic chemical vapor deposition (MOCVD), or other suitable process. The extrinsic base 126 may be composed of a compound semiconductor, such as a III-V material, or an elemental semiconductor, such as polysilicon.

[0036] The extrinsic base 126 is highly doped in situ with a p-type dopant, such as magnesium for compound semiconductors or boron for polysilicon. The extrinsic base 126 is doped with the same dopant type as the intrinsic base 120. The extrinsic base 126 typically contains a higher level of dopant than the intrinsic base 120 to facilitate the formation of a low-resistance extrinsic contact and to suppress base recombination current (and therefore base leakage) by repelling minority carriers. The all-around extrinsic base 126 is advantageous for reducing base access resistance and improving electrostatic control relative to the intrinsic base 120. In some embodiments, the extrinsic base 126 has a wider bandgap compared to the intrinsic base 120, which is advantageous for repelling minority carriers and therefore suppressing base leakage.

[0037] 8, a structure 100 is shown having a first interlayer dielectric (ILD) 128, according to one embodiment. The structure 100 with the extrinsic base 126 formed thereon is subjected to an etching process, such as a reactive ion etching process, to remove the portion of the extrinsic base 126 that extends beyond the first mask 124 and expose a portion of the top surface of the first spacer 108. The first ILD 128 may be deposited over the exposed portion of the top surface of the first spacer 108.

[0038] The first ILD 128 is deposited such that the top surface of the first ILD 128 is substantially coplanar with the top surface of the mask 124. The first ILD 128 may be formed from a low-k dielectric material (having k<4.0), including, but not limited to, silicon oxide, spin-on glass, flowable oxide, high-density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The first ILD 128 is deposited by a deposition process, including, but not limited to, CVD, PVD, plasma-enhanced CVD, atomic layer deposition (ALD), evaporation, chemical solution deposition, or a similar process. After the first ILD 128 is deposited, a planarization process, such as a CMP process, may be used to remove excess first ILD 128 from the top surface of the structure 100.

[0039] 9, structure 100 is shown with first mask 124 removed, according to one embodiment. First mask 124 is removed using known techniques to expose the top surface of second oxide layer 122. After first mask 124 is removed, an optional planarization process, such as a CMP process, may be used to remove traces of first mask 124 from the top surface of second oxide layer 122.

[0040] 10 , a structure 100 having an opening 132 is shown, according to one embodiment. A second mask 130 is deposited using a known deposition technique, such as atomic layer deposition. The second mask 130 may be fabricated from the same or substantially the same material as the first mask 124. Next, the top portion of the second dielectric layer 122 over the intrinsic base 120 is removed using a known patterning technique (e.g., using patterned photoresist as an etch mask). The second mask 130 protects the portion of the structure 100 covered by the second mask 130 from damage during subsequent fabrication processes.

[0041] After the second mask 130 is deposited, an etching process, such as a reactive ion etching process, is used to remove the portions of the second dielectric layer 122 that are not covered by the second mask 130. The etching process also removes a portion of the first dielectric layer 114 to form an opening 132, exposing the top surface of the second spacer 112. The opening 132 extends from the top surface of the second mask 130 to the top surface of the second spacer 112. The opening 132 is wider than the intrinsic base 120 and encompasses it.

[0042] 11 , a structure 100 having a collector 134 is shown, according to one embodiment. A single-crystalline layer or a large-grain polycrystalline layer is epitaxially grown on the exposed top surfaces of the intrinsic base 120 and the second spacer 112 to form the collector 134. The collector 134 may be grown using any suitable growth process, such as chemical vapor deposition (CVD) (liquid phase (LP) or reduced-pressure chemical vapor deposition (RPCVD)), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), metalorganic chemical vapor deposition (MOCVD), or other suitable process. The collector 134 may be fabricated from indium aluminum arsenide, indium phosphide, or indium gallium phosphide in some embodiments.

[0043] The collector 134 is heavily doped with an n-type dopant, such as tellurium. The collector 134 may be doped with the same dopant as the emitter 106, but with a different dopant than the intrinsic base 120 and the extrinsic base 126. In some embodiments, the collector 134 has a top portion heavily doped with an n-type dopant (e.g., to reduce series resistance) and a bottom portion moderately doped with an n-type dopant, for example, with a relatively low doping of the same type (e.g., to suppress Auger recombination). In one embodiment, the collector 134 and the emitter 106 may be heavily doped with an n-type dopant, while the intrinsic base 120 and the extrinsic base 126 may be doped with a p-type dopant, such as magnesium. Furthermore, the extrinsic base 126 may be doped to a higher level, while the intrinsic base 120 may be doped to a lower level. In one embodiment, the collector 134 may be referred to as a second emitter or collector 134 .

[0044] 12 , a structure 100 is shown having a second interlayer dielectric (ILD) 136, according to one embodiment. Once the collector 134 is epitaxially grown, the second mask 130 is removed. An optional planarization process, such as a CMP process, may be used to remove all traces of the second mask 130 from the second oxide layer 122 and the top surface of the first ILD 128. The second ILD 136 may be deposited such that the top surface of the collector 134 is completely covered by the second ILD 136. The second ILD 136 may be fabricated from the same or substantially the same material as the first ILD 128. The second ILD 136 is deposited by a deposition process, including, but not limited to, CVD, PVD, plasma-enhanced CVD, atomic layer deposition (ALD), evaporation, chemical solution deposition, or similar processes. After second ILD 136 is deposited, a planarization process, such as a CMP process, may be used to remove excess second ILD 136 from the top surface of structure 100.

[0045] Referring now to FIG. 13a, a structure 100 is shown having a collector contact 138 and an extrinsic base contact 140, according to one embodiment. The collector contact 138 extends through the second ILD 136 to the collector 134 and is formed in a trench. A resist, such as photoresist, may be deposited and patterned to remove the second ILD 136 and form the collector contact trench. An etching process, such as reactive ion etching (RIE), may be performed using the patterned resist as an etch mask to remove the second ILD 136 until the collector 134 is exposed. The collector contact trench is filled with a conductive material or a combination of conductive materials to form the collector contact 138. The conductive material filling may be a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material may be deposited by any suitable deposition process, such as, for example, CVD, PECVD, PVD, plating, thermal or electron beam evaporation, or sputtering. A planarization process, such as CMP, is performed to remove all conductive material from the surface of second ILD 136.

[0046] The extrinsic base contact 140 extends from the surface of the second ILD 136, through the second dielectric layer 122, the first dielectric layer 114, the second spacer 112, and to the extrinsic base 126. The extrinsic base contact 140 is formed by patterning a trench in the second ILD 136. A resist, such as photoresist, may be deposited and patterned to remove the second ILD 136, the second dielectric layer 122, the first dielectric layer 114, the second spacer 112, and the extrinsic base 126 to form the extrinsic base contact trench. Using the patterned resist as an etch mask, an etching process, such as RIE, may be performed to remove the second ILD 136, the first and second dielectric layers 114, 122, and the second spacer 112 until the extrinsic base 126 is exposed. The base contact trench is filled with a conductive material or a combination of conductive materials to form the extrinsic base contact 140. The conductive material may be a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or electron beam evaporation, or sputtering. A planarization process, such as CMP, is performed to remove all conductive material from the surface of the second ILD 136.

[0047] 13b, a top view of structure 100 is shown with collector contact 138, extrinsic base contact 140, and emitter contact 142, according to one embodiment. Emitter contact 142 is formed above and in direct contact with emitter 106. Emitter contact 142 may be fabricated from a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof.

[0048] As shown in FIGS. 13a-13b, the resulting structure 100 comprises a vertical compound semiconductor BJT with a full-circumference extrinsic base 126 surrounding a graded intrinsic base 120. Forming the entire BJT structure by epitaxial growth allows each epitaxially grown layer, such as the emitter 106, intrinsic base 120, extrinsic base 126, and collector 134, to have a bandgap that can be precisely controlled and gradually varied (i.e., graded) as desired during epitaxial growth. Additionally, each of the epitaxially grown layers can be doped with various dopants and various doping levels, which can also be varied as desired during epitaxial growth. This allows for custom tuning of the BJT for a wide range of applications, including high-speed devices based on narrow-bandgap semiconductor materials and high-voltage devices based on wide-bandgap semiconductor materials. The emitter 106, intrinsic base 120, and collector 134 may be fabricated from III-V semiconductor materials. While the exemplary embodiment described with respect to Figures 1-13 is an npn bipolar transistor, it will be understood that a pnp bipolar transistor may be formed in a similar manner by reversing the doping types.

[0049] Surrounding the intrinsic base 120 with the extrinsic base 126 reduces the base access resistance and improves the electrostatic characteristics of the device. Additionally, embodiments of the present invention eliminate the need for sidewall etching, i.e., stepwise tapering or stepwise patterning of the device layers, to create access regions for contact formation to different layers, thereby enabling the fabrication of high-density vertical transistors with a full-circumference extrinsic base 126. By eliminating sidewall etching, sidewall etch damage is also eliminated, and therefore the recombination current and resulting leakage associated with sidewall damage are also eliminated.

[0050] The description of various embodiments of the present invention has been presented for purposes of illustration, but it is not intended that the disclosed embodiments be exhaustive or limiting. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications to commercially available technologies, or technical improvements, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A vertical bipolar junction transistor, an intrinsic base epitaxially grown on the first emitter or collector; a second collector or emitter formed on the intrinsic base; an extrinsic base formed around the entire periphery of the intrinsic base, the extrinsic base being separated from the first emitter or collector by a first spacer, and the extrinsic base being separated from the second collector or emitter by a second spacer; Equipped with the intrinsic base is compositionally graded so that a portion closer to the emitter has a smaller bandgap than a portion closer to the collector, and the extrinsic base has a larger bandgap than the intrinsic base; Vertical bipolar junction transistor.

2. 2. The vertical bipolar junction transistor of claim 1, wherein the emitter or collector has a larger bandgap than the intrinsic base.

3. A vertical bipolar junction transistor as described in claim 1, wherein the extrinsic base is doped with the same type of dopant as the intrinsic base but at a higher level than the intrinsic base.

4. 2. The vertical bipolar junction transistor of claim 1, wherein said intrinsic base is doped with a p-type dopant, and said first emitter or collector and said second collector or emitter are doped with an n-type dopant.

5. 2. The vertical bipolar junction transistor of claim 1, wherein said intrinsic base is doped with an n-type dopant, and said first emitter or collector and said second collector or emitter are doped with a p-type dopant.

6. 2. The vertical bipolar junction transistor of claim 1, wherein the first emitter or collector, the intrinsic base, and the second collector or emitter are fabricated from III-V semiconductor materials.

7. 10. The vertical bipolar junction transistor of claim 1, further comprising an isolation layer isolating the first emitter or collector from a substrate.

8. A vertical bipolar junction transistor as described in claim 1, wherein the intrinsic base comprises indium aluminum gallium arsenide, and the portion closer to the emitter contains more gallium and less aluminum than the portion closer to the collector.

9. 1. A method of forming a vertical bipolar junction transistor, comprising: epitaxially growing an intrinsic base on the first emitter or collector; epitaxially growing a second collector or emitter on the intrinsic base; epitaxially growing an extrinsic base all around the intrinsic base, the extrinsic base being separated from the first emitter or collector by a first spacer and the extrinsic base being separated from the second collector or emitter by a second spacer; Including, epitaxially growing the intrinsic base includes compositionally grading the intrinsic base so that a portion of the intrinsic base proximate an emitter has a smaller bandgap than a portion of the intrinsic base proximate a collector; epitaxially growing the extrinsic base includes doping the extrinsic base more highly than the intrinsic base; A method for forming a vertical bipolar junction transistor.

10. 10. The method of forming a vertical bipolar junction transistor of claim 9, wherein the compositionally graded intrinsic base is formed of indium aluminum gallium arsenide, and compositionally grading the intrinsic base comprises increasing an aluminum content and decreasing a gallium content in the intrinsic base from a portion adjacent to the emitter toward a portion adjacent to the collector.

11. 11. The method of forming a vertical bipolar junction transistor of claim 10, further comprising increasing the aluminum content and decreasing the gallium content in the intrinsic base to increase the bandgap of the intrinsic base.

12. 12. The method for forming a vertical bipolar junction transistor of claim 11, wherein the bandgap of the intrinsic base is smaller in gallium-rich and aluminum-poor portions of the intrinsic base.

13. 10. The method for forming a vertical bipolar junction transistor of claim 9, wherein the emitter or collector has a larger bandgap than the intrinsic base.

14. 10. The method for forming a vertical bipolar junction transistor of claim 9, wherein the extrinsic base has a larger bandgap than the intrinsic base.

15. 10. The method for forming a vertical bipolar junction transistor of claim 9, wherein said intrinsic base is doped with a p-type dopant, and said first emitter or collector and said second collector or emitter are doped with an n-type dopant.

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