Semiconductor device and data storage system including the same

Abstract

To provide a semiconductor device and data storage system, improving integration density and reliability.SOLUTION: A semiconductor device includes: a lower structure including a peripheral circuit; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure; a vertical memory structure penetrating through the stack structure in a vertical direction; a first barrier structure 68a and a second barrier structure 68b penetrating through the stack structure in the vertical direction and parallel to each other; a supporter pattern 65 penetrating through the stack structure in the vertical direction and spaced apart from the first and second barrier structures; and a plurality of through contact plugs 80 penetrating through the stack structure in the vertical direction between the first and second barrier structures. The first barrier structure includes first barrier patterns 68a_1 arranged in a first direction and spaced apart from each other, and second barrier patterns 68a_2 arranged in the first direction and spaced apart from each other. Each of the first and second barrier patterns includes a linear shape extending in the first direction X.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a data storage system including the same. [Background technology]

[0002] In data storage systems requiring data storage, semiconductor devices capable of storing high-capacity data are in demand. Therefore, methods for increasing the data storage capacity of semiconductor devices have been researched. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally has been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-33244 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor device and a data storage system including the semiconductor device that improves the integration degree and reliability. [Means for solving the problem]

[0005] a first barrier structure and a second barrier structure, the first barrier structure including a first barrier pattern and a second barrier pattern, the first barrier pattern ... second barrier pattern including a second barrier pattern and a second barrier pattern, the first barrier pattern including a first barrier pattern and a second barrier pattern, the first barrier pattern including a first barrier pattern and a second barrier pattern, the first barrier pattern including a first barrier pattern and a second barrier pattern, the second barrier pattern including a first barrier pattern and a second barrier pattern, the first barrier pattern including a first barrier pattern and a second barrier pattern, the second barrier pattern including a second barrier pattern and a second barrier pattern, the first barrier pattern including a

[0006] According to another aspect of the present invention, a semiconductor device includes a lower structure including a peripheral circuit, a stacked structure on the lower structure, extending from a memory cell region and having a staircase shape, the stacked structure including interlayer insulating layers and horizontal layers alternately stacked in the memory cell region, a first main isolation structure and a second main isolation structure on the lower structure, the first main isolation structure and the second main isolation structure being parallel to each other and penetrating the stacked structure, a vertical memory structure vertically penetrating the memory cell region of the stacked structure, a support pattern penetrating a staircase region of the stacked structure, a first barrier structure and a second barrier structure being parallel to each other and penetrating the staircase region of the stacked structure between the first main isolation structure and the second main isolation structure, and a support pattern penetrating the stacked structure between the first barrier structure and the second barrier structure. and a plurality of via contact plugs, wherein the horizontal layer includes a gate horizontal layer and an insulating horizontal layer, the supporter pattern penetrates the gate horizontal layer, and the plurality of via contact plugs penetrate the insulating horizontal layer, each of the first and second barrier structures includes first barrier patterns arranged in a first direction and spaced apart from each other, and second barrier patterns arranged in the first direction and spaced apart from each other, at least a portion of each of the first and second barrier patterns has a line shape extending in the first direction, and in the first barrier pattern and the second barrier pattern adjacent to each other, a portion of the first barrier pattern faces a portion of the second barrier pattern in a second direction perpendicular to the first direction.

[0007] In order to achieve the above object, a data storage system according to one aspect of the present invention includes a main substrate, a semiconductor device on the main substrate, and a controller electrically connected to the semiconductor device on the main substrate, wherein the semiconductor device includes a lower structure including a peripheral circuit, a stacked structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, a vertical memory structure vertically penetrating the stacked structure, first and second barrier structures vertically penetrating the stacked structure and parallel to each other, a support pattern vertically penetrating the stacked structure and spaced apart from the first and second barrier structures, and a support pattern vertically penetrating the stacked structure and spaced apart from the first and second barrier structures. and a plurality of through contact plugs that penetrate the stacked structure in the vertical direction between the barrier structure and the second barrier structure, the first barrier structure including first barrier patterns that are arranged in a first direction and spaced apart from each other, and second barrier patterns that are arranged in the first direction and spaced apart from each other, at least a portion of each of the first and second barrier patterns having a line shape extending in the first direction, and a portion of the first barrier pattern facing a portion of the second barrier pattern in a second direction perpendicular to the first direction. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a device with improved integration and reliability.

[0009] The various beneficial advantages and effects of the present invention are not limited to the above, but can be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view schematically showing a semiconductor device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a partially enlarged plan view showing a portion indicated by "A" in FIG. [Figure 3]FIG. 3 is a partially enlarged plan view showing the portion indicated by "B" in FIG. 2. [Figure 4a] FIG. 2 is a cross-sectional view schematically illustrating an area cut along line II' in FIG. [Figure 4b] FIG. 4 is a cross-sectional view schematically showing a region cut along line II-II′ in FIG. 3. [Figure 5a] FIG. 4b is a partially enlarged cross-sectional view schematically showing an enlarged portion of FIG. 4a indicated by "A1a." [Figure 5b] 4b is a partially enlarged cross-sectional view schematically showing an enlarged portion of FIG. 4a indicated by "A1b." FIG. [Figure 5c] 4 is a partially enlarged cross-sectional view schematically illustrating an enlarged area cut along line VV' in FIG. 3. FIG. [Figure 5d] 4b is a partially enlarged cross-sectional view schematically showing an enlarged portion indicated by "A2" in FIG. 4a. FIG. [Figure 6a] FIG. 4 is a plan view showing some components in the plane of FIG. 3. [Figure 6b] FIG. 4 is a plan view showing some components in the plane of FIG. 3. [Figure 7a] FIG. 10 is a partially enlarged plan view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 7b] FIG. 10 is a partially enlarged plan view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 7c] FIG. 10 is a partially enlarged plan view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 8a] FIG. 10 is a partially enlarged plan view showing a part of a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 8b] FIG. 10 is a partially enlarged plan view showing a part of a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 8c] FIG. 10 is a partially enlarged plan view showing a part of a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 8d] FIG. 10 is a partially enlarged plan view showing a part of a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 8e]FIG. 10 is a partially enlarged plan view showing a part of a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 9] FIG. 10 is a partially enlarged plan view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 10] FIG. 10 is a plan view showing some components in the plane of FIG. 9. [Figure 11] FIG. 10 is a plan view showing some components in the plane of FIG. 9. [Figure 12] FIG. 10 is a partially enlarged cross-sectional view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 13] FIG. 10 is a partially enlarged cross-sectional view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 14a] FIG. 10 is a partially enlarged plan view showing a modified example of the semiconductor device according to the embodiment of the present invention. [Figure 14b] 14b is a cross-sectional view showing the area cut along line III-III' in FIG. 14a. [Figure 15] 2 is a cross-sectional view showing a modified example of the area cut along line II' in FIG. 1. FIG. [Figure 16] 1A to 1C are cross-sectional views schematically illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views schematically illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 18a] 1A to 1C are cross-sectional views schematically illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 18b] 1A to 1C are cross-sectional views schematically illustrating a method of forming a semiconductor device according to an embodiment of the present invention. [Figure 19] 1 is a diagram illustrating a schematic diagram of an exemplary data storage system including a semiconductor device according to an embodiment of the present invention. [Figure 20] 1 is a perspective view that schematically illustrates an exemplary data storage system including a semiconductor device according to an embodiment of the present invention. [Figure 21] 1 is a cross-sectional view that schematically illustrates an exemplary data storage system including a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0012] First, a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 1 to 4b. Figure 1 is a plan view schematically showing a semiconductor device according to one embodiment of the present invention, Figure 2 is a partially enlarged plan view enlarging a portion indicated by "A" in Figure 1, Figure 3 is a partially enlarged plan view enlarging a portion indicated by "B" in Figure 2, Figure 4a is a cross-sectional view schematically showing a region cut along line I-I' in Figure 1, and Figure 4b is a cross-sectional view schematically showing a region cut along line II-II' in Figure 3.

[0013] Referring to Figures 1 to 4b, the semiconductor device 1 according to this embodiment includes a lower structure 3, a stacked structure ST, a plurality of vertical memory structures 54, a barrier structure 68, a plurality of supporter patterns 65, and a plurality of peripheral through contact plugs 80.

[0014] The lower structure 3 includes a peripheral circuit 7. For example, the lower structure 3 includes a semiconductor substrate 5, peripheral transistors 8 on the semiconductor substrate 5, peripheral wiring 10 electrically connected to the peripheral transistors 8, peripheral pads 11 electrically connected to the peripheral wiring 10, and a lower insulating layer 13 covering the peripheral transistors 8, the peripheral wiring 10, and the peripheral pads 11 on the semiconductor substrate 5. The peripheral transistors 8 and the peripheral wiring 10 constitute the peripheral circuit 7. The peripheral transistors 8 include a peripheral gate 8a and a peripheral source / drain 8b.

[0015] The lower structure 3 further includes a pattern structure 16. For example, the pattern structure 16 includes a lower pattern layer 18, a first intermediate pattern layer 20 and a second intermediate pattern layer 21 spaced apart from each other on the lower pattern layer 18, and an upper pattern layer 23 covering the first and second intermediate pattern layers (20, 21) on the lower pattern layer 18.

[0016] As an example, the lower pattern layer 18 includes a first polysilicon, the first intermediate pattern layer 20 includes a second polysilicon, and the upper pattern layer 23 includes a third polysilicon. For example, the lower pattern layer 18, the first intermediate pattern layer 20, and the upper pattern layer 23 include polysilicon having an N-type conductivity.

[0017] As an example, upper pattern layer 23 contacts lower pattern layer 18 between first intermediate pattern layer 20 and second intermediate pattern layer 21 and passes through a portion of second intermediate pattern layer 21 to contact lower pattern layer 22 .

[0018] As an example, the second intermediate pattern layer 21 includes at least two kinds of materials. For example, the second intermediate pattern layer 21 includes a silicon nitride layer and a silicon oxide layer covering the upper and lower surfaces of the silicon nitride layer. As another example, the second intermediate pattern layer 21 includes a polysilicon layer and a silicon oxide layer covering the upper and lower surfaces of the polysilicon layer.

[0019] As an example, the lower structure 3 further includes a first gap fill insulating layer 26a and a second gap fill insulating layer 26b penetrating the pattern structure 16, and an outer insulating layer 26c on the outer surface of the pattern structure 16. The first and second gap fill insulating layers (26a, 26b) and the outer insulating layer 26c include silicon oxide.

[0020] The laminated structure ST includes interlayer insulating layers (33, 37, 41) and horizontal layers (35, 39, 43).

[0021] The interlayer insulating layers (33, 37, 41) and the horizontal layers (35, 39, 43) are alternately and repeatedly stacked in the first region MCA of the laminated structure ST, and extend from the first region MCA to the second region SA of the laminated structure ST, forming a staircase shape in the second region SA. Therefore, the laminated structure ST has a staircase shape in the second region SA.

[0022] In the embodiment, the first region MCA is referred to as a memory cell region or a memory cell region, and the second region SA is referred to as a staircase region, a connecting region, or a contact region.

[0023] The laminated structure ST includes a lower laminated structure ST_L, a first upper laminated structure ST_U1 on the lower laminated structure ST_L, and a second upper laminated structure ST_U2 on the first upper laminated structure ST_U1.

[0024] The lower stacked structure ST_L includes alternately stacked lower interlayer insulating layers 33 and lower horizontal layers 35. The lowermost and uppermost layers of the lower interlayer insulating layers 33 and the lower horizontal layers 35 are lower interlayer insulating layers. As an example, the uppermost lower interlayer insulating layer of the lower interlayer insulating layers 33 has a thickness greater than the thicknesses of the remaining lower interlayer insulating layers.

[0025] The first upper stacked structure ST_U1 includes first upper interlayer insulating layers 37 and first upper horizontal layers 39 that are alternately stacked. The lowermost and uppermost layers of the first upper interlayer insulating layers 37 and the first upper horizontal layers 39 are first upper interlayer insulating layers. As an example, the uppermost first upper interlayer insulating layer of the first upper interlayer insulating layers 37 has a thickness greater than the thicknesses of the remaining first upper interlayer insulating layers.

[0026] The second upper stacked structure ST_U2 includes second upper interlayer insulating layers 41 and second upper horizontal layers 43 that are alternately stacked. The lowermost and uppermost layers of the second upper interlayer insulating layers 41 and the second upper horizontal layers 43 are second upper interlayer insulating layers. As an example, the uppermost second upper interlayer insulating layer of the second upper interlayer insulating layers 41 has a thickness greater than the thicknesses of the remaining second upper interlayer insulating layers.

[0027] As an example, the staircase region SA of the stacked structure ST includes staircase regions (USa, ISa, LSa) of the second upper stacked structure ST_U2, staircase regions (USb, ISb, LSb) of the first upper stacked structure ST_U1, and staircase region SL2 of the lower stacked structure ST_L, which are arranged in order in a direction from the memory cell region MCA toward the staircase region SA, for example, in the first direction X.

[0028] The staircase region SL2 of the lower laminated structure ST_L has a staircase shape that gradually decreases in the first direction X by a first height difference.

[0029] In the staircase region SA, the first and second upper laminated structures (ST_U1, ST_U2) have substantially the same or similar planar staircase shapes. For example, in the staircase region SA, each of the first and second upper laminated structures (ST_U1, ST_U2) includes an upper staircase region (USa, USb), a middle staircase region (ISa, ISb), and a lower staircase region (LSa, LSb) arranged in order in the first direction X.

[0030] In each of the first and second upper laminated structures (ST_U1, ST_U2), the upper staircase region (USa, USb) includes a first upper staircase region (US1a, US2a) having a staircase shape that decreases by a first height difference in the first direction X, and a second upper staircase region (US1b, US2b) including a staircase shape that increases by a first height difference from the first upper staircase region (US1a, US2a) in the first direction X.

[0031] In each of the first and second upper laminate structures ST_U1 and ST_U2, the lower staircase regions LS1a and LS1b have a staircase shape that gradually decreases in height in the first direction X by a first height difference.

[0032] In each of the first and second upper laminated structures (ST_U1, ST_U2), the intermediate stair region (ISa, ISb) includes a first intermediate stair region (IS1a, IS2a), a stair connection region (CSa, CSb), and a second intermediate stair region (IS1b, IS2b), which are arranged sequentially in the first direction X.

[0033] In each of the first and second upper laminate structures (ST_U1, ST_U2), the first intermediate staircase region (IS1a, IS2a) has an upper surface located at a higher height level than the second intermediate staircase region (IS1b, IS2b).

[0034] The first intermediate staircase region (IS1a, IS2a) and the second intermediate staircase region (IS1b, IS2b) each have a staircase shape that decreases by a second height difference that is greater than the first height difference in a first direction X. The first intermediate staircase region (IS1a, IS2a) and the second intermediate staircase region (IS1b, IS2b) each have a staircase shape that decreases by a first height difference or increases by a first height difference in a second direction Y that is perpendicular to the first direction X.

[0035] In each of the first and second upper laminate structures (ST_U1, ST_U2), the staircase connection region (CSa, CSb) is substantially flat in the first direction X and has a staircase shape that is lowered by a first height difference or raised by a first height difference in the second direction Y.

[0036] In the stacked structure ST, the lower horizontal layer 35 includes a lower gate horizontal layer 35G and a lower insulating horizontal layer 35I, the first upper horizontal layer 39 includes a first upper gate horizontal layer 39G and a first upper insulating horizontal layer 39I, and the second upper horizontal layer 43 includes a second upper gate horizontal layer 43G and a second upper insulating horizontal layer 43I. For example, at any one height level, any one horizontal layer includes any one gate horizontal layer and at least one insulating horizontal layer connected to any one gate horizontal layer.

[0037] In the stacked structure ST, a region where the gate horizontal layers (35G, 39G, 43G) are located is defined as a gate stacked region ST_G, and a region where the insulating horizontal layers (35I, 39I, 43I) are located is defined as an insulating stacked region ST_I.

[0038] The interlayer insulating layers (33, 37, 41) are made of silicon oxide, and the insulating horizontal layers (35I, 39I, 43I) are made of an insulating material different from that of the interlayer insulating layers (33, 37, 41), such as silicon nitride.

[0039] In the staircase region SA, a plurality of insulating stack regions ST_I are arranged. For example, the insulating stack regions ST_I are arranged in order in the first direction X and include a first insulating stack region ST_Ia and a second insulating stack region ST_Ib that are spaced apart from each other.

[0040] As an example, the first insulating stack region ST_Ia is arranged within the lower stack structure ST_L, the first upper stack structure ST_U1, and the second upper stack structure ST_U2, and the second insulating stack region ST_Ib is arranged within the lower stack structure ST_L and the first upper stack structure ST_U1.

[0041] In the lower stack structure ST_L, the lower insulating horizontal layer 35I includes a lower insulating horizontal layer 35Ia disposed in the first insulating stack region ST_Ia and a lower insulating horizontal layer 35Ib disposed in the second insulating stack region ST_Ib. Therefore, any one of the lower horizontal layers 35 includes any one gate horizontal layer 35G and multiple insulating horizontal layers (35Ia, 35Ib) connected to any one gate horizontal layer 35G.

[0042] In the first upper stack structure ST_U1, the first upper insulating horizontal layer 39I includes a first upper insulating horizontal layer 39Ia arranged in the first insulating stack region ST_Ia and a first upper insulating horizontal layer 39Ib arranged in the second insulating stack region ST_Ib. Therefore, any one horizontal layer of the first upper horizontal layer 39 includes any one gate horizontal layer 39G and multiple insulating horizontal layers (39Ia, 39Ib) connected to any one gate horizontal layer 39G.

[0043] In the second upper stacked structure ST_U2, the second upper insulating horizontal layer 43I is disposed within the first insulating stacked region ST_Ia.

[0044] In the staircase region SA of the stacked structure ST, the gate horizontal layers (35G, 39G, 43G) have gate pad regions (35P, 39P, 43P). The gate pad regions (35P, 39P, 43P) are not covered by other gate horizontal layers.

[0045] A capping insulating structure 90 is disposed to cover the stack structure ST. The capping insulating structure 90 includes a plurality of stacked silicon oxide layers.

[0046] A vertical memory structure 54 is disposed to pass through the memory cell area MCA of the stacked structure ST. The vertical memory structure 54 is in contact with the pattern structure 16. The vertical memory structure 54 passes through the gate horizontal layers (35G, 39G, 43G).

[0047] A plurality of supporter patterns 65 are arranged to extend through the staircase region SA of the stacked structure ST into the capping insulating structure 90. The plurality of supporter patterns 65 penetrate the gate horizontal layers (35G, 39G, 43G) of the gate stack region ST_G of the stacked structure ST.

[0048] A barrier structure 68 is arranged which extends through the stepped region SA of the stack structure ST and into the capping insulating structure 90 .

[0049] Gate contact plugs 82 are disposed in contact with the gate pad regions (35P, 39P, 43P) of the gate horizontal layers (35G, 39G, 43G) and extend into the capping insulating structure 90. The gate pad regions (35P, 39P, 43P) in contact with the gate contact plugs 82 are formed of a conductive material.

[0050] Some of the gate contact plugs 82 are dummy gate contact plugs 82d.

[0051] A plurality of peripheral via contact plugs 80 are arranged to pass through the stack structure ST and extend into the capping insulating structure 90. The plurality of peripheral via contact plugs 80 pass through the insulating stack region ST_I of the stack structure ST. The plurality of peripheral via contact plugs 80 include a plurality of peripheral via contact plugs that pass through the first insulating stack region ST_Ia and a plurality of peripheral via contact plugs that pass through the second insulating stack region ST_Ib.

[0052] The plurality of peripheral via contact plugs 80 extend downward from the portion penetrating the stacked structure ST, and are electrically connected to the peripheral pads 11 of the peripheral circuit 7 through the gap fill insulating layers 26 a and 26 b.

[0053] Within the capping insulating structure 90, a bit line connection pattern 85a electrically connected to the vertical memory structure 54, a gate connection pattern 85b electrically connected to the gate contact plug 82, and a peripheral connection pattern 85c electrically connected to a plurality of peripheral through contact plugs 80 are arranged.

[0054] A bit line 93a is disposed on the bit line connecting pattern 85a, and a gate connecting wire 93b is disposed on the gate connecting pattern 85b and the peripheral connecting pattern 85c.

[0055] The vertical memory structure 54 is electrically connected to a bit line 93a. The gate horizontal layers (35G, 39G, 43G) are electrically connected to the peripheral circuit 7 via a gate contact plug 82, a gate connecting wiring 93b, and a plurality of peripheral through-contact plugs 80.

[0056] Isolation structures 77 are disposed so as to extend through the stack structure ST in the vertical direction Z and into the capping insulating structure 90. Each isolation structure 77 has a line shape extending in the first direction X.

[0057] The isolation structure 77 includes first and second main isolation structures 77m1 and 77m2 that are parallel to each other and spaced apart from each other in the second direction Y of the stacked structure ST.

[0058] The isolation structure 77 includes auxiliary isolation structures 77s disposed between the first and second main isolation structures 77m1 and 77m2 and penetrating the laminated structure ST. Each of the auxiliary isolation structures 77s has a length shorter than the length of the laminated structure ST in the first direction X.

[0059] The auxiliary isolation structures 77s are arranged in the staircase region SA of the stack structure ST, and at least one of the auxiliary isolation structures 77s extends into the memory cell region MCA of the stack structure ST.

[0060] In the memory cell area MCA, upper select gate isolation patterns 50 are arranged between the isolation structures 77. The upper select gate isolation patterns 50 space the gate horizontal layers (35G, 39G, 43G) that are upper select gate lines and are located at a higher level than the gate horizontal layers that are word lines in the second direction Y.

[0061] Next, the planar shape of the barrier structure 68 will be mainly described with reference to FIGS.

[0062] 2 and 3, the barrier structure 68 includes a plurality of barrier patterns spaced apart from each other in the first direction X and the second direction Y. Some of the barrier patterns penetrate the gate horizontal layers (35G, 39G, 43G), and some of the barrier patterns penetrate between the gate stack region ST_G including the gate horizontal layers (35G, 39G, 43G) and the insulating stack region ST_I including the insulating horizontal layers (35I, 39I, 43I).

[0063] The barrier structures 68 include a first barrier structure 68a and a second barrier structure 68b that are parallel to each other and extend in a first direction X, and a third barrier structure 68c and a fourth barrier structure 68d that are parallel to each other and extend in a second direction Y. The first to fourth barrier structures (68a, 68b, 68c, 68d) are rectangular ring-shaped. The first barrier structure 68a is adjacent to the first main isolation structure 77m1, and the second barrier structure 68b is adjacent to the second main isolation structure 71m2.

[0064] The first barrier structure 68a includes first barrier patterns 68a_1 arranged in the first direction X and spaced apart from each other, and second barrier patterns 68a_2 arranged in the first direction X and spaced apart from each other. The first barrier patterns 68a_1 and the second barrier patterns 68a_2 are arranged in a zigzag shape.

[0065] At least a portion of each of the first and second barrier patterns (68a_1, 68a_2) has a line shape extending in the first direction X. For example, each of the first and second barrier patterns (68a_1, 68a_2) has a bar shape extending in the first direction X.

[0066] For example, the first and second barrier patterns 68a_1 and 68a_2 have the same width W1 in the second direction Y.

[0067] As an example, the length L1 in the first direction X of at least one of the first barrier patterns 68a_1 is the same as the length L2 in the first direction X of at least one of the second barrier patterns 68a_2.

[0068] Of the first and second barrier patterns (68a_1, 68a_2), the first barrier pattern 68a_1 includes a first portion L1a, a second portion L1b, and a third portion L1c. In the first barrier pattern 68a_1, the first portion L1a and the third portion L1c face the second barrier pattern 68a_2 in the second direction Y, while the second portion L1b does not face the second barrier pattern 68a_2 in the second direction Y.

[0069] Here, the length of the second portion L1b in the first direction X is the same as the distance between the second barrier patterns 68a_2 adjacent to each other in the first direction X.

[0070] As an example, the length in the first direction X of a part of the first barrier pattern 68a_1 that faces a part of the second barrier pattern 68a_2 in the second direction Y is greater than the width in the first direction X of the supporter pattern 65. For example, in the first barrier pattern 68a_1, the length in the first direction X of at least one of the first portion L1a and the third portion L1c is greater than the width in the first direction X of the supporter pattern 65.

[0071] For example, in the first barrier pattern 68a_1, the length in the first direction X of at least one of the first portion L1a and the third portion L1c is at least twice the width in the first direction X of the supporter pattern 65.

[0072] For example, in the first barrier pattern 68a_1, the length in the first direction X of at least one of the first portion L1a and the third portion L1c is substantially the same as the length of the second portion L1b.

[0073] For example, in the first barrier pattern 68a_1, the length in the first direction X of at least one of the first portion L1a and the third portion L1c is greater than the length of the second portion L1b.

[0074] As an example, in the first barrier pattern 68a_1, the length in the first direction X of at least one of the first portion L1a and the third portion L1c is at least twice as long as the length of the second portion L1b.

[0075] As an example, in the first barrier pattern 68a_1, the length in the first direction X of at least one of the first portion L1a and the third portion L1c is three or more times longer than the length of the second portion L1b.

[0076] For example, the separation distance d1b between the first barrier pattern 68a_1 and the second barrier pattern 68a_2 is smaller than the length in the first direction X of at least one of the first portion L1a and the third portion L1c in the first barrier pattern 68a_1.

[0077] For example, the separation distance d1b between the first barrier pattern 68a_1 and the second barrier pattern 68a_2 is smaller than the length in the first direction X of the second portion L1b of the first barrier pattern 68a_1.

[0078] For example, the first barrier structure 68a further includes first inner barrier patterns 68a_3 spaced apart from each other and arranged in the first direction, and the first inner barrier patterns 68a_3 and the second barrier patterns 68a_2 are arranged in a zigzag pattern.

[0079] The second barrier structure 68b has a mirror-symmetric structure with the first barrier structure 68a, for example, the second barrier structure 68b includes third and fourth barrier patterns (68b_1, 68b_2) corresponding to the first and second barrier patterns (68a_1, 68a_2) and the first inner barrier pattern 68a_3 of the first barrier structure 68a, respectively, and a second inner barrier pattern 68b_3.

[0080] The third barrier structure 68c is disposed between one end of the first barrier structure 68a and one end of the second barrier structure 68b. The third barrier structure 68c includes first inner barrier patterns 68c_1 and second inner barrier patterns 68c_2 arranged in the second direction Y and spaced apart from each other. In the third barrier structure 68c, the first inner barrier patterns 68c_1 and the second inner barrier patterns 68c_2 are arranged in a zigzag shape.

[0081] In the embodiment, the term “horizontal pattern” will be used instead of “barrier pattern.” For example, in the third barrier structure 68c, the first inner barrier pattern 68c_1 and the second inner barrier pattern 68c_2 will be referred to as the first horizontal pattern and the second horizontal pattern, respectively.

[0082] The fourth barrier structure 68d is a mirror image of the third barrier structure 68c.

[0083] In the third barrier structure 68c, each of the first and second inner barrier patterns (68c_1, 68c_2) includes a line-shaped portion extending in the second direction Y. For example, in the third barrier structure 68c, each of the first and second inner barrier patterns (68c_1, 68c_2) is a bar-shaped portion extending in the second direction Y.

[0084] In the third barrier structure 68c, the first inner barrier pattern 68c_1 is adjacent to an edge of the auxiliary isolation structure 77s. The edge of the auxiliary isolation structure 77s faces a center portion of the first inner barrier pattern 68c_1 of the third barrier structure 68c. For example, the edge of any one of the auxiliary isolation structures 77s faces a center portion of any one of the first inner barrier patterns 68c_1 of the third barrier structure 68c.

[0085] The barrier structure 68 further includes an edge barrier pattern 68e disposed on an edge of the first barrier structure 68a, and spaced apart in the first direction X from the first and second barrier patterns 68a_1 and 68a_2 of the first barrier structure 68a.

[0086] Lower select gate isolation patterns 36 are arranged to separate the gate horizontal layer 35G, which is a lower select gate line among the gate horizontal layers (35G, 39G, 43G), into a plurality of portions. Any one of the lower select isolation patterns 36 overlaps an end of any one of the auxiliary isolation structures 77s, for example, an auxiliary isolation structure arranged in the center, and extends to the insulating stack region ST_I. The lower select gate isolation patterns 36 are located at a height level lower than the gate horizontal layers (39G, 43G), which are word lines among the gate horizontal layers (35G, 39G, 43G).

[0087] For example, the first barrier pattern 68a_1 is spaced apart from the insulating horizontal layer in the insulating stack region ST_I and in contact with the gate horizontal layer in the gate stack region ST_G.

[0088] As an example, each third barrier pattern 68b_1 includes a portion in contact with the insulating horizontal layer of the insulating stack region ST_I and a portion in contact with the gate horizontal layer of the gate stack region ST_G.

[0089] For example, the first inner barrier pattern 68c_1 contacts the insulating horizontal layer in the insulating stack region ST_I and is spaced apart from the gate horizontal layer in the gate stack region ST_G.

[0090] The interfaces BR that contact the insulating horizontal layer of the insulating stack region ST_I and the gate horizontal layer of the gate stack region ST_G are disposed inside the barrier structures 68 and contact one of the barrier patterns. For example, the interfaces BR include an interface BR1 that is disposed inside the first barrier structure 68a and contacts the second barrier pattern 68a_2, an interface BR2 that is disposed inside the second barrier structure 68b and contacts the fourth barrier pattern 68b_2, and an interface BR3 that is disposed inside the third barrier structure 68c and contacts the first and second inner barrier patterns (68c_1, 68c_2).

[0091] Next, an example of the pattern structure 16, stack structure ST, and vertical memory structure 54 will be described with reference to Figure 5a. Figure 5a is a partially enlarged cross-sectional view of the portion indicated by "A1a" in Figure 4a.

[0092] 5a, in the stacked structure ST, each of the gate horizontal layers (35G, 39G, 43G) includes a first gate layer 45 and a second gate layer 47. The first gate layer 45 covers the upper and lower surfaces of the second gate layer 47 and is interposed between the second gate layer 47 and the vertical memory structure 54.

[0093] As an example, the first gate layer 45 includes a dielectric material and the second gate layer 47 includes a conductive material, such as a high-k dielectric such as AlO, and the second gate layer 47 includes a conductive material such as TiN, WN, Ti, or W.

[0094] As another example, the first gate layer 45 includes a first conductive material (e.g., TiN or W), and the second gate layer 47 includes a second conductive material (e.g., Ti or W) different from the first conductive material.

[0095] As yet another example, each of the first and second gate layers (45, 47) is formed of doped polysilicon, a metal-semiconductor compound (e.g., TiSi, TaSi, CoSi, NiSi, or WSi), a metal nitride (e.g., TiN, TaN, or WN), or a metal (e.g., Ti or W).

[0096] As an example, the first lower horizontal gate layer 35g_La arranged at the bottom of the horizontal gate layers (35G, 39G, 43G) is a lower erase control gate electrode, and the second lower horizontal gate layer 35g_Lb on the first lower horizontal gate layer 35g_La is a lower select gate electrode, for example, a ground select gate electrode. The first upper horizontal gate layer 43g_Ua of the horizontal gate layers (35G, 39G, 43G) is an upper select gate electrode, for example, a string select gate electrode, and the second upper horizontal gate layer 43g_Ub on the first upper horizontal gate layer 43g_Ua is an upper erase control gate electrode. The first lower horizontal gate layer 35g_La may be one or multiple layers stacked in the vertical direction Z, and the second upper horizontal gate layer 43g_Ub may be one or multiple layers stacked in the vertical direction Z.

[0097] As an example, at least some of the gate horizontal layers (39G, 43M) among the gate horizontal layers (35G, 39G, 43G) arranged between the second lower gate horizontal layer 35g_Lb and the first upper gate horizontal layer 43g_Ua are word lines.

[0098] The vertical memory structure 54 includes an insulating core pattern 60, a channel layer 58 covering the sides and bottom of the insulating core pattern 60, an information storage structure 56 disposed on the outer sides and bottom of the channel layer 58, and a pad pattern 62 on the insulating core pattern 60 in contact with the channel layer 58.

[0099] The insulating core pattern 60 includes silicon oxide, the channel layer 58 includes polysilicon, and the pad pattern 62 includes at least one of doped polysilicon, a metal nitride (e.g., TiN), a metal (e.g., W), and a metal-semiconductor compound (e.g., TiSi).

[0100] The information storage structure 56 includes a first dielectric layer 56a, a second dielectric layer 56c, and an information storage layer 56b between the first dielectric layer 56a and the second dielectric layer 56c. The second dielectric layer 56c contacts the channel layer 58, and the information storage layer 56b is spaced apart from the channel layer 58. The first dielectric layer 56a includes silicon oxide or silicon oxide doped with impurities. The second dielectric layer 56c includes at least one of silicon oxide and a high-k dielectric. The information storage layer 56b includes a region for storing information in a semiconductor device such as a flash memory device. For example, the information storage layer 56b includes a material that traps charges, such as silicon nitride.

[0101] The first intermediate pattern layer 20 formed as a polysilicon layer penetrates the information storage structure 56 and contacts the channel layer 58. Therefore, the first intermediate pattern layer 20 separates the information storage structure 56 into a lower portion 56L and an upper portion 56U.

[0102] The side of the vertical memory structure 54 has an inflection portion 54V in the region where the second upper stacked structure ST_U2 and the first upper stacked structure ST_U1 are adjacent to each other. For example, the vertical memory structure 54 includes a lower vertical portion 54L disposed within the first upper stacked structure ST1_U1 and an upper vertical portion 54U disposed within the second upper stacked structure ST_U2. The width of the lower region of the upper vertical portion 54U is smaller than the width of the upper region of the lower vertical portion 54L. Due to this difference in width size, the side of the vertical memory structure 54 has a bent portion, i.e., an inflection portion 54V, in the region where the upper vertical portion 54U and the lower vertical portion 54L are adjacent to each other.

[0103] As an example, vertical memory structure 54 extends through upper pattern layer 23 and first intermediate pattern layer 20 in turn into lower pattern layer 18 .

[0104] The bit line connecting pattern 85 a contacts the pad pattern 62 of the vertical memory structure 54 .

[0105] Next, an example of a barrier structure 68 will be described with reference to Figure 5b. Figure 5b is a partially enlarged cross-sectional view of the portion designated "A1b" in Figure 4b.

[0106] 5b, one of the barrier patterns of the barrier structure 68, for example, the second barrier pattern 68a_2, contacts the insulating horizontal layers (35I, 39I, 43I) and the gate horizontal layers (35G, 39G, 43G) of the stacked structure ST. The barrier structure 68 extends into the lower pattern layer 18, sequentially passing through the upper pattern layer 23 and the second intermediate pattern layer 21.

[0107] As an example, the second intermediate pattern layer 21 includes a first layer 19a, a second layer 19b, and a third layer 19c stacked in this order, where the second layer 19b is a polysilicon layer or a silicon nitride layer, and the first and third layers (19a, 19c) are silicon oxide layers.

[0108] As an example, the barrier structure 68 is formed of an insulating material layer. For example, the barrier structure 68 is formed of a silicon oxide layer. Therefore, the vertical memory structure (54 in FIG. 5a) has a material layer with a different cross-sectional structure than the barrier structure 68.

[0109] Next, an example of a support pattern 65 will be described with reference to Fig. 5c. The support pattern 65 in Fig. 5c is a support pattern adjacent to the barrier structure 68 in Fig. 3. Fig. 5c is a partially enlarged cross-sectional view showing the same cross-sectional area as that of Fig. 5b.

[0110] 5c, the support pattern 65 penetrates the gate horizontal layers (35G, 39G, 43G) of the stacked structure ST. The support pattern 65 extends through the upper pattern layer 23 and the second intermediate pattern layer 21 in order into the lower pattern layer 18.

[0111] As an example, the support pattern 65 is formed of the same material as the barrier structure 68. For example, the support pattern 65 and the barrier structure 68 include silicon oxide.

[0112] For example, the support pattern 65 and the barrier structure 68 are formed simultaneously, so that the support pattern 65 and the barrier structure 68 have upper surfaces at the same height level.

[0113] Next, an example of the peripheral via contact plug 80 will be described with reference to Figure 5d. Figure 5d is a partially enlarged cross-sectional view of the portion indicated by "A2" in Figure 4a.

[0114] Referring to FIG. 5d, the peripheral via contact plugs 80 penetrate the insulating horizontal layers (35I, 39I, 43I) of the stacked structure ST and extend downward to be electrically connected to the peripheral pads 11 of the peripheral circuit 7.

[0115] 6a, an example of the second lower gate horizontal layer 35g_Lb, which is the upper select gate electrode, e.g., the ground select gate electrode, described in FIG. 5a, will be described. FIG. 6a shows the second lower gate horizontal layer 35g_Lb and the insulating horizontal layer 35I′ connected to the second lower gate horizontal layer 35g_Lb at a position corresponding to the plan view of FIG. 2.

[0116] 6a, the second lower gate horizontal layer 35g_Lb includes a first ground selection gate electrode layer GSL_1 and a second ground selection gate electrode layer GSL_2 that are physically separated from each other. The first and second ground selection gate electrode layers GSL_1 and GSL_2 that are electrically separated from each other are connected to a single insulating horizontal layer 35I′.

[0117] For example, when the second lower gate horizontal layer 35g_Lb is made of a conductive material, the first and second ground selection gate electrode layers GSL_1 and GSL_2 contact one insulating horizontal layer 35I'.

[0118] For example, when the second lower gate horizontal layer 35g_Lb is formed of the first gate layer 45, which is a dielectric material layer, and the second gate layer 47, which is a conductive material layer, as described in FIG. 5A, the first gate layer, i.e., the insulating layer 45, is interposed between the first and second ground selection gate electrode layers (GSL_1, GSL_2) and one insulating horizontal layer 35I'. Therefore, the first and second ground selection gate electrode layers (GSL_1, GSL_2) are connected to one insulating horizontal layer 35I' through the first gate layer 45, which is a dielectric material layer. Therefore, in a plan view corresponding to FIG. 2, the second lower gate horizontal layer 35g_Lb is divided into two spaced-apart gate horizontal layers (GSL_1, GSL_2), and the two spaced-apart gate horizontal layers (GSL_1, GSL_2) are connected to one insulating horizontal layer 35I' while contacting each other. Therefore, an interface BR is formed between the two gate horizontal layers (GSL_1, GSL_2) and one insulating horizontal layer 35I'. The two gate horizontal layers (GSL_1, GSL_2), which are spaced apart and electrically isolated from each other, contact one insulating horizontal layer 35I' of the first insulating stack region (ST_Ia in FIG. 1 ) and one insulating horizontal layer 35I' of the second insulating stack region (ST_Ib in FIG. 1 ). Therefore, any one of the horizontal layers of the lower stack structure ST_L, for example, the top horizontal layer 35, includes a plurality of gate horizontal layers (GSL_1, GSL_2) spaced apart from each other, the insulating horizontal layer 35I' of the first insulating stack region (ST_Ia in FIG. 1 ), and the insulating horizontal layer 35I' of the second insulating stack region (ST_Ib in FIG. 1 ).

[0119] 3 are openings (68h, 65h, 77h, 36h) penetrating the second lower gate horizontal layer 35g_Lb. Accordingly, the first ground selection gate electrode layer GSL_1 of the multiple selection gate electrode layers surrounds each side of the first barrier pattern (68a_1 in FIG. 3) of the first barrier structure 68a, and the second ground selection gate electrode layer GSL_2 surrounds each side of the third barrier pattern 68b_1 of the second barrier structure 68b.

[0120] As an example, the interface BR between the two gate horizontal layers (GSL_1, GSL_2) and one insulating horizontal layer 35I′ contacts one of the openings 68h through which the barrier structure 68 is formed.

[0121] 6b is a plan view showing one of the gate horizontal layers 39G and 43M, which are word lines, described in FIG. 5a, and one insulating horizontal layer 43I′ connected to and in contact with the gate horizontal layer 43M. Here, the gate horizontal layer 43M is the n-th word line layer WLn.

[0122] 6b, any one of the gate horizontal layers WLn is connected to any one of the insulating horizontal layers 43I′ and surrounds the side of any one of the insulating horizontal layers 43I′. Any one of the gate horizontal layers WLn is disposed at a height level higher than the first and second ground selection gate electrode layers GSL_1 and GSL_2.

[0123] For example, when the gate horizontal layer WLn is made of a conductive material, the gate horizontal layer WLn, which is a word line, contacts the insulating horizontal layer 43I'.

[0124] As an example, when the gate horizontal layer WLn is formed of a first gate layer 45, which is a dielectric material layer as described in FIG. 5a, and a second gate layer 47, which is a conductive material layer, the second gate layer 47 is defined as a word line, and the first gate layer, i.e., the insulating layer 45, is interposed between the word line and one insulating horizontal layer 43I′.

[0125] The barrier structure 68, the support pattern 65, and the isolation structure 77 described in FIG. 3 are openings (68h, 65h, 77h) that penetrate the gate horizontal layer WLn.

[0126] As an example, the interface BR between the gate horizontal layer WLn and one of the insulating horizontal layers 43I' contacts one of the openings 68h through which the barrier structure 68 is formed.

[0127] The gate horizontal layer WLn has a gate pad region GP at an end in the first direction X, and the gate pad region GP is electrically connected to the gate contact plug 82 .

[0128] Therefore, any one of the gate horizontal layers, that is, one word line layer WLn, overlaps in the vertical direction Z with two gate horizontal layers GSL_1 and GSL_2, which are ground selection gate electrodes.

[0129] As an example, when any one gate horizontal layer, i.e., one word line layer WLn, is a word line located in the lower region of the first upper stack structure ST_U1, the first upper horizontal layer 39 including the word line includes one word line, a first upper insulating horizontal layer 39I of the first insulating stack region (ST_Ia in FIG. 1), and a first upper insulating horizontal layer 39I of the second insulating stack region (ST_Ib in FIG. 1).

[0130] As an example, when any one gate horizontal layer, i.e., one word line, is a word line located in the upper region of the first upper stack structure ST_U1 or the second upper stack structure ST_U2, the horizontal layer (39 or 43) including the word line includes one word line layer WLn and an insulating horizontal layer (39I or 43I) of the first insulating stack region (ST_Ia in FIG. 1). Therefore, the first horizontal layer 35 located at a first height level among the horizontal layers (35, 39, 43) arranged between the first main isolation structure 77m1 and the second main isolation structure 77m2 includes gate horizontal layers (GSL_1, GSL_2 in FIG. 6a) which are a plurality of select gate electrodes, an insulating horizontal layer (35I in FIG. 4a) of the first insulating stack region (ST_Ia in FIG. 1), and an insulating horizontal layer (35I in FIG. 4a) of the second insulating stack region (ST_Ib in FIG. 1), and the second horizontal layer located at a second height level higher than the first height level includes a gate horizontal layer (39G in FIG. 4a) which is any one of the first word lines. 1), an insulating horizontal layer (39I in FIG. 4a) of the first insulating stack region (ST_Ia in FIG. 1), and an insulating horizontal layer (39I in FIG. 4a) of the second insulating stack region (ST_Ib in FIG. 1). A third horizontal layer 43 located at a third height level higher than the second height level includes a gate horizontal layer (43G as a word line among 43G in FIG. 4a) which is any one of the second word lines, an insulating horizontal layer (43I in FIG. 4a) of the first insulating stack region (ST_Ia in FIG. 1), and an insulating horizontal layer (43I in FIG. 4a) of the second insulating stack region (ST_Ib in FIG. 1).

[0131] Next, with reference to Figures 7a to 7c, modifications of the boundary surface BR that contacts the insulating horizontal layer of the insulating stack region ST_I and the gate horizontal layer of the gate stack region ST_G described in Figure 3 will be described. Figures 7a to 7c are partially enlarged plan views showing a part of a modification of the semiconductor device according to one embodiment of the present invention.

[0132] In a modified example, referring to FIG. 7a, the interface BRa contacting the insulating horizontal layer of the insulating stack region ST_I and the gate horizontal layer of the gate stack region ST_G is disposed between the second barrier pattern 68a_2 and the first inner barrier pattern 68a_3 of the first barrier structure 68a.

[0133] In another variation, referring to FIG. 7b, the interface BRb contacting the insulating horizontal layer of the insulating stack region ST_I and the gate horizontal layer of the gate stack region ST_G is disposed between the first inner barrier patterns 68a_3 of the first barrier structure 68a.

[0134] 7c, in another modification, an interface BRc between the insulating horizontal layer of the insulating stack region ST_I and the gate horizontal layer of the gate stack region ST_G has a convex shape in a direction toward the plurality of peripheral via contact plugs 80 while contacting a side surface of the first inner barrier pattern 68a_3 of the first barrier structure 68a. For example, the gate horizontal layer of the gate stack region ST_G has a shape that protrudes from the barrier structure 68 toward the plurality of peripheral via contact plugs 80 while filling spaces between the barrier patterns of the barrier structure 68 and penetrating the barrier structure 68.

[0135] Next, various modified examples of the barrier structure 68 described in Fig. 3 will be described with reference to Fig. 8a to Fig. 8e, respectively. Fig. 8a to Fig. 8e are partially enlarged plan views showing parts of modified examples of a semiconductor device according to an embodiment of the present invention.

[0136] In a modified example, referring to FIG. 8a, the first barrier structure 168a includes a first barrier pattern 168a_1 and a second barrier pattern 168a_2, which respectively correspond to the first barrier pattern 68a_1 and the second barrier pattern 68a_2 of the first barrier structure 68a described in FIG. 3.

[0137] The second barrier structure 168b has a mirror-symmetric structure with the first barrier structure 168a. The third barrier structure 168c includes a first inner barrier pattern 168c_1 having a bar shape extending in the second direction Y, and a second inner barrier pattern 168c_2 having a bar shape extending in the second direction Y and arranged in a zigzag pattern with respect to the first inner barrier pattern 168c_1.

[0138] One edge barrier pattern 168e1 of the edge barrier patterns 68e described in FIG. 3 is connected to one barrier pattern of the third barrier structure 168c, and the other edge barrier pattern 168e2 is spaced apart from the third barrier structure 168c.

[0139] The boundary surface BRd that contacts the insulating horizontal layer of the insulating stack region ST_I and the gate horizontal layer of the gate stack region ST_G contacts the first to third barrier structures (168a, 168b, 168c).

[0140] 8b, in a modified example, a first barrier structure 68a' includes a first barrier pattern 68a_1', a second barrier pattern 68a_2', and a first inner barrier pattern 68a_3', which correspond to the first barrier pattern 68a_1, the second barrier pattern 68a_2, and the first inner barrier pattern 68a_3, respectively, of the first barrier structure 68a described in FIG. 3. Each of the second barrier pattern 68a_2' and the first inner barrier pattern 68a_3' has a length greater than that of the first barrier pattern 68a_1'.

[0141] The second barrier structure 68b' has a mirror-symmetric structure with the first barrier structure 68a'. The third barrier structure 68c' includes a bar-shaped first inner barrier pattern 168c_1 extending in the second direction Y, and a bar-shaped second inner barrier pattern 168c_2 extending in the second direction Y and arranged in a zigzag pattern with respect to the first inner barrier pattern 168c_1.

[0142] The boundary surface BR' that contacts the insulating horizontal layer of the insulating stack region ST_I and the gate horizontal layer of the gate stack region ST_G contacts the first to third barrier structures (68a', 68b', 68c').

[0143] In a modified example, referring to FIG. 8c, the first barrier structure 268a includes a first barrier pattern 268a_1 arranged in sequence in a first direction X, a second barrier pattern 268a_2 arranged in sequence in the first direction X, a third barrier pattern 268a_3 arranged in sequence in the first direction X, and a fourth barrier pattern 268a_4 arranged in sequence in the first direction X.

[0144] The separation distance between the first barrier pattern 268a_1 and the first main isolation structure 77m1 is substantially the same as the separation distance between the second barrier pattern 268a_2 and the first main isolation structure 77m1. The separation distance between the third barrier pattern 268a_3 and the first main isolation structure 77m1 is substantially the same as the separation distance between the fourth barrier pattern 268a_4 and the first main isolation structure 77m1. The separation distance between the first barrier pattern 268a_1 and the first main isolation structure 77m1 is smaller than the separation distance between the third barrier pattern 268a_3 and the first main isolation structure 77m1.

[0145] In the first barrier pattern 268a_1 and second barrier pattern 268a_2 adjacent to each other, the first barrier pattern 268a_1 includes a bar-shaped first horizontal portion 268H1 extending in the first direction X and a second horizontal portion 268V1 extending from a part of the first horizontal portion 268H1 in the second direction Y away from the first main isolation structure 77m1. The first horizontal portion 268H1 includes a first portion 268H1a ​​facing the second barrier pattern 268a_2 in the second direction Y and a second portion 268H1b not facing the second barrier pattern 268a_2 in the second direction Y. The second horizontal portion 268V1 extends from the second portion 268H1b.

[0146] The second barrier pattern 268a_2 includes a bar-shaped first horizontal portion 268H2 extending in the first direction X and a second horizontal portion 268V2 extending in the second direction Y from a part of the first horizontal portion 268H2 toward the first main isolation structure 77m1. The first horizontal portion 268H2 includes a first portion 268H2a facing the first barrier pattern 268a_1 in the second direction Y and a second portion 268H2b not facing the first barrier pattern 268a_1 in the second direction Y. The second horizontal portion 268V2 extends from the second portion 268H2b.

[0147] In the third barrier pattern 268a_3 and fourth barrier pattern 268d_2 adjacent to each other, the third barrier pattern 268a_3 includes a bar-shaped first horizontal portion 268H3 extending in the first direction X and a second horizontal portion 268V3 extending from a part of the first horizontal portion 268H3 in the second direction Y away from the first main isolation structure 77m1. The first horizontal portion 268H3 includes a first portion 268H3a facing the fourth barrier pattern 268a_4 in the second direction Y and a second portion 268H3b not facing the fourth barrier pattern 268a_4 in the second direction Y. The second horizontal portion 268V3 extends from the second portion 268H3b.

[0148] The fourth barrier pattern 268d_2 includes a bar-shaped first horizontal portion 268H4 extending in the first direction X and a second horizontal portion 268V4 extending in the second direction Y from a part of the first horizontal portion 268H4 toward the first main isolation structure 77m1. The first horizontal portion 268H4 includes a first portion 268H4a facing the third barrier pattern 268a_3 in the second direction Y and a second portion 268H4b not facing the third barrier pattern 268a_3 in the second direction Y. The second horizontal portion 268V4 extends from the second portion 268H4b.

[0149] The second horizontal portion 268V1 of the first barrier pattern 268a_1 faces the first portion 268H3a of the third barrier pattern 268a_3. The second horizontal portion 268V4 of the fourth barrier pattern 268a_4 faces the first portion 268H2a of the second barrier pattern 268a_2.

[0150] The second barrier structure 268b has a mirror symmetrical structure with the first barrier structure 268a. The third barrier structure 268c includes first and second inner barrier patterns (268c_1, 268c_2) corresponding to the first and second inner barrier patterns (68c_1, 68c_2) of the third barrier structure 68c described in FIG. 3.

[0151] At least one of the edge barrier patterns 268e located in the first direction X at the edge of the first barrier structure 168a is connected to at least one of the first and second inner barrier patterns (268c_1, 268c_2) of the third barrier structure 268c.

[0152] The boundary surface BRe that contacts the insulating horizontal layer of the insulating stack region ST_I and the gate horizontal layer of the gate stack region ST_G contacts the first to third barrier structures (268a, 268b, 268c).

[0153] In a modified example, referring to FIG. 8d, the first barrier structure 368a includes a first barrier pattern 368a_1 arranged in sequence in a first direction X, a second barrier pattern 368a_2 arranged in sequence in the first direction X, a third barrier pattern 368a_3 arranged in sequence in the first direction X, and a fourth barrier pattern 368a_4 arranged in sequence in the first direction X.

[0154] The separation distance between the first barrier pattern 368a_1 and the first main isolation structure 77m1 is substantially the same as the separation distance between the second barrier pattern 368a_2 and the first main isolation structure 77m1. The separation distance between the third barrier pattern 368a_3 and the first main isolation structure 77m1 is substantially the same as the separation distance between the fourth barrier pattern 368a_4 and the first main isolation structure 77m1. The separation distance between the first barrier pattern 368a_1 and the first main isolation structure 77m1 is smaller than the separation distance between the third barrier pattern 368a_3 and the first main isolation structure 77m1.

[0155] Any one of the first barrier patterns 368a_1 includes a bar-shaped first horizontal portion 368H1 extending in the first direction X and a second horizontal portion 368V1 extending from a part of the first horizontal portion 368H1 in the second direction Y away from the first main isolation structure 77m1. The first horizontal portion 368H1 includes a first portion 368H1a ​​and a third portion 368H1c facing the second barrier pattern 368a_2 in the second direction Y, and a second portion 368H1b not facing the second barrier pattern 368a_2 in the second direction Y. The second horizontal portion 368V1 extends from the second portion 368H1b. The second portion 368H1b is disposed between the first portion 368H1a ​​and the third portion 368H1c.

[0156] Any one of the second barrier patterns 368a_2 includes a bar-shaped first horizontal portion 368H2 extending in the first direction X and a second horizontal portion 368V2 extending in the second direction Y from a part of the first horizontal portion 368H2 toward the first main isolation structure 77m1. The first horizontal portion 368H2 includes a first portion 368H2a and a third portion 368H2c facing the first barrier pattern 368a_1 in the second direction Y, and a second portion 368H2b not facing the first barrier pattern 368a_1 in the second direction Y. The second horizontal portion 368V2 extends from the second portion 368H2b. The second portion 368H2b is disposed between the first portion 368H2a and the third portion 368H2c.

[0157] The third barrier pattern 368a_3 has the same shape as the first barrier pattern 368a_1, and the fourth barrier pattern 368a_4 has the same shape as the second barrier pattern 368a_2.

[0158] The second barrier structure 368b is a mirror image of the first barrier structure 368a. The third barrier structure 368c includes first and second inner barrier patterns 368c_1 and 368c_2, which correspond to the first and second inner barrier patterns 68a_3 and 68c_2 of the third barrier structure 68c described in FIG. 3.

[0159] At least one of the edge barrier patterns 368e located in the first direction X at the edge of the first barrier structure 368a is connected to at least one of the first and second inner barrier patterns (368c_1, 368c_2) of the third barrier structure 368c.

[0160] The boundary surface BRf, which contacts the insulating horizontal layer of the insulating stack region ST_I and the gate horizontal layer of the gate stack region ST_G, contacts the first to third barrier structures (368a, 368b, 368c).

[0161] In a modified example, referring to FIG. 8e, the first barrier structure 468a includes a first barrier pattern 468a_1 arranged in sequence in the first direction X and a second barrier pattern 468a_2 arranged in sequence in the first direction X.

[0162] Any one of the first barrier patterns 468a_1 includes first horizontal portions (468H1, 468H2) in the shape of parallel bars, and a second horizontal portion 468V connecting the first horizontal portions (468H1, 468H2).

[0163] The first horizontal portions (468H1, 468H2) are bar-shaped and extend in the first direction X, and are spaced apart in the second direction Y. The second horizontal portion 468V is bar-shaped and extends in the second direction Y from the center of the first horizontal portions (468H1, 468H2).

[0164] The second barrier pattern 468a_2 has a bar shape including a first portion that does not face the first barrier pattern 468a_1, and a second portion that extends from the first portion between the first horizontal portions (468H1, 468H2) and faces the second horizontal portion 468V.

[0165] Each of the first horizontal portions (468H1, 468H2) includes first and third portions (468H1a, 468H1c) facing the second barrier pattern 468a_2 and a second portion 468H1b not facing the second barrier pattern 468a_2 and disposed between the first and third portions (468H1a, 468H1c). The second horizontal portion 468V extends from the second portion 468H1b.

[0166] The second barrier structure 468b has a mirror symmetrical structure with the first barrier structure 468a. The third barrier structure 468c includes first and second inner barrier patterns (468c_1, 468c_2) corresponding to the first and second inner barrier patterns (68c_1, 68c_2) of the third barrier structure 68c described in FIG. 3.

[0167] At least one of the edge barrier patterns 468e located in the first direction X at the edge of the first barrier structure 468a is connected to at least one of the first and second inner barrier patterns (468c_1, 468c_2) of the third barrier structure 468c.

[0168] The boundary surface BRg that contacts the insulating horizontal layer of the insulating stack region ST_I and the gate horizontal layer of the gate stack region ST_G contacts the first to third barrier structures (468a, 468b, 468c).

[0169] Next, a modified example of the planar shape in Fig. 2 will be described with reference to Fig. 9. Fig. 9 is a plan view corresponding to the plan view in Fig. 2.

[0170] 9, a plurality of auxiliary isolation structures 177s are disposed between a first main isolation structure 77m1 and a second main isolation structure 77m2. A gate stack region ST_G and an insulating stack region ST_I surrounded by the gate stack region ST_G are disposed between the first main isolation structure 77m1 and the second main isolation structure 77m2.

[0171] A first auxiliary isolation structure 177Sa of any one of the multiple auxiliary isolation structures 177s extends between the insulating stack region ST_I and the first main isolation structure 77m1, and the remaining auxiliary isolation structures 117s have ends facing the insulating stack region ST_I.

[0172] A barrier structure 568 is disposed between the first auxiliary separation structure 177Sa and the second main separation structure 77m2. The barrier structure 568 is identical to any one of the various forms of barrier structures described in FIGS. 2 and 8a - 8e.

[0173] An additional supporter pattern 165 is disposed between the first auxiliary separation structure 177Sa and the first main separation structure 77m1. Each of the additional supporter patterns 165 is in the shape of a bar extending in the first direction X. Each of the additional supporter patterns 165 has a length in the first direction X that is greater than the width of each of the supporter patterns 65.

[0174] Similar to the lower selection gate separation pattern 36 described in FIGS. 2 and 3, a lower selection gate separation pattern 136 is disposed to separate at least three of the lower selection gate lines, which are the lower gate horizontal layers 35G among the gate horizontal layers (35G, 39G, 43G). Any one of the lower selection separation patterns 136 overlaps with an end of any one of the auxiliary separation structures of the auxiliary separation structures 177s, for example, the end of the auxiliary separation structure disposed in the central part, and extends to the insulating laminated region ST_I. The lower selection gate separation pattern 136 is located at a height level lower than the gate horizontal layers (39G, 43G), which are the word lines among the gate horizontal layers (35G, 39G, 43G).

[0175] Referring to FIG. 10, an exemplary example of the second lower gate horizontal layer 35g_Lb, which is the ground selection gate electrode described in FIG. 5a, will be described. FIG. 10 shows the second lower gate horizontal layer 35g_Lb and the insulating horizontal layer 35I' connected to the second lower gate horizontal layer 35g_Lb at a position corresponding to the plan view of FIG. 9.

[0176] 10, the second lower gate horizontal layer 35g_Lb includes a first ground selection gate electrode GSL_1a, a second ground selection gate electrode GSL_1b, and a third ground selection gate electrode GSL_1c that are physically separated from each other. The second and third ground selection gate electrodes GSL_1b and GSL_1c that are spaced apart from each other are connected to a single insulating horizontal layer 35I", and the first ground selection gate electrode GSL_1a is spaced apart from the insulating horizontal layer 35I".

[0177] For example, when the second lower gate horizontal layer 35g_Lb is made of a conductive material, the second and third ground selection gate electrodes GSL_1b and GSL_1c contact one insulating horizontal layer 35I''.

[0178] As an example, when the second lower gate horizontal layer 35g_Lb is formed of the first gate layer 45, which is a dielectric material layer, and the second gate layer 47, which is a conductive material layer, as described in FIG. 5a, the first gate layer 45 is interposed between the second and third ground selection gate electrodes (GSL_1b, GSL_1c) and one insulating horizontal layer 35I″. Therefore, the second and third ground selection gate electrodes (GSL_1b, GSL_1c) are connected to one insulating horizontal layer 35I″ via the first gate layer 45, which is a dielectric material layer.

[0179] The barrier structure 568, the support pattern 65, the additional support pattern 165, the isolation structure 177s, and the lower select gate isolation pattern 136 in FIG. 9 are openings (568h, 65h, 165h, 177h, 136h) that penetrate the second lower gate horizontal layer 35g_Lb.

[0180] 11 is a plan view showing one of the gate horizontal layers 39G and 43M, which are word lines described in FIG. 5A, and one insulating horizontal layer 43I' connected to and in contact with the gate horizontal layer 43M. Here, the gate horizontal layer 43M is the n-th word line layer WLn'.

[0181] Referring to FIG. 6b, any one of the gate horizontal layers WLn' is connected to any one of the insulating horizontal layers 43I' and surrounds the side surfaces of any one of the insulating horizontal layers 43I'.

[0182] For example, when the gate horizontal layer WLn is made of a conductive material, the gate horizontal layer WLn, which is a word line, contacts the insulating horizontal layer 43I'.

[0183] As an example, when the gate horizontal layer WLn is formed of a first gate layer 45 which is a dielectric material layer and a second gate layer 47 which is a conductive material layer as described in FIG. 5a, the second gate layer 47 is defined as a word line, and the first gate layer 45 is interposed between the word line and one insulating horizontal layer 43I′.

[0184] The barrier structure 68, the support pattern 65, the additional support pattern 165, and the isolation structure 177 described in FIG. 3 are openings (68h, 65h, 165h, 177h) that penetrate the gate horizontal layer WLn'.

[0185] The gate horizontal layer WLn′ has a gate pad region GP at an end in the first direction X, and the gate pad region GP is electrically connected to the gate contact plug 82 .

[0186] Therefore, any one gate horizontal layer, that is, one word line WLn, overlaps three gate horizontal layers, that is, three ground selection gate electrodes (GSL_1a, GSL_1b, GSL_1c).

[0187] Next, a modified example of the barrier structure 68 described in Fig. 5b will be described with reference to Fig. 12. Fig. 12 is a partially enlarged cross-sectional view showing a modified example of the barrier structure 68 in the partially enlarged cross-sectional view of Fig. 5b.

[0188] 12, the cross-sectional shape of the barrier structure 68 in FIG. 5b is modified to have a cross-sectional shape similar to that of the vertical memory structure 54. Therefore, the modified barrier structure 668 includes the same material as that of the vertical memory structure 54. For example, the barrier structure 668 includes a dummy insulating core pattern 60d, a dummy channel layer 58d covering the side and bottom of the dummy insulating core pattern 60d, a dummy information storage structure 56d disposed on the outer side and bottom of the dummy channel layer 58d, and a dummy pad pattern 62d on the dummy insulating core pattern 60d in contact with the dummy channel layer 58d. The side of the barrier structure 668 has an inflection portion 668V corresponding to the inflection portion (54V in FIG. 5a) of the side of the vertical memory structure (54 in FIG. 5a). For example, the barrier structure 668 includes a lower vertical portion 668L, an upper vertical portion 668U above the lower vertical portion 668L, and an inflection portion 668V between the lower vertical portion 668L and the upper vertical portion 668U.

[0189] Next, a modified example of the supporter pattern 65 described in Fig. 5c will be described with reference to Fig. 13. Fig. 13 is a partially enlarged cross-sectional view showing a modified example of the supporter pattern 65 in the partially enlarged cross-sectional view of Fig. 5c.

[0190] 13, the cross-sectional shape of the supporter pattern 65 in FIG. 5c is modified to resemble the cross-sectional shape of the vertical memory structure 54. Therefore, the modified supporter pattern 665 includes the same material as the vertical memory structure 54. For example, the supporter pattern 665 includes a dummy insulating core pattern 60d', a dummy channel layer 58d' covering the side and bottom of the dummy insulating core pattern 60d', a dummy information storage structure 56d' disposed on the outer side and bottom of the dummy channel layer 58d', and a dummy pad pattern 62d' on the dummy insulating core pattern 60d' in contact with the dummy channel layer 58d'. The side of the supporter pattern 665 has an inflection portion 665V corresponding to the inflection portion (54V in FIG. 5a) of the side of the vertical memory structure (54 in FIG. 5a). For example, the supporter pattern 665 includes a lower vertical portion 665L, an upper vertical portion 665U on the lower vertical portion 665L, and an inflection portion 665V between the lower vertical portion 665L and the upper vertical portion 665U.

[0191] Next, an example of a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 14a and 14b, in which Figure 14a is a plan view schematically showing a semiconductor device according to an embodiment of the present invention, and Figure 14b is a cross-sectional view schematically showing a region cut along line III-III' in Figure 14a.

[0192] 14a and 14b, the semiconductor device 1 according to the present embodiment further includes a through region BA located in the memory cell region MCA in the second direction Y. The through region BA is disposed between the memory cell regions MCA.

[0193] The penetration area BA is defined by main isolation structures 77m, at least one of which extends from at least one of the first and second main isolation structures (77m1, 77m2) in FIG.

[0194] The same stacked structure ST as described above is disposed in the through region BA. In the through region BA, the gate stacked region ST_G of the stacked structure ST is disposed in a region adjacent to the main isolation structure 77m, and the insulating stacked region ST_I of the stacked structure ST is disposed in a central region of the through region BA. In the stacked structure ST, the height of the top surface in the memory cell region MCA is the same as the height of the top surface in the through region BA.

[0195] Within the penetration area BA, a barrier structure 768 is arranged which penetrates the stack structure ST adjacent to the main isolation structure 77m.

[0196] The barrier structure 768 includes a first barrier structure 768a and a second barrier structure 768b that are parallel to each other and spaced apart in the second direction Y. Each of the first and second barrier structures (768a, 768b) is the same as any one of the various types of first barrier structures described in Figures 2 and 8a to 8e. For example, each of the first and second barrier structures (768a, 768b) includes the same barrier pattern as the first barrier structure 68a of Figure 3.

[0197] In the penetration region BA, a peripheral through contact plug 680 is disposed which penetrates the insulating stack region ST_I of the stack structure ST, extends downward, penetrates the gap fill insulating layer 26d which penetrates the pattern structure 16, and contacts the peripheral pad 11 of the peripheral circuit 7. The insulating stack region ST_I of the stack structure ST in the penetration region BA is defined as a third insulating stack region ST_Ic.

[0198] In the through region BA, the interface between the gate stack region ST_G and the insulating stack region ST_I contacts the barrier structure 768.

[0199] As described above, the bit line 93a is disposed on the vertical memory structure 54 disposed in the memory cell area MCA. The bit line 93a has a line shape extending in the second direction Y. The bit line 93a crosses the upper part of the through region BA.

[0200] The bit line 93a is electrically connected to the peripheral via contact plug 680. Therefore, the vertical memory structure 54 is electrically connected to the peripheral circuit 7 through the bit line 93a and the peripheral via contact plug 680.

[0201] Next, a modified example of the semiconductor device according to one embodiment of the present invention will be described with reference to Fig. 15. Fig. 15 is a cross-sectional view schematically showing a region cut along line II' in Fig. 1.

[0202] 15 , in a modified example, a semiconductor device 1a includes a first structure 900F and a second structure 900S. The first structure 900F includes a semiconductor substrate 5 and a peripheral circuit 7 as described with reference to FIGS. 1 to 4b. The peripheral circuit 7 includes peripheral transistors 8, peripheral wiring 10, and peripheral pads 11 as described with reference to FIGS. 1 to 4b. The first structure 900F includes a lower insulating layer 13′ that covers the peripheral circuit 7 on the semiconductor substrate 5 and has an upper surface that is coplanar with the upper surfaces of the peripheral pads 11.

[0203] The second structure 900S includes a pattern structure 16 as described in Figures 1 to 4b, a stack structure ST, a capping insulating structure 90, a vertical memory structure 54, a plurality of support patterns 65, a barrier structure 68, a gate contact plug 82, a plurality of peripheral through contact plugs 80, a bit line 93a, and a gate connecting wiring 93b.

[0204] The second structure 900S further includes an intermediate insulating layer 14 disposed between the pattern structure 16 and the first structure 900F, and bond pads 12 that are bonded to and in contact with the peripheral pads 11 of the first structure 900F. As an example, the peripheral pads 11 and the bond pads 12 are formed of a copper material. The intermediate insulating layer 14 covers the peripheral pads 11 and contacts the lower insulating layer 13′ of the first structure 900F.

[0205] The first structure 900F is one semiconductor chip, and the second structure 900S is one semiconductor chip. Through the wafer bonding process, the peripheral pads 11 of the first structure 900F, which is one semiconductor chip, and the bonding pads 12 of the second structure 900S, which is also one semiconductor chip, are bonded while contacting each other. Therefore, the semiconductor device 1a includes the bonded first and second structures (900F, 900S), i.e., two bonded semiconductor chips.

[0206] In this embodiment, the peripheral circuit 7 of the first structure 900F is described as being disposed below the stacked structure ST of the second structure 900S, but the technical concept of the present invention is not limited thereto. For example, the technical concept of the present invention includes an embodiment in which a peripheral circuit corresponding to the peripheral circuit 7 is disposed above the stacked structure ST of the second structure 900S with respect to the stacked structure ST of the second structure 900S. In this case, a peripheral circuit corresponding to the peripheral circuit 7 and a semiconductor substrate corresponding to the semiconductor substrate 5 are disposed in this order above the stacked structure ST of the second structure 900S.

[0207] 16 to 18b are cross-sectional views that schematically illustrate a method of forming a semiconductor device according to one embodiment of the present invention.

[0208] 16, a lower structure 3 is formed. The lower structure 3 includes a semiconductor substrate 5, a peripheral circuit 7 on the semiconductor substrate 5, a lower insulating layer 13 covering the peripheral circuit 7 on the semiconductor substrate 5, a pattern structure 16 on the lower insulating layer 13, gap fill insulating layers (26a, 26b) penetrating the pattern structure 16, and an outer insulating layer 26c covering the outer surface of the pattern structure 16. The pattern structure 16 includes a lower pattern layer 18, an intermediate pattern layer 19 on the lower pattern layer 18, and an upper pattern layer 23 on the intermediate pattern layer 19. The intermediate pattern layer 19 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, which are stacked in this order. The lower and upper pattern layers (18, 23) are polysilicon layers.

[0209] A preliminary lower laminate structure ST_L' is formed on the lower structure 3. The preliminary lower laminate structure ST_L' includes lower interlayer insulating layers 33 and preliminary lower horizontal layers 35' that are alternately and repeatedly stacked. A capping insulating layer is formed to cover the preliminary lower laminate structure ST_L'.

[0210] A first preliminary upper laminate structure ST_U1' is formed on the preliminary lower laminate structure ST_L'. The first preliminary upper laminate structure ST_U1' includes a first upper interlayer insulating layer 37 and a first preliminary upper horizontal layer 39', which are alternately stacked. The preliminary lower horizontal layer 35' and the first preliminary upper horizontal layer 39' are made of silicon nitride. A capping insulating layer 90a is formed to cover the first preliminary upper laminate structure ST_U1'.

[0211] A lower vertical structure 54L' is formed to pass through the preliminary lower laminate structure ST_L' and the first preliminary upper laminate structure ST_U1'.

[0212] Referring to FIG. 17, a second preliminary upper stack structure ST_U2' is formed on the first preliminary upper stack structure ST_U1'. The second preliminary upper stack structure ST_U2' includes second upper interlayer insulating layers 41 and second preliminary upper horizontal layers 43', which are alternately stacked. The second preliminary upper horizontal layers 43' are formed of silicon nitride. A capping insulating layer 90b is formed to cover the second preliminary upper stack structure ST_U2'. Because the capping insulating layer 90b is formed of the same material as the capping insulating layer 90a formed in FIG. 16, the boundary between the capping insulating layer 90b and the capping insulating layer 90a formed in FIG. 16 is unclear or non-existent. Hereinafter, the component referred to as the capping insulating layer will be described as a single layer, without distinguishing them as separate boundaries, due to the unclear boundary.

[0213] The preliminary lower laminate structure ST_L', the first preliminary upper laminate structure ST_U1', and the second preliminary upper laminate structure ST_U2' constitute the preliminary laminate structure ST'. After forming a preliminary channel hole that penetrates the second preliminary upper laminate structure ST_U2' and exposes the lower vertical structure 54L', the lower vertical structure 54L' is removed to form a channel hole that penetrates the preliminary laminate structure ST'. The vertical memory structure 54 is formed in the channel hole.

[0214] 18a and 18b, a barrier structure 68 and a support pattern (65 in FIGS. 2 and 3) are formed through the pre-layer structure ST′. For example, the barrier structure 68 and the support pattern (65 in FIGS. 2 and 3) are formed simultaneously. For example, the barrier structure 68 and the support pattern (65 in FIGS. 2 and 3) are formed of silicon oxide. After forming the capping insulating layer 90c, an isolation trench for forming the isolation structure 77 is formed. The isolation trench extends through the pre-layer structure ST′ into the pattern structure 16. The intermediate pattern layer in the memory cell area MCA exposed by the isolation trench is replaced with a first intermediate pattern layer 20. The first intermediate pattern layer 20 is formed as a polysilicon layer, and the remaining intermediate pattern layer is referred to as a second intermediate pattern layer 21.

[0215] An etching process is performed to partially etch the preliminary lower horizontal layer 35', the first preliminary upper horizontal layer 39', and the second preliminary upper horizontal layer 43' exposed by the isolation trenches to form empty spaces, and gate horizontal layers are formed to fill the empty spaces. The gate horizontal layers (35G, 39G, 43G) are as described in FIG. 5a. The remaining horizontal layers of the preliminary lower horizontal layer 35', the first preliminary upper horizontal layer 39', and the second preliminary upper horizontal layer 43' are referred to as insulating horizontal layers (35I, 39I, 43I). Thus, horizontal layers including the gate horizontal layers (35G, 39G, 43G) and the insulating horizontal layers (35I, 39I, 43I) are formed. Thus, a stack structure ST including the horizontal layers is formed. Next, isolation structures (77m1, 77m2) are formed to fill the isolation trenches.

[0216] 4a and 4b, an additional capping insulating layer is formed to form peripheral via contact plugs 80 and gate contact plugs 82. Then, an additional capping insulating layer is formed to form capping insulating structures 90. Then, connecting patterns 85a, 85b, and 85c are formed to form bit lines 93a and gate connecting wires 93b.

[0217] In the embodiment, as described with reference to FIG. 17 , during the etching process for partially etching the preliminary lower horizontal layer 35′, the first preliminary upper horizontal layer 39′, and the second preliminary upper horizontal layer 43′ exposed by the isolation trench to form a void space, the barrier structure 68 lengthens the path of the etching gas or etching solution for etching the preliminary lower horizontal layer 35′, the first preliminary upper horizontal layer 39′, and the second preliminary upper horizontal layer 43′. The barrier structure 68 prevents the preliminary lower horizontal layer 35′, the first preliminary upper horizontal layer 39′, and the second preliminary upper horizontal layer 43′ located in the area surrounded by the barrier structure 68 from being etched. This increases the planar area of ​​the insulating stack region ST_I defined between the first and second main isolation structures (77m1 and 77m2 in FIGS. 2 and 3). Therefore, the barrier structure 68 increases the space for disposing the peripheral via contact plug 80 without increasing the total area. This improves the integration density of the semiconductor device 1.

[0218] In the embodiment, the supporter pattern 65 can prevent the interlayer insulating layers (33, 37, 41) from bending or deforming during an etching process that partially etches the preliminary lower horizontal layer 35′, the first preliminary upper horizontal layer 39′, and the second preliminary upper horizontal layer 43′ exposed by the isolation trench to form empty spaces. Therefore, the supporter pattern 65 can prevent some of the gate horizontal layers (35G, 39G, 43G) from becoming thin or short-circuiting, thereby improving the reliability of the semiconductor device 1.

[0219] FIG. 19 is a diagram that schematically illustrates an exemplary data storage system including a semiconductor device according to one embodiment of the present invention.

[0220] 19, an exemplary data storage system 1000 according to one embodiment of the present invention includes a semiconductor device 1100 and a controller 1200 electrically coupled to the semiconductor device 1100. The data storage system 1000 is a storage device including the semiconductor device 1100 or an electronic device including a storage device. For example, the data storage system 1000 is a solid state drive device (SSD) including the semiconductor device 1100, a Universal Serial Bus (USB), a computing system, a medical device, or a communication device.

[0221] In an embodiment, data storage system 1000 is an electronic system that stores data.

[0222] The semiconductor device 1100 is a semiconductor device according to any one of the embodiments described above with reference to Figures 1 to 15. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0223] In one embodiment, the first structure 1100F is positioned next to the second structure 1100S.

[0224] In one embodiment, the semiconductor device 1000 includes two semiconductor chips bonded to each other. For example, in the semiconductor device 1000, the first structure 1100F is one semiconductor chip, and the second structure 1100S is one semiconductor chip bonded to the first structure 1100F by a wafer bonding process. For example, a pad made of a copper material on the first structure 1100F and a pad made of a copper material on the second structure 1100S are bonded to each other while contacting each other. Therefore, the semiconductor device 1000 includes the first and second structures (1100F, 1100S) bonded to each other, i.e., two semiconductor chips bonded to each other.

[0225] The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. For example, the first structure 1100F includes the peripheral circuit (7 in FIG. 4a or FIG. 15) described above.

[0226] The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0227] The above-mentioned pattern structure (16 in FIG. 4a) includes silicon layers (18, 20, 23) having N-type conductivity, which are the common source line CSL.

[0228] In the second structure 1100S, each memory cell string CSTR includes lower transistors (LT1, LT2) adjacent to a common source line CSL, upper transistors (UT1, UT2) adjacent to a bit line BL, and a plurality of memory cell transistors MCT arranged between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of the lower transistors (LT1, LT2) and the number of the upper transistors (UT1, UT2) may vary depending on the embodiment.

[0229] In one embodiment, the upper transistors (UT1, UT2) comprise string selection transistors, and the lower transistors (LT1, LT2) comprise ground selection transistors. The gate lower lines (LL1, LL2) are the gate electrodes of the lower transistors (LT1, LT2), respectively. The word line WL is the gate electrode of the memory cell transistor MCT, and the gate upper lines (UL1, UL2) are the gate electrodes of the upper transistors (UT1, UT2), respectively.

[0230] The above-mentioned gate horizontal layers (35G, 39G, 43G) constitute the gate lower lines (LL1, LL2), word lines WL, and gate upper lines (UL1, UL2). For example, as shown in FIG. 5a, the first and second lower gate horizontal layers (35g_La, 35Lb) constitute the gate lower lines (LL1, LL2), the gate horizontal layers (39G, 43M) constitute the word lines WL, and the first and second upper gate horizontal layers (43g_Ua, 43g_Ub) constitute the gate upper lines (UL1, UL2).

[0231] In one embodiment, the lower transistors (LT1, LT2) include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors (UT1, UT2) include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 is used in an erase operation that erases data stored in the memory cell transistor MCT using a gate-induced drain leakage (GIDL) phenomenon.

[0232] The common source line CSL, the first and second gate lower lines (LL1, LL2), the word line WL, and the first and second gate upper lines (UL1, UL2) are electrically connected to the decoder circuit 1110 via a first connecting wiring 1115 extending from within the first structure 1100F to the second structure 1100S.

[0233] The first connecting wire 1115 is composed of the gate contact plug 82, the gate connecting wire 93b, and the peripheral through contact plug 80 described above.

[0234] The bit lines BL are electrically connected to the page buffer 1120 via second interconnections 1125 extending from within the first structure 1100F to the second structure 1100S. The bit lines BL are the bit lines (93a in FIGS. 4a, 4b, and 15) described above.

[0235] In the first structure 1100F, a decoder circuit 1110 and a page buffer 1120 perform control operations on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controlled by a logic circuit 1130. The semiconductor device 1000 communicates with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 is electrically connected to the logic circuit 1130 via an input / output connecting wiring 1135 extending from within the first structure 1100F to the second structure 1100S.

[0236] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on the embodiment, the data storage system 1000 includes multiple semiconductor devices 1100, in which case the controller 1200 controls the multiple semiconductor devices 1000.

[0237] The processor 1210 controls the controller 1200 and other components of the data storage system 1000. The processor 1210 operates according to predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a NAND interface 1221 that handles communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors MCTs of the semiconductor device 1100, and data to be read from the memory cell transistors MCTs of the semiconductor device 1100 are transmitted via the NAND interface 1221. The host interface 1230 provides communication between the data storage system 1000 and an external host. Upon receiving a control command from the external host via the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0238] FIG. 20 is a schematic perspective view of a data storage system including an exemplary semiconductor device according to one embodiment of the present invention.

[0239] 20, an exemplary data storage system 2000 according to an embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are connected to the controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0240] The main board 2001 includes a connector 2006 including a plurality of pins that are coupled to an external host. The number and arrangement of the pins in the connector 2006 vary depending on the communication interface between the data storage system 2000 and the external host. In one embodiment, the data storage system 2000 communicates with the external host via any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Storage (UFS). In one embodiment, the data storage system 2000 operates using power supplied from the external host via the connector 2006. The data storage system 2000 further includes a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0241] The controller 2002 records data to or reads data from the semiconductor package 2003 to improve the operating speed of the data storage system 2000 .

[0242] The DRAM 2004 is a buffer memory for mitigating the speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 also operates as a kind of cache memory, providing space for temporarily storing data during control operations for the semiconductor package 2003. When the data storage system 2000 includes the DRAM 2004, the controller 2002 further includes a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0243] The semiconductor package 2003 includes first and second semiconductor packages (2003a, 2003b) spaced apart from each other. Each of the first and second semiconductor packages (2003a, 2003b) includes a plurality of semiconductor chips 2200. Each of the semiconductor chips 2200 includes a semiconductor device according to any one of the embodiments described above with reference to FIGS. 1 to 15.

[0244] Each of the first and second semiconductor packages (2003a, 2003b) includes a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each of the semiconductor chips 2200, a connecting structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.

[0245] Package substrate 2100 is a printed circuit board that includes package top pads 2130. Each semiconductor chip 2200 includes input / output pads 2210.

[0246] In one embodiment, the connecting structure 2400 is a bonding wire that electrically connects the I / O pad 2210 and the package upper pad 2130. Therefore, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 are electrically connected to each other by a bonding wire method and are electrically connected to the package upper pad 2130 of the package substrate 2100. Depending on the embodiment, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 are electrically connected to each other by a connecting structure including a through silicon via (TSV), instead of the connecting structure 2400 in the form of a bonding wire.

[0247] In one embodiment, the controller 2002 and the semiconductor chip 2200 are included in one package. For example, the controller 2002 and the semiconductor chip 2200 are mounted on an interposer substrate separate from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 are connected to each other by wiring formed on the interposer substrate.

[0248] 21 is a cross-sectional view schematically illustrating an exemplary semiconductor package according to an embodiment of the present invention. FIG. 21 illustrates an embodiment of the exemplary semiconductor package 2003 of FIG. 20, and conceptually illustrates a region of the semiconductor package 2003 of FIG. 20 cut along section line IV-IV′.

[0249] 21, in a semiconductor package 2003, a package substrate 2100 is a printed circuit board. The package substrate 2100 includes a package substrate body 2120, package upper pads 2130 disposed on the upper surface of the package substrate body 2120, package lower pads 2125 disposed on the lower surface of the package substrate body 2120 or exposed through the lower surface, and internal wiring 2135 electrically connecting the package upper pads 2130 and the package lower pads 2125 inside the package substrate body 2120. The package upper pads 2130 are electrically connected to a connecting structure 2400. The package lower pads 2125 are connected to a wiring pattern 2005 of a main board 2001 of a data storage system 2000 via a conductive connecting portion 2800, as shown in FIG. 20.

[0250] Each semiconductor chip 2200 includes a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 stacked in order on the semiconductor substrate 3010. The first structure 3100 includes a peripheral circuit region including peripheral wiring 3110. The second structure 3200 includes a common source line 3205, a gate stack structure 3210 on the common source line 3205, a memory channel structure 3220 and an isolation structure 3230 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the memory channel structure 3220, and a gate connecting wiring (93b in FIG. 4a) electrically connected to a word line (WL in FIG. 19) of the gate stack structure 3210. The first structure 3100 includes the first structure 1100F in FIG. 19, and the second structure 3200 includes the second structure 1100S in FIG. 19. Therefore, each of the semiconductor chips 2200 includes the semiconductor device 1 according to any one of the embodiments described above with reference to FIGS.

[0251] Each of the semiconductor chips 2200 includes a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 penetrates the gate stack structure 3210 and is further disposed outside the gate stack structure 3210. The through wiring 3245 is the peripheral through contact plug 680 shown in FIG.

[0252] Each of the semiconductor chips 2200 further includes an input / output connecting wiring 3265 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200, and an input / output pad 2210 electrically connected to the input / output connecting wiring 3265.

[0253] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0254] BA penetration area BL Bit Line BR, BR1~BR3 interface CSa, CSb Stair connection area CSL Common Source Line CSTR Memory Cell String GP gate pad area GSL_1, GSL_2: First and second ground selection gate electrode layers (gate horizontal layers) GSL_1a, GSL_1b, GSL_1c 1st to 3rd ground selection gate electrode ISa, ISb intermediate staircase area IS1a, IS1b 1st intermediate staircase area IS2a, IS2b 2nd intermediate staircase area LS1a, LS2b 1st lower staircase area LS2 2nd lower staircase area LL1, LL2 First and second gate lower lines LT1 Lower erase control transistor (lower transistor) LT2 Ground selection transistor (lower transistor) MCA memory cell area (first area, memory area) MCT memory cell transistor SA Staircase region (second region, connecting region, contact region) ST laminated structure ST' Pre-laminate structure ST_G Gate stack area ST_I Insulating stacked area ST_Ia, ST_Ib, ST_Ic 1st to 3rd insulating laminated regions ST_L Lower laminated structure ST_L' spare lower laminate structure ST_U1, ST_U2 1st and 2nd upper stack structures ST_U1', ST_U2' 1st and 2nd spare upper stack structures UL1, UL2 1st and 2nd gate upper lines USa, USb Upper staircase area UT1 String selection transistor (upper transistor) UT2 Upper erase control transistor (upper transistor) WL Word Line WLn, WLn' nth word line layer (gate horizontal layer) 1, 1a Semiconductor device 3 Substructure 5. Semiconductor substrate 7 Peripheral circuits 8 Peripheral transistors 10 Peripheral wiring 11 Peripheral Pads 12 Bonding Pads 13, 13' Lower insulating layer 14 Intermediate insulating layer 16 Pattern Structures 18, 23 Lower and upper pattern layers 19 Intermediate pattern layer 19a, 19b, 19c 1st to 3rd layer 20, 21 First and second intermediate pattern layers 26a, 26b First and second gap fill insulating layers 26c outer insulation layer 26d Gap fill insulating layer 33 Lower interlayer insulating layer 35 Lower horizontal layer (top horizontal layer) (1st horizontal layer) 35' Reserve Lower Horizontal Layer 35G Lower Gate Horizontal Layer 35g_La First lower gate horizontal layer (lower erase control gate electrode) 35g_Lb Second lower gate horizontal layer (lower select gate electrode, ground select gate electrode) 35I Lower insulating horizontal layer 35I', 35I", 43I' Insulating horizontal layer 35P gate pad area 36, 136 Lower select gate isolation pattern 36h, 65h, 68h, 77h, 136h, 165h, 177h, 568h opening 37, 41 First and second upper interlayer insulating layers 39, 43 1st and 2nd upper horizontal layer 39', 43' 1st and 2nd preliminary upper horizontal layers 39G First Upper Gate Horizontal Layer 39I, 43I First and second upper insulating horizontal layers 39P, 43P gate pad area 43G Gate horizontal layer (word line) 43g_Ua First upper gate horizontal layer (upper select gate electrode, string select gate electrode) 43g_Ub Second upper gate horizontal layer (upper erase control gate electrode) 43M, 43G Second upper gate horizontal layer 45 Gate dielectric layer (first gate layer) (insulating layer) 47 gate electrode layer (second gate layer, word line) 50 Upper select gate separation line 54 Vertical Memory Structure 54L' Lower vertical structure 54L, 665L, 668L lower vertical section 54U, 665U, 668U Upper vertical section 54V, 665V, 668V bending section 56 Information storage structure 56a, 56c First and second dielectric layers 56b Information storage layer 56d Dummy information storage structure 56L, 56U lower and upper parts 58 Channel Layer 58d, 58d' dummy channel layer 60 insulating core pattern 60d, 60d' dummy insulating core pattern 62 Pad Patterns 62d, 62d' dummy pad patterns 65, 665 supporter pattern 68, 568, 668, 768 Barrier structures 68a, 68a', 168a, 268a, 368a, 468a, 768a First Barrier Structure 68b, 68b', 168b, 268b, 368b, 468b, 768b Second Barrier Structure 68c, 68c', 168c, 268c, 368c, 468c Third Barrier Structure 68d Fourth Barrier Structure 68a_1, 68a_1', 168a_1, 268a_1, 368a_1, 468a_1 First barrier pattern 68a_2, 68a_2', 168a_2, 268a_2, 368a_2, 468a_2 Second barrier pattern 68a_3, 68a_3', 68c_1, 168c_1, 268c_1, 368c_1, 468c_1 First inner barrier pattern 68b_3, 68c_2, 168c_2, 268c_2, 368c_2, 468c_2 Second inner barrier pattern 68b_1, 268a_3, 368a_3 Third barrier pattern 68b_2, 268a_4, 368a_4 4th barrier pattern 68e, 168e1, 168e2, 268e, 468e edge barrier patterns 77s, 177s Auxiliary separation structure 77, 177 separation structure 77m Main separation structure 77m1, 77m2 1st and 2nd main separation structures 80, 680 Peripheral through contact plug 82 Gate contact plug 82d Dummy gate contact plug 85a Bit line connection pattern 85b Gate connection pattern 85c Peripheral Connecting Pattern 90 Capping insulation structure 90a, 90b, 90c Capping insulating layer 93a Bit Line 93b Gate connecting wiring 165 additional supporter patterns 177Sa 1st auxiliary separation structure 268H1, 268H2, 268H3, 268H4, 368H1, 368H2, 468H1, 468H2 1st horizontal part 268H1a, 268H2a, 268H3a, 268H4a, 368H1a, 368H2a, 468H1a ​​Part 1 268H1b, 268H2b, 268H3b, 268H4b, 368H1b, 368H2b, 468H1b 2nd part 268V1, 268V2, 268V3, 268V4, 368V1, 368V2, 468V 2nd horizontal section 368H1c, 368H2c, 468H1c 3rd part 900F, 900S 1st and 2nd structures 1000, 2000 Data Storage System 1100 Semiconductor devices 1100F, 1100S 1st and 2nd structures 1101 Input / Output Pad 1110 Decoder Circuit 1115, 1125 1st and 2nd connection wiring 1120 page buffer 1130 Logic Circuit 1135 Input / output connection wiring 1200 Controller 1210 processor 1220 NAND controller 1221 NAND interface 1230 Host Interface 2001 Main board 2002 Controller 2003 Semiconductor Package 2003a, 2003b First and second semiconductor packages 2004 DRAM 2005 Wiring Pattern 2006 Connector 2100 package substrate 2120 Package substrate main body 2125 Package bottom pad 2130 Package top pad 2135 Internal wiring 2200 semiconductor chips 2210 Input / Output Pad 2300 Adhesive layer 2400 Connected structures 2500 molding layer 2800 Conductive connection part 3010 Semiconductor substrate 3100, 3200 1st and 2nd structures 3110 Peripheral wiring 3205 Common Source Line 3210 Gate stack structure 3220 Memory Channel Structure 3230 Separation Structure 3240 bit lines 3245 Through Wiring 3265 Input / output connection wiring

Claims

1. a substructure including peripheral circuits; a laminated structure including interlayer insulating layers and horizontal layers alternately and repeatedly stacked on the lower structure; a vertical memory structure that penetrates the stacked structure in a vertical direction; a first barrier structure and a second barrier structure that are parallel to each other and penetrate the stacked structure in the vertical direction; a support pattern that penetrates the laminate structure in the vertical direction and separates it from the first and second barrier structures; a plurality of via contact plugs that penetrate the stack structure in the vertical direction between the first barrier structure and the second barrier structure; the first barrier structure includes first barrier patterns spaced apart from one another and arranged in a first direction, and second barrier patterns spaced apart from one another and arranged in the first direction, each of the first and second barrier patterns has a line shape extending in the first direction; a portion of the first barrier pattern faces a portion of the second barrier pattern in a second direction perpendicular to the first direction, the second barrier pattern being adjacent to the first barrier pattern and the second barrier pattern being adjacent to the second barrier pattern; further comprising a third barrier structure disposed between an end of the first barrier structure and an end of the second barrier structure; the third barrier structure includes a horizontal pattern; The semiconductor device is characterized in that each of the horizontal patterns has a line shape extending in the second direction.

2. 2. The semiconductor device according to claim 1, wherein a length in the first direction of a portion of the second barrier pattern and a portion of the first barrier pattern facing the second direction is greater than a width in the first direction of the support pattern.

3. 2. The semiconductor device according to claim 1, wherein the length in the first direction of a portion of the second barrier pattern and a portion of the first barrier pattern facing the second direction is at least twice as large as the width in the first direction of the supporter pattern.

4. the second barrier structure includes third barrier patterns spaced apart from one another and arranged in the first direction, and fourth barrier patterns spaced apart from one another and arranged in the first direction, each of the third and fourth barrier patterns has a line shape extending in the first direction; 2. The semiconductor device according to claim 1, wherein, in the third and fourth barrier patterns adjacent to each other, a portion of the third barrier pattern faces a portion of the fourth barrier pattern in the second direction.

5. the first barrier structure further includes inner barrier patterns spaced apart from each other and arranged in the first direction, each of the inner barrier patterns has a line shape extending in the first direction; 2. The semiconductor device according to claim 1, wherein, in the inner barrier pattern and the second barrier pattern adjacent to each other, a portion of the inner barrier pattern faces a portion of the second barrier pattern in the second direction.

6. The semiconductor device of claim 1 , wherein the horizontal pattern has an end portion facing the first barrier structure in the second direction.

7. The semiconductor device of claim 1 , wherein one of the horizontal patterns is connected to one of the first and second barrier patterns.

8. 2. The semiconductor device according to claim 1, wherein, in a first barrier pattern and a second barrier pattern adjacent to each other, the length of the second barrier pattern in the first direction is greater than the length of the first barrier pattern in the first direction.

9. further comprising a plurality of isolation structures that penetrate the laminated structure in the vertical direction; The plurality of isolation structures include: a first main isolation structure and a second main isolation structure parallel to each other; a secondary isolation structure between the first main isolation structure and the second main isolation structure, the first and second barrier structures are disposed between the first main isolation structure and the second main isolation structure; 2. The semiconductor device of claim 1, wherein at least two of the auxiliary isolation structures have ends facing a region of the stack structure located between the first barrier structure and the second barrier structure.

10. The horizontal layers include a first horizontal layer located at a first height level and a second horizontal layer located at a second height level higher than the first height level; the first horizontal layer includes a plurality of select gate electrode layers spaced apart from each other and a first insulating horizontal layer connected to the plurality of select gate electrode layers; the second horizontal layer includes a first word line layer and a second insulating horizontal layer connected to the first word line layer; the first word line layer overlaps the plurality of select gate electrode layers in the vertical direction; the second insulating horizontal layer overlaps the first insulating horizontal layer in the vertical direction; 2. The semiconductor device according to claim 1, wherein the plurality of through contact plugs penetrate the first and second insulating horizontal layers.

11. the first horizontal layer further includes a first insulating layer between the plurality of select gate electrode layers and the first insulating horizontal layer; 11. The semiconductor device of claim 10, wherein the second horizontal layer further comprises a second insulating layer between the one first word line layer and the second insulating horizontal layer.

12. The semiconductor device of claim 10 , wherein the first word line layer and a first select gate electrode layer of the plurality of select gate electrode layers surround each side of the first barrier pattern.

13. 11. The semiconductor device of claim 10, wherein a portion of the first barrier structure contacts at least one of the first and second insulating horizontal layers.

14. the horizontal layers further include a third horizontal layer higher than the second height level; the first horizontal layer further includes a third insulating horizontal layer connected to the plurality of selection gate electrode layers; the second horizontal layer further includes a fourth insulating horizontal layer connected to the one first word line layer; the third horizontal layer includes one second word line layer and a fifth insulating horizontal layer connected to the one second word line layer; the first insulating horizontal layer, the second insulating horizontal layer, and the fifth insulating horizontal layer overlap in the vertical direction; the third insulating horizontal layer and the fourth insulating horizontal layer overlap in the vertical direction; 11. The semiconductor device of claim 10, wherein the third insulating horizontal layer and the fourth insulating horizontal layer do not overlap the first insulating horizontal layer, the second insulating horizontal layer, and the fifth insulating horizontal layer in the vertical direction.

15. the plurality of through contact plugs are electrically connected to peripheral pads of the peripheral circuit; 2. The semiconductor device according to claim 1, wherein the vertical memory structure includes an insulating core pattern, a channel layer covering at least a side surface of the insulating core pattern, and an information storage structure on an outer surface of the channel layer.

16. a substructure including peripheral circuits; a stacked structure on the lower structure, extending from a memory cell region and having a staircase shape, the stacked structure including interlayer insulating layers and horizontal layers alternately stacked in the memory cell region; a first main isolation structure and a second main isolation structure that are parallel to each other and penetrate the stacked structure on the lower structure; a vertical memory structure that vertically penetrates the memory cell region of the stacked structure; a support pattern penetrating the staircase region of the laminated structure; a first barrier structure and a second barrier structure parallel to each other and penetrating a staircase region of the stacked structure between the first main isolation structure and the second main isolation structure; a plurality of via contact plugs penetrating the stack structure between the first barrier structure and the second barrier structure; the horizontal layers include a gate horizontal layer and an insulating horizontal layer; the support pattern penetrates the gate horizontal layer; the plurality of through contact plugs penetrate the insulating horizontal layer; each of the first and second barrier structures includes a first barrier pattern spaced apart from one another and arranged in a first direction, and a second barrier pattern spaced apart from one another and arranged in the first direction; At least a portion of each of the first and second barrier patterns has a line shape extending in the first direction, a portion of the first barrier pattern faces a portion of the second barrier pattern in a second direction perpendicular to the first direction, the second barrier pattern being adjacent to the first barrier pattern and the second barrier pattern being adjacent to the second barrier pattern; further comprising a third barrier structure disposed between an end of the first barrier structure and an end of the second barrier structure; the third barrier structure includes a horizontal pattern; The semiconductor device is characterized in that each of the horizontal patterns has a line shape extending in the second direction.

17. 17. The semiconductor device of claim 16, wherein a length in the first direction of a portion of the second barrier pattern and a portion of the first barrier pattern facing the second direction is at least twice as large as a width in the first direction of the supporter pattern.

18. The main board and a semiconductor device on the main substrate; a controller electrically connected to the semiconductor device on the main board; The semiconductor device includes: a substructure including peripheral circuits; a laminated structure including interlayer insulating layers and horizontal layers alternately and repeatedly stacked on the lower structure; a vertical memory structure that penetrates the stacked structure in a vertical direction; a first barrier structure and a second barrier structure that are parallel to each other and penetrate the stacked structure in the vertical direction; a support pattern that penetrates the laminate structure in the vertical direction and separates it from the first and second barrier structures; a plurality of via contact plugs that penetrate the stack structure in the vertical direction between the first barrier structure and the second barrier structure; the first barrier structure includes first barrier patterns spaced apart from one another and arranged in a first direction, and second barrier patterns spaced apart from one another and arranged in the first direction, At least a portion of each of the first and second barrier patterns has a line shape extending in the first direction, a portion of the first barrier pattern faces a portion of the second barrier pattern in a second direction perpendicular to the first direction, the second barrier pattern being adjacent to the first barrier pattern and the second barrier pattern being adjacent to the second barrier pattern; further comprising a third barrier structure disposed between an end of the first barrier structure and an end of the second barrier structure; the third barrier structure includes a horizontal pattern; A data storage system, wherein each of the horizontal patterns is in the form of a line extending in the second direction.

19. a length in the first direction of a portion of the second barrier pattern and a portion of the first barrier pattern facing the second direction is greater than a width in the first direction of the support pattern; The horizontal layers include a first horizontal layer located at a first height level and a second horizontal layer located at a second height level higher than the first height level; the first horizontal layer includes a plurality of select gate electrode layers spaced apart from each other and a first insulating horizontal layer connected to the plurality of select gate electrode layers; the second horizontal layer includes a first word line layer and a second insulating horizontal layer connected to the first word line layer; the first word line layer overlaps the plurality of select gate electrode layers in the vertical direction; the second insulating horizontal layer overlaps the first insulating horizontal layer in the vertical direction; the plurality of through contact plugs are electrically connected to peripheral pads of the peripheral circuit by passing through the first and second insulating horizontal layers; 20. The data storage system of claim 18, wherein the vertical memory structure includes an insulating core pattern, a channel layer covering at least the sides of the insulating core pattern, and an information storage structure on an outer surface of the channel layer.

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