Wiring board and method for manufacturing the same

Abstract

To suppress deterioration of a manufacturing efficiency while securing connection reliability with an electronic component.SOLUTION: A wiring board includes: a wiring layer comprising a first pad in which a concave part is formed on a front surface, and a second pad in which a concave part deeper than the concave part of the first pad is formed to the front surface; an insulation layer having a first open part penetrated to the concave part of the first pad while coating to the wiring layer and a second open part of a large diameter from the first open part while being penetrated to the concave part of the second pad; a first metal layer that fills an inner part of the first open part and the second open part, is extended to an upper surface of the insulation layer, and includes the concave part at the position overlapped with the first open part and the second open part in a plan view; and a second metal layer that is formed so as to be overlapped to the first metal layer, in which one part is housed in the concave part of the upper surface of the first metal layer. A thickness of a part extended to the upper surface of the insulation layer is uniform in the first metal layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] Generally, wiring boards on which semiconductor chips are mounted have bumps formed as connection terminals for the semiconductor chip. Bumps are metal protrusions that connect to the conductor layer of the wiring board and protrude outward from openings in the solder resist layer that covers the conductor layer. Such bumps may have a two-layer structure formed by plating two different types of metal, for example.

[0003] Specifically, a first metal layer, such as copper, is plated in and around an opening in a solder resist layer, and a second metal layer, such as tin or solder, is plated on top of the first metal layer. Then, a reflow process is performed to melt and solidify only the second metal layer, forming a spherical bump. Because the melting point of the second metal layer is lower than that of the first metal layer, setting an appropriate reflow temperature allows the bump to be formed by melting only the second metal layer without melting the first metal layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-136652 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-093404 Summary of the Invention [Problem to be solved by the invention]

[0005] Incidentally, a wiring substrate and a semiconductor chip are sometimes connected via multiple bumps. That is, for example, connection terminals for inputting and outputting electrical signals and connection terminals for applying a power supply voltage are sometimes provided separately. In such cases, the diameters of the bumps serving as connection terminals are not necessarily the same, and bumps of different diameters may be provided. Specifically, for example, bumps for inputting and outputting electrical signals may be relatively small, while bumps for applying a power supply voltage may be relatively large, resulting in a mixture of small and large diameter bumps.

[0006] When these bumps are formed using the two-layer plating described above, the larger diameter bumps are taller than the smaller diameter bumps. In other words, in the plating process for the first and second metal layers, the same thickness of plating is applied to the small and large diameter bumps, so the volume of the second metal layer in the larger diameter bump is larger than the volume of the second metal layer in the small diameter bump. When these second metal layers are melted and solidified, their surfaces become spherical. In this state, the larger diameter bumps protrude higher than the smaller diameter bumps.

[0007] When bumps of different heights are mixed, the reliability of the connection between the wiring board and the semiconductor chip decreases. In other words, with small-diameter bumps, the tops of the bumps may not make sufficient contact with the electrodes on the semiconductor chip, resulting in open defects. Therefore, for small-diameter bumps, additional plating may be applied to increase the volume of the second metal layer, making the bumps taller, so that the heights of the large-diameter bumps and the small-diameter bumps are aligned.

[0008] However, if only small-diameter bumps are plated with the second metal layer, the number of steps in the manufacturing process of the wiring board increases, resulting in increased costs and reduced yields. Specifically, if only small-diameter bumps are plated with the second metal layer, resist patterning is performed to mask the large-diameter bumps, followed by plating with tin or solder. This additional plating requires additional steps, such as patterning, reducing the efficiency of manufacturing the wiring board.

[0009] Such a decrease in manufacturing efficiency occurs not only in wiring boards on which semiconductor chips are mounted, but can also occur in wiring boards on which other electronic components are mounted via a plurality of bumps.

[0010] The disclosed technology has been developed in consideration of these points, and aims to provide a wiring board and a method for manufacturing a wiring board that can suppress a decrease in manufacturing efficiency while ensuring connection reliability with electronic components. [Means for solving the problem]

[0011] In one aspect, the wiring board disclosed in the present application comprises: a wiring layer having a first pad with a recess formed in its surface and a second pad with a recess formed in its surface that is deeper than the recess of the first pad; an insulating layer covering the wiring layer and having a first opening that penetrates to the recess of the first pad and a second opening that penetrates to the recess of the second pad and has a larger diameter than the first opening; a first metal layer that fills the inside of the first opening and the second opening, extends to an upper surface of the insulating layer, and has a recess at a position that overlaps with the first opening and the second opening in a planar view; and a second metal layer that is formed on top of the first metal layer and has a portion that is stored in the recess in the upper surface of the first metal layer, wherein the first metal layer has a uniform thickness in the portion that extends to the upper surface of the insulating layer. [Effects of the Invention]

[0012] According to one aspect of the wiring board and the method for manufacturing the wiring board disclosed in the present application, it is possible to suppress a decrease in manufacturing efficiency while ensuring connection reliability with electronic components. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram showing a configuration of a wiring board according to an embodiment. [Figure 2] FIG. 2 is a flow diagram showing a method for manufacturing a semiconductor package according to an embodiment. [Figure 3] FIG. 3 is a diagram showing a specific example of forming a core substrate. [Figure 4] FIG. 4 is a diagram showing a specific example of build-up. [Figure 5] FIG. 5 is a diagram showing a specific example of forming a solder resist layer. [Figure 6] FIG. 6 is a diagram showing a specific example of terminal formation. [Figure 7] FIG. 7 is a diagram showing a specific example of mounting a semiconductor chip. [Figure 8] FIG. 8 is a flow chart showing the terminal forming step. [Figure 9] FIG. 9 is a diagram showing openings in the solder resist layer. [Figure 10] FIG. 10 is a diagram illustrating the formation of a seed layer. [Figure 11] FIG. 11 is a diagram illustrating patterning. [Figure 12] FIG. 12 is a diagram illustrating the formation of the first metal layer. [Figure 13] FIG. 13 is a diagram illustrating the formation of the second metal layer. [Figure 14] FIG. 14 is a diagram illustrating resist peeling. [Figure 15] FIG. 15 is a diagram illustrating the reflow. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, an embodiment of a wiring board and a method for manufacturing a wiring board disclosed in the present application will be described in detail with reference to the drawings. However, the present invention is not limited to this embodiment.

[0015] Fig. 1 is a diagram showing the configuration of a wiring board 100 according to one embodiment. Fig. 1 schematically shows a cross section of the wiring board 100. The wiring board 100 shown in Fig. 1 can be used, for example, as a substrate for a semiconductor package on which a semiconductor chip is mounted.

[0016] The wiring board 100 has a layered structure and includes a core substrate 110, a multilayer wiring structure 120, and solder resist layers 130 and 140. In the following description, the solder resist layer 140 is the bottom layer and the solder resist layer 130 is the top layer, as shown in Fig. 1, but the wiring board 100 may be used, for example, upside down, or in any position.

[0017] Core substrate 110 is made by forming wiring layers 113 by plating on both sides of base material 111, which is a plate-shaped insulator. Wiring layers 113 on both sides are connected by vias 112 as necessary.

[0018] The multilayer wiring structure 120 is formed by stacking layers including an insulating insulating layer 121 and a conductive wiring layer 122. In Fig. 1, two layers are stacked in the multilayer wiring structure 120 above the core substrate 110, and two layers are stacked in the multilayer wiring structure 120 below the core substrate 110, but the number of stacked layers may be one layer or three or more layers.

[0019] Pads 123 and 124 are formed on the uppermost wiring layer 122, which are connected to bumps 150 and 160, respectively, which serve as connection terminals with the semiconductor chip. Specifically, pad 123 is formed on the wiring layer 122 that is connected to small-diameter bump 150, and pad 124 is formed on the wiring layer 122 that is connected to large-diameter bump 160. Recesses are formed on the surfaces of pads 123 and 124, and bumps 150 and 160 connect to wiring layer 122 at these recesses.

[0020] The solder resist layer 130 is a layer that covers the uppermost wiring layer 122 of the multilayer wiring structure 120 and protects the wiring. The solder resist layer 130 is a layer made of an insulating photosensitive resin such as an acrylic resin or a polyimide resin, and is one of the insulating layers. The solder resist layer 130 may also be formed using an insulating non-photosensitive resin such as an epoxy resin.

[0021] The solder resist layer 130 side of the wiring board 100 is the surface on which electronic components such as semiconductor chips are mounted. Openings 131 and 132 are formed in the solder resist layer 130 at the positions where the semiconductor chips are to be mounted. That is, the openings 131 and 132 are formed at the positions where the bumps 150 and 160 of the solder resist layer 130 are to be formed. The openings 131 and 132 have different diameters, with the opening 132 having a larger diameter than the opening 131. If the solder resist layer 130 is formed using a photosensitive resin, the openings 131 and 132 can be formed by exposure and development. Alternatively, if the solder resist layer 130 is formed using a non-photosensitive resin, the openings 131 and 132 can be formed by laser processing.

[0022] Pads 123 and 124 are exposed on the bottom surfaces of openings 131 and 132, respectively, and bumps 150 and 160 are connected to pads 123 and 124. That is, small-diameter bump 150 is formed in small-diameter opening 131 and connected to pad 123, and large-diameter bump 160 is formed in large-diameter opening 132 and connected to pad 124.

[0023] The bumps 150 and 160 have a two-layer structure made of two different metals. Specifically, the bump 150 has a first metal layer 151 made of, for example, copper and a second metal layer 152 made of, for example, tin, with a layer of, for example, nickel interposed between the bonding surface of the first metal layer 151 and the second metal layer 152. Meanwhile, the bump 160 also has a first metal layer 161 made of, for example, copper and a second metal layer 162 made of, for example, tin, with a layer of, for example, nickel interposed between the bonding surface of the first metal layer 161 and the second metal layer 162. In these bumps 150 and 160, a recess is formed in the center of the top surface of the first metal layers 151 and 161, and the center of the top surface of the first metal layers 151 and 161 is lower than the surrounding area. However, the recess in the first metal layer 151 is shallower and has a smaller volume than the recess in the first metal layer 161. The second metal layers 152 and 162, parts of which are housed in these recesses, protrude upward in a spherical shape.

[0024] Because bump 160 has a larger diameter than bump 150, second metal layer 162 has a larger volume than second metal layer 152. However, because the recess formed in first metal layer 161 has a larger volume than first metal layer 151, more of second metal layer 162 is stored in the recess. As a result, the height of the top of second metal layer 162 from the surface of solder resist layer 130 is lower. Therefore, even if second metal layer 162, which has a larger volume than second metal layer 152, protrudes significantly upward, the heights of the tops of bump 150 and bump 160 are equal. Therefore, when a semiconductor chip is mounted above bumps 150 and 160, for example, the tops of bumps 150 and 160 are in reliable contact with the electrodes of the semiconductor chip, improving connection reliability.

[0025] The solder resist layer 140 is a layer that covers the lowest wiring layer 122 of the multilayer wiring structure 120 and protects the wiring. The solder resist layer 140 is a layer made of an insulating photosensitive resin such as an acrylic resin or a polyimide resin, and is one of the insulating layers. The solder resist layer 140 may also be formed using an insulating non-photosensitive resin such as an epoxy resin.

[0026] The solder resist layer 140 side of the wiring board 100 is the surface that is connected to external components, devices, etc. Openings 141 are formed in the solder resist layer 140 at positions where external connection terminals for electrical connection to external components or devices will be formed, and the wiring layer 122 of the multilayer wiring structure 120 is exposed through the openings 141. External connection terminals, such as solder balls, are formed in the openings 141. When the solder resist layer 140 is formed using a photosensitive resin, the openings 141 can be formed by exposure and development. When the solder resist layer 140 is formed using a non-photosensitive resin, the openings 141 can be formed by laser processing.

[0027] Next, a method for manufacturing a semiconductor package having wiring substrate 100 configured as described above will be described with reference to a flow chart in FIG. 2, using a specific example.

[0028] First, a core substrate 110 serving as a support member for the wiring board 100 is formed (step S101). Specifically, as shown in FIG. 3, vias 112 are formed in a base material 111, which is a plate-shaped insulator, and wiring layers 113 made of a metal such as copper are formed on both sides of the base material 111 by, for example, copper foil or copper plating. The wiring layers 113 on both sides of the base material 111 are connected by vias 112 formed by plating with a metal such as copper, as necessary. The base material 111 can be made of a reinforcing material such as woven glass fabric impregnated with an insulating resin such as epoxy resin. In addition to woven glass fabric, other reinforcing materials such as nonwoven glass fabric, woven aramid fabric, or nonwoven aramid fabric can also be used. In addition to epoxy resin, other insulating resins such as polyimide resin or cyanate resin can also be used.

[0029] Then, a multilayer wiring structure 120 is formed on the upper and lower surfaces of the core substrate 110 by a build-up method (step S102). Specifically, as shown in Fig. 4, for example, an insulating layer 121 is formed on the upper and lower surfaces of the core substrate 110, and a wiring layer 122 is formed on the surface of the insulating layer 121. The insulating layer 121 is formed using an insulating resin such as an epoxy resin or a polyimide resin. The wiring layer 122 is formed by plating a metal such as copper.

[0030] The wiring layer 113 and the wiring layer 122 of the core substrate 110, or the wiring layers 122 of adjacent layers, are connected by vias 125 formed by plating with a metal such as copper, as necessary. A plurality of insulating layers 121 and a plurality of wiring layers 122 may be stacked on the upper and lower surfaces of the core substrate 110. On the uppermost wiring layer 122, pads 123 are formed at positions where small diameter bumps 150 are to be formed, and pads 124 are formed at positions where large diameter bumps 160 are to be formed.

[0031] When the multilayer wiring structure 120 is formed, the outermost wiring layer 122 of the multilayer wiring structure 120 is covered with solder resist layers 130 and 140 (step S103). For example, the uppermost wiring layer 122 of the multilayer wiring structure 120 stacked on the upper surface of the core substrate 110 is covered with the solder resist layer 130, and the lowermost wiring layer 122 of the multilayer wiring structure 120 stacked on the lower surface of the core substrate 110 is covered with the solder resist layer 140.

[0032] 5, openings 131 and 132 are formed in solder resist layer 130 on the side where the semiconductor chip is mounted, at positions where connection terminals for the semiconductor chip will be provided. At this time, the diameters of openings 131 and 132 are different because the size of the connection terminals varies depending on, for example, the type of electrode on the semiconductor chip. That is, opening 131, where connection terminals for inputting and outputting electrical signals are formed, has a relatively small diameter, whereas opening 132, where connection terminals for applying a power supply voltage are formed, has a relatively large diameter. Pads 123 and 124 included in wiring layer 122 of multilayer wiring structure 120 are exposed at the bottoms of openings 131 and 132.

[0033] On the other hand, openings 141 are formed in the solder resist layer 140 on the side that is connected to external components or devices at positions where external connection terminals are to be provided. The bottom of the openings 141 exposes the lowermost wiring layer 122 of the multilayer wiring structure 120. When a photosensitive resin is used for the solder resist layers 130 and 140, the openings 131, 132, and 141 can be formed by exposure and development. When a non-photosensitive resin is used for the solder resist layers 130 and 140, the openings 131, 132, and 141 can be formed by laser processing.

[0034] Then, connection terminals for connecting a semiconductor chip are formed in the openings 131 and 132 of the solder resist layer 130 (step S104). That is, for example, as shown in FIG. 6, a small-diameter bump 150 is formed in the opening 131, and a large-diameter bump 160 is formed in the opening 132. Both the bumps 150 and 160 have a two-layer structure, with second metal layers 152 and 162 overlapping the first metal layers 151 and 161 and protruding upward in a spherical shape. The first metal layers 151 and 161 and the second metal layers 152 and 162 are both formed by plating.

[0035] The first metal layer 151 is formed by, for example, copper plating the opening 131 and its surroundings, filling the opening 131 and extending around the opening 131 on the upper surface of the solder resist layer 130. A recess is formed in the first metal layer 151 at a position that overlaps with the opening 131 in a plan view, and the upper surface around the recess is formed at a position higher than the upper surface of the solder resist layer 130. Then, the second metal layer 152 is formed on the upper surface of the first metal layer 151 by, for example, tin plating via a nickel layer. The second metal layer 152 is melted and solidified through a reflow process, and protrudes upward in a spherical shape.

[0036] On the other hand, the first metal layer 161 is formed by, for example, copper plating the opening 132 and its surroundings, filling the opening 132 and extending around the opening 132 on the upper surface of the solder resist layer 130. A recess is formed in the first metal layer 161 at a position overlapping the opening 132 in a plan view, and the upper surface around the recess is formed at a position higher than the upper surface of the solder resist layer 130. The recess formed in the first metal layer 161 is deeper and has a larger volume than the recess formed in the first metal layer 151. The second metal layer 162 is then formed on the upper surface of the first metal layer 161 by, for example, tin plating via a nickel layer. The second metal layer 162 is melted and solidified through a reflow process, and protrudes upward in a spherical shape.

[0037] Because portions of the second metal layers 152 and 162 are stored in the recesses of the first metal layers 151 and 161, respectively, the height of the tops of the second metal layers 152 and 162 is lower than when no recesses are formed in the first metal layers 151 and 161. At this time, because the volume of the recesses in the first metal layer 161 is larger than the volume of the recesses in the first metal layer 151, more of the second metal layer 162 is stored in the recesses than the second metal layer 152. As a result, even though the volume of the second metal layer 162 of the large-diameter bump 160 is larger than the volume of the second metal layer 152 of the small-diameter bump 150, the heights from the upper surface of the solder resist layer 130 to the tops of the bumps 150 and 160 are the same. The process of forming the bumps 150 and 160 will be described in detail later.

[0038] After the bumps 150, 160 are formed on the solder resist layer 130 side, external connection terminals are formed on the solder resist layer 140 side (step S105). Then, a semiconductor chip is mounted on the solder resist layer 130 side (step S106), and the bumps 150, 160 are connected to the electrodes of the semiconductor chip. Specifically, as shown in FIG. 7, for example, external connection terminals such as solder balls 170 are formed in the openings 141 of the solder resist layer 140. Then, the semiconductor chip 200 is mounted above the bumps 150, 160, and the electrodes 210 of the semiconductor chip 200 are bonded to the bumps 150, and the electrodes 220 of the semiconductor chip 200 are bonded to the bumps 160. At this time, the bumps 210a, 220a provided on the electrodes 210, 220 of the semiconductor chip 200 and the bumps 150, 160 are melted and solidified by reflow. Therefore, at the joints between the electrodes 210, 220 and the bumps 150, 160, the bumps 210a, 220a and the bumps 150, 160 are mixed together and melted and solidified.

[0039] The joints between the electrodes 210, 220 and the bumps 150, 160 are sealed with underfill resin 230, resulting in a semiconductor package in which the semiconductor chip 200 is mounted on the wiring substrate 100. The order of the above-described process of forming the external connection terminals and the process of mounting the semiconductor chip may be reversed. That is, after the semiconductor chip 200 is mounted on the wiring substrate 100, external connection terminals such as solder balls 170 may be formed in the openings 141 of the solder resist layer 140.

[0040] Next, the process of forming the bumps 150, 160 that serve as connection terminals for the semiconductor chip 200 will be described more specifically with reference to the flow chart shown in FIG.

[0041] When the multilayer wiring structure 120 is stacked on the upper surface of the core substrate 110, the uppermost wiring layer 122 of the multilayer wiring structure 120 is covered with a solder resist layer 130. At this time, the pads 123 and 124 included in the uppermost wiring layer 122 are also covered with the solder resist layer 130. Openings 131 and 132 are formed in the solder resist layer 130, as shown in FIG. 9, for example. The opening diameter of the opening 131 is, for example, about 20 to 30 μm, and the depth is, for example, about 13 to 23 μm. The opening diameter of the opening 132 is, for example, about 30 to 40 μm, and the depth is, like the opening 131, about 13 to 23 μm. Then, recesses 123a and 124a are formed in the pads 123 and 124 exposed at the bottoms of the openings 131 and 132, respectively (step S201).

[0042] Specifically, in a post-processing step for removing insulating resin residue after the openings 131 and 132 are formed by exposure and development or laser processing, excessive etching is performed, forming recesses 123a and 124a on the surfaces of the pads 123 and 124. That is, by prolonging the time that the pads 123 and 124 exposed at the bottoms of the openings 131 and 132 are immersed in the etching solution, the insulating resin residue remaining on the surfaces of the pads 123 and 124 is removed and the recesses 123a and 124a are formed. At this time, because the diameter of the opening 132 is larger than that of the opening 131, the exposed area of ​​the pad 124 exposed at the bottom of the opening 132 is larger than the exposed area of ​​the pad 123 exposed at the bottom of the opening 131, and the pad 124 is eroded to a greater extent. As a result, the recess 124a formed in the pad 124 is deeper than the recess 123a formed in the pad 123.

[0043] When the openings 131 and 132 are formed by laser processing, it is also possible to form the recesses 123a and 124a in the pads 123 and 124 by excessive laser irradiation. That is, even after the openings 131 and 132 are formed by irradiating the solder resist layer 130 with a laser, the recesses 123a and 124a can be formed in the surfaces of the pads 123 and 124 by continuing to irradiate the pads 123 and 124 exposed at the bottoms of the openings 131 and 132 with the laser. At this time, by irradiating the pad 124 with the laser for a longer period of time than the pad 123, the recesses 124a can be made deeper than the recesses 123a.

[0044] Once the openings 131 and 132 are formed in the solder resist layer 130 and the recesses 123a and 124a are formed in the pads 123 and 124, a seed layer is formed on the surface of the solder resist layer 130 (step S202). That is, as shown in Fig. 10, for example, a seed layer 301 is formed on the surface of the solder resist layer 130 and on the entire surfaces of the pads 123 and 124 exposed in the openings 131 and 132 by, for example, electroless copper plating or copper sputtering. The thickness of the seed layer 301 is, for example, about 0.40 to 0.60 µm, and it can be formed by, for example, performing electroless copper plating at a bath temperature of 34±2°C for 15 minutes.

[0045] Then, patterning is performed to form a circuit pattern on the surface of wiring board 100 (step S203). Specifically, as shown in Fig. 11, dry film resist 302 is attached to the surface of wiring board 100, and then the circuit pattern is exposed and developed, and the dry film resist is removed from the wiring portion including openings 131 and 132. The opening diameter of dry film resist 302 around opening 131 is, for example, about 27 to 47 µm, and the opening diameter of dry film resist 302 around opening 132 is, for example, about 60 to 80 µm. The thickness of dry film resist 302 is, for example, about 30 to 40 µm.

[0046] Then, for example, copper plating is applied to form first metal layers 151, 161 in openings 131, 132 (step S204). At this time, first metal layers 151, 161 can be formed by copper plating using a copper sulfate plating solution containing, for example, a polymer (suppressor), a brightener (accelerator), and a leveler. As the polymer (suppressor), for example, a nonionic surfactant such as polyethylene glycol (polyether compound) can be used, and as the brightener (accelerator), for example, an organic sulfur-based compound such as bis(3-sulfoporovyl)disulfide can be used. Furthermore, as the leveler, for example, a quaternary amine compound can be used.

[0047] By performing copper plating for a predetermined time at a predetermined current density using the above-described copper sulfate plating solution, copper is deposited in the areas where dry film resist 302 has been removed, forming first metal layers 151 and 161 in areas including the interiors of openings 131 and 132. Here, by continuing copper plating for a shorter time than usual, the thicknesses of copper deposited around small-diameter opening 131 and large-diameter opening 132 become equal, as shown in FIG. 12 , for example, and the thicknesses of the portions of first metal layers 151 and 161 extending over the upper surface of solder resist layer 130 become uniform. At the same time, recesses 151a and 161a are formed in first metal layers 151 and 161 at positions that overlap openings 131 and 132, respectively, in a plan view.

[0048] The lower portions of the first metal layers 151 and 161 are respectively housed in the recesses 123a and 124a of the pads 123 and 124. However, as described above, the recess 124a is deeper and has a larger volume than the recess 123a. Therefore, the volume of the first metal layer 161 housed in the recess 124a is larger than the volume of the first metal layer 151 housed in the recess 123a. Even if the first metal layers 151 and 161 are formed by copper plating for the same amount of time, the recess 161a is deeper and has a larger volume than the recess 151a. Furthermore, by forming the first metal layers 151 and 161 in the recesses 123a and 124a of the pads 123 and 124, the adhesion of the first metal layers 151 and 161 can be improved by an anchor effect. This prevents the bumps 150 and 160 that are finally formed from falling off the wiring substrate 100.

[0049] After the first metal layers 151, 161 are formed by copper plating, the second metal layers 152, 162 are formed in the openings 131, 132 by, for example, tin plating (step S205). At this time, as shown in FIG. 13 , for example, nickel layers 303, 304 may be interposed between the first metal layers 151, 161 and the second metal layers 152, 162. The nickel layers 303, 304 are formed to a uniform thickness along the surfaces of the first metal layers 151, 161. The presence of the nickel layers 303, 304 prevents the copper of the first metal layers 151, 161 from eluting or diffusing into the tin of the second metal layers 152, 162. The nickel layers 303, 304 have a thickness of, for example, approximately 1 to 5 μm and can be formed by nickel plating using electrolytic nickel plating conditions, for example, a current density of 1.0 ASD and a plating time of 17.2 minutes. In addition, in order to prevent the dissolution and diffusion of copper from the first metal layers 151, 161, a layer of a metal other than nickel having a higher melting point than the metal of the second metal layers 152, 162 may be interposed between the first metal layers 151, 161 and the second metal layers 152, 162.

[0050] When forming the second metal layers 152, 162, plating is applied to a uniform thickness in the openings 131, 132. As a result, recesses 152a, 162a are formed on the upper surfaces of the second metal layers 152, 162, similar to the upper surfaces of the first metal layers 151, 161. The thickness of the second metal layers 152, 162 is, for example, approximately 10 to 20 μm, and can be formed by tin plating using electrolytic tin plating conditions such as a current density of 1.5 ASD and a plating time of 23.3 minutes. The second metal layers 152, 162 may be formed using various solder metals other than tin, such as a tin-silver alloy, a tin-silver-copper alloy, or a tin-bismuth alloy.

[0051] After the second metal layers 152 and 162 are formed, the dry film resist 302 is stripped (step S206). For example, a caustic soda or amine-based alkaline stripper is used for the stripping. Flash etching is then performed to remove the unplated portions of the seed layer 301. In the flash etching, the etching solution also permeates the side surfaces of the first metal layers 151 and 161 exposed on the upper surface of the solder resist layer 130, causing side etching. In this embodiment, the heights of the exposed side surfaces of the first metal layers 151 and 161 are equal, so the side etching amounts of the first metal layers 151 and 161 are equal. As a result, the first metal layers 151 and 161 are equally likely to fall off the solder resist layer 130. By appropriately controlling the side etching amount, both the first metal layers 151 and 161 can be prevented from falling off.

[0052] 14, the seed layer 301, the first metal layer 151, the nickel layer 303, and the second metal layer 152 are stacked in the opening 131, forming a conductor portion that protrudes from the upper surface of the solder resist layer 130. Also, the seed layer 301, the first metal layer 161, the nickel layer 304, and the second metal layer 162 are stacked in the opening 132, forming a conductor portion that protrudes from the upper surface of the solder resist layer 130. Recesses 152a and 162a remain in the centers of the second metal layers 152 and 162, respectively.

[0053] In this state, reflow is performed at a reflow temperature that melts the second metal layers 152, 162 (step S207). That is, the second metal layers 152, 162 are melted at a high temperature and then cooled to solidify the second metal layers 152, 162. At this time, because the melting point of the metal (e.g., copper) that forms the first metal layers 151, 161 is higher than the melting point of the metal (e.g., tin) that forms the second metal layers 152, 162, the first metal layers 151, 161 do not melt, and only the second metal layers 152, 162 melt and solidify.

[0054] As a result, as shown in FIG. 15 , the upper surfaces of the second metal layers 152 and 162 protrude spherically, forming bumps 150 and 160. A portion of the second metal layer 152 is housed in a recess 151a formed in the first metal layer 151, and a portion of the second metal layer 162 is housed in a recess 161a formed in the first metal layer 161. Because the volume of the recess 161a is larger than the volume of the recess 161a, the volume housed in the recess is larger for the second metal layer 162, and the tops of the second metal layers 152 and 162 are at the same height. That is, even if the second metal layers 152 and 162 are formed simultaneously by a single plating process, the heights from the upper surface of the solder resist layer 130 to the tops of the bumps 150 and 160 are the same. As a result, when the semiconductor chip 200 is mounted, the bumps 150 and 160 are reliably in contact with the electrodes 210 and 220 of the semiconductor chip 200, preventing open defects. Furthermore, the top of only one of the bumps 150, 160 is not excessively pressed by the semiconductor chip 200 and stretched in the lateral direction, and short circuit defects caused by adjacent bumps coming into contact with each other can be avoided.

[0055] As described above, according to this embodiment, when bumps are formed by plating in openings in a solder resist layer of a wiring board, recesses corresponding to the diameter of the openings are formed in the pads exposed at the bottom of the openings. The larger the diameter of the opening, the deeper the recess formed in the first metal layer. As a result, when the second metal layer overlying the first metal layer is melted and solidified, the larger the diameter of the opening, the more of the second metal layer is embedded in the recess in the first metal layer. As a result, even if the diameters of multiple openings are different, the heights from the surface of the solder resist layer to the tops of the bumps formed in each opening can be made equal, thereby ensuring connection reliability with electronic components connected to the bumps on the wiring board. Furthermore, since additional processes such as plating are not required to equalize the bump heights, a decrease in manufacturing efficiency can be suppressed. [Explanation of symbols]

[0056] 100 wiring board 110 Core Board 111 Base material 112, 125 via 113, 122 wiring layer 120 Multilayer wiring structure 121 Insulating layer 123, 124 Pads 123a, 124a recesses 130, 140 Solder resist layer 131, 132, 141 Openings 150, 160 bump 151, 161 1st metal layer 151a, 152a, 161a, 162a Recesses 152, 162 2nd metal layer 170 solder balls

Claims

1. a wiring layer including a first pad having a recess formed on its surface and a second pad having a recess formed on its surface that is deeper than the recess of the first pad; an insulating layer covering the wiring layer and including a first opening penetrating to the recess of the first pad and a second opening penetrating to the recess of the second pad and having a larger diameter than the first opening; a first metal layer that fills the first opening and the second opening, extends on an upper surface of the insulating layer, and has recesses at positions that overlap the first opening and the second opening in a plan view; a second metal layer formed on the first metal layer and a portion of the second metal layer stored in a recess in the top surface of the first metal layer; The wiring board according to claim 1, wherein the first metal layer has a uniform thickness in a portion extending on the upper surface of the insulating layer.

2. The recess formed at the position overlapping the second opening is deeper than the recess formed at the position overlapping the first opening.

2. The wiring board according to claim 1.

3. The second metal layer has a surface farther from the first metal layer that protrudes in a spherical shape.

2. The wiring board according to claim 1.

4. The first metal layer is formed from a metal having a higher melting point than the metal forming the second metal layer.

2. The wiring board according to claim 1.

5. the first metal layer includes copper; The second metal layer includes tin.

2. The wiring board according to claim 1.

6. a nickel layer interposed between the first metal layer and the second metal layer; 2. The wiring board according to claim 1, further comprising:

7. forming a wiring layer including a first pad and a second pad; forming an insulating layer that covers the wiring layer and has a first opening that penetrates to the first pad and a second opening that penetrates to the second pad and has a larger diameter than the first opening; forming a recess in the surface of the first pad exposed at the bottom of the first opening, and forming a recess deeper than the recess in the first pad in the surface of the second pad exposed at the bottom of the second opening; forming a first metal layer by plating a metal, the first metal layer filling the first opening and the second opening, extending on the upper surface of the insulating layer, and having recesses at positions overlapping the first opening and the second opening in a plan view; forming a second metal layer overlying the first metal layer by plating another metal; a step of melting the second metal layer and then solidifying it; 10. A method for manufacturing a wiring board, wherein the step of forming the first metal layer is performed by making the thickness of the portion extending on the upper surface of the insulating layer uniform.

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