Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes a first insulating layer including a cavity, a connecting member disposed in the cavity, and a second insulating layer disposed on the connecting member and including a material different from that of the first insulating layer, wherein the width of the second insulating layer is greater than the width of the connecting member.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. [Background technology]

[0002] As the performance of electrical and electronic products continues to improve, technologies for arranging more semiconductor elements on a semiconductor package circuit board with a limited size are being proposed and researched. However, because a typical semiconductor package is designed to mount only one semiconductor element, there is a limit to how much performance can be achieved.

[0003] Recently, semiconductor packages have been developed that use multiple substrates to arrange multiple semiconductor devices. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on a circuit board. This allows for efficient use of the mounting area of ​​the semiconductor devices and allows for high-speed signal transmission via short signal transmission paths between the semiconductor devices.

[0004] Due to these advantages, the above-mentioned semiconductor package is widely used in mobile devices and the like.

[0005] In addition, semiconductor packages applied to products that provide the Internet of Things (IOT), autonomous vehicles, and high-performance servers are becoming more highly integrated, and the number of semiconductor elements and / or the size of each semiconductor element is increasing, or the functional parts of the semiconductor element are being divided, expanding the concept to semiconductor chiplets.

[0006] This makes intercommunication between semiconductor devices and / or semiconductor chiplets important, and thus there is a trend to place an interposer between a semiconductor package circuit board and a semiconductor device.

[0007] The interposer functions as a redistribution layer that gradually increases the width of a circuit pattern from the semiconductor device toward the semiconductor package in order to facilitate intercommunication between semiconductor devices and / or semiconductor chiplets or to interconnect the semiconductor device and a semiconductor package circuit board, thereby facilitating transmission of electrical signals between the semiconductor device and a semiconductor package circuit board having a circuit pattern that is relatively larger than the circuit pattern of the semiconductor device.

[0008] Meanwhile, a package circuit board and / or an interposer applied to a semiconductor package may include a connecting member connected to a semiconductor device and / or a semiconductor chiplet. The connecting member functions to horizontally connect a plurality of semiconductor devices and / or semiconductor chiplets. Accordingly, the connecting member may be embedded in the package circuit board and / or the interposer. In this case, the package circuit board and / or the interposer may include a plurality of bump units connected to the semiconductor device and / or the semiconductor chiplet. The bump units may include a first bump that does not vertically overlap the connecting member and a second bump that vertically overlaps the connecting member and horizontally overlaps the first bump.

[0009] In this case, the first bump and the second bump may have different widths in the horizontal direction and / or different thicknesses in the vertical direction. That is, the width and / or thickness of the second bump may depend on the width and height of the pads provided on the connecting member, but the width and height of the first bump do not depend on the width and / or height of the pads provided on the connecting member. That is, when the integration density of the number of I / O (Input and Output) terminals of the connecting member is high, the amount of current generated during plating of the first and second bumps may differ depending on the diameter and density of via holes in the insulating layer and / or protective layer disposed on the pads of the connecting member, and as a result, the width of the second bump may differ from the width of the first bump.

[0010] Therefore, the first bump and the second bump according to the conventional technology may have a height deviation due to a difference in width and / or thickness between them. Furthermore, if a height deviation occurs between the first bump and the second bump, a semiconductor device and / or a semiconductor chiplet may not be stably mounted on the first bump and the second bump. This may result in problems such as a decrease in the operating characteristics, reliability, and yield of the semiconductor device and / or the semiconductor chiplet. Summary of the Invention [Problem to be solved by the invention]

[0011] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0012] Also, an embodiment provides a semiconductor package including a circuit board and a connecting member embedded in the circuit board.

[0013] Furthermore, the embodiments provide a circuit board capable of minimizing the height deviation between a plurality of electrodes connected to a plurality of semiconductor elements, and a semiconductor package including the same.

[0014] Furthermore, the embodiments provide a circuit board in which the surface of the upper metal layer disposed on a plurality of electrodes can have a uniform height, and a semiconductor package including the same.

[0015] In addition, the embodiments provide a circuit board and a semiconductor package including the same that can solve electrical reliability problems and / or mechanical reliability problems that occur due to differences in the thermal expansion coefficients between the insulating layer of the circuit board and the connecting members.

[0016] Furthermore, the embodiments provide a circuit board capable of improving the adhesion between a plurality of insulating layers, electrode portions, and upper metal layers, and a semiconductor package including the same.

[0017] In addition, the embodiments provide a circuit board and a semiconductor package including the same that can prevent the intermetallic joint (IMC) formed between the conductive adhesive and the conductive metal layer from diffusing into the bump portion.

[0018] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0019] A circuit board according to an embodiment includes a first insulating layer including a cavity, a connecting member disposed in the cavity, and a second insulating layer disposed on the connecting member and including a material different from that of the first insulating layer, wherein the width of the second insulating layer is greater than the width of the connecting member.

[0020] The second insulating layer also includes a non-conductive adhesive material.

[0021] The upper surface of the first insulating layer and the upper surface of the second insulating layer have a step.

[0022] The upper surface of the second insulating layer is located lower than the upper surface of the first insulating layer.

[0023] The semiconductor device further includes a third insulating layer disposed on the first insulating layer and the second insulating layer, and the lower surface of the third insulating layer includes a first lower surface in contact with the upper surface of the first insulating layer and a second lower surface in contact with the upper surface of the second insulating layer, and the first and second lower surfaces of the third insulating layer have a step.

[0024] The semiconductor device further includes a bump portion including a first bump disposed on the first insulating layer and a second bump disposed on the second insulating layer, wherein the first bump does not overlap the connecting member in the vertical direction, and the second bump overlaps the connecting member in the vertical direction and overlaps the first bump in the horizontal direction.

[0025] Furthermore, at least one of the upper and lower surfaces of the first bump is located on the same plane as at least one of the upper and lower surfaces of the second bump.

[0026] The connecting member also includes an insulating member, a pad portion arranged on the insulating member, and a connection portion arranged on the pad portion and electrically connecting the second bump and the pad portion, and the second insulating layer embeds the pad portion and the connection portion.

[0027] The second insulating layer also includes an extension that extends toward a side surface of the insulating member of the connecting member and wraps around at least a portion of the side surface of the insulating member.

[0028] Furthermore, the horizontal width of the second bump is smaller than the horizontal width of the first bump.

[0029] The first bump is disposed in a first recess provided on the upper surface of the first insulating layer, the upper surface of the first bump being higher than the upper surface of the first insulating layer, and the first bump having a first slope whose width increases toward the lower surface of the first insulating layer; the second bump is disposed in a second recess provided on the upper surface of the second insulating layer, the upper surface of the second bump being higher than the upper surface of the second insulating layer, and the second bump having a second slope whose width increases toward the lower surface of the second insulating layer.

[0030] Moreover, the first inclination and the second inclination are inclined in the same direction and have the same angle.

[0031] The semiconductor device further includes an upper metal layer including a first upper metal layer disposed on the first bump and a second upper metal layer disposed on the second bump.

[0032] Further, the first slope of the first bump has a first portion that overlaps the first insulating layer horizontally while being spaced apart from the inner wall of the first recess of the first insulating layer, and the second slope of the second bump has a second portion that overlaps the first insulating layer horizontally while being spaced apart from the inner wall of the first recess of the first insulating layer.

[0033] Additionally, the third insulating layer is disposed on the first insulating layer and the second insulating layer, and is in contact with the first portion of the first bump and the second portion of the second bump.

[0034] In addition, the first upper metal layer protrudes onto the third insulating layer while contacting the first portion of the first bump, and the second upper metal layer protrudes onto the third insulating layer while contacting the second portion of the second bump.

[0035] On the other hand, the semiconductor package of the embodiment includes the above-mentioned circuit board, a first semiconductor element arranged on a portion of the first upper metal layer and a portion of the second upper metal layer of the circuit board, and a second semiconductor element arranged on a remaining portion of the first upper metal layer and a remaining portion of the second upper metal layer. [Effects of the Invention]

[0036] According to an embodiment, a circuit board and a semiconductor package including the circuit board include a first insulating layer having a cavity, a connecting member disposed in the cavity, and a second insulating layer disposed on the connecting member. The second insulating layer stably fixes the connecting member and relieves thermal stress acting on the semiconductor package, thereby minimizing damage transmitted to the connecting member. This prevents thermal stress from being transmitted to the connecting member via the second insulating layer. For example, the second insulating layer can act as a buffer to buffer stress. This allows the connecting member to be stably coupled to the semiconductor package, thereby improving the physical and mechanical reliability of the connecting member.

[0037] Specifically, the second insulating layer is provided to surround the pad portion of the connecting member and the connection portion disposed on the pad portion. The second insulating layer also surrounds at least a portion of the bump portion disposed on the connection portion. Thus, the second insulating layer of the embodiment functions to buffer stress transmitted to the bump portion, the pad portion, and the connection portion. Therefore, the embodiment prevents cracks from occurring in the connection portion due to stress. Thus, the embodiment can improve the reliability of electrical connections between the pad portion, the connection portion, and the bump portion. Therefore, the embodiment can stably connect multiple semiconductor devices using the connecting member, thereby improving the operational reliability of the multiple semiconductor devices.

[0038] In addition, the horizontal width of the second insulating layer is greater than the horizontal width of the connecting member, thereby maximizing the buffering effect of the second insulating layer in the embodiment, thereby further improving the physical and electrical reliability of the semiconductor package.

[0039] The second insulating layer may also include an extension. In this case, the extension may extend toward the side of the connecting member. For example, the extension may cover at least a portion of the side of the connecting member. This allows the connecting member to be more stably positioned within the cavity and further minimizes stress transmitted to the connecting member. Furthermore, if air is filled around the side of the connecting member, heat generated in the semiconductor device or semiconductor package may cause the air to expand, resulting in mechanical damage such as cracks in the semiconductor package. Therefore, if the second insulating layer does not include an extension, the side of the connecting member may be covered with another material to improve operational reliability.

[0040] Meanwhile, the second insulating layer may have a step with the first insulating layer. For example, the top surface of the second insulating layer may be positioned lower than the top surface of the first insulating layer. This may increase the contact area with a third insulating layer disposed on the first and second insulating layers, thereby resolving the problem of the third insulating layer peeling off from the first and / or second insulating layers. Furthermore, the first and second insulating layers may have different thermal expansion coefficients, such that at least one of the layers may expand or contract more than the other. In this case, the top surface of the second insulating layer may have a step with the top surface of the first insulating layer, thereby resolving the problem of peeling off between the first and second insulating layers due to expansion or contraction, thereby improving the mechanical reliability of the semiconductor package.

[0041] The semiconductor package of the embodiment also includes bump portions disposed on the first and second insulating layers. The bump portion includes a first bump penetrating at least a portion of the first insulating layer and protruding onto the first insulating layer. The bump portion also includes a second bump penetrating at least a portion of the second insulating layer and protruding onto the second insulating layer. In this case, the horizontal width of the second bump may be smaller than the horizontal width of the first bump. That is, at least a portion of the second bump may be embedded in the second insulating layer, thereby making the width of the second bump smaller than the width of the first bump. This allows the embodiment to reduce the pitch of pad portions provided on the connecting member, thereby reducing the volume of the connecting member. Therefore, the embodiment allows for a reduction in the volume of the semiconductor package.

[0042] Additionally, the side of the bump portion including the first and second bumps may include a first slope adjacent to the upper surface of the bump portion and a second slope different from the first slope, the second slope increasing in width toward the lower surface of the bump portion. The first slope and the second slope may be provided by a planarization process or pre-treatment process of the bump portion. For example, the bump portion may include a plurality of first bumps and a plurality of second bumps, each of which may include the first slope and the second slope. This allows the bump portion to have a uniform height, thereby minimizing height variations between the bumps. Furthermore, the embodiment may allow the bump portion including the plurality of bumps to have the same height. This allows the semiconductor device to be stably disposed on the bump portion, thereby enabling the semiconductor device to operate smoothly. Therefore, the embodiment may improve the operating characteristics of a semiconductor package and an electronic product including the same.

[0043] In addition, the first slope of the bump portion may be covered via a third insulating layer or an upper metal layer. In some embodiments, the first slope of the bump portion may contact the third insulating layer or the upper metal layer, thereby increasing the contact area therebetween. This increases the bonding strength between the bump portion and the third insulating layer or the upper metal layer, thereby resolving the problem of peeling between them. This improves the mechanical and / or electrical reliability of a circuit board and a semiconductor package including the same.

[0044] The first slope of the bump portion may include a portion that overlaps the first or second insulating layer but does not contact the first or second insulating layer. At least a portion of the first slope may be covered with the upper metal layer or the third insulating layer. This prevents the connection material, such as solder, from diffusing into the bump portion. The embodiment also allows the intermetallic compound formed by the connection material to be separated from the first wiring electrode, thereby resolving problems with cracks or reduced electrical characteristics of the bump portion that may be caused by the intermetallic compound.

[0045] In addition, the embodiment allows the bump portions to have uniform heights, thereby improving the signal transmission characteristics of the circuit board and the semiconductor package. For example, the embodiment can minimize signal transmission loss caused by differences in height between the bump portions. Furthermore, the embodiment can prevent changes in impedance characteristics caused by differences in height. As a result, the embodiment can further improve the mechanical reliability and physical reliability of the semiconductor package and electronic products including the same. [Brief explanation of the drawings]

[0046] [Figure 1a] 1 is a cross-sectional view showing a semiconductor package according to a first embodiment. [Figure 1b] FIG. 10 is a cross-sectional view showing a semiconductor package according to a second embodiment. [Figure 1c] FIG. 10 is a cross-sectional view showing a semiconductor package according to a third embodiment. [Figure 1d] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fourth embodiment. [Figure 1e] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fifth embodiment. [Figure 2a] FIG. 1 is a cross-sectional view showing a circuit board according to an embodiment. [Figure 2b] FIG. 2b shows a modified example of the circuit board of FIG. 2a. [Figure 3] FIG. 2B is an enlarged view of a region R1 in FIG. 2A. [Figure 4] FIG. 10 is an enlarged view of a region R1 of the circuit board according to the second embodiment. [Figure 5] FIG. 10 is an enlarged view of a region R1 of the circuit board according to the third embodiment. [Figure 6] FIG. 10 is an enlarged view of a region R1 of the circuit board according to the fourth embodiment. [Figure 7] FIG. 10 is an enlarged view of a region R1 of a circuit board according to a fifth embodiment. [Figure 8] FIG. 13 is an enlarged view of a region R1 of a circuit board according to a sixth embodiment. [Figure 9] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 10] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 11] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 12] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 13] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 14] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 15] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 16] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 17] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 18] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 19] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 20] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 21] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 22] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. [Figure 23] 2b is a diagram showing a method for manufacturing the circuit board shown in FIG. 2a in the order of steps. DETAILED DESCRIPTION OF THE INVENTION

[0047] Hereinafter, the embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Regardless of the drawing numbers, identical or similar components will be assigned the same reference numerals, and redundant descriptions thereof will be omitted. The suffixes "module" and "unit" used in the following description are used or mixed together solely for the convenience of drafting the specification, and do not have any distinct meanings or roles. Furthermore, in describing the embodiments disclosed herein, if a detailed description of related publicly known technology is deemed to obscure the gist of the embodiments disclosed herein, such a detailed description will be omitted. Furthermore, the accompanying drawings are merely provided to facilitate understanding of the embodiments disclosed herein, and the technical concept disclosed herein should not be limited by the accompanying drawings. It should be understood that the accompanying drawings include all modifications, equivalents, and alternatives within the concept and technical scope of the present invention.

[0048] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0049] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that it may be directly coupled or connected to the other component, but that there may be other components in between. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no other components in between.

[0050] The singular expression includes the plural expression unless the context clearly indicates otherwise.

[0051] In this application, the use of terms such as "comprises" or "having" is intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described herein, and should be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0052] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0053] -Electronic Devices-

[0054] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments can be applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various semiconductor elements may be mounted in the semiconductor package.

[0055] The semiconductor device may include active and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above.

[0056] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and the like.

[0057] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0058] Furthermore, the electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, it is not limited to these, and it may also be any other electronic device that processes data.

[0059] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package according to the embodiment may have various package structures including the circuit board described below.

[0060] In one embodiment, the circuit board may be a first circuit board described below.

[0061] In other embodiments, the circuit board may be a second circuit board, as described below.

[0062] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, and Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment.

[0063] Referring to FIG. 1 a, the semiconductor package of the first embodiment includes a first circuit board 1100 , a second circuit board 1200 , and a semiconductor device 1300 .

[0064] The first circuit board 1100 may refer to a package circuit board.

[0065] For example, the first circuit board 1100 may provide a space to which at least one external circuit board is coupled. The external circuit board may refer to the second circuit board 1200 coupled on the first circuit board 1100. Alternatively, the external circuit board may refer to a main board included in an electronic device coupled to the lower part of the first circuit board 1100.

[0066] Although not shown in the drawings, the first circuit board 1100 may provide a space in which at least one semiconductor element is mounted.

[0067] The first circuit board 1100 can include at least one insulating layer and an electrode portion disposed on the at least one insulating layer.

[0068] A second circuit board 1200 may be disposed on the first circuit board 1100 .

[0069] The second circuit board 1200 may be an interposer. For example, the second circuit board 1200 may provide a space in which at least one semiconductor device is mounted. The second circuit board 1200 may be connected to at least one semiconductor device 1300. For example, the second circuit board 1200 may provide a space in which a first semiconductor device 1310 and a second semiconductor device 1320 are mounted. The second circuit board 1200 may electrically connect the first semiconductor device 1310 and the second semiconductor device 1320, while also electrically connecting the first and second semiconductor devices 1310 and 1320 to the first circuit board 1100. That is, the second circuit board 1200 may function as a horizontal connection between multiple semiconductor devices and a vertical connection between the semiconductor device and a package circuit board.

[0070] 1a illustrates two semiconductor elements 1310 and 1320 disposed on the second circuit board 1200, but is not limited to this. For example, one semiconductor element may be disposed on the second circuit board 1200, or alternatively, three or more semiconductor elements may be disposed on the second circuit board 1200. Furthermore, while FIG. 1a illustrates a structure in which two semiconductor elements 1310 and 1320 are horizontally connected, a structure in which three or more semiconductor elements are horizontally connected may also be used.

[0071] The second circuit board 1200 may be disposed between at least one or more semiconductor devices 1300 and the first circuit board 1100 .

[0072] In one embodiment, second circuit board 1200 may be an active interposer. Second circuit board 1200 of the embodiment may have a vertically stacked structure on first circuit board 1100 and may have the functions of multiple logic chips. Having the functions of logic chips may mean having the functions of active and passive elements. Furthermore, the active interposer may perform the functions of the logic chips while also performing the signal transmission function between a second logic chip disposed thereon and first circuit board 1100 and the horizontal electrical signal connection function between semiconductor devices 1300.

[0073] According to another embodiment, the second circuit board 1200 may be a passive interposer. For example, the second circuit board 1200 may function as a signal relay between the semiconductor device 1300 and the first circuit board 1100 and may have passive element functions such as a resistor, capacitor, or inductor. For example, the number of terminals on the semiconductor device 1300 is gradually increasing due to factors such as 5G, the Internet of Things (IOT), improved image quality, and increased communication speed. That is, the number of terminals provided on the semiconductor device 1300 is increasing, and as a result, the width of the terminals and the spacing between the terminals are decreasing. In this case, the first circuit board 1100 may be connected to a main board of an electronic device. Therefore, in order for the electrodes provided on the first circuit board 1100 to have the width and spacing required for connection to the semiconductor device 1300 and the main board, respectively, the thickness of the first circuit board 1100 increases or the layer structure of the first circuit board 1100 becomes complex. Therefore, in the first embodiment, the second circuit board 1200 can be disposed on the first circuit board 1100 and the semiconductor device 1300. The second circuit board 1200 can include electrodes having fine widths and intervals corresponding to the terminals of the semiconductor device 1300.

[0074] The semiconductor device 1300 may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific integrated circuit (ASIC), or the like, or a chipset including a specific combination of the foregoing. The memory chip may be a stacked memory such as HBM. The memory chip may also include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0075] On the other hand, the semiconductor package of the first embodiment includes a connecting portion.

[0076] For example, the semiconductor package may include a first connection portion 1410 disposed between the first circuit board 1100 and the second circuit board 1200. The first connection portion 1410 may electrically connect the first circuit board 1100 and the second circuit board 1200 while coupling them to each other.

[0077] For example, the semiconductor package may include a second connection portion 1420 disposed between the second circuit board 1200 and the semiconductor device 1300. The second connection portion 1420 electrically connects the semiconductor device 1300 to the second circuit board 1200 while coupling the semiconductor device 1300 to the second circuit board 1200.

[0078] The semiconductor package may include a third connection portion 1430 disposed on the lower surface of the first circuit board 1100. The third connection portion 1430 may couple the first circuit board 1100 to the main board and electrically connect them.

[0079] In this case, the first connecting unit 1410, the second connecting unit 1420, and the third connecting unit 1430 can electrically connect the multiple components using at least one bonding method of wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connecting unit 1410, the second connecting unit 1420, and the third connecting unit 1430 have the function of electrically connecting the multiple components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as the electrically connected part, not the solder or wire.

[0080] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). The solder bonding method may refer to electrically connecting multiple components using a material including at least one of Sn, Ag, and Cu. The inter-metal direct bonding method may refer to directly bonding multiple components through recrystallization by applying heat and pressure between the multiple components without using a material such as solder, wire, or conductive adhesive. The inter-metal direct bonding method may refer to a bonding method using the second connecting portion 1420. In this case, the second connecting portion 1420 may refer to a metal layer formed between the multiple components through the recrystallization.

[0081] Specifically, the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 may be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 by applying heat and pressure to the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430.

[0082] In this case, the electrodes on which the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 are arranged in at least one of the first circuit board 1100 and the second circuit board 1200 may be provided with protrusions that protrude outward away from the insulating layer of the circuit board. The protrusions may protrude outward from the first circuit board 1100 or the second circuit board 1200.

[0083] The protrusion may be referred to as a bump, a post, a pillar, or the like. Preferably, the protrusion may refer to an electrode of the second circuit board 1200 on which a second connection portion 1420 for coupling with the semiconductor device 1300 is disposed. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, short circuits may occur between the second connection portions 1420 respectively connected to the terminals of the semiconductor device 1300 by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portions 1420 and prevent short circuits between the conductive adhesive such as solder. Therefore, in the embodiment, the electrode of the second circuit board 1200 on which the second connection portion 1420 is disposed can be manufactured to include a protrusion in order to ensure the degree of matching, the diffusion force, and the diffusion prevention force that prevents the intermetallic compound (IMC) formed between the conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the circuit board.

[0084] The connecting member may also be referred to as a bridge circuit board. For example, the connecting member 1210 may include a redistribution layer. The connecting member 1210 may electrically connect a plurality of semiconductor devices horizontally. The connecting member 1210 may perform a signal connection between chiplets, which are functionally separated semiconductor devices due to issues such as barriers and yield in semiconductor processes while the integration density of devices such as transistors is increasing. Alternatively, the connecting member 1210 may perform a signal connection between devices having different functions, such as a CPU and a GPU, or a GPU and an HBM. Furthermore, since there is a large difference between the width of a circuit pattern of a semiconductor package and that of a semiconductor device, a buffering function for the circuit pattern is required for electrical connection. Here, the buffering function may mean having an intermediate size between the width of a circuit pattern of the semiconductor package and that of the semiconductor device. The redistribution layer may perform the buffering function.

[0085] In one embodiment, the connecting member 1210 may be an inorganic bridge. As an example, the inorganic bridge may include a silicon bridge. That is, the connecting member 1210 may include a silicon circuit substrate and a redistribution layer disposed on the silicon circuit substrate.

[0086] In other embodiments, the connecting member 1210 can be an organic bridge. For example, the connecting member 1210 can include an organic material. For example, the connecting member 1210 can include an organic circuit board that includes an organic material instead of a silicon circuit board.

[0087] The above-mentioned connecting member 1210 may be embedded in the second circuit board 1200 .

[0088] For this purpose, the second circuit board 1200 may include a cavity, and the connecting member 1210 may be disposed in the cavity of the second circuit board 1200. The connecting member 1210 may horizontally connect multiple semiconductor elements disposed on the second circuit board 1200.

[0089] 1b, the semiconductor package of the second embodiment may include a second circuit board 1200 and a semiconductor device 1300. In this case, the semiconductor package of the second embodiment may have a structure in which the first circuit board 1100 is omitted compared to the semiconductor package of the first embodiment.

[0090] That is, the second circuit board 1200 of the second embodiment can function as a package circuit board while also functioning as an interposer.

[0091] The first connection portion 1410 disposed on the bottom surface of the second circuit board 1200 can couple the second circuit board 1200 to a main board of an electronic device.

[0092] Referring to FIG. 1 c, the semiconductor package of the third embodiment may include a first circuit board 1100 and a semiconductor device 1300 .

[0093] In this case, the semiconductor package of the third embodiment may have a structure in which the second circuit board 1200 is omitted compared to the semiconductor package of the first embodiment.

[0094] That is, the first circuit board 1100 of the third embodiment can function as a package circuit board and also as a connection between the semiconductor devices 1300 and the main board. To this end, the first circuit board 1100 can include a connecting member 1110 for connecting between the plurality of semiconductor devices. The connecting member 1110 can be an inorganic bridge or an organic bridge for connecting between the plurality of semiconductor devices.

[0095] Referring to FIG. 1d, the semiconductor package of the fourth embodiment may further include a third semiconductor element 1330 compared to the semiconductor package of the third embodiment.

[0096] For this purpose, a fourth connection portion 1440 may be disposed on the lower surface of the first circuit board 1100.

[0097] The third semiconductor element 1330 may be disposed on the fourth connection portion 1400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor elements are mounted on both the upper and lower sides.

[0098] In this case, the third semiconductor element 1330 may have a structure in which it is disposed on the lower surface of the second circuit board 1220 in the semiconductor package of FIG. 1b.

[0099] 1e, the semiconductor package of the sixth embodiment includes a first circuit board 1100. First and second semiconductor devices 1310 and 1320 are disposed on the first circuit board 1100. To this end, a first connecting portion 1410 is disposed between the first circuit board 1100 and the first and second semiconductor devices 1310 and 1320. When the first connecting portion 1410 is provided in a fine pattern, the first connecting portion 1410 may include protrusions protruding from the first circuit board 1100 toward the first and second semiconductor devices 1310 and 1320 in order to perform thermal compression bonding as described above.

[0100] A connecting member 1110 may be embedded in the first circuit board 1110. The connecting member 1110 may connect the first and second semiconductor elements 1310 and 1320 horizontally.

[0101] The first circuit board 1100 also includes a conductive coupling portion 1450. The conductive coupling portion 1450 protrudes further from the first circuit board 1100 toward the second semiconductor element 1320 than the first connecting portion 1410. When the first connecting portion 1410 includes a protrusion, the conductive coupling portion 1450 is provided to protrude further toward the first and second semiconductor elements than the protrusion.

[0102] According to this embodiment, a third semiconductor element 1330 is disposed on the conductive coupling part 1450. In this case, the third semiconductor element 1330 may represent an active interposer or a passive interposer. The third semiconductor element 1330 is connected to the first circuit board 1100 via the conductive coupling part 1450. In addition, a second connection part 1420 is disposed between the first and second semiconductor elements 1310 and 1320 and the third semiconductor element 1330.

[0103] As a result, the third semiconductor element 1330 is electrically connected to the first and second semiconductor elements 1310 and 1320 via the second connection portion 1420 .

[0104] That is, the third semiconductor element 1330 is connected to the first circuit board 1100 through the conductive coupling part 1450 , and is also connected to the first and second semiconductor elements 1310 and 1320 through the second connection part 1420 .

[0105] At this time, the third semiconductor device 1330 may be supplied with a power signal and / or power via the conductive coupling part 1450. In addition, the third semiconductor device 1330 may transmit and receive communication signals to and from the first and second semiconductor devices 1310 and 1320 via the second connection part 1420, or may electrically connect the first and second semiconductor devices 1310 and 1320 horizontally.

[0106] The semiconductor package of the fifth embodiment supplies a power signal and / or power to the third semiconductor element 1330 via the conductive coupling portion 1450, thereby providing sufficient power for driving the third semiconductor element 1330, smoothly controlling the power supply operation, and suppressing interference between signals when the first to third semiconductor elements 1310, 1320, and 1330 are connected.

[0107] Meanwhile, in a modification of the fifth embodiment, the third semiconductor device 1330 may have a structure in which it is disposed on a package circuit board. In this case, a semiconductor package including the third semiconductor device 1330 is provided in a package-on-package (POP) structure disposed on the first circuit board 1100. Exemplarily, the third semiconductor device 1330 may be a memory package including a memory chip. The memory package may be coupled to the conductive coupling part 1450. In this case, the memory package may not be directly connected to the first and second semiconductor devices 1310 and 1320. Here, "not directly connected" means that the memory package is not connected via the second connecting part 1420. That is, the third semiconductor device 1330 is connected to the first and second semiconductor devices 1310 and 1320 via wiring included in the first circuit board 1100.

[0108] The circuit board of the embodiment will be described below, which may be either the first circuit board 1100 or the second circuit board 1200 of the semiconductor package.

[0109] FIG. 2a is a cross-sectional view showing a circuit board according to one embodiment, FIG. 2b is a diagram showing a modified example of the circuit board of FIG. 2a, and FIG. 3 is an enlarged view of a region R1 of FIG. 2a.

[0110] The circuit board of the embodiment will be specifically described below with reference to FIGS. 2a, 2b, and 3. FIG.

[0111] 2a, 2b, and 3, the circuit board includes a circuit board and a connecting member 200 embedded in the circuit board. The connecting member 200 is disposed in the circuit board and can horizontally connect multiple semiconductor elements mounted on the circuit board via the connecting member 200.

[0112] For this purpose, a high-density electrode pattern may be provided on the connecting member 200. Also, the connecting member 200 may include at least one of an inorganic bridge and an organic bridge.

[0113] The connecting member 200 includes a pad portion 210. The pad portion 210 may refer to an electrode pattern disposed on the uppermost side of the connecting member 200. A connection portion 220 is provided on the pad portion 210 of the connecting member 200. The connection portion 220 may be, but is not limited to, solder. The connection portion 220 allows the pad portion 210 of the connecting member 200 to be coupled to a second bump 152 of the bump portion 150, which will be described later. Although not shown in the drawings, the pad portion 210 of the connecting member 200 may include a protruding portion. If the protruding portion is included, the connection portion 220 may not be necessary. Therefore, the protruding portion of the connecting member 200 may be provided to protrude from the upper surface of the circuit board and may be provided as an integral structure with the second bump 152.

[0114] Meanwhile, the circuit board provides a space in which the connecting member 200 is embedded. The circuit board may also provide a space in which a plurality of semiconductor elements are mounted. For example, a first semiconductor element including a first terminal and a second semiconductor element including a second terminal are mounted on the circuit board and spaced apart from each other in the horizontal direction. At least one first terminal of the first semiconductor element and at least one second terminal of the second semiconductor element are electrically connected to each other via the connecting member 200. Therefore, terminals for mutual signal exchange are electrically connected to the connecting member 200.

[0115] The circuit board includes a first insulating layer 110 .

[0116] The first insulating layer 110 may include an organic material that does not include a reinforcing material, which allows for excellent processability, slimming of the circuit board, and miniaturization of the electrode portion of the circuit board. For example, the first insulating layer 110 of the circuit board may be made of Ajinomoto Build-up Film (ABF), a product sold by Ajinomoto Co., Inc., or may be made of FR-4, bismaleimide triazine (BT), photoimageable dielectric resin (PID), BT, etc.

[0117] The first insulating layer 110 may be provided in multiple layers. The first insulating layer 110 may be provided in an inner layer of the circuit board. Being provided in an inner layer may mean that another insulating layer may be disposed above and / or below the first insulating layer 110.

[0118] Illustratively, the first insulating layer 110 may include, but is not limited to, a first layer 111, a second layer 112, a third layer 113, and a fourth layer 114.

[0119] In one embodiment, the first layer 111, the second layer 112, the third layer 113, and the fourth layer 114 of the first insulating layer 110 may be made of the same insulating material, but are not limited to this, and at least one layer may be made of a different insulating material from the other layers.

[0120] In other embodiments, at least one of the first layer 111, second layer 112, third layer 113, and fourth layer 114 of the first insulating layer 110 can include a different insulating material than at least one of the others.

[0121] If the first layer 111, the second layer 112, the third layer 113, and the fourth layer 114 of the first insulating layer 110 are made of the same material, the interfaces between the layers may not be easily distinguished. In this case, the layers may be distinguished by an electrode portion disposed in the first insulating layer 110.

[0122] For example, the electrode portion includes wiring electrodes WE provided at the interfaces between the first layer 111, the second layer 112, the third layer 113, and the fourth layer 114 in the first insulating layer 110. The electrode portion also includes via electrodes VE provided between the wiring electrodes WE arranged on different layers. The horizontal width of the wiring electrode WE is different from the horizontal width of the via electrode VE. Therefore, the difference between the widths of the wiring electrode WE and the via electrode VE can be used to distinguish between layers. Furthermore, the inclination of the side surface of the wiring electrode WE can be different from the inclination of the side surface of the via electrode VE. Therefore, the difference between the inclination of the side surface of the wiring electrode WE and the via electrode VE can be used to distinguish between layers.

[0123] On the other hand, even if the first layer 111, the second layer 112, the third layer 113, and the fourth layer 114 of the first insulating layer 110 contain the same insulating material, the interfaces therebetween may be distinct.

[0124] Through the laminated structure of the first insulating layer 110 described above, the circuit board of the embodiment can efficiently electrically connect at least one semiconductor device and / or the second circuit board to the main board.

[0125] Meanwhile, in one embodiment, at least one of the first layer 111, second layer 112, third layer 113, and fourth layer 114 of the first insulating layer 110 may include a reinforcing member 110G. In one embodiment, the reinforcing member 110G may represent glass fiber. In another embodiment, the reinforcing member 110G may represent GCP (Glass Core Primer). When the reinforcing member 110G represents glass fiber, at least one of the first to fourth layers 111, 112, 113, and 114 of the first insulating layer 110 is provided as a core layer.

[0126] The reinforcing member 110G is distinguished from the filler. For example, the reinforcing member 110G may include a reinforcing material extending horizontally within the first insulating layer 110, which is different from inorganic fillers spaced apart from each other. For example, the horizontal length or width of the reinforcing member 110G may be different from the horizontal length or width of the filler. For example, the reinforcing member 110G may be arranged in a curved shape within the first insulating layer 110, such that the horizontal width of the reinforcing member 110G may be greater than the horizontal width of the first insulating layer 110.

[0127] In the embodiment, at least one of the first layer 111, the second layer 112, the third layer 113, and the fourth layer 114 of the first insulating layer 110 includes a reinforcing member 110G, thereby improving the rigidity of the circuit board. For example, the reinforcing member 110G can prevent the circuit board from warping significantly in a specific direction. Therefore, warping of the first insulating layer 110 can be prevented during the manufacturing process of the circuit board, thereby improving the positional accuracy of the wiring electrodes WE and the via electrodes VE and further improving the alignment between them. Furthermore, as the rigidity of the circuit board is ensured, a semiconductor device can be stably bonded to the circuit board, thereby improving the operating characteristics of the semiconductor device. Furthermore, as the rigidity of the circuit board is ensured, the connecting member 200 can be stably embedded in the circuit board. Therefore, the embodiment can stably support the connecting member 200, thereby minimizing thermal stress transmitted to the connecting member 200. Therefore, the embodiment can improve signal transmission characteristics through the connecting member 200. Furthermore, electronic products and / or servers to which the semiconductor package of the embodiment is applied can be made to operate stably, thereby improving the reliability of the products.

[0128] On the other hand, when the reinforcing member 110G is included in at least one of the first layer 111, the second layer 112, the third layer 113, and the fourth layer 114 of the first insulating layer 110, the reinforcing member 110G is located adjacent to the lower surface of the first insulating layer 110. For example, the reinforcing member 110G may be provided in the fourth layer 114 adjacent to the lower surface of the first insulating layer 110. For example, the vertical distance from the upper surface of the first insulating layer 110 to the uppermost end of the reinforcing member 110G may be greater than the vertical distance from the lower surface of the first insulating layer 110 to the lowermost end of the reinforcing member 110G. A semiconductor element may be electrically coupled to the first layer 111 of the first insulating layer 110. The width and spacing of wiring electrodes disposed on the first layer 111 of the first insulating layer 110 may need to be reduced due to the miniaturization of the width and spacing of terminals of the semiconductor element. In contrast, wiring electrodes disposed under the fourth layer 114 of the first insulating layer 110 may be connected to an external circuit board (e.g., a package circuit board or a main board) and thus may have a relatively large width and spacing. In this case, it may be difficult to miniaturize wiring electrodes disposed on an insulating layer provided with a reinforcing member 110G due to manufacturing process constraints imposed by the reinforcing member. Therefore, in this embodiment, the reinforcing member 110G may be disposed on the fourth layer 114 adjacent to the lower surface of the first insulating layer 110, thereby improving the rigidity of the circuit board and enabling miniaturization of wiring electrodes disposed on the first layer 111, second layer 112, and third layer 113 of the first insulating layer 110. Therefore, the connecting member 200 disposed within the first insulating layer 110 may not overlap the reinforcing member 110G in the horizontal direction.

[0129] 2a illustrates the layer including the reinforcing member 110G as being disposed at the bottom of the first insulating layer 110, but the embodiment is not limited thereto. For example, referring to FIG. 2b, the layer including the reinforcing member 110G may be disposed at the center of the stacked structure in the thickness direction of the first insulating layer 110. In this case, layers not including a reinforcing member may be provided above and below the layer including the reinforcing member 110G.

[0130] For example, the first insulating layer 110 may include a layer including a reinforcing member 110G, and multiple layers having a mutually symmetrical number of layers but not including the reinforcing member 110G may be stacked above and below the layer including the reinforcing member 110G.

[0131] Meanwhile, the first insulating layer 110 includes a cavity 110C. The cavity 110C provides a space in which the connecting member 200 is disposed. According to one embodiment, the cavity 110C may include a region having the same width as the connecting member 200. That is, at least a portion of the inner wall of the cavity 110C may be in contact with a side surface of the connecting member 200. Thus, the connecting member 200 may be disposed within the cavity 110C of the first insulating layer 110 and may be fixed in position via the first insulating layer 110. Therefore, this embodiment may prevent the connecting member 200 from warping due to thermal stress, thereby improving the physical and mechanical reliability of the circuit board.

[0132] The second insulating layer 120 is disposed on the connecting member 200. The second insulating layer 120 covers an upper region of the connecting member 200. The second insulating layer 120 is provided in a cavity 100C of the first insulating layer 110. The inner wall of the cavity 100C has a step. For example, a portion of the inner wall of the cavity 100C contacts the second insulating layer 120. Another portion of the inner wall of the cavity 100C contacts the connecting member 200. The inner wall of the cavity 100C that contacts the second insulating layer 120 and the inner wall of the cavity 100C that contacts the connecting member 200 have a step. For example, the width of the cavity 100C changes in the direction from the upper surface of the first insulating layer 110 to the lower surface of the first insulating layer 110. Furthermore, the horizontal width of the cavity 100C on the inner wall in contact with the second insulating layer 120 is different from the horizontal width of the cavity 100C on the inner wall in contact with the connecting member 200. Preferably, the horizontal width of the cavity 100C on the inner wall in contact with the second insulating layer 120 is larger than the horizontal width of the cavity 100C on the inner wall in contact with the connecting member 200.

[0133] According to one embodiment, the second insulating layer 120 includes an insulating material different from that of the first insulating layer 110. The second insulating layer 120 has physical properties different from those of the first insulating layer 110. For example, the thermal expansion coefficient of the second insulating layer 120 may be different from that of the first insulating layer 110. For example, the rigidity of the second insulating layer 120 may be different from that of the first insulating layer 110. Preferably, the rigidity of the second insulating layer 120 may be less than that of the first insulating layer 110. This may reduce thermal stress and other stresses applied to the connecting member 200. Furthermore, when the connecting member 200 is formed as an organic bridge, the embodiment may reduce damage, such as cracks, to the semiconductor package caused by the difference in thermal expansion coefficient between the organic bridge and the first insulating layer 110.

[0134] For example, the second insulating layer 120 may be a non-conductive paste (NCP), but the embodiment is not limited thereto, and the second insulating layer 120 may include an insulating material that can stably fix the connecting member 200 and reduce thermal stress acting on the semiconductor package, thereby minimizing stress transferred to the connecting member 200.

[0135] Specifically, the connecting member 200 disposed in the cavity 110C of the first insulating layer 110 vertically overlaps the second insulating layer 120. This prevents stress in the first insulating layer 110 from being transferred to the connecting member 200. The second insulating layer 120 can act as a buffer to buffer the stress.

[0136] In an embodiment in which the connecting member 200 includes the pad portion 210 and is connected to the second bump 152 via the connection portion 220, the second insulating layer 120 is provided to surround the pad portion 210 of the connecting member 200 and the connection portion 220 disposed on the pad portion 210. The embodiment may buffer stress transmitted to the second bump 152, the pad portion 210, and the connection portion 220 using the second insulating layer 120. Therefore, the embodiment may prevent cracks from occurring in the connection portion 220 due to stress. As a result, the embodiment may improve the reliability of electrical connection between the pad portion 210, the connection portion 220, and the second bump 152. Therefore, the embodiment may stably connect multiple semiconductor devices using the connecting member 200, thereby improving the operational reliability of the multiple semiconductor devices.

[0137] Meanwhile, the horizontal width of the second insulating layer 120 is greater than the horizontal width of the connecting member 200. The embodiment can maximize the effect of the buffering function via the second insulating layer 120, thereby further improving the physical reliability and electrical reliability of the semiconductor package.

[0138] The second insulating layer 120 may include an extension 120CP. The extension 120CP of the second insulating layer 120 may extend toward a side surface of the connecting member 200. For example, the extension 120CP of the second insulating layer 120 may cover at least a portion of the side surface of the connecting member 200. This may allow the connecting member 200 to be more stably disposed within the cavity 110C, and may further minimize stress transmitted to the connecting member 200.

[0139] According to another embodiment, the connecting member 200 may be an organic bridge. When provided as an organic bridge, a circuit layer may be provided with a fine pattern for signal connection between semiconductor devices. Therefore, the connecting member 200 may include a PID (Photo Imageable Dielectric) material. According to this embodiment, the PID material has a higher thermal expansion coefficient than the first insulating layer 110 or the second insulating layer 120. Therefore, the PID material has a higher expansion coefficient due to heat generated during operation, which may cause cracks in the connecting member 200 or the first insulating layer 110. The second insulating layer 120 functions to mitigate the difference in thermal expansion coefficients, thereby improving the operational reliability of the semiconductor device package.

[0140] Meanwhile, the second insulating layer 120 may have a step with the first insulating layer 110. For example, the top surface 120T of the second insulating layer 120 may be located lower than the top surface 110T of the first insulating layer 110. This may improve the contact area between the third insulating layer 130 disposed on the first insulating layer 110 and the second insulating layer 120, thereby resolving the problem of the third insulating layer 130 peeling off from the first insulating layer 110 and / or the second insulating layer 120. Furthermore, the first insulating layer 110 and the second insulating layer 120 may have different thermal expansion coefficients, such that at least one of them may expand or contract more than at least the other. In this case, the embodiment can solve the problem of peeling between the first insulating layer 110 and the second insulating layer 120 caused by expansion or contraction by making the upper surface 120T of the second insulating layer 120 and the upper surface 110T of the first insulating layer 110 have a step, thereby improving the mechanical reliability of the semiconductor package.

[0141] Meanwhile, the circuit board may further include a third insulating layer 130 and a fourth insulating layer 140 .

[0142] The third insulating layer 130 is disposed on the upper surfaces of the first insulating layer 110 and the second insulating layer 120 , and the fourth insulating layer 140 is disposed on the lower surface of the first insulating layer 110 .

[0143] The third insulating layer 130 and the fourth insulating layer 140 may be resist layers.

[0144] For example, the third insulating layer 130 may be a first resist layer disposed on the top side of the circuit board, and the fourth insulating layer 140 may be a second resist layer disposed on the bottom side of the circuit board.

[0145] In one embodiment, the third insulating layer 130 and the fourth insulating layer 140 may include the same insulating material as the first insulating layer 110. However, the embodiment is not limited thereto, and the third insulating layer 130 and the fourth insulating layer 140 may be a solder resist, which is an insulating material different from that of the first insulating layer 110.

[0146] The third insulating layer 130 can function to protect the upper surface 110T of the first insulating layer 110 and the upper surface 120T of the second insulating layer 120. The fourth insulating layer 140 can function to protect the lower surface of the first insulating layer 110. Therefore, the third insulating layer 130 and the fourth insulating layer 140 can be said to be protective layers.

[0147] According to one embodiment, the lower surface of the third insulating layer 130 has a step. For example, the third insulating layer 130 may include a first lower surface in contact with the upper surface 110T of the first insulating layer 110 and a second lower surface in contact with the upper surface 120T of the second insulating layer 120. The second lower surface of the third insulating layer 130 may be positioned lower than the first lower surface. This may increase the contact area between the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130, thereby improving the bonding strength between them.

[0148] The third insulating layer 130 and the fourth insulating layer 140 may be solder resist layers containing an organic polymer material. The third insulating layer 130 and the fourth insulating layer 140 may include an epoxy acrylate resin. For example, the third insulating layer 130 and the fourth insulating layer 140 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and the third insulating layer 130 and the fourth insulating layer 140 may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0149] The circuit board includes an electrode portion.

[0150] The electrode portion is disposed in the first insulating layer 110 and the second insulating layer 120. At least a part of the electrode portion protrudes above the first insulating layer 110 and the second insulating layer 120.

[0151] The electrode portion may be divided into wiring electrodes WE and via electrodes VE according to their positions or functions. The via electrodes VE may be disposed between wiring electrodes WE disposed on different layers and may electrically connect them in the vertical direction. When the first insulating layer 110 has a four-layer structure, the via electrodes VE may include first to fourth via electrodes disposed on each layer of the first insulating layer 110.

[0152] The wiring electrode arranged on the uppermost side of the wiring electrode WE of the electrode portion can have an ETS (Embedded Trace Substrate) structure.

[0153] For example, a recess may be formed on each of the top surfaces of the first insulating layer 110 and the second insulating layer 120, and at least a portion of the wiring electrode WE may be formed within the recess. In this case, the ETS structure is advantageous for miniaturization compared to wiring electrodes having a typical protruding structure. Therefore, the embodiment makes it possible to form wiring electrodes corresponding to the size and pitch of terminals provided on a semiconductor device. Through this, the embodiment may improve circuit integration. Furthermore, the embodiment may minimize the transmission distance of signals transmitted through the semiconductor device, thereby minimizing signal transmission loss.

[0154] Meanwhile, the wiring electrode WE includes a bump portion 150 disposed on the uppermost side thereof. The bump portion 150 can function as a pad to be connected to a semiconductor element.

[0155] The wiring electrodes WE also include a terminal electrode 160 disposed at the bottom. The terminal electrode 160 may function as a terminal connected to an external circuit board (for example, a package circuit board or a main board).

[0156] The bump portion 150 includes a first bump 151 disposed in a recess provided in the upper surface of the first insulating layer 110. The bump portion 150 also includes a second bump 152 disposed in a recess provided in the upper surface of the second insulating layer 120.

[0157] The first bump 151 and the second bump 152 overlap in the horizontal direction. At this time, the first bump 151 and the second bump 152 are disposed on insulating layers made of different insulating materials. That is, the first bump 151 is disposed on the first insulating layer 110 containing the first insulating material. The second bump 152 is disposed on the second insulating layer 120 containing a second insulating material different from the first insulating material.

[0158] The first bump 151 does not overlap the connecting member 200 in the vertical direction. Moreover, the first bump 151 does not overlap the second insulating layer 120 in the vertical direction. Moreover, the second bump 152 overlaps the connecting member 200 in the vertical direction. Moreover, the second bump 152 overlaps the second insulating layer 120 in the vertical direction.

[0159] Exemplarily, the horizontal width of the first bump 151 may be different from the horizontal width of the second bump 152. According to the embodiment, when the second bump 152 is disposed on the second insulating layer 120, thermal stress or stress transmitted to the second bump 152 by the second insulating layer 120 may be reduced. Therefore, the horizontal width of the second bump 152 may be smaller than the horizontal width of the first bump 151. Thus, the embodiment may improve the circuit integration degree of the second bump 152, thereby reducing the volume of the semiconductor package.

[0160] According to this embodiment, a portion of the first bump 151 is embedded in the first insulating layer 110, and a portion of the second bump 152 is embedded in the second insulating layer 120. That is, the contact area between the first bump 151 and the first insulating layer 110 is different from the contact area between the second bump 152 and the second insulating layer 120. Therefore, stress due to heat generated during operation of the semiconductor device or heat applied from the outside is applied differently to the first bump 151 and the second bump 152. Furthermore, when the connecting member 200 is provided as an organic bridge, considering the thermal expansion coefficient of the connecting member 200, it may be more advantageous for operational reliability if the horizontal width of the first bump 151 is larger than the horizontal width of the second bump 152.

[0161] However, this is not limited to this, and if the horizontal width of the first bump 151 is reduced to improve the circuit integration density of the first bump 151, the horizontal width of the first bump 151 and the horizontal width of the second bump 152 can be freely designed to be equal.

[0162] The second bump 152 is connected to the connecting member 200 including a relatively fine electrode pattern. In this case, the second bump 152 may have a horizontal width smaller than the horizontal width of the first bump 151, thereby reducing the horizontal width of the pad portion 210 of the connecting member 200. Therefore, the embodiment may reduce the volume of the connecting member 200.

[0163] Meanwhile, at least a portion of the first bump 151 may be disposed in a recess formed in the upper surface 110T of the first insulating layer 110, and the remaining portion may protrude above the upper surface 110T of the first insulating layer 110. In terms of orbit, the upper surface 151T of the first bump 151 may be positioned higher than the upper surface 110T of the first insulating layer 110, and the lower surface 151B of the first bump 151 may be positioned lower than the upper surface 110T of the first insulating layer 110. By embedding at least a portion of the first bump 151 in the first insulating layer 110, the adhesion between the first bump 151 and the first insulating layer 110 may be improved, thereby solving the problem of the first bump 151 peeling off from the first insulating layer 110. Furthermore, the upper surface 151T of the first bump 151 may be positioned higher than the upper surface 110T of the first insulating layer 110, and may also be positioned higher than the upper surface of the third insulating layer 130. As a result, the embodiment can facilitate the mounting process of a semiconductor element on the first bump 151, and when multiple first bumps 151 and second bumps 152 are provided, the deviation in height of each bump can be reduced, thereby improving the processability of the semiconductor package.

[0164] Meanwhile, at least a portion of the second bump 152 may be disposed in a recess formed in the upper surface 120T of the second insulating layer 120, and the remaining portion may protrude above the upper surface 120T of the second insulating layer 120. Specifically, the upper surface 152T of the second bump 152 may be positioned higher than the upper surface 120T of the second insulating layer 120, and the lower surface 152B of the second bump 152 may be positioned lower than the upper surface 120T of the second insulating layer 120. By embedding at least a portion of the second bump 152 in the second insulating layer 120, the adhesion between the second bump 152 and the second insulating layer 120 may be improved, thereby solving the problem of the second bump 152 peeling off from the second insulating layer 120. Furthermore, the upper surface 152T of the second bump 152 may be positioned higher than the upper surface 120T of the second insulating layer 120 and may further be positioned higher than the upper surface of the third insulating layer 130. As a result, the embodiment allows the mounting process of the semiconductor element on the second bump 152 to be easily performed, and when multiple first bumps 151 and second bumps 152 are provided, the height deviation of each bump can be reduced, thereby improving the processability of the semiconductor package.

[0165] The first bump 151 and the second bump 152 are disposed on the first insulating layer 110 and the second insulating layer 120, respectively. Disposed on the first and second insulating layers 110 and 120 means that at least a portion of the bump protrudes and the other portion is recessed. That is, if the portions are recessed in different insulating layers, a height difference between the first bump 151 and the second bump 152 may occur. As will be described later, by providing each of the first and second bumps 151 and 152 with a portion protruding and the other portion recessed, the height difference between the first and second bumps 151 and 152 can be reduced.

[0166] On the other hand, the first bump 151 and the second bump 152 are located on the same plane.

[0167] Preferably, the top surface 151T of the first bump 151 may be located on the same plane as the top surface 152T of the second bump 152. The bottom surface 151B of the first bump 151 may be located on the same plane as the wave surface 152B of the second bump 152.

[0168] That is, the first bump 151 and the second bump 152 can have the same height.

[0169] As a result, the embodiment allows a semiconductor device to be stably coupled to the first bump 151 and the second bump 152. For example, if the first bump 151 and the second bump 152 are not flat but have a height difference, the semiconductor device may be coupled to the first bump 151 and the second bump 152 in an inclined state corresponding to the height difference. Furthermore, if the first bump 151 and the second bump 152 have a height difference, a problem may occur in which a pad positioned relatively higher may be connected to a terminal of the semiconductor device, but a pad positioned relatively lower may not be electrically connected to the terminal of the semiconductor device. In contrast, the upper surfaces of the first bump 151 and the second bump 152 in the embodiment may be flat and may be arranged on the same plane. As a result, a semiconductor device may be stably coupled to the first bump 151 and the second bump 152. Therefore, the embodiment can ensure smooth operation of semiconductor devices, and further ensure smooth operation of electronic products or servers, thereby improving product reliability.

[0170] Meanwhile, each of the first bump 151 and the second bump 152 may penetrate the third insulating layer 130 so that at least a portion thereof may protrude onto the third insulating layer 130 .

[0171] Meanwhile, an upper metal layer 170 is disposed on the first bump 151 and the second bump 152. The upper metal layer 170 includes a first upper metal layer 171 disposed on the first bump 151 and a second upper metal layer 172 disposed on the second bump 152.

[0172] The first upper metal layer 171 may be provided surrounding at least a portion of the top surface and side surfaces of the first bump 151. The first upper metal layer 171 may be a bonding portion on which a conductive adhesive such as solder is disposed for bonding with a semiconductor element.

[0173] For example, the first upper metal layer 171 may be a bonding portion for bonding with a connecting member such as a semiconductor device and / or an interposer. The first upper metal layer 171 may include a metal different from that of the first bump 151. For example, the first upper metal layer 171 may include a metal material for improving the adhesive strength between the first bump 151 and the conductive adhesive. In addition, the first upper metal layer 171 may include a metal material for preventing an intermetallic compound (IMC) from diffusing toward the first bump 151 due to the placement of the conductive adhesive.

[0174] For example, the first upper metal layer 171 may include nickel. When the first upper metal layer 171 includes nickel, the adhesion between the first bump 151 and the conductive adhesive can be improved and the diffusion of intermetallic compounds can be prevented. For example, intermetallic compounds can have poor mechanical and electrical reliability issues. In particular, when the first bump 151 includes copper, mechanical and / or electrical reliability issues, such as cracks and / or reduced electrical properties, caused by the intermetallic compounds can be exacerbated. In this case, when the first upper metal layer 171 includes nickel and is provided surrounding the exposed surface of the first bump 151, it can prevent the diffusion of the conductive adhesive, such as solder, and prevent the formation of intermetallic compounds, thereby improving the electrical and mechanical reliability of the semiconductor package. Meanwhile, the first upper metal layer 171 may include metals other than nickel. For example, the first upper metal layer 171 may include gold. For example, the first upper metal layer 171 may include palladium.

[0175] Meanwhile, the first upper metal layer 171 may cover the entire top surface of the first bump 151 while also covering at least a portion of the side surface of the first bump 151. For example, at least a portion of the side surface of the first bump 151 may protrude above the third insulating layer 130. The first upper metal layer 171 may cover the protruding side surface of the first bump 151. Furthermore, at least a portion of the first upper metal layer 171 may be disposed on the third insulating layer 130. This may improve the adhesion between the first upper metal layer 171 and the first bump 151, thereby improving the bonding strength between them. Furthermore, the embodiment may further prevent the diffusion of intermetallic compounds into the gap between the first bump 151 and the third insulating layer 130.

[0176] Also, the second upper metal layer 172 may be provided surrounding at least a portion of the top surface and side surface of the second bump 152. The second upper metal layer 172 may be a bonding portion on which a conductive adhesive such as solder is disposed for bonding to a semiconductor element.

[0177] For example, the second upper metal layer 172 may be a bonding portion for bonding with a connecting member such as a semiconductor device and / or an interposer. The second upper metal layer 172 may include a metal different from that of the second bump 152. For example, the second upper metal layer 172 may include a metal material for improving adhesion between the second bump 152 and the conductive adhesive. The second upper metal layer 172 may also include a metal material for preventing intermetallic compounds (IMCs) from diffusing toward the second bump 152 due to the placement of the conductive adhesive. For example, the second upper metal layer 172 may include nickel. When the second upper metal layer 172 includes nickel, the adhesion between the first bump 151 and the conductive adhesive can be improved and the diffusion of intermetallic compounds can be prevented. Meanwhile, the second upper metal layer 172 may include a metal other than nickel. For example, the second upper metal layer 172 may include gold. For example, the second upper metal layer 172 may include palladium.

[0178] Meanwhile, the second upper metal layer 172 may cover the entire top surface of the second bump 152 while covering at least a portion of the side surface of the second bump 152. For example, at least a portion of the side surface of the second bump 152 may protrude above the third insulating layer 130. The second upper metal layer 172 may cover the protruding side surface of the second bump 152. Also, at least a portion of the second upper metal layer 172 may be disposed on the third insulating layer 130. This may improve the adhesion between the second upper metal layer 172 and the second bump 152, thereby improving the bonding strength between them. Furthermore, the embodiment may further prevent the diffusion of intermetallic compounds into the gap between the second bump 152 and the third insulating layer 130.

[0179] 4, 5, 6, and 8, the first upper metal layer 171 and the second upper metal layer 172 may be in contact with the first insulating layer 110 and the second insulating layer 120, respectively. Therefore, the adhesive strength between the first upper metal layer 171 and the first insulating layer 110 may be different from the adhesive strength between the second upper metal layer 172 and the second insulating layer 120. In addition, the mechanical and electrical properties, such as heat transfer characteristics, may be different. When the integration density of the second bump 152 is different from the integration density of the first bump 151, the first upper metal layer 171 and the second upper metal layer 172 may be configured to be in contact with different insulating layers, taking into account the adhesive strength and mechanical and electrical properties, such as heat transfer characteristics.

[0180] 7, the first upper metal layer 171 and the second upper metal layer 172 may be in contact with the same material. If the density of the first upper metal layer 171 is similar to that of the second upper metal layer 172, the first and second upper metal layers 171 and 172 may have widths smaller than the widths of the first bump 151 and the second bump 152, respectively.

[0181] Meanwhile, a lower metal layer 180 may be disposed on the lower surface of the terminal electrode 160 of the wiring electrode WE. The lower metal layer 180 may include the same metal material as the upper metal layer 170, but is not limited thereto.

[0182] In the following, modified examples of the structures of the bump portion 150, the third insulating layer 130, and the upper metal layer 170 according to the embodiment will be described.

[0183] The bump portion 150 described below may be either one of the first bump 151 and the second bump 152 in FIG. 2a. In one embodiment, the first bump 151 and the second bump 152 may have the same shape and structure. Therefore, the bump portion 150 described below may refer to either the first bump 151 or the second bump 152. Note that the upper metal layer 170 described below may refer to either the first or second upper metal layer 171, 172.

[0184] Furthermore, the insulating layer 100 described below may refer to either the first insulating layer 110 or the second insulating layer 120. For example, if the bump portion 150 described below is the first bump 151, the insulating layer 100 may refer to the first insulating layer 110. For example, if the bump portion 150 described below is the second bump 152, the insulating layer 100 may refer to the second insulating layer 120.

[0185] Fig. 4 is an enlarged view of a region R1 of a circuit board according to a second embodiment, Fig. 5 is an enlarged view of a region R1 of a circuit board according to a third embodiment, Fig. 6 is an enlarged view of a region R1 of a circuit board according to a fourth embodiment, Fig. 7 is an enlarged view of a region R1 of a circuit board according to a fifth embodiment, and Fig. 8 is an enlarged view of a region R1 of a circuit board according to a sixth embodiment.

[0186] 4, the bump portion 150 may include a tapered, inclined side surface with a varying width. The side surface of the bump portion 150 may include a portion with a varying inclination. Here, the portion with a varying inclination refers to a portion in which not only the direction of the inclination but also the size of the inclination changes.

[0187] For example, the side of the bump portion 150 may include a first slope 150S1 adjacent to the upper surface 150T of the bump portion 150 and gradually increasing in width toward the lower surface of the bump portion 150. The side of the bump portion 150 may also include a second slope 150S2 adjacent to the lower surface of the bump portion 150 and different from the first slope 150S1. The second slope 150S2 may be perpendicular to the upper surface 150T and / or the lower surface of the bump portion 150, but is not limited thereto. The interior angle between the upper surface 150T of the bump portion 150 and the first slope 150S1 of the bump portion 150 may be an obtuse angle. The interior angle between the upper surface 150T of the bump portion 150 and the first slope 150S1 may be in the range of 95 degrees to 160 degrees. Preferably, the interior angle between the top surface 150T of the bump portion 150 and the first inclination 150S1 may be in the range of 100 degrees to 150 degrees. More preferably, the interior angle between the top surface 150T of the bump portion 150 and the first inclination 150S1 may be in the range of 105 degrees to 140 degrees.

[0188] If the interior angle between the top surface 150T of the bump portion 150 and the first slope 150S1 is less than 95 degrees, the effect of increasing the contact area between the upper metal layer 170 and the bump portion 150 may be insufficient. This may result in a problem of the upper metal layer 170 peeling off from the bump portion 150. For example, thermal stress may cause expansion and / or contraction of the circuit board, which may result in a mechanical reliability problem in which the upper metal layer 170 peels off from the bump portion 150. Furthermore, if the interior angle between the top surface 150T of the bump portion 150 and the first slope 150S1 exceeds 160 degrees, the difference between the horizontal width of the top surface 150T of the bump portion 150 and the horizontal width of the bottom surface may increase. The greater the difference in width, the greater the transmission loss of signals transmitted through the bump portion 150, which may result in degradation of signal transmission characteristics. Furthermore, if the width of the upper surface 150T becomes too small as the width difference increases, the upper metal layer 170 may not be stably disposed on the bump portion 150, and furthermore, a semiconductor element may not be stably bonded to the upper metal layer 170. Furthermore, if the width of the lower surface of the bump portion 150 becomes too large as the width difference increases, it may be difficult to miniaturize the line width and spacing of the bump portion 150. This may make it difficult to thin the circuit board, and the volume of the semiconductor package and the electronic product or server including the same may increase.

[0189] The second inclination 150S2 of the bump portion 150 may connect the lower end of the first inclination 150S1 and the lower surface of the bump portion 150. The second inclination 150S2 may be inclined more than the first inclination 150S1 with respect to the upper surface 150T of the bump portion 150. Also, the second inclination 150S may be inclined less than the first inclination 150S1 with respect to the lower surface of the bump portion 150.

[0190] Preferably, the interior angle between the upper surface 150T of the bump portion 150 and the second slope 150S2 may be smaller than the interior angle between the upper surface 150T and the first slope 150S1. Preferably, the interior angle between the upper surface 150T of the bump portion 150 and the second slope 150S2 may be close to 90 degrees.

[0191] The interior angle between the upper surface 150T of the bump portion 150 and the second inclination 150S2 may be in the range of 80 degrees to 100 degrees. Preferably, the interior angle between the upper surface 150T of the bump portion 150 and the second inclination 150S2 may be in the range of 82 degrees to 98 degrees. More preferably, the interior angle between the upper surface 150T of the bump portion 150 and the second inclination 150S2 may be in the range of 85 degrees to 95 degrees. If the interior angle between the upper surface 150T of the bump portion 150 and the second inclination 150S2 is outside the range of 80 degrees to 100 degrees, the difference in width between the upper surface 150T and the lower surface of the bump portion 150 increases, which may increase signal transmission loss and degrade signal transmission characteristics.

[0192] Meanwhile, the first slope 150S1 and the second slope 150S2 of the bump unit 150 may be provided by a process of planarizing the bump unit 150 or a pretreatment process before forming the upper metal layer 170. For example, in an embodiment, a process of etching the top surface 150T of the bump unit 150 may be performed after forming the bump unit 150. Through this, in an embodiment, the first and second bumps of the bump unit 150 may have the same thickness and surface height. Through this, in an embodiment, changes in the characteristics of signals transmitted through the bump unit 150 may be minimized. For example, impedance matching may be performed by adjusting the thickness and / or width of the bump unit 150. In this case, if the first and second bumps of the bump unit 150 have different thicknesses and / or heights due to plating deviations or the like, the impedance characteristics may change, which may result in electrical reliability issues.

[0193] Therefore, in the embodiment, the bump portion 150 includes a first slope 150S1 and a second slope 150S2, thereby improving the adhesion between the bump portion 150 and the upper metal layer 170 while preventing changes in the electrical characteristics of the bump portion 150.

[0194] Meanwhile, the vertical length (e.g., vertical thickness H1) of the bump portion 150 is preferably in the range of 15 μm to 40 μm. For example, the vertical length H1 of the bump portion 150 may be in the range of 20 μm to 35 μm. More preferably, the vertical length H1 of the bump portion 150 may have a thickness in the range of 22 μm to 32 μm. If the vertical length H1 of the bump portion 150 is less than 15 μm, the allowable current of signals that can be transmitted through the bump portion 150 may be reduced. If the vertical length H1 of the bump portion 150 is less than 15 μm, a semiconductor element may not be stably bonded to the bump portion 150. If the vertical length H1 of the bump portion 150 exceeds 40 μm, the thickness of the circuit board, semiconductor package, and electronic product may increase.

[0195] On the other hand, the vertical length H2 of the first slope 150S1 of the bump portion 150 may be greater than the vertical length H3 of the second slope 150S2 of the bump portion 150.

[0196] The vertical length H2 of the first slope 150S1 of the bump portion 150 may be in the range of 60% to 80% of the vertical length H1 between the upper surface 150T and the lower surface of the bump portion 150. Preferably, the vertical length H2 of the first slope 150S1 of the bump portion 150 may be in the range of 65% to 78% of the vertical length H1 between the upper surface 150T and the lower surface of the bump portion 150. More preferably, the vertical length H2 of the first slope 150S1 of the bump portion 150 may be in the range of 65% to 75% of the vertical length H1 between the upper surface 150T and the lower surface of the bump portion 150.

[0197] If the vertical length H2 of the first slope 150S1 of the bump portion 150 is less than 60% of the vertical length H1 between the upper surface 150T and the lower surface of the bump portion 150, the flatness of the bump portion 150 may be insufficient or the effect of increasing the contact area with the upper metal layer 170 may be insufficient. If the vertical length H2 of the first slope 150S1 of the bump portion 150 is more than 80% of the vertical length H1 between the upper surface 150T and the lower surface of the bump portion 150, the difference in width between the upper surface 150T and the lower surface of the bump portion 150 may become large.

[0198] Correspondingly, the vertical length H3 of the second slope 150S2 of the bump portion 150 can be in the range of 20% to 40% of the vertical length H1 between the upper surface 150T and the lower surface of the bump portion 150, and preferably, the vertical length H3 of the second slope 150S2 of the bump portion 150 can be in the range of 22% to 35% of the vertical length H1 between the upper surface 150T and the lower surface of the bump portion 150. More preferably, if the vertical length H3 of the second slope 150S2 of the bump portion 150 is out of the range of 25% to 35% of the vertical length H1 between the upper surface 150T and the lower surface of the bump portion 150, the effect of increasing the adhesion between the insulating layer 100 and the bump portion 150 may be insufficient, or the difference in width between the upper surface 150T and the lower surface of the bump portion 150 may become large.

[0199] Meanwhile, at least a portion of the first slope 150S1 of the bump portion 150 may not contact the insulating layer 100. For example, the first slope 150S1 of the bump portion 150 may include an overlapping portion that horizontally overlaps the insulating layer 100 and a non-overlapping portion that does not horizontally overlap the insulating layer 100. The overlapping portion of the first slope 150S1 of the bump portion 150 may not contact the insulating layer 100. For example, the overlapping portion of the first slope 150S1 of the bump portion 150 may be spaced apart from the inner wall 110W of the recess in the insulating layer 100. For example, at least a portion of the first slope 150S1 of the bump portion 150 may horizontally overlap the inner wall 110W of the insulating layer 100 but not contact the inner wall 110W. For example, the bump portion 150 may have a crevice corresponding to the first slope 150S1. The first slope 150S1 of the bump portion 150 may be in contact with the upper metal layer 170. This increases the contact area between the upper metal layer 170 and the bump portion 150, thereby improving the electrical and / or mechanical reliability of the circuit board.

[0200] In the embodiment, the bump portion 150 includes a tapered inclination, thereby preventing a semiconductor device from being coupled in an inclined state due to a height difference between the first bump 151 and the second bump 152 of the bump portion 150. Thus, the embodiment can minimize signal transmission loss in the circuit board and the semiconductor package caused by the height difference. Furthermore, the embodiment can address changes in impedance characteristics caused by the height difference. Furthermore, the embodiment can ensure stable operation of a semiconductor device mounted on a circuit board. Thus, the embodiment can further improve the mechanical and physical reliability of a semiconductor package and an electronic product including the same, thereby further improving product reliability.

[0201] Meanwhile, the via electrode VE may have a tapered slope whose width changes along the vertical direction. In this case, the slope directions of the via electrodes VE arranged in the insulating layer 100 may be the same as each other. Also, the slope direction of the slope VES of the side surface of the via electrode VE may be the same as the slope direction of the first slope 150S1 of the bump portion 150. However, the angle of the slope VES of the side surface of the via electrode VE may be different from the angle of the first slope 150S1 of the pad 151.

[0202] The upper metal layer 170 may be provided to cover the first slope 150S1 of the bump portion 150. At least a portion of the first slope 150S1 may horizontally overlap the insulating layer 100. For example, the upper metal layer 170 may be provided in a crevice of the bump portion 150, through which at least a portion of the upper metal layer 170 may horizontally overlap the inner wall 110W of the insulating layer 100 and the first slope 150S1 of the bump portion 150. This may increase the contact area between the upper metal layer 170 and the bump portion 150, and may further solve the problem of the upper metal layer 170 peeling off from the bump portion 150. Furthermore, the embodiment may prevent intermetallic compounds from diffusing into the gap between the insulating layer 100 and the side surface of the bump portion 150, thereby improving the mechanical and physical reliability of the semiconductor package.

[0203] The horizontal width of the upper metal layer 170 may be greater than the horizontal width of the bump portion 150. Thus, the upper metal layer 170 may include a first portion 170-1 that vertically overlaps the bump portion 150 and a second portion 170-2 that does not vertically overlap the bump portion 150. The first portion 170-1 of the upper metal layer 170 may be disposed on the bump portion 150 and may contact the upper surface 150T and the first slope 150S1 of the bump portion 150. The second portion 170-2 of the upper metal layer 170 may be disposed on the insulating layer 100 and may contact the upper surface 110T of the insulating layer 100. The side surface 170S of the second portion 170-2 of the upper metal layer 170 may have a slope. For example, the side surface 170S of the second portion 170-2 of the upper metal layer 170 may have a slope inclined in the same direction as the first slope 150S1 of the bump portion 150. The horizontal width of the upper metal layer 170 may be greater than the width of the opening 130R of the third insulating layer 130. Therefore, the side surface 170S of the upper metal layer 170 may be covered with the third insulating layer 130. In this case, the side surface 170S of the upper metal layer 170 may have a slope whose width gradually increases from the upper surface to the lower surface of the upper metal layer 170, thereby increasing the contact area between the upper metal layer 170 and the third insulating layer 130. Therefore, the embodiment may solve the problem of the third insulating layer 130 peeling off from the insulating layer 100 and / or the upper metal layer 170.

[0204] 5, the third insulating layer 130 may be disposed on the insulating layer 100. The third insulating layer 130 may include an opening that overlaps the bump portion 150 vertically.

[0205] In the circuit board of the third embodiment of FIG. 5, the upper metal layer 170 may be disposed after the third insulating layer 130 is laminated.

[0206] The horizontal width of the opening in the third insulating layer 130 may be larger than the horizontal width of the bump portion 150. This may cause the third insulating layer 130 not to overlap the bump portion 150 vertically. For example, an inner wall 130IW of the opening in the third insulating layer 130 and an inner wall 110W of the insulating layer 100 may have a step in the horizontal direction. For example, the opening in the third insulating layer 130 may be formed as a non-solder mask defined (NSMD).

[0207] The upper metal layer 170 may be disposed on the bump portion 150. The upper metal layer 170 may be disposed on the third insulating layer 130. For example, the upper metal layer 170 may protrude above the third insulating layer 130 while filling the openings in the third insulating layer 130. The upper metal layer 170 may be divided into a plurality of regions along the vertical direction.

[0208] The upper metal layer 170 may include a first region 170-1 protruding above the third insulating layer 130. The horizontal width of the first region 170-1 of the upper metal layer 170 may be greater than the horizontal width of the opening in the third insulating layer 130. Therefore, at least a portion of the first region 170-1 of the upper metal layer 170 may contact the upper surface of the third insulating layer 130. A side surface 170S1 of the first region 170-1 of the upper metal layer 170 may have a slope such that the width gradually increases from the upper surface to the lower surface of the upper metal layer 170.

[0209] The upper metal layer 170 may include a second region 170-2 disposed in the opening of the third insulating layer 130. A side surface 170S2 of the second region 170-2 of the upper metal layer 170 may be in contact with an inner wall 130IW of the opening 130R of the third insulating layer 130.

[0210] The upper metal layer 170 may include a third region 170-3 that fills the crevice of the bump portion 150. A side surface 170S3 of the third region 170-3 of the upper metal layer 170 may contact the inner wall 110W of the insulating layer 100.

[0211] Therefore, the side surfaces of the upper metal layer 170 may have steps in the horizontal direction. For example, the side surfaces 170S1 of the first region 170-1, the side surfaces 170S2 of the second region 170-2, and the side surfaces 170S1 of the third region 170-3 of the upper metal layer 170 may have steps.

[0212] For example, the horizontal width of the first region 170-1, the horizontal width of the second region 170-2, and the horizontal width of the third region 170-3 of the upper metal layer 170 may be different from one another. Therefore, the side surface of the upper metal layer 170 may have a step. In the embodiment, by having the step on the side surface of the upper metal layer 170, the contact area between the upper metal layer 170 and the third insulating layer 130 and the bump portion 150 may be further improved, thereby solving the problem of peeling of the upper metal layer 170.

[0213] In addition, in the embodiment, since the side of the upper metal layer 170 has a step, the distance between the intermetallic compound that can diffuse along the side of the upper metal layer 170 and the bump portion 150 can be further increased, and the problem of reduced electrical reliability and mechanical reliability that may occur due to the intermetallic compound can be more efficiently solved.

[0214] In addition, the upper metal layer 170 of the embodiment is disposed so as to protrude above the third insulating layer 130, thereby improving the degree of bonding between the upper metal layer 170 and the terminals of the semiconductor device. For example, in the embodiment, thermal compression bonding may be performed to reduce the volume of a connecting member such as solder. In this case, the upper metal layer 170 is disposed so as to protrude above the third insulating layer 130, thereby improving the degree of alignment between the terminals of the semiconductor device and the upper metal layer 170 during the thermal compression bonding process.

[0215] 6, the third insulating layer 130 may be disposed on the insulating layer 100. The third insulating layer 130 may include an opening that vertically overlaps the bump portion 150.

[0216] In this case, in one embodiment, the upper metal layer 170 may be formed before the third insulating layer 130 is disposed, and in another embodiment, the upper metal layer 170 may be formed after the third insulating layer 130 is disposed.

[0217] The horizontal width of the opening 130R of the third insulating layer 130 may be larger than the horizontal width of the bump portion 150. This means that the third insulating layer 130 does not need to vertically overlap the bump portion 150. For example, an inner wall 130IW of the opening of the third insulating layer 130 and an inner wall 110W of the insulating layer 100 may have a step.

[0218] The upper metal layer 170 may be disposed on the bump portion 150. The upper metal layer 170 may be disposed on the insulating layer 100. In this case, the upper metal layer 170 may not be disposed on the third insulating layer 130. For example, the upper metal layer 170 may not overlap the third insulating layer 130 in the vertical direction.

[0219] For example, the side surface 170S1 of the upper metal layer 170 may not contact the inner wall 130IW of the opening 130R of the third insulating layer 130. For example, the side surface 170S1 of the upper metal layer 170 may be horizontally spaced apart from the inner wall 130IW of the opening 130R of the third insulating layer 130. This allows the embodiment to increase the volume of a connecting member, such as solder, without increasing the thickness of the semiconductor package. Furthermore, the embodiment may solve the problem of electrical shorts, which may occur when adjacent upper metal layers 170 come into contact with each other due to pressure generated during the semiconductor device mounting process. For example, a space may be provided between the side surface 170S1 of the upper metal layer 170 and the inner wall 130IW of the opening 130R of the third insulating layer 130, and the space may function as a dam to prevent overflow of the connecting member due to pressure. This allows the embodiment to stably bond a semiconductor device onto the upper metal layer 170, thereby improving the mechanical and / or electrical reliability of the semiconductor package.

[0220] In addition, the upper surface of the upper metal layer 170 may be positioned higher than the upper surface of the third insulating layer 130. As a result, the embodiment may improve alignment between the upper metal layer 170 and the terminals of the semiconductor device.

[0221] 7, the third insulating layer 130 may have an opening with a horizontal width smaller than the horizontal width of the bump portion 150. Also, the third insulating layer 130 may be formed before the upper metal layer 170 is formed in the manufacturing process of the circuit board.

[0222] That is, the third insulating layer 130 may be formed before the upper metal layer 170 is formed, so that the crevice of the bump portion 150 may be filled with the third insulating layer 130 .

[0223] For example, the third insulating layer 130 may be disposed on the insulating layer 100 and the bump portion 150. The lower surface of the third insulating layer 130 may include a first lower surface in contact with the upper surface of the insulating layer 100 and a second lower surface in contact with the bump portion 150.

[0224] In addition, the second lower surface of the third insulating layer 130 may include a portion that contacts the first slope 150S1 of the bump portion 150. For example, the second lower surface of the third insulating layer 130 may have a slope corresponding to the first slope 150S1 of the bump portion 150. This may increase the contact area between the third insulating layer 130 and the bump portion 150, thereby improving the bonding strength therebetween.

[0225] In addition, the second lower surface of the third insulating layer 130 may include a portion that contacts the upper surface of the bump portion 150, but is not limited thereto.

[0226] For example, the horizontal width of the opening in the third insulating layer 130 may be smaller than the horizontal width of the upper surface 150T of the bump portion 150, thereby allowing at least a portion of the second lower surface of the third insulating layer 130 to contact the upper surface 150T of the bump portion 150.

[0227] In another embodiment, the horizontal width of the opening in the third insulating layer 130 may be larger than the horizontal width of the upper surface 150T of the bump portion 150, so that the second lower surface of the third insulating layer 130 can contact at least a portion of the slope 150S1 without contacting the upper surface 150T of the bump portion 150. In this case, at least a portion of the first slope 150S1 of the bump portion 150 can contact the upper metal layer 170 without contacting the third insulating layer 130.

[0228] Meanwhile, an upper metal layer 170 may be disposed on the bump portion 150. The upper metal layer 170 may protrude above the third insulating layer .

[0229] The upper metal layer 170 may include a first region 170-1 protruding above the third insulating layer 130 and a second region 170-2 disposed in the opening in the third insulating layer 130. The horizontal width of the first region 170-1 of the upper metal layer 170 may be greater than the horizontal width of the opening in the third insulating layer 130. This allows at least a portion of the first region 170-1 of the upper metal layer 170 to overlap the third insulating layer 130 in the vertical direction.

[0230] As a result, the embodiment may reduce the horizontal width of the upper metal layer 170 by disposing the upper metal layer 170 after the openings in the third insulating layer 130 are formed. Therefore, the embodiment may increase the spacing between adjacent conductive pads. This may more efficiently prevent short circuits caused by electrical contact between the conductive pads during the process of mounting a semiconductor device. Therefore, the embodiment may further improve the electrical reliability of the semiconductor package.

[0231] Meanwhile, referring to FIG. 8, the third insulating layer 130 may be disposed on the insulating layer 100 and may include an opening 130R that vertically overlaps the upper metal layer 170.

[0232] The inner wall of the opening 130R in the third insulating layer 130 may include a portion having a curved surface. The inner wall of the opening 130R in the third insulating layer 130 may include a first inner wall 130IW1 that is adjacent to the upper surface of the third insulating layer 130 and whose width decreases toward the lower surface of the third insulating layer 130. The first inner wall 130IW1 of the third insulating layer 130 may not be in contact with the upper metal layer 170. The first inner wall 130IW1 of the third insulating layer 130 has a curved surface with a specific radius of curvature.

[0233] The bottom end of the first inner wall 130IW1 of the opening 130R of the third insulating layer 130 may be located lower than the top surface of the upper metal layer 170. As a result, at least a portion of the side surface of the upper metal layer 170 may not be covered by the third insulating layer 130. For example, at least a portion of the side surface 170S of the upper metal layer 170 may horizontally overlap the first inner wall 130IW1. This allows the embodiment to allow a connecting member disposed on the upper metal layer 170 to contact at least a portion of the side surface 170S of the upper metal layer 170. This allows the embodiment to increase the contact area between the upper metal layer 170 and the connecting member, thereby improving the mutual coupling strength. Therefore, the embodiment allows a semiconductor device to be stably coupled to the upper metal layer 170, thereby enabling the semiconductor device to operate stably.

[0234] The inner wall of the opening 130R in the third insulating layer 130 may include a second inner wall 130IW2 adjacent to the lower surface of the third insulating layer 130. The second inner wall 130IW2 of the opening 130R in the third insulating layer 130 may be in contact with the upper metal layer 170. For example, the second inner wall 130IW2 of the opening 130R in the third insulating layer 130 may have a slope corresponding to the slope of the side surface 170S of the upper metal layer 170.

[0235] Therefore, in the embodiment, at least a portion of the side surface 170S of the upper metal layer 170 may not be covered with the third insulating layer 130, and the remaining portion may be covered with the third insulating layer 130. Through this, the embodiment may increase the contact area between the upper metal layer 170 and the connecting member, while efficiently preventing the intermetallic compound formed by the connecting member from diffusing into the bump portion 150. Through this, the embodiment may improve the mechanical reliability and / or electrical reliability of the circuit board.

[0236] A semiconductor package according to an embodiment includes a first insulating layer having a cavity, a connecting member disposed in the cavity, and a second insulating layer disposed on the connecting member. The second insulating layer stably fixes the connecting member and alleviates thermal stress acting on the semiconductor package, thereby minimizing damage transmitted to the connecting member. This prevents thermal stress from being transmitted to the connecting member via the second insulating layer. For example, the second insulating layer can act as a buffer that buffers stress. This allows the connecting member to be stably coupled to the semiconductor package, thereby improving the physical and mechanical reliability of the connecting member.

[0237] Specifically, the second insulating layer is provided to surround the pad portion of the connecting member and the connection portion disposed on the pad portion. The second insulating layer also surrounds at least a portion of the bump portion disposed on the connection portion. Thus, the second insulating layer of the embodiment functions to buffer stress transmitted to the bump portion, the pad portion, and the connection portion. Therefore, the embodiment prevents cracks from occurring in the connection portion due to stress. Thus, the embodiment can improve the reliability of electrical connections between the pad portion, the connection portion, and the bump portion. Therefore, the embodiment can stably connect multiple semiconductor devices using the connecting member, thereby improving the operational reliability of the multiple semiconductor devices.

[0238] In addition, the horizontal width of the second insulating layer is greater than the horizontal width of the connecting member, thereby maximizing the buffering effect of the second insulating layer in the embodiment, thereby further improving the physical and electrical reliability of the semiconductor package.

[0239] The second insulating layer may also include an extension. In this case, the extension of the second insulating layer may extend toward the side of the connecting member. For example, the extension of the second insulating layer may cover at least a portion of the side of the connecting member. This allows the connecting member to be more stably disposed within the cavity and further minimizes stress transmitted to the connecting member. Furthermore, if air is filled around the side of the connecting member, heat generated in the semiconductor device or semiconductor package may cause the air to expand, resulting in mechanical damage such as cracks in the semiconductor package. Therefore, if the second insulating layer does not include an extension, the side of the connecting member may be covered with another material to improve operational reliability.

[0240] Meanwhile, the second insulating layer may have a step with the first insulating layer. For example, the top surface of the second insulating layer may be positioned lower than the top surface of the first insulating layer. This may increase the contact area between the third insulating layer disposed on the first and second insulating layers, thereby resolving the problem of the third insulating layer peeling off from the first and / or second insulating layers. Furthermore, the first and second insulating layers may have different thermal expansion coefficients, such that at least one of the layers may expand or contract more than the other. In this case, the top surface of the second insulating layer may have a step with the top surface of the first insulating layer, thereby resolving the problem of peeling off between the first and second insulating layers due to expansion or contraction, thereby improving the mechanical reliability of the semiconductor package.

[0241] The semiconductor package of the embodiment also includes bump portions disposed on the first and second insulating layers. The bump portion includes a first bump penetrating at least a portion of the first insulating layer and protruding onto the first insulating layer. The bump portion also includes a second bump penetrating at least a portion of the second insulating layer and protruding onto the second insulating layer. In this case, the horizontal width of the second bump may be smaller than the horizontal width of the first bump. That is, at least a portion of the second bump may be embedded in the second insulating layer, thereby making the width of the second bump smaller than the width of the first bump. This allows the embodiment to reduce the pitch of pad portions provided on the connecting member, thereby reducing the volume of the connecting member. Therefore, the embodiment allows for a reduction in the volume of the semiconductor package.

[0242] Additionally, the side of the bump portion including the first and second bumps may include a first slope adjacent to the upper surface of the bump portion and a second slope different from the first slope, the second slope increasing in width toward the lower surface of the bump portion. The first slope and the second slope may be provided by a planarization process or pre-treatment process of the bump portion. For example, the bump portion may include a plurality of first bumps and a plurality of second bumps, each of which may include the first slope and the second slope. This allows the bump portion to have a uniform height, thereby minimizing height variations between the bumps. Furthermore, the embodiment may allow the bump portion including the plurality of bumps to have the same height. This allows the semiconductor device to be stably disposed on the bump portion, thereby enabling the semiconductor device to operate smoothly. Therefore, the embodiment may improve the operating characteristics of a semiconductor package and an electronic product including the same.

[0243] In addition, the first slope of the bump portion may be covered via a third insulating layer or an upper metal layer. In some embodiments, the first slope of the bump portion may contact the third insulating layer or the upper metal layer, thereby increasing the contact area therebetween. This increases the bonding strength between the bump portion and the third insulating layer or the upper metal layer, thereby resolving the problem of peeling between them. This improves the mechanical and / or electrical reliability of a circuit board and a semiconductor package including the same.

[0244] The first slope of the bump portion may include a portion that overlaps the first or second insulating layer but does not contact the first or second insulating layer. At least a portion of the first slope may be covered with the upper metal layer or the third insulating layer. This prevents the connection material, such as solder, from diffusing into the bump portion. The embodiment also allows the intermetallic compound formed by the connection material to be separated from the first wiring electrode, thereby resolving problems with cracks or reduced electrical characteristics of the bump portion that may be caused by the intermetallic compound.

[0245] In addition, the embodiment allows the bump portions to have uniform heights, thereby improving the signal transmission characteristics of the circuit board and the semiconductor package. For example, the embodiment can minimize signal transmission loss caused by differences in height between the bump portions. Furthermore, the embodiment can prevent changes in impedance characteristics caused by differences in height. As a result, the embodiment can further improve the mechanical reliability and physical reliability of the semiconductor package and electronic products including the same.

[0246] A method for manufacturing the circuit board shown in FIG. 2a will be described below.

[0247] 9 to 23 are diagrams showing the manufacturing method of the circuit board shown in FIG. 2a in the order of steps.

[0248] Referring to FIG. 9 , an embodiment provides an insulating member serving as a base for manufacturing a circuit board. The insulating member may be a carrier board CB. For example, the carrier board CB may include a carrier insulating layer CB1 and carrier metal layers CB2 and CB3. The carrier metal layers CB2 and CB3 may have a two-layer structure. For example, the carrier metal layers CB2 and CB3 may be metal layers including different metal materials. A first carrier metal layer CB2 may be disposed below the carrier insulating layer CB1. The first carrier metal layer CB2 may include a first metal material. The first metal material may include copper. The carrier insulating layer CB1 and the first carrier metal layer CB2 may be a copper clad laminate (CCL). A second carrier metal layer CB3 may be disposed below the first carrier metal layer CB2. The second carrier metal layer CB3 may include a second metal material different from the first metal material. The second metal material may include nickel. For example, the second carrier metal layer CB2 may be formed of a metal material that is not etched by the etchant used to etch the first metal material. This prevents the bump portion 150 from being etched during a seed layer etching process included in a circuit board manufacturing process. This minimizes height variations among the first bumps 151 and the second bumps 152 of the bump portion 150. While FIG. 9 illustrates the first and second carrier metal layers CB2 and CB3 disposed on one side of the carrier insulating layer CB1, this is not limiting. For example, the first and second carrier metal layers CB2 and CB3 may be disposed on both sides of the carrier insulating layer CB1, respectively. In this case, a process for simultaneously manufacturing multiple circuit boards may be performed on both sides of the carrier insulating layer CB1.

[0249] 10, in this embodiment, a process of forming a bump portion 150 on the second carrier metal layer CB3 may be performed. The bump portion 150 may be formed by electrolytic plating using the second carrier metal layer CB3 as a seed layer.

[0250] 11 , an embodiment may perform a process of stacking a first insulating layer 110 on a second carrier metal layer CB3. For example, an embodiment may perform a process of forming a fourth layer 114 of the first insulating layer 110 on the second carrier metal layer CB3. The first insulating layer 110 may be disposed to entirely embed the bump portion 150.

[0251] 12 , in an embodiment, a step of forming a via electrode VE and a wiring electrode WE on a fourth layer 114 of the first insulating layer 110 can be performed. In addition, in an embodiment, a step of forming a third layer 113 on the fourth layer 114 of the first insulating layer 110 can be performed. In addition, in an embodiment, a step of forming a via electrode VE and a wiring electrode WE on the third layer 113 can be performed.

[0252] 13, in this embodiment, a process may be performed in which the first insulating layer 110 is processed to form a cavity 100C. The cavity 100C may vertically overlap the second bump 152 of the bump portion 150. Therefore, the second bump 152 may expose the cavity 100C.

[0253] 14, in this embodiment, a process of forming a second insulating layer 120 in the cavity 100C may be performed. The second insulating layer 120 may have physical properties different from those of the first insulating layer 110. For example, the second insulating layer 120 may be, but is not limited to, a non-conductive adhesive material. Preferably, the second insulating layer 120 may include an insulating material that is capable of thermocompression bonding (TC bonding).

[0254] 15, in the embodiment, a process of electrically coupling the pad portion 210 of the connecting member 200 to the second bump 152 of the bump unit 150 may be performed in a state where the connection portion 220 is disposed below the pad portion 210 of the connecting member 200. In this case, in the embodiment, some of the wiring electrodes disposed on the outermost periphery of the circuit board may be used as guide points GP to recognize the placement position of the connecting member 200.

[0255] 16 , in this embodiment, the pad portion 210 of the connecting member 200 may be embedded in the second insulating layer 120 by applying pressure under an applied temperature in a bonding device. In this case, the second insulating layer 120 may expand to the side of the connecting member 200 due to the pressure, thereby forming an extension portion 120CP that encloses at least a portion of the side of the connecting member 200.

[0256] Referring to FIG. 17, in this embodiment, an additional lamination process may be performed on the third layer 113 of the first insulating layer 110 to manufacture a multi-layer circuit board.

[0257] 18, an embodiment may perform a process of removing the carrier board CB. To this end, an embodiment may perform a process of removing the carrier insulating layer CB1. Then, an embodiment may perform a process of removing the first carrier metal layer CB2. In this case, the second carrier metal layer CB3 may include a different metal material from the first carrier metal layer CB2, and therefore may not be removed in the process of removing the first carrier metal layer CB2.

[0258] 19, in this embodiment, a process of removing the second carrier metal layer CB3 by etching may be performed. At this time, the second carrier metal layer CB3 includes a metal material different from that of the bump portion 150, so that the bump portion 150 does not need to be removed in the process of removing the second carrier metal layer CB3.

[0259] 20 , in an embodiment, a plasma etching process may be performed to remove portions of the top surfaces of the first insulating layer 110 and the second insulating layer 120. In this case, the first insulating layer 110 and the second insulating layer 120 may contain different insulating materials. For example, the filler content in the second insulating layer 120 may be less than the filler content in the first insulating layer 110. As a result, a step may be formed between the top surface 110T of the first insulating layer 110 and the top surface 120T of the second insulating layer 120 after the etching process. For example, the top surface 110T of the first insulating layer 110 may be higher than the top surface 120T of the second insulating layer 120.

[0260] Referring to FIG. 21, an embodiment may include a step of forming a third insulating layer 130 on the first insulating layer 110 and the second insulating layer 120, and a step of forming a fourth insulating layer 140 below the first insulating layer 110.

[0261] 22, in an embodiment, a process of reducing the thickness of the third insulating layer 130 may be performed. Through this, the top surface of the third insulating layer 130 may be positioned lower than the top surface of the bump portion 150. In addition, in an embodiment, a process of exposing and developing the fourth insulating layer 140 to form at least one opening may be performed.

[0262] Referring to FIG. 23, in this embodiment, a process of forming an upper metal layer 170 on the bump portion 150 and forming a lower metal layer 180 under the terminal electrode 160 may be performed.

[0263] Meanwhile, when a semiconductor package having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect a semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical shorts between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it functions as a signal transmission device, it can solve noise problems. As a result, a circuit board having the above-described inventive features can maintain stable functionality in IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0264] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0265] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0266] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. a first insulating layer including a cavity; a connecting member disposed within the cavity; a second insulating layer disposed on the connecting member and including a material different from that of the first insulating layer; The width of the second insulating layer is greater than the width of the connecting member.

2. The circuit board of claim 1 , wherein the second insulating layer comprises a non-conductive adhesive material.

3. The circuit board according to claim 1 , wherein the upper surface of the first insulating layer and the upper surface of the second insulating layer have a step.

4. The circuit board according to claim 3 , wherein an upper surface of the second insulating layer is located lower than an upper surface of the first insulating layer.

5. further comprising a third insulating layer disposed on the first insulating layer and the second insulating layer; The lower surface of the third insulating layer is a first lower surface in contact with the upper surface of the first insulating layer and a second lower surface in contact with the upper surface of the second insulating layer; 5. The circuit board according to claim 3, wherein the first and second lower surfaces of the third insulating layer have a step.

6. a bump unit including a first bump disposed on the first insulating layer and a second bump disposed on the second insulating layer; the first bump does not overlap the connecting member in a vertical direction; The circuit board according to claim 5 , wherein the second bumps overlap the connecting members in a vertical direction and the first bumps in a horizontal direction.

7. The circuit board according to claim 6 , wherein at least one of the upper and lower surfaces of the first bump is flush with at least one of the upper and lower surfaces of the second bump.

8. The connecting member is an insulating member; a pad portion disposed on the insulating member; a connecting portion disposed on the pad portion and electrically connecting the second bump and the pad portion, The circuit board according to claim 6 , wherein the second insulating layer embeds the pad portion and the connection portion.

9. The circuit board according to claim 8 , wherein the second insulating layer includes an extension that extends toward a side surface of the insulating member of the connecting member and wraps around at least a portion of the side surface of the insulating member.

10. The circuit board according to claim 6 , wherein the horizontal width of the second bump is smaller than the horizontal width of the first bump.

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