Printed wiring board and method for manufacturing printed wiring board

Abstract

This printed wiring board comprises: a base film that has a first surface and a second surface which is the reverse surface of the first surface; a first conductive pattern that is on the first surface; and a first insulating layer that is on the first surface so as to cover the first conductive pattern. Within the first insulating layer, there are a plurality of first voids.

Description

[Technical Field]

[0001] The present disclosure relates to a printed wiring board and a method for manufacturing a printed wiring board. This application claims priority to Japanese Patent Application No. 2021-119547, filed on July 20, 2021. The entire contents of the Japanese patent application are incorporated herein by reference. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2016-9854 (Patent Document 1) describes a printed wiring board. The printed wiring board described in Patent Document 1 has a base film, a conductive pattern, and an adhesive layer (insulating layer). The base film has a main surface. The conductive pattern is on the main surface of the base film. The insulating layer covers the conductive pattern on the main surface of the base film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-9854 Summary of the Invention

[0004] The printed wiring board of the present disclosure includes a base film having a first surface and a second surface opposite the first surface, a first conductive pattern on the first surface, and a first insulating layer on the first surface so as to cover the first conductive pattern. A plurality of first voids are present in the first insulating layer.

[0005] The method for manufacturing a printed wiring board of the present disclosure includes the steps of preparing a base film having a first surface and a second surface opposite to the first surface, forming a first conductive pattern on the first surface, and forming a first insulating layer on the first surface so as to cover the first conductive pattern. The step of forming the first insulating layer includes the step of introducing a plurality of first voids into the first insulating layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a printed wiring board 100. FIG. [Figure 2] FIG. 2 is a bottom view of printed wiring board 100. FIG. [Figure 3A] FIG. 3A is a cross-sectional view taken along line IIIA-IIIA in FIG. [Figure 3B] FIG. 3B is a cross-sectional view taken along line IIIB-IIIB in FIG. [Figure 4] FIG. 4 is a process diagram showing a method for manufacturing printed wiring board 100. [Figure 5] FIG. 5 is a cross-sectional view of printed wiring board 100 after first layer forming step S21a has been performed. [Figure 6] FIG. 6 is a cross-sectional view of printed wiring board 100 after through-hole forming step S21b has been performed. [Figure 7A] FIG. 7A is a first cross-sectional view of printed wiring board 100 after second layer forming step S21c has been performed. [Figure 7B] FIG. 7B is a second cross-sectional view of printed wiring board 100 after second layer forming step S21c has been performed. [Figure 8A] FIG. 8A is a first cross-sectional view of printed wiring board 100 after resist formation step S22 has been performed. [Figure 8B] FIG. 8B is a second cross-sectional view of printed wiring board 100 after resist formation step S22 has been performed. [Figure 9A] FIG. 9A is a first cross-sectional view of printed wiring board 100 after first electrolytic plating step S23 has been performed. [Figure 9B] FIG. 9B is a second cross-sectional view of printed wiring board 100 after first electrolytic plating step S23 has been performed. [Figure 10A] FIG. 10A is a first cross-sectional view of printed wiring board 100 after resist removal step S24 has been performed. [Figure 10B] FIG. 10B is a second cross-sectional view of printed wiring board 100 after resist removal step S24 has been performed. [Figure 11A]FIG. 11A is a first cross-sectional view of printed wiring board 100 after seed layer removal step S25 has been performed. [Figure 11B] FIG. 11B is a second cross-sectional view of printed wiring board 100 after seed layer removal step S25 has been performed. [Figure 12A] FIG. 12A is a first cross-sectional view of printed wiring board 100 after second electrolytic plating step S26 has been performed. [Figure 12B] FIG. 12B is a second cross-sectional view of printed wiring board 100 after second electrolytic plating step S26 has been performed. DETAILED DESCRIPTION OF THE INVENTION

[0007] [Problem to be solved by this disclosure] It is preferable to use a resin material with high heat resistance (i.e., a high glass transition point) for the insulating layer covering the conductive pattern. However, resin materials with high heat resistance tend to have a high modulus of elasticity. Therefore, if a resin material with high heat resistance (high modulus of elasticity) is used for the insulating layer covering the conductive pattern, there is a risk that the printed wiring board will warp significantly due to an increase in temperature.

[0008] The present disclosure has been made in view of the above-described problems of the conventional art. More specifically, the present invention provides a printed wiring board and a method for manufacturing the printed wiring board that can suppress warping due to temperature rise.

[0009] [Effects of this disclosure] According to the printed wiring board and the method for manufacturing the printed wiring board of the present disclosure, it is possible to suppress warping caused by an increase in temperature.

[0010] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0011] (1) A printed wiring board according to an embodiment includes a base film having a first surface and a second surface opposite to the first surface, a first conductive pattern on the first surface, and No. 1and a first insulating layer on the first surface so as to cover the conductive pattern. A plurality of first voids exist in the first insulating layer. The printed wiring board of (1) above can suppress warping due to temperature rise.

[0012] (2) In the printed wiring board of (1), the area ratio of the plurality of first voids in the first insulating layer in a cross-sectional view may be 3% or more. The printed wiring board of (2) can further suppress warping due to temperature rise.

[0013] (3) In the printed wiring board of (1) or (2) above, the thermal expansion coefficient of the first insulating layer is 3.0 × 10 -5 / K or more. According to the printed wiring board of (3) above, even if the thermal expansion coefficient of the first insulating layer is large, warping due to temperature rise can be suppressed.

[0014] (4) In the printed wiring boards of (1) to (3) above, the first insulating layer may have an elastic modulus of 2 GPa or more. The printed wiring board of (4) above can have improved heat resistance.

[0015] (5) In the printed wiring boards of (1) to (4) above, the first conductive pattern may have a first seed layer on the first surface, a first core on the first seed layer, and a first shrink layer covering the first core. The printed wiring board of (5) above can increase the pattern rate of the first conductive pattern.

[0016] (6) In the printed wiring boards of (1) to (5) above, the height of the first conductive pattern may be greater than the width of the first conductive pattern. The printed wiring board of (6) above can reduce the wiring resistance of the first conductive pattern.

[0017] (7) In the printed wiring boards of (1) to (6) above, the height of the first conductive pattern may be greater than the thickness of the base film.

[0018] (8) In the printed wiring boards of (1) to (7), the first conductive pattern may have a spiral shape in a plan view. The printed wiring board of (8) can reduce deviation in the direction of warping due to temperature rise.

[0019] (9) The printed wiring boards of (1) to (8) above may further include a second conductive pattern on the second surface and a second insulating layer on the second surface so as to cover the second conductive pattern. A plurality of second voids may be present in the second insulating layer. The value obtained by dividing the total area of ​​the first conductive pattern in a plan view by the area of ​​the first surface may differ from the value obtained by dividing the total area of ​​the second conductive pattern in a plan view by the area of ​​the second surface.

[0020] (10) A method for manufacturing a printed wiring board according to an embodiment includes the steps of preparing a base film having a first surface and a second surface opposite the first surface, forming a first conductive pattern on the first surface, and forming a first insulating layer on the first surface so as to cover the first conductive pattern. The step of forming the first insulating layer includes the step of introducing a plurality of first voids into the first insulating layer. The method for manufacturing a printed wiring board according to (10) above makes it possible to suppress warpage.

[0021] (11) In the method for manufacturing a printed wiring board described in (10) above, the step of forming the first insulating layer may include the steps of mixing hollow microcapsules into uncured insulating material, applying the insulating material to the first surface so as to cover the first conductive pattern, and heating the insulating material to harden it.

[0022] [Details of the embodiments of the present disclosure] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0023] (Configuration of printed wiring board according to embodiment) A printed wiring board according to an embodiment (referred to as "printed wiring board 100") will be described below.

[0024] FIG. 1 is a plan view of the printed wiring board 100. FIG. 2 is a bottom view of the printed wiring board 100. In FIGS. 1 and 2, the first insulating layer 30 and the second insulating layer 50 are omitted. FIG. 3A is a cross-sectional view taken along line IIIA-IIIA in FIG. 1. FIG. 3B is a cross-sectional view taken along line IIIB-IIIB in FIG. 1. As shown in FIGS. 1, 2, 3A, and 3B, the printed wiring board 100 has a base film 10, a first conductive pattern 20, a first insulating layer 30, a second conductive pattern 40, and a second insulating layer 50.

[0025] The base film 10 has a first surface 10a and a second surface 10b. The first surface 10a and the second surface 10b are the main surfaces of the base film 10. The second surface 10b is the surface opposite to the first surface 10a. A through hole 10c is formed in the base film 10. The through hole 10c penetrates the base film 10 in the thickness direction.

[0026] The thickness of the base film 10 is defined as thickness T1. Thickness T1 is preferably 50 μm or less. Thickness T1 is more preferably 20 μm or less. This makes it possible to increase the volume ratio of the first conductive pattern 20 and the second conductive pattern 40. The base film 10 is made of a flexible insulating resin material. In other words, the printed wiring board 100 is a flexible printed wiring board. Specific examples of materials that can be used to form the base film 10 include polyimide, polyethylene terephthalate, and fluororesin.

[0027] The first conductive pattern 20 is disposed on the first surface 10a. The first conductive pattern 20 has a spiral shape in a plan view (when viewed from a direction perpendicular to the first surface 10a). In other words, the first conductive pattern 20 forms a coil.

[0028] The first conductive pattern 20 includes, for example, a first seed layer 21, a first core 22, and a first shrink layer 23.

[0029] The first seed layer 21 is on the first surface 10a. The first seed layer 21 has, for example, a first layer and a second layer. The first layer of the first seed layer 21 is on the first surface 10a. The first layer of the first seed layer 21 is formed, for example, from a nickel-chromium alloy. Copper may be formed on the nickel-chromium alloy. The first layer of the first seed layer 21 is, for example, a sputtered layer. The second layer of the first seed layer 21 is on the first layer of the first seed layer 21. The second layer of the first seed layer 21 is, for example, a sputtered layer, an electroless plated layer, or a layer in which a sputtered layer and an electroless plated layer are stacked.

[0030] The first core 22 is on the first seed layer 21. The first core 22 is formed of, for example, copper. The first core 22 is, for example, an electrolytic plating layer. The first shrink layer 23 covers the side surfaces of the first seed layer 21 and the first core 22 and the top surface of the first core 22. The first shrink layer 23 is, for example, an electrolytic plating layer.

[0031] The width of the first conductive pattern 20 is defined as width W1, and the height of the first conductive pattern 20 is defined as height H1. The height H1 is, for example, larger than the width W1. That is, the aspect ratio of the first conductive pattern 20 (the value obtained by dividing the height H1 by the width W1) is, for example, 1 or more. The aspect ratio of the first conductive pattern 20 is preferably 1.5 or more. The height H1 is, for example, equal to or larger than the thickness T1. The height H1 is, for example, equal to or larger than 40 μm.

[0032] The first pattern ratio is the value obtained by dividing the total area of ​​the first conductive pattern 20 by the area of ​​the region sandwiched between the innermost and outermost peripheries of the first conductive pattern 20. The first pattern ratio is, for example, 30 percent or more. The first pattern ratio may be 40 percent or more.

[0033] The first insulating layer 30 is on the first surface 10a so as to cover the first conductive pattern 20. The first insulating layer 30 is made of an insulating resin material. Specific examples of materials that may be used to form the first insulating layer 30 include epoxy, urethane, and polyimide.

[0034] The elastic modulus of the first insulating layer 30 is, for example, 2 GPa or more. This makes it possible to improve the heat resistance of the printed wiring board 100. The elastic modulus of the first insulating layer 30 may be 4 GPa or more. The elastic modulus of the first insulating layer 30 is the elastic modulus of the material that constitutes the first insulating layer 30. The elastic modulus of the first insulating layer 30 is, for example, 12 GPa or less. The elastic modulus of the first insulating layer 30 is measured by the nanoindentation method defined in ISO14577.

[0035] The thermal expansion coefficient of the first insulating layer 30 is, for example, 3.0×10 -5 / K or more. As a result, even if the thermal expansion coefficient of the first insulating layer 30 is large, warping of the printed wiring board 100 due to temperature rise can be suppressed by introducing the first voids 31. The thermal expansion coefficient of the first insulating layer 30 is 4.5×10 -5 The thermal expansion coefficient of the first insulating layer 30 may be, for example, 9.0×10 -5 / K or less. The thermal expansion coefficient of the first insulating layer 30 is 2.0×10 -4 / K or less. By setting the thermal expansion coefficient of the first insulating layer 30 within this range, it is possible to sufficiently suppress warping of the printed wiring board 100 due to temperature rise by introducing the first voids 31. The thermal expansion coefficient of the first insulating layer 30 is the thermal expansion coefficient of the material of the first insulating layer 30. The thermal expansion coefficient of the first insulating layer 30 is measured by TMA (Thermal Mechanical Analysis).

[0036] A plurality of first voids 31 exist in the first insulating layer 30. The first voids 31 exist at least between portions of the adjacent first conductive patterns 20. The shape of the first voids 31 is, for example, spherical. However, the shape of the first voids 31 is not limited to this.

[0037] In a cross-sectional view, the area ratio of the plurality of first voids 31 in the first insulating layer 30 is, for example, 3 percent or more. This makes it possible to further suppress warping of the printed wiring board 100 due to an increase in temperature. In a cross-sectional view, the area ratio of the plurality of first voids 31 in the first insulating layer 30 may be 5 percent or more. In a cross-sectional view, the area ratio of the plurality of first voids 31 in the first insulating layer 30 is, for example, 30 percent or less. The area ratio of the plurality of first voids 31 in the first insulating layer 30 in a cross-sectional view is calculated by obtaining a cross-sectional image of the first insulating layer 30 using a microscope (optical microscope or electron microscope) and performing image processing on the obtained cross-sectional image.

[0038] The average diameter of the multiple first voids 31 is, for example, 5 μm or less. This makes it possible to improve the insulation between adjacent portions of the first conductive pattern 20. The average diameter of the multiple first voids 31 is, for example, 0.3 μm or more. This makes it possible to reduce the number of multiple first voids 31 in the first insulating layer 30, thereby reducing manufacturing costs. The average diameter of the multiple first voids 31 is calculated by the following method.

[0039] When calculating the average diameter of the multiple first voids 31, first, a cross-sectional image of the first insulating layer 30 is obtained using a microscope (optical microscope or electron microscope). Second, image processing is performed on the cross-sectional image to calculate the area of ​​each of the multiple first voids 31 included in the cross-sectional image. The square root of the value obtained by dividing the area of ​​each of the multiple first voids 31 included in the cross-sectional image by π / 4 becomes the circle-equivalent diameter of each of the multiple first voids 31 included in the cross-sectional image. Third, the value obtained by dividing the sum of the circle-equivalent diameters of each of the multiple first voids 31 included in the cross-sectional image by the total number of the multiple first voids 31 included in the cross-sectional image is considered to be the average diameter of the multiple first voids 31.

[0040] Microcapsules 32 (not shown) may be present on the surface of the first void 31. The microcapsules 32 are hollow and made of an insulating resin material.

[0041] The second conductive pattern 40 is disposed on the second surface 10b. The second conductive pattern 40 has a spiral shape in a plan view (when viewed from a direction perpendicular to the second surface 10b). In other words, the second conductive pattern 40 forms a coil. The second conductive pattern 40 is electrically connected to the first conductive pattern 20.

[0042] The second conductive pattern 40 includes, for example, a second seed layer 41, a second core 42, and a second shrink layer 43.

[0043] The second seed layer 41 is on the second surface 10b. The second seed layer 41 has, for example, a first layer and a second layer. The first layer of the second seed layer 41 is on the second surface 10b. The first layer of the second seed layer 41 is formed, for example, of a nickel-chromium alloy. Copper may be formed on the nickel-chromium alloy. The first layer of the second seed layer 41 is, for example, a sputtered layer. The second layer of the second seed layer 41 is on the first layer of the second seed layer 41. The second layer of the second seed layer 41 is, for example, a sputtered layer, an electroless plated layer, or a layer in which a sputtered layer and an electroless plated layer are stacked.

[0044] The second core 42 is on the second seed layer 41. The second core 42 is formed of, for example, copper. The second core 42 is, for example, an electrolytic plating layer. The second shrink layer 43 covers the side surfaces of the second seed layer 41 and the second core 42 and the top surface of the second core 42. The second shrink layer 43 is, for example, an electrolytic plating layer.

[0045] The width of the second conductive pattern 40 is width W2, and the height of the second conductive pattern 40 is height H2. The height H2 is, for example, larger than the width W2. That is, the aspect ratio of the second conductive pattern 40 (the value obtained by dividing the height H2 by the width W2) is, for example, 1 or more. The aspect ratio of the second conductive pattern 40 is preferably 1.5 or more. The height H2 is, for example, equal to or larger than the thickness T1. The height H2 is, for example, 40 μm or more.

[0046] The second pattern ratio is the value obtained by dividing the total area of ​​the second conductive pattern 40 by the area of ​​the region sandwiched between the innermost and outermost peripheries of the second conductive pattern 40. The second pattern ratio is, for example, different from the first pattern ratio. The second pattern ratio is, for example, higher than the first pattern ratio. The second pattern ratio is, for example, 40 percent or more. The second pattern ratio may also be 50 percent or more.

[0047] The second layer of the first seed layer 21 and the second layer of the second seed layer 41 are connected to each other on the inner wall surface of the through hole 10c. The first core 22 and the second core 42 are connected to each other on the inner wall surface of the through hole 10c. The first shrink layer 23 and the second shrink layer 43 are configured to cover the first core 22 and the second core 42, respectively. This means that the first conductive pattern 20 and the second conductive pattern 40 are electrically connected.

[0048] The second insulating layer 50 is on the second surface 10b so as to cover the second conductive pattern 40. The second insulating layer 50 is made of an insulating resin material. Specific examples of materials that may be used to form the second insulating layer 50 include epoxy, urethane, and polyimide.

[0049] The elastic modulus of the second insulating layer 50 is, for example, 2 GPa or more. This makes it possible to improve the heat resistance of the printed wiring board 100. The elastic modulus of the second insulating layer 50 may be 4 GPa or more. The elastic modulus of the second insulating layer 50 is, for example, 12 GPa or less. The elastic modulus of the second insulating layer 50 is the elastic modulus of the constituent material of the second insulating layer 50. The elastic modulus of the second insulating layer 50 is measured by the same method as the elastic modulus of the first insulating layer 30.

[0050] The thermal expansion coefficient of the second insulating layer 50 is, for example, 3.0×10 -5 / K or more. As a result, even if the thermal expansion coefficient of the second insulating layer 50 is large, warping of the printed wiring board 100 due to temperature rise can be suppressed by introducing the second voids 51. The thermal expansion coefficient of the second insulating layer 50 is 4.5×10 -5The thermal expansion coefficient of the second insulating layer 50 may be, for example, 9.0×10 -5 / K or less. The thermal expansion coefficient of the second insulating layer 50 is 2.0×10 -4 or less. By setting the thermal expansion coefficient of the second insulating layer 50 within this range, it is possible to sufficiently suppress warping of the printed wiring board 100 due to temperature rise by introducing the second voids 51. The thermal expansion coefficient of the second insulating layer 50 is the thermal expansion coefficient of the constituent material of the second insulating layer 50. The thermal expansion coefficient of the second insulating layer 50 is measured by the same method as that of the first insulating layer 30.

[0051] A plurality of second voids 51 exist in the second insulating layer 50. The second voids 51 exist at least between portions of the adjacent second conductive patterns 40. The shape of the second voids 51 is, for example, spherical. However, the shape of the second voids 51 is not limited to this.

[0052] In a cross-sectional view, the area ratio of the plurality of second voids 51 in the second insulating layer 50 is, for example, 3 percent or more. This makes it possible to further suppress warping of the printed wiring board 100 due to an increase in temperature. In a cross-sectional view, the area ratio of the plurality of second voids 51 in the second insulating layer 50 may be 5 percent or more. In a cross-sectional view, the area ratio of the plurality of second voids 51 in the second insulating layer 50 is, for example, 30 percent or less. The area ratio of the plurality of second voids 51 in the second insulating layer 50 in a cross-sectional view is measured by the same method as the area ratio of the plurality of first voids 31 in the first insulating layer 30 in a cross-sectional view.

[0053] The average diameter of the second voids 51 is, for example, 5 μm or less. This makes it possible to improve the insulation between adjacent portions of the second conductive pattern 40. The average diameter of the second voids 51 is, for example, 0.3 μm or more. This makes it possible to reduce the number of second voids 51 in the second insulating layer 50, thereby lowering manufacturing costs. The average diameter of the second voids 51 is measured by the same method as for the average diameter of the first voids 31. Microcapsules 52 (not shown) may be present on the surface of the second voids 51. The microcapsules 52 are hollow and made of an insulating resin material.

[0054] (Method of manufacturing a printed wiring board according to an embodiment) A method for manufacturing the printed wiring board 100 will be described below.

[0055] 4 is a process diagram showing a method for manufacturing printed wiring board 100. As shown in FIG. 4, the method for manufacturing printed wiring board 100 includes a preparation step S1, a conductive pattern formation step S2, and an insulating layer formation step S3.

[0056] In the preparation step S1, a base film 10 is prepared. The conductive pattern formation step S2 is performed after the preparation step S1. In the conductive pattern formation step S2, a first conductive pattern 20 and a second conductive pattern 40 are formed.

[0057] The conductive pattern formation process S2 includes a seed layer formation process S21, a resist formation process S22, a first electrolytic plating process S23, a resist removal process S24, a seed layer removal process S25, and a second electrolytic plating process S26. The resist formation process S22 is performed after the seed layer formation process S21. The first electrolytic plating process S23 is performed after the resist formation process S22. The resist removal process S24 is performed after the first electrolytic plating process S23. The seed layer removal process S25 is performed after the resist removal process S24. The second electrolytic plating process S26 is performed after the seed layer removal process S25.

[0058] The seed layer forming step S21 includes a first layer forming step S21a, a through hole forming step S21b, and a second layer forming step S21c. Fig. 5 is a cross-sectional view of the printed wiring board 100 after the first layer forming step S21a has been performed. As shown in Fig. 5, in the first layer forming step S21a, the first layer of the first seed layer 21 and the first layer of the second seed layer 41 are formed. The first layer of the first seed layer 21 and the first layer of the second seed layer 41 are formed, for example, by sputtering the first surface 10a and the second surface 10b.

[0059] 6 is a cross-sectional view of the printed wiring board 100 after the through hole forming step S21b has been performed. As shown in Fig. 6, in the through hole forming step S21b, the through hole 10c is formed. The through hole 10c is formed using, for example, a laser, a drill, or the like.

[0060] FIG. 7A is a first cross-sectional view of printed wiring board 100 after second layer forming step S21c has been performed. FIG. 7B is a second cross-sectional view of printed wiring board 100 after second layer forming step S21c has been performed. FIG. 7A is related to FIG. 3A, and FIG. 7B is related to FIG. 3B. As shown in FIGS. 7A and 7B, in second layer forming step S21c, the second layer of first seed layer 21 and the second layer of second seed layer 41 are formed. For example, the second layer of first seed layer 21 and the second layer of second seed layer 41 are formed by performing electroless plating on the first layer of first seed layer 21, the first layer of second seed layer 41, and the inner wall surface of through hole 10c.

[0061] FIG. 8A is a first cross-sectional view of the printed wiring board 100 after the resist formation step S22 has been performed. FIG. 8B is a second cross-sectional view of the printed wiring board 100 after the resist formation step S22 has been performed. FIG. 8A is related to FIG. 3A, and FIG. 8B is related to FIG. 3B. As shown in FIGS. 8A and 8B, in the resist formation step S22, a resist 60 is formed on the first seed layer 21 and the second seed layer 41. In forming the resist 60, first, a photosensitive organic material is applied on the first seed layer 21 and the second seed layer 41. Instead of applying the photosensitive organic material, a dry film resist may be disposed on the first seed layer 21 and the second seed layer 41. Second, the applied photosensitive organic material (dry film resist) is exposed and developed to be patterned, thereby forming the resist 60. The first seed layer 21 and the second seed layer 41 are partially exposed from the resist 60.

[0062] 9A is a first cross-sectional view of printed wiring board 100 after first electrolytic plating step S23 has been performed. FIG. 9B is a second cross-sectional view of printed wiring board 100 after first electrolytic plating step S23 has been performed. FIG. 9A is related to FIG. 3A, and FIG. 9B is related to FIG. 3B. As shown in FIGS. 9A and 9B, in first electrolytic plating step S23, first core body 22 and second core body 42 are formed. First core body 22 and second core body 42 are formed on first seed layer 21 and second seed layer 41 exposed from resist 60, respectively, by passing a current through first seed layer 21 and second seed layer 41 to perform electrolytic plating.

[0063] 10A is a first cross-sectional view of the printed wiring board 100 after the resist removal step S24 has been performed. FIG. 10B is a second cross-sectional view of the printed wiring board 100 after the resist removal step S24 has been performed. FIG. 10A is related to FIG. 3A, and FIG. 10B is related to FIG. 3B. As shown in FIGS. 10A and 10B, in the resist removal step S24, the resist 60 is peeled off and removed from the first seed layer 21 and the second seed layer 41. After the resist 60 has been peeled off, the first seed layer 21 is exposed between portions of the adjacent first cores 22, and the second seed layer 41 is exposed between portions of the second cores 42.

[0064] 11A is a first cross-sectional view of the printed wiring board 100 after the seed layer removal step S25 has been performed. FIG. 11B is a second cross-sectional view of the printed wiring board 100 after the seed layer removal step S25 has been performed. FIG. 11A is related to FIG. 3A, and FIG. 11B is related to FIG. 3B. As shown in FIGS. 11A and 11B, in the seed layer removal step S25, the first seed layer 21 exposed between portions of the first core 22 adjacent to each other and the second seed layer 41 exposed between portions of the second core 42 adjacent to each other are removed by etching. This etching is, for example, wet etching.

[0065] Fig. 12A is a first cross-sectional view of printed wiring board 100 after second electrolytic plating step S26 has been performed. Fig. 12B is a second cross-sectional view of printed wiring board 100 after second electrolytic plating step S26 has been performed. Fig. 12A is related to Fig. 3A, and Fig. 12B is related to Fig. 3B. As shown in Figs. 12A and 12B, in second electrolytic plating step S26, first shrink layer 23 and second shrink layer 43 are formed.

[0066] The first shrink layer 23 is formed so as to cover the first seed layer 21 and the first core 22 by passing a current through the first seed layer 21 and the first core 22 to perform electrolytic plating. The second shrink layer 43 is formed so as to cover the second seed layer 41 and the second core 42 by passing a current through the second seed layer 41 and the second core 42 to perform electrolytic plating.

[0067] The insulating layer forming process S3 is performed after the conductive pattern forming process S2. The insulating layer forming process S3 includes a microcapsule mixing process S31, an insulating material applying process S32, and an insulating material hardening process S33. The insulating material applying process S32 is performed after the microcapsule mixing process S31. The insulating material hardening process S33 is performed after the insulating material applying process S32.

[0068] In the microcapsule mixing step S31, microcapsules are mixed into the uncured insulating material. The microcapsules are made of an insulating resin material and are filled with a volatile liquid.

[0069] In the insulating material application step S32, the insulating material having microcapsules mixed therein is applied onto the first surface 10a so as to cover the first conductive pattern 20, and is also applied onto the second surface 10b so as to cover the second conductive pattern 40.

[0070] In the insulating material curing step S33, the insulating material applied to the first surface 10a and the second surface 10b is heated and cured to form the first insulating layer 30 and the second insulating layer 50, respectively. At this time, the liquid in the microcapsules evaporates, turning them into hollow microcapsules 32 and microcapsules 52, and forming first voids 31 and second voids 51. In this way, the printed wiring board 100 having the structure shown in Figures 1, 2, 3A, and 3B is formed.

[0071] Although the above describes an example in which the first conductive pattern 20 and the second conductive pattern 40 are formed by a semi-additive method, the first conductive pattern 20 and the second conductive pattern 40 may also be formed by a subtractive method.

[0072] In the above, the first void 31 and the second void 51 were formed by mixing microcapsules filled with liquid into the uncured insulating material, but the first void 31 and the second void 51 may also be formed by stirring the uncured insulating material and introducing air bubbles into the uncured insulating material.

[0073] (Effects of the Printed Wiring Board According to the Embodiment) The effects of the printed wiring board 100 will be described below.

[0074] As the temperature of the printed wiring board 100 rises, the first insulating layer 30 (second insulating layer 50) between adjacent portions of the first conductive patterns 20 (second conductive patterns 40) may thermally expand, causing the printed wiring board 100 to warp.

[0075] However, in the printed wiring board 100, the first insulating layer 30 (second insulating layer 50) has a plurality of first voids 31 (second voids 51), which reduces the effective elastic modulus and thermal expansion coefficient of the first insulating layer 30 (second insulating layer 50). Therefore, the printed wiring board 100 can suppress warping caused by an increase in temperature.

[0076] Warping of the printed wiring board 100 due to an increase in temperature becomes significant when the first insulating layer 30 (second insulating layer 50) has a high elastic modulus and thermal conductivity. According to the printed wiring board 100, warping due to an increase in temperature can be suppressed even in such cases. From another perspective, according to the printed wiring board 100, heat resistance can be improved by using a material with a high elastic modulus and thermal conductivity (i.e., a material with high heat resistance) for the first insulating layer 30 (second insulating layer 50).

[0077] Warping of the printed wiring board 100 due to temperature rise becomes more pronounced when the first pattern ratio and the second pattern ratio are different. Furthermore, warping of the printed wiring board 100 due to temperature rise becomes more pronounced when the aspect ratio of the first conductive pattern 20 (second conductive pattern 40) is large. Furthermore, warping of the printed wiring board 100 due to temperature rise becomes more pronounced when the base film 10 is thin. Even in these cases, the printed wiring board 100 can suppress warping due to temperature rise.

[0078] (simulation) Below, a description will be given of a simulation that was performed to confirm the effects of printed wiring board 100. In this simulation, as shown in Table 1, Sample 1 to Sample 25 were used as samples of printed wiring board 100.

[0079] [Table 1]

[0080] In Samples 1 to 25, the elastic modulus of the first insulating layer 30 (the elastic modulus of the material constituting the first insulating layer 30) and the elastic modulus of the second insulating layer 50 (the elastic modulus of the material constituting the second insulating layer 50) were set to either 4 GPa or 12 GPa. In addition, in Samples 1 to 25, the thermal expansion coefficient of the first insulating layer 30 (the thermal conductivity of the material constituting the first insulating layer 30) and the thermal expansion coefficient of the second insulating layer 50 (the thermal conductivity of the material constituting the second insulating layer 50) were set to 4.5×10 -5 / K and 9.0×10 -5 / K.

[0081] In Samples 1 to 25, the area ratio of the first voids 31 in the first insulating layer 30 and the area ratio of the second voids 51 in the second insulating layer 50 were either 0 percent, 5 percent, 10 percent, 20 percent, or 30 percent. In Samples 1 to 25, the first pattern ratio was either 50 percent or 70 percent, and the second pattern ratio was either 65 percent or 85 percent.

[0082] In Samples 1 to 25, heights H1 and H2 were either 50 μm or 70 μm. Although not shown in Table 1, thickness T1 was 12.5 μm in Samples 1 to 25. The planar shape of Samples 1 to 25 was a 1 cm square.

[0083] The amount of warpage was calculated for Samples 1 to 25. The amount of warpage was defined as the distance between the reference plane and the farthest point on the sample when the sample was placed on the reference plane. The amount of warpage was calculated by increasing the temperature of the sample by 50°C.

[0084] As shown in Table 1, the amount of warpage of Sample 1 was greater than the amounts of warpage of Samples 2 to 5, and the amount of warpage of Sample 6 was greater than the amounts of warpage of Samples 7 to 10. The amount of warpage of Sample 11 was greater than the amounts of warpage of Samples 12 to 15, and the amount of warpage of Sample 16 was greater than the amounts of warpage of Samples 17 to 20. The amount of warpage of Sample 21 was greater than the amounts of warpage of Samples 22 to 25.

[0085] In Sample 1, there were no first voids 31 in the first insulating layer 30, and no second voids 51 in the second insulating layer 50. Sample 1 was similar to Samples 2 to 5 except for the area ratio of the first voids 31 in the first insulating layer 30 and the area ratio of the second voids 51 in the second insulating layer 50.

[0086] In Sample 6, no first voids 31 were present in the first insulating layer 30, and no second voids 51 were present in the second insulating layer 50. Sample 6 was similar to Samples 7 to 10 except for the area ratio of the first voids 31 in the first insulating layer 30 and the area ratio of the second voids 51 in the second insulating layer 50.

[0087] In Sample 11, there were no first voids 31 in the first insulating layer 30, and no second voids 51 in the second insulating layer 50. Sample 11 was similar to Samples 12 to 15 except for the area ratio of the first voids 31 in the first insulating layer 30 and the area ratio of the second voids 51 in the second insulating layer 50.

[0088] In Sample 16, there were no first voids 31 in the first insulating layer 30, and no second voids 51 in the second insulating layer 50. Sample 16 was similar to Samples 17 to 20 except for the area ratio of the first voids 31 in the first insulating layer 30 and the area ratio of the second voids 51 in the second insulating layer 50.

[0089] In Sample 21, there were no first voids 31 in the first insulating layer 30, and no second voids 51 in the second insulating layer 50. Sample 21 was similar to Samples 22 to 25 except for the area ratio of the first voids 31 in the first insulating layer 30 and the area ratio of the second voids 51 in the second insulating layer 50.

[0090] From these comparisons, it was revealed through simulation that the presence of the first void 31 (second void 51) in the first insulating layer 30 (second insulating layer 50) suppresses warping of the printed wiring board 100 due to an increase in temperature.

[0091] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not the above-described embodiments, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0092] 10 base film, 10a first surface, 10b second surface, 10c through hole, 20 first conductive pattern, 21 first seed layer, 22 first core, 23 first shrink layer, 30 first insulating layer, 31 first void, 32 microcapsules, 40 second conductive pattern, 41 second seed layer, 42 second core, 43 second shrink layer, 50 second insulating layer, 51 second void, 52 microcapsules, 60 resist, 100 printed wiring board, H1, H2 height, S1 preparation step, S2 conductive pattern formation step, S3 insulating layer formation step, S21 seed layer formation step, S21a first layer formation step, S21b through hole formation step, S21c second layer formation step, S22 resist formation step, S23 first electrolytic plating step, S24 resist removal step, S25 seed layer removal step, S26 Second electrolytic plating process, S31 microcapsule mixing process, S32 insulating material application process, S33 insulating material hardening process, T1 thickness, W1, W2 width.

Claims

1. a base film having a first surface and a second surface opposite the first surface; a first conductive pattern on the first surface, the first conductive pattern having a spiral shape in a plan view; a first insulating layer on the first surface so as to cover the first conductive pattern; a plurality of first voids are present in the first insulating layer; A printed wiring board, wherein the interior of each of the plurality of first voids is hollow.

2. The printed wiring board according to claim 1 , wherein an area ratio of the plurality of first voids in the first insulating layer in a cross-sectional view is 3 percent or more.

3. The thermal expansion coefficient of the first insulating layer is 3.0×10 －５ 2. The printed wiring board according to claim 1, wherein the tensile strength is 1 / K or more.

4. The printed wiring board according to claim 1 , wherein the first insulating layer has an elastic modulus of 2 GPa or more.

5. 2. The printed wiring board according to claim 1, wherein the first conductive pattern has a first seed layer on the first surface, a first core on the first seed layer, and a first shrink layer covering the first core.

6. The printed wiring board according to claim 1 , wherein the height of the first conductive pattern is greater than the width of the first conductive pattern.

7. The printed wiring board according to claim 1 , wherein the height of the first conductive pattern is greater than the thickness of the base film.

8. a second conductive pattern on the second surface; a second insulating layer on the second surface so as to cover the second conductive pattern; a plurality of second voids are present in the second insulating layer; 8. The printed wiring board according to claim 1, wherein a value obtained by dividing a total area of ​​the first conductive patterns in a planar view by an area of ​​the first surface is different from a value obtained by dividing a total area of ​​the second conductive patterns in a planar view by an area of ​​the second surface.

9. providing a base film having a first surface and a second surface opposite the first surface; forming a first conductive pattern on the first surface, the first conductive pattern having a spiral shape in a plan view; forming a first insulating layer on the first surface to cover the first conductive pattern; forming the first insulating layer includes introducing a plurality of first voids into the first insulating layer; A method for manufacturing a printed wiring board, wherein the interior of each of the plurality of first voids is hollow.

10. 10. The method for manufacturing a printed wiring board according to claim 9, wherein the step of forming the first insulating layer comprises the steps of: mixing hollow microcapsules into an uncured insulating material; applying the insulating material to the first surface so as to cover the first conductive pattern; and heating the insulating material to harden it.

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