Display substrate and display device

Abstract

To enhance transmittance of a display region.SOLUTION: A display substrate comprises a display region, at least one first signal line, and at least one connecting wire. The display region includes a first display region and a second display region, at least part of the second display region surrounds the first display region, the first display region includes at least one first light-emitting element, the second display region includes at least one first pixel circuit, at least one first signal line includes a first main body portion and a first winding portion, the first main body portion extends along a first direction, at least part of the first winding portion extends along a direction intersecting with the first direction, at least one first signal line is electrically connected to at least one first pixel circuit so as to transmit a first driving signal to at least one first pixel circuit, and at least one first pixel circuit is electrically connected to the first light-emitting element through corresponding connecting wire respectively, and the first pixel circuit is configured to drive the first light-emitting element respectively.SELECTED DRAWING: Figure 5A

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to PCT patent applications PCT / CN2020 / 073993, PCT / CN2020 / 073995, PCT / CN2020 / 073996, and PCT / CN2020 / 074001, filed on January 23, 2020, the entire disclosures of which are incorporated herein by reference for all purposes.

[0002] The embodiments of the present disclosure relate to a display substrate and a display device. [Background technology]

[0003] Organic light-emitting diode (OLED) display devices have various characteristics, including a wide viewing angle, high contrast, fast response time, wide color gamut, high screen-to-body ratio, self-luminescence, light weight, and thinness. Furthermore, compared with inorganic light-emitting display devices, OLED display devices have advantages such as higher luminance and lower driving voltage. Due to these characteristics and advantages, OLED display devices have gradually gained attention and can be applied to devices with display functions, such as mobile phones, displays, notebook computers, smart watches, digital cameras, instrumentation, and flexible wearable devices. With the further development of display technology, display devices with high screen-to-body ratios can no longer meet people's needs, and full-screen display devices are becoming the future development trend of display technology. Summary of the Invention [Means for solving the problem]

[0004] At least one embodiment of the present disclosure provides a display substrate including a display area, at least one first signal line, and at least one connecting wire, the display area including a first display area and a second display area at least partially surrounding the first display area, the first display area including at least one first light-emitting element, the second display area including at least one first pixel circuit, the at least one first signal line including a first body portion and a first winding portion, the first body portion extending along a first direction, the first winding portion being wired offset from an imaginary extension line of the first body portion along the first direction, the at least one first signal line electrically connected to the at least one first pixel circuit to transmit a first drive signal to the at least one first pixel circuit, the at least one first pixel circuit electrically connected to the at least one first light-emitting element via a corresponding connecting wire, and the at least one first pixel circuit configured to drive the at least one first light-emitting element, respectively.

[0005] For example, in at least one example of the display substrate, the display region further includes a third display region, the third display region surrounds at least a portion of the second display region, the at least one first light-emitting element includes a plurality of first light-emitting elements, the second display region includes a plurality of second light-emitting elements, the third display region includes a plurality of third light-emitting elements, and the at least one first signal line is configured to drive the first light-emitting elements and the third light-emitting elements arranged in parallel along the first direction.

[0006] For example, in at least one example of the display substrate, the display substrate further includes at least one second signal line, the at least one second signal line includes a second body portion, the second body portion extends along a second direction intersecting the first direction, a virtual extension line of the first body portion extending along the first direction intersects with a virtual extension line of the second body portion extending along the second direction within the first display area, and the second body portion of the at least one second signal line is electrically connected to the at least one first pixel circuit to transmit a second drive signal different from the first drive signal to the at least one first pixel circuit.

[0007] For example, in at least one example of the display substrate, the at least one connection wiring extends from the first display area to the second display area along the second direction.

[0008] For example, in at least one example of the display substrate, the first body portion includes a first sub-portion and a second sub-portion separated by the first display area, the first sub-portion and the second sub-portion are electrically connected via the first winding portion, and at least a portion of the first winding portion intersects with a virtual connecting line located between the first sub-portion and the second sub-portion and extending along the first direction.

[0009] For example, in at least one example of the display substrate, the first winding portion is an arcuate wire, a first end of the arcuate wire is connected to an end of the first sub-portion that is close to the second sub-portion, and a second end of the arcuate wire is connected to an end of the second sub-portion that is close to the first sub-portion; or the first winding portion includes a first line segment, a second line segment, and a third line segment that are connected in sequence, and an end of the first line segment that is not connected to the second line segment is connected to an end of the first sub-portion that is close to the second sub-portion, and an end of the third line segment that is not connected to the second line segment is connected to an end of the second sub-portion that is close to the first sub-portion; the second line segment extends along the first direction; and the first line segment and the third line segment extend along a second direction that intersects the first direction.

[0010] For example, in at least one example of the display substrate, the second display area has an inner edge and an outer edge, and the inner edge of the second display area surrounds the first winding portion.

[0011] For example, in at least one example of the display substrate, the at least one first signal line further includes a second winding portion, a first end of the second winding portion electrically connected to the second sub-portion, a second end of the second winding portion electrically connected to a corresponding first pixel circuit, the second winding portion includes a first line portion and a second line portion sequentially connected to each other, an end of the first line portion not connected to the second line portion becomes a first end of the second winding portion, and an end of the second line portion not connected to the first line portion becomes a second end of the second winding portion, the first line portion extends along a second direction intersecting the first direction, the second line portion extends along the first direction and is arranged in parallel with the second sub-portion in the second direction, and during operation, a current in the second line portion flows in a direction opposite to that of the main body portion.

[0012] For example, in at least one example of the display substrate, the display substrate further includes a peripheral region surrounding the display region, and the first line portion is located entirely in the peripheral region and is arranged parallel to the second display region in the first direction.

[0013] For example, in at least one example of the display substrate, the first line portion is located entirely within the second display area, and at least a portion of the first line portion is arranged parallel to the first display area in the first direction.

[0014] For example, in at least one example of the display substrate, the display substrate further includes a peripheral region surrounding the display region, wherein the first line portion includes a first portion, a second portion, and a third portion that are sequentially connected, the first portion of the first line portion is electrically connected to the second sub-portion, the third portion of the first line portion is electrically connected to the second line portion, the first portion of the first line portion is located in the peripheral region and is arranged in parallel with the second display region in the first direction, the second portion of the first line portion extends from the peripheral region to the second display region along the first direction, the third portion of the first line portion is located in the second display region, and a virtual extension line of the third portion of the first line portion extending along the second direction is arranged in parallel with the first display region in the first direction.

[0015] For example, in at least one example of the display substrate, the at least one first signal line further includes a third winding portion, a first end of the third winding portion electrically connected to the first sub-portion, a second end of the third winding portion electrically connected to a corresponding first pixel circuit, and the first pixel circuit connected to the second winding portion is different from the first pixel circuit connected to the third winding portion.

[0016] For example, in at least one example of the display substrate, the third winding portion includes a third line portion and a fourth line portion connected in sequence, one end of the third line portion that is not connected to the fourth line portion becomes a first end of the third winding portion, one end of the fourth line portion that is not connected to the third line portion becomes a second end of the third winding portion, the third line portion extends along the second direction and is arranged in parallel with the first line portion in the first direction, the fourth line portion extends along the first direction and is arranged in parallel with the first sub-portion in the second direction, and during operation, the current in the fourth line portion flows in the same direction as the current in the main body portion.

[0017] For example, in at least one example of the display substrate, the first main body portion, the first winding portion, and the second line portion are located on a first electrode layer of the display substrate, the first line portion is located on a second electrode layer of the display substrate, the first electrode layer and the second electrode layer overlap in the normal direction of the display surface of the display substrate, and the first line portion is electrically connected to the second sub-portion and the second line portion via a first via hole and a second via hole, respectively, in an insulating layer between the first electrode layer and the second electrode layer.

[0018] For example, in at least one example of the display substrate, each of the at least one first pixel circuit includes a thin film transistor, the thin film transistor including a gate and a source / drain, the source / drain being located on the first electrode layer, and the gate being located on the second electrode layer.

[0019] For example, in at least one example of the display substrate, the first winding portion surrounds the first display area and is entirely located in the second display area, the first winding portion includes a fifth line portion, a sixth line portion, and a seventh line portion that are sequentially connected to the first winding portion, the fifth line portion is electrically connected to the first sub-portion, the seventh line portion is electrically connected to the second sub-portion, the sixth line portion extends along the first direction, the fifth line portion and the seventh line portion extend along a second direction that intersects with the first direction, the sixth line portion is arranged in parallel in the first direction with a virtual connecting line that is located between the first sub-portion and the second sub-portion and extends along the first direction, the sixth line portion at least partially overlaps with a first pixel circuit electrically connected to the sixth line portion, and during operation, the current in the sixth line portion flows in the same direction as the current in the main body portion.

[0020] For example, in at least one example of the display substrate, the first winding portion surrounds the first display area and is entirely located in the second display area, and includes an eighth wire portion and a ninth wire portion connected in sequence to the first winding portion, the eighth wire portion is electrically connected to the first body portion and extends along the second direction, the ninth wire portion extends along the first direction and is arranged in parallel with a virtual extension line of the first body portion in the first direction, and during operation, a current in the ninth wire portion flows in the same direction as a current in the body portion, and the ninth wire portion is electrically connected to a first pixel circuit configured to drive the first number of first light-emitting elements arranged in parallel along the first direction in the first display area.

[0021] For example, in at least one example of the display substrate, the second signal line further includes a fourth winding portion, and the fourth winding portion is wired offset from a virtual extension line of the second body portion along the second direction, the second body portion includes a third sub-portion and a fourth sub-portion separated by the first display area, the third sub-portion and the fourth sub-portion are electrically connected via the fourth winding portion, and the fourth winding portion is located between the third sub-portion and the fourth sub-portion and is wired offset from a virtual connection line extending along the second direction.

[0022] For example, in at least one example of the display substrate, each of the at least one first pixel circuit includes a thin film transistor, the thin film transistor includes a gate and a source / drain, the source / drain, the first winding portion and the second signal line are all located on the first electrode layer, and the first body portion and the gate are located on the second electrode layer.

[0023] For example, in at least one example of the display substrate, a portion of the at least one connecting wiring that is in the first display area is a transparent wiring.

[0024] At least one embodiment of the present disclosure further provides a display device comprising any one of the display substrates provided by at least one embodiment of the present disclosure.

[0025] For example, in at least one example of the display substrate, the display device further includes a sensor provided on a non-display side of the display substrate, overlapping the first display area in a direction normal to the display surface of the display substrate, and configured to receive and process optical signals passing through the first display area. [Brief explanation of the drawings]

[0026] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments are briefly introduced below. Obviously, the drawings described below are only related to some embodiments of the present disclosure and do not limit the present disclosure.

[0027] [Figure 1A] FIG. 2 is a schematic cross-sectional view of a display substrate. [Figure 1B] FIG. 1B is a schematic plan view of the display substrate shown in FIG. 1A. [Figure 1C] FIG. 1C is a schematic diagram of a partial region of the display substrate shown in FIG. 1B. [Figure 1D] 1C is a schematic diagram of a part of a first display region and a part of a second display region of the display substrate shown in FIG. 1B. [Figure 2A] 1 is a schematic plan view of a display substrate provided in accordance with at least one embodiment of the present disclosure. [Figure 2B] 2B is a schematic plan view of a first display region and a second display region of the display substrate shown in FIG. 2A. FIG. [Figure 2C] 2C is an example of a first display region and a second display region of the display substrate shown in FIG. 2B. [Figure 2D] FIG. 2D is an enlarged view of a partial region of FIG. 2C. [Figure 2E] 2E is an enlarged view of a partial area of ​​the first display area shown in FIG. 2D. [Figure 2F] 2B is an enlarged view of a partial area of ​​the third display area of ​​the display substrate shown in FIG. 2A. [Figure 3] 1 is a schematic cross-sectional view of a display device provided in accordance with at least one embodiment of the present disclosure. [Figure 4]2B is a first example of the display substrate shown in FIG. 2A. [Figure 5A] 5 is a first schematic diagram showing a first display region, a second display region, and a part of a peripheral region of the display substrate shown in FIG. 4. FIG. [Figure 5B] 5 is a second schematic diagram showing a first display region, a second display region, and a part of a peripheral region of the display substrate shown in FIG. 4. FIG. [Figure 5C] 5 is a third schematic diagram showing a first display region, a second display region, and a part of a peripheral region of the display substrate shown in FIG. 4. FIG. [Figure 5D] 1 shows a schematic diagram of a stack structure of a first light-emitting element and a first pixel circuit for driving the first light-emitting element, provided by at least one embodiment of the present disclosure; [Figure 5E] FIG. 10 shows a schematic diagram of a stack structure of a second pixel unit provided by at least one embodiment of the present disclosure. [Figure 5F] FIG. 10 shows a schematic diagram of a stack structure of a third pixel unit provided by at least one embodiment of the present disclosure. [Figure 5G] FIG. 10 is a schematic diagram of a stacked structure of a second pixel unit, a first wire portion of a second winding portion, and a second sub-portion of a first body portion provided by at least one embodiment of the present disclosure. [Figure 5H] FIG. 10 shows a schematic diagram of another stack structure of a second pixel unit provided by at least one embodiment of the present disclosure. [Figure 5I] 5B is a schematic cross-sectional view taken along line HH' shown in FIG. 5A. [Figure 6] 2B is a second example of the display substrate shown in FIG. 2A. [Figure 7A] 7 is a first schematic diagram showing a first display region, a second display region, and a part of a peripheral region of the display substrate shown in FIG. 6. FIG. [Figure 7B] 7 is a second schematic diagram showing a first display region, a second display region, and a part of a peripheral region of the display substrate shown in FIG. 6. FIG. [Figure 8] 2B is a third example of the display substrate shown in FIG. 2A. [Figure 9A]9 is a first schematic diagram showing a first display region, a second display region, and a part of a peripheral region of the display substrate shown in FIG. 8. FIG. [Figure 9B] 9 is a second schematic diagram showing a first display region, a second display region, and a part of a peripheral region of the display substrate shown in FIG. 8. FIG. [Figure 10] 2B is a fourth example of the display substrate shown in FIG. 2A. [Figure 11] 2B is a fifth example of the display substrate shown in FIG. 2A. [Figure 12A] 12 is a first schematic diagram showing a first display region, a second display region, and a part of a peripheral region of the display substrate shown in FIG. 11. FIG. [Figure 12B] 12 is a second schematic diagram showing a first display region, a second display region, and a part of a peripheral region of the display substrate shown in FIG. 11. FIG. [Figure 12C] FIG. 12C is a schematic plan view corresponding to a partial region of FIG. 12B. [Figure 13A] FIG. 2B is a schematic plan view of a sixth example of the display substrate 01 shown in FIG. 2A. [Figure 13B] 2B is another schematic plan view of the sixth example of the display substrate shown in FIG. 2A. FIG. [Figure 13C] 2B is yet another schematic plan view of the sixth example of the display substrate shown in FIG. 2A. FIG. [Figure 13D] FIG. 13D is a schematic plan view corresponding to the partial region REG_B shown in FIG. 13C. [Figure 14] 2B is a schematic plan view of a seventh example of the display substrate shown in FIG. 2A. FIG. [Figure 15] 2B is a schematic plan view of an eighth example of the display substrate shown in FIG. 2A. FIG. [Figure 16] 2B is another schematic plan view of the eighth example of the display substrate shown in FIG. 2A. FIG. [Figure 17] A pixel circuit provided by at least one embodiment of the present disclosure, and a light-emitting element driven by the pixel electrode. [Figure 18] FIG. 18 is a schematic structural diagram of the 7T1C pixel circuit shown in FIG. [Figure 19] FIG. 2 is a schematic diagram illustrating a structure of a sub-pixel according to an embodiment of the present disclosure. [Figure 20] 1A-1C are schematic diagrams illustrating layouts of particular layers within a subpixel, respectively, according to some embodiments of the present disclosure. [Figure 21] 1A-1C are schematic diagrams illustrating layouts of particular layers within a subpixel, respectively, according to some embodiments of the present disclosure. [Figure 22] 1A-1C are schematic diagrams illustrating layouts of particular layers within a subpixel, respectively, according to some embodiments of the present disclosure. [Figure 23] 1A-1C are schematic diagrams illustrating layouts of particular layers within a subpixel, respectively, according to some embodiments of the present disclosure. [Figure 24] FIG. 24 is a schematic diagram illustrating a stacked layout of the layers shown in FIGS. 20 to 23 in a sub-pixel according to one embodiment of the present disclosure. [Figure 25] FIG. 24 is a schematic diagram illustrating a stacked layout of the layers shown in FIGS. 20 to 23 in a sub-pixel according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0028] In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are not all the embodiments, but are only a part of the embodiments of the present invention. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the protection scope of the present invention.

[0029] Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention belongs. As used in this disclosure, the terms "first," "second," and similar words do not denote any order, quantity, or importance, but are used only to distinguish between different components. Similarly, similar words such as "one," "an," "the," and "the" do not denote a limitation of quantity, but rather denote the presence of at least one. Similar words such as "comprise" or "contain" mean that the element or thing appearing before the word covers the elements or things listed after the word and their equivalents, but does not exclude other elements or things. Similar words such as "connect" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "top," "bottom," "left," "right," and the like are used only to denote relative positions, and if the absolute positions of the objects described change, the relative positions may change accordingly.

[0030] The inventors of the present disclosure have discovered that for a current display substrate equipped with an under-screen sensor (e.g., a camera), in order to increase the transmittance of the display area of ​​the display substrate corresponding to the under-screen sensor (e.g., a camera), the pixel density per unit area (PPI) of the light-emitting elements in the display area corresponding to the under-screen sensor (camera) is smaller than the pixel density per unit area of ​​the light-emitting elements in other display areas of the display substrate. An exemplary description will now be given with reference to Figures 1A and 1B.

[0031] Fig. 1A is a schematic cross-sectional view of a display substrate 500, Fig. 1B is a schematic plan view of the display substrate 500 shown in Fig. 1A, and the display substrate 500 shown in Fig. 1A corresponds to line BB' of the display substrate 10 shown in Fig. 1B. Fig. 1C is a schematic view of a partial region 513 of the display substrate 500 shown in Fig. 1B.

[0032] As shown in FIG. 1A , the display substrate 500 includes a display layer 510 and a sensing layer 520, with the sensing layer 520 located on the non-display side (i.e., the side away from the user) of the display substrate 500. As shown in FIGS. 1A to 1C , the display layer 510 includes a first display region 511 and a second display region 512. The first display region 511 includes a plurality of first pixel units 531 arranged in an array, each including a first light-emitting element and a first pixel circuit. The second display region 512 includes a plurality of second pixel units 532 arranged in an array, each including a second light-emitting element and a second pixel circuit. For example, the plurality of first light-emitting elements and the plurality of second light-emitting elements have the same structure and performance characteristics, and the plurality of first pixel circuits and the plurality of second first pixel circuits have the same structure and performance characteristics.

[0033] As shown in FIG. 1A, the sensing layer 520 includes a sensor 521, which overlaps the first display area 511 in the normal direction of the display surface of the display substrate 500 and is configured to receive and process optical signals passing through the first display area 511.

[0034] As shown in FIG. 1C, in order to reduce the blocking of optical signals incident on the first display area 511 and transmitted toward the sensor 521 by elements within the first display area 511, the distribution density per unit area of ​​the multiple first pixel units 531 in the first display area 511 is smaller than the distribution density per unit area of ​​the multiple second pixel units 532 in the second display area 512, and the distribution density per unit area of ​​the multiple first light-emitting elements in the first display area 511 is smaller than the distribution density per unit area of ​​the multiple second light-emitting elements in the second display area 512.

[0035] The inventors of the present disclosure have further discovered that although the transmittance of the display area corresponding to the under-screen sensor (camera) of the display substrate can be improved to some extent by reducing the distribution density per unit area (PPI) of the first light-emitting elements and increasing the distance between adjacent first light-emitting elements, the effect of improving the transmittance is still limited, and it is difficult to fully meet users' demands for capturing high-quality photos with an under-screen camera.

[0036] 1A to 1C, data cables 541 and gate lines 542 of the display substrate pass through a first display area 511. FIG. 1D is a schematic diagram of a portion of the first display area and a portion of the second display area of ​​the display substrate 500 shown in FIG. 1B. As shown in FIG. 1D, the data cables 541 pass through the first display area 511.

[0037] The inventors of the present disclosure also discovered that the data cables 541 and gate lines 542 passing through the first display area 511 not only block the light entering the first display area 511 and casting towards the sensor 521, but also may cause diffraction, which may result in ghosting in the image output from the sensor, thus further reducing the quality of the image output by the sensor.

[0038] At least one embodiment of the present disclosure provides a display substrate and a display device, the display substrate including a display region, at least one first signal line, and at least one connecting wire, the display region including a first display region and a second display region at least partially surrounding the first display region, the first display region including at least one first light-emitting element, the second display region including at least one first pixel circuit, the at least one first signal line including a first body portion and a first winding portion, the first body portion extending along a first direction, at least a portion of the first winding portion extending along a direction intersecting the first direction, the at least one first signal line electrically connected to the at least one first pixel circuit to transmit a first drive signal to the at least one first pixel circuit, the at least one first pixel circuit electrically connected to the at least one first light-emitting element via a corresponding connecting wire, and each of the at least one first pixel circuits configured to drive the at least one first light-emitting element.

[0039] At least one embodiment of the present disclosure further provides a display device including any one of the display substrates provided by at least one embodiment of the present disclosure, wherein the display substrate and the display device can increase the transmittance of the first display region.

[0040] The following provides a non-limiting description of the display substrate and display device provided by at least one embodiment of the present disclosure through several examples or embodiments. As described below, different features of these specific examples or embodiments can be combined with each other without contradicting each other to obtain new examples or embodiments, and these new examples or embodiments also fall within the protection scope of the present disclosure.

[0041] FIG. 2A is a schematic plan view of a display substrate 01 provided according to at least one embodiment of the present disclosure. As shown in FIG. 2A, the display substrate 01 includes a display area 10 and a peripheral area 14. The display area 10 includes a first display area 11, a second display area 12, and a third display area 13, and the peripheral area 14 surrounds at least a portion (e.g., the entirety) of the third display area 13. For example, as shown in FIG. 2A, the first display area 11, the second display area 12, and the third display area 13 do not overlap with each other. For example, as shown in FIG. 2A, the third display area 13 surrounds at least a portion (e.g., a part) of the second display area 12. For example, as shown in FIG. 2A, the third display area 13 surrounds a part of the second display area 12. Note that in some examples, the display substrate 01 may not include the peripheral area 14.

[0042] 2B is a schematic plan view of the first display region 11 and the second display region 12 of the display substrate 01 shown in FIG. 2A. For example, as shown in FIG. 2A and FIG. 2B, the second display region 12 surrounds at least a portion (e.g., the entirety) of the first display region 11.

[0043] 2A and 2B, the first display area 11 may have a circular shape and the second display area 12 may have a rectangular shape, but the embodiments of the present disclosure are not limited thereto. Also, for example, the first display area 11 and the second display area 12 may both have a rectangular shape or other suitable shape.

[0044] Fig. 2C shows an example of the first display region 11 and the second display region 12 of the display substrate 01 shown in Fig. 2B. Fig. 2D is an enlarged view of the partial region REG1 of Fig. 2C. Fig. 2E is an enlarged view of the partial region REG3 of the first display region 11 shown in Fig. 2D.

[0045] For example, as shown in FIGS. 2C to 2E , the first display region 11 includes a plurality of first light-emitting elements 411. For clarity, the related drawings schematically illustrate the first light-emitting elements 411 using the anode structures 4111 of the first light-emitting elements 411. For example, as shown in FIGS. 2C to 2E , the first display region 11 includes a plurality of first pixel units 41 arranged in an array, each of the plurality of first pixel units 41 including a first number of first light-emitting elements 411 configured to emit light of a second number of colors. For example, as shown in FIGS. 2C to 2E , the anode structures 4111 of different first light-emitting elements 411 in the first number of first light-emitting elements 411 have different shapes. Correspondingly, the different first light-emitting elements 411 in the first number of first light-emitting elements 411 have different shapes.

[0046] For example, as shown in FIGS. 2C to 2E , the first quantity may be four and the second quantity may be three, i.e., each of the plurality of first pixel units 41 includes four first light-emitting elements 411, and the four first light-emitting elements 411 are configured to emit light of three colors (e.g., red, green, and blue). For example, each of the plurality of first pixel units 41 includes four first light-emitting elements 411 (e.g., GGRB, i.e., two green light-emitting elements, one red light-emitting element, and one blue light-emitting element), and the four light-emitting elements (e.g., GGRB) are configured to emit green, green, red, and blue light, respectively. Furthermore, for example, when each of the plurality of first pixel units 41 includes four first light-emitting elements 411, the arrangement of the four first light-emitting elements 411 is not limited to GGRB, and the arrangement of the four first light-emitting elements 411 may also be RGBG or other appropriate arrangement. It should be noted that in some examples, both the first quantity and the second quantity may be three, in which case each of the plurality of first pixel units 41 includes three first light-emitting elements 411 (eg, RGB).

[0047] For example, as shown in FIGS. 2C and 2D , the second display area 12 includes a plurality of first pixel circuits 412. For example, the plurality of first pixel circuits 412 are configured to drive a plurality of first light-emitting elements 411 in a one-to-one correspondence. For example, the white rectangular frames shown in FIGS. 2C and 2D represent first pixel driving units, and each first pixel driving unit includes a first number of pixel circuits. For example, in the second display area 12 shown in FIGS. 2C and 2D , the ratio of the number of first pixel driving units to the number of first pixel units 41 is 3, and accordingly, for every three first pixel driving units, only the pixel circuit of one first pixel driving unit is used to drive the first light-emitting element 411. Therefore, the pixel circuit included in the first pixel driving unit for driving the first light-emitting element 411 is referred to as the first pixel circuit 412, and the pixel circuit included in the first pixel driving unit that does not drive the first light-emitting element 411 is referred to as a dummy pixel circuit. For example, the first pixel circuits 412 and the dummy pixel circuits have the same circuit structure. For example, each of the first number of first pixel circuits 412 included in the first pixel driving unit for driving the first light-emitting elements 411 is configured to drive the first number of first light-emitting elements 411 of a corresponding one of the plurality of first pixel units 41 in a one-to-one correspondence. For example, as shown in FIGS. 2C to 2E , the plurality of first light-emitting elements 411 are arranged in an array, and the plurality of first pixel circuits 412 are arranged in the array. For clarity, the specific structures of the first light-emitting elements 411 and the first pixel circuits 412 are described in the example shown in FIG. 5D and are omitted here.

[0048] For example, as shown in FIGS. 2C and 2D , the second display area 12 further includes a plurality of second pixel units 42, each of which includes a second light-emitting element 421 (e.g., a first number of second light-emitting elements 421) and a second pixel circuit 422 (e.g., a first number of second pixel circuits 422) for driving the second light-emitting element 421. For example, as shown in FIGS. 2C and 2D , each of the plurality of second pixel units 42 includes a second light-emitting element 421 and a second pixel circuit 422 (i.e., a rectangular frame at least partially overlapping the second light-emitting element 421) that at least partially overlap in the normal direction of the display surface of the display substrate 01 (e.g., a direction perpendicular to the display substrate 01). For example, as shown in FIGS. 2C and 2D , the plurality of second pixel units 42 are arranged in an array. For clarity, the specific structure of the second pixel unit 42 will be described in the example shown in FIG. 5E and will not be described here. It should be noted that the rectangular frame shown in FIG. 2D is only used to explain the second pixel circuit 422, and does not indicate the specific shape of the second pixel circuit 422 or the specific boundary of the second pixel circuit 422.

[0049] For example, the first number of second light-emitting elements 421 included in the second pixel unit 42 and the first number of first light-emitting elements 411 included in the first pixel unit 41 have the same arrangement method and structure. For example, the first number of second pixel circuits 422 included in the second pixel unit 42 and the first number of first pixel circuits 412 included in the first pixel driving unit for driving the first light-emitting elements 411 have the same arrangement method and structure.

[0050] FIG. 2F is an enlarged view of a partial region REG2 of the third display region 13 of the display substrate 01 shown in FIG. 2A. For example, as shown in FIG. 2F, the third display region 13 includes a plurality of third pixel units 43, each of which includes a third light-emitting element 431 (e.g., a first number of third light-emitting elements 431) and a third pixel circuit 432 (e.g., a first number of third pixel circuits 432) for driving the third light-emitting element 431. For example, as shown in FIG. 2F, each of the plurality of third pixel units 43 includes a third light-emitting element 431 and a third pixel circuit 432 that at least partially overlap in the normal direction of the display surface of the display substrate 01. For clarity, the specific structure of the third pixel unit 43 is described in the example shown in FIG. 5F and is omitted here. Note that the rectangular frame shown in FIG. 2F is used only to illustrate the third pixel circuit 432 and does not indicate the specific shape or boundary of the third pixel circuit 432.

[0051] For example, the first number of third light-emitting elements 431 included in the third pixel unit 43 have the same arrangement and structure as the first number of first light-emitting elements 411 included in the first pixel unit 41. For example, the first number of third pixel circuits 432 included in the third pixel unit 43 have the same arrangement and structure as the first number of first pixel circuits 412 included in the first pixel driving unit for driving the first light-emitting elements 411.

[0052] 2D and 2F, the distribution density per unit area of ​​the plurality of first light-emitting elements 411 in the first display region 11 is smaller than the distribution density per unit area of ​​the plurality of third light-emitting elements 431 in the second display region 12, and the distribution density per unit area of ​​the plurality of second light-emitting elements 421 in the second display region 12 is smaller than the distribution density per unit area of ​​the plurality of third light-emitting elements 431 in the second display region 12. For example, the first display region 11 and the second display region 12 may be referred to as low-resolution regions of the display substrate 01. For example, as shown in FIG. 2D, the distribution density per unit area of ​​the plurality of first light-emitting elements 411 in the first display region 11 is equal to the distribution density per unit area of ​​the plurality of second light-emitting elements 421 in the second display region 12.

[0053] Fig. 3 is a schematic cross-sectional view of a display device 03 provided according to at least one embodiment of the present disclosure. As shown in Fig. 3, the display device 03 includes the display substrate 01 shown in Fig. 2A. The schematic cross-sectional view of the display device 03 shown in Fig. 3 corresponds to the line AA' shown in Fig. 2A. As shown in Fig. 3, the display device 03 further includes a sensor 02.

[0054] For example, the display substrate 01 includes a display side and a non-display side opposite each other, and the display substrate 01 is configured so that a display operation is performed on the display side of the display substrate 01, i.e., the display side of the display substrate 01 is the light-emitting side of the display substrate 01 and faces the user. The display side and the non-display side are arranged opposite each other in the normal direction of the display surface of the display substrate 01.

[0055] 3, the sensor 02 and the first display region 11 overlap in the normal direction of the display surface of the display substrate 01 (for example, a direction perpendicular to the display substrate 01), and are configured to receive and process optical signals passing through the first display region 11, which may be visible light, infrared light, etc. For example, no pixel circuit is arranged in the first display region 11, in which case the transmittance of the first display region 11 can be increased.

[0056] For example, by arranging a plurality of first pixel circuits 412 configured to drive a plurality of first light-emitting elements 411 in one-to-one correspondence in the second display region 12 and arranging the sensor 02 and the first display region 11 so as to overlap in the normal direction of the display surface of the display substrate 01, it is possible to reduce the blocking of optical signals incident on the first display region 11 and transmitted toward the sensor 02 by elements in the first display region 11, thereby improving the signal-to-noise ratio of the image output by the sensor 02. For example, the first display region 11 may be referred to as a high light transmission region of a low-resolution region of the display substrate 01.

[0057] For example, the sensor 02 may be an image sensor for collecting an image of the external environment facing the light-collecting surface of the sensor 02, such as a CMOS image sensor or a CCD image sensor, and may also be an infrared sensor, a distance sensor, or the like. For example, if the display device 03 is a mobile terminal such as a mobile phone or a notebook, the sensor 02 may be implemented as a camera of the mobile terminal such as a mobile phone or a notebook, and may include an optical device for modulating the light path, such as a lens, a mirror, or an optical waveguide, as necessary. For example, the sensor 02 may include photosensitive pixels arranged in an array. For example, each photosensitive pixel may include a photosensitive detector (e.g., a photodiode, a phototransistor) and a switching transistor (e.g., a switching transistor). For example, the photodiode may convert an incident optical signal into an electrical signal, and the switching transistor may be electrically connected to the photodiode to control whether the photodiode is in a state to collect the optical signal and the time for collecting the light.

[0058] In some examples, in the first display region 11, only the anode of the first light-emitting element 411 is opaque, i.e., the wiring used to drive the first light-emitting element 411 bypasses the first display region 11 or is set as transparent wiring. In this case, not only can the transmittance of the first display region 11 be further increased, but diffraction by each element in the first display region 11 can also be reduced. An illustrative description will be given below with reference to the example shown in FIG. 4.

[0059] Fig. 4 is a first example of the display substrate 01 shown in Fig. 2A. Fig. 5A is a first schematic diagram showing a first display region 11, a second display region 12, and a portion of the peripheral region 14 of the display substrate 01 shown in Fig. 4.

[0060] As shown in Figures 4 and 5A, the display substrate 01 includes at least one first signal line 20, at least one second signal line 30, and at least one connecting wire 60. For clarity, the sizes of the first display area 11 and the second display area 12 are enlarged in Figure 4, and the size of the third display area 13 is reduced in the first direction D1. For ease of explanation, Figure 4 also shows a data driving circuit.

[0061] In one example, the at least one first signal line includes a plurality of first signal lines, and the at least one first pixel circuit includes a plurality of first pixel circuits; in another example, the at least one first signal line includes one first signal line, and the at least one first pixel circuit includes a plurality of first pixel circuits; and in yet another example, the at least one first signal line includes a plurality of first signal lines, and the at least one first pixel circuit includes one first pixel circuit.

[0062] For example, as shown in Figures 4 and 5A, the first display area 11 includes at least one first light-emitting element 411, the second display area 12 includes at least one first pixel circuit 412, at least one connection wiring 60 is electrically connected to the at least one first pixel circuit 412 and the at least one first light-emitting element 411 in a one-to-one correspondence, and the at least one first pixel circuit 412 is configured to drive the at least one first light-emitting element 411 in a one-to-one correspondence.

[0063] 4 and 5A, at least one connection wiring 60 extends along the second direction D2 from the first display region 11 to the second display region 12. Note that, as shown in FIG. 5A, a line segment connected between a first number of first light-emitting elements 411 included in each first pixel unit 41 and a first number of first pixel circuits 412 included in each first pixel driving unit for driving the first light-emitting elements 411 represents a first number (e.g., four) of connection wirings 60.

[0064] For example, as shown in Figures 4 and 5A, at least one first pixel circuit 412 is arranged in parallel with at least one first light-emitting element 411 driven in one-to-one correspondence by the at least one first pixel circuit 412 in a second direction D2 that intersects (e.g., is perpendicular to) the first direction D1.

[0065] For example, a portion of the at least one connecting wire 60 located in the first display area 11 may be a transparent wire. In this case, the transmittance of the first display area 11 and the signal-to-noise ratio of the image output by the sensor 02 may be further improved, and diffraction caused by opaque wires may be avoided, thereby further improving the image quality of the image output by the sensor. For example, the at least one connecting wire 60 may be made entirely of a transparent conductive material. For example, the transparent conductive material may be selected from transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0066] In some examples, the connecting wiring 60 may include a first portion in the first display area and a second portion in the second display area, which are electrically connected to each other, in order to reduce the resistance of the connecting wiring 60 and increase the signal transmission speed of the connecting wiring 60. The first portion includes a first light-transmitting wiring layer made of a transparent conductive material, and the second portion includes a metal wiring layer made of a metal material, which is omitted here.

[0067] For example, as shown in Figures 4 and 5A, at least one connecting wiring 60 includes multiple connecting wirings 60, at least one first light-emitting element 411 includes multiple first light-emitting elements 411, and at least one of the multiple connecting wirings 60 has a length greater than twice the distance between two adjacent first pixel units 41.

[0068] For example, since the resistances of the multiple connection wires 60 are equal to each other, the uniformity of the drive current can be improved (for example, when the data signals are equal to each other). For example, as shown in Figures 4 and 5A, since the lengths of the multiple connection wires 60 are equal to each other, when the multiple connection wires 60 are made of the same material, the resistances of the multiple connection wires 60 are equal to each other.

[0069] 4 and 5A, at least one first signal line 20 includes a first body portion 21 and a first winding portion 22, the first body portion 21 extending along a first direction D1, and the first winding portion 22 being wired so as to be offset from an imaginary extension line 213 of the first body portion 21 along the first direction D1. For example, at least a portion of the first winding portion 22 extends along a direction intersecting the first direction D1. For example, at least a portion of the first winding portion 22 extends along a direction perpendicular to the first direction D1.

[0070] 4 , at least one second signal line 30 includes a second body portion 32, which extends along the second direction D2, and an imaginary extension line of the first body portion 21 along the first direction D1 and an imaginary extension line of the second body portion 32 along the second direction D2 intersect within the first display area 11. In some examples, the second signal line 30 also includes a winding portion (e.g., a winding portion that surrounds the first display area 11), thereby allowing the second signal line to still simultaneously drive pixel circuits located on both sides of the first display area 11 in the second direction D2 and in the same row without passing through the first display area, which is omitted here.

[0071] Although the first and second signal lines are shown to drive corresponding pixel circuits, the first and second signal lines intersect at the locations of the pixel circuits they drive, but the embodiments of the present disclosure are not limited thereto. For example, the first and second signal lines may be closely adjacent to the pixel circuits driven by the first and second signal lines but may not intersect at the locations of the pixel circuits, and corresponding wiring may be used to electrically connect the pixel circuits to the corresponding first and second signal lines.

[0072] For example, as shown in FIG. 4, at least one first signal line 20 is electrically connected to at least one first pixel circuit 412 to transmit a first drive signal to the at least one first pixel circuit 412, and the second body portion 32 of at least one second signal line 30 is electrically connected to at least one first pixel circuit 412 to transmit a second drive signal different from the first drive signal to the at least one first pixel circuit 412.

[0073] For example, as shown in FIG. 4, at least one first signal line 20 is electrically connected to the data driving circuit 50 to receive a first driving signal from the data driving circuit 50, i.e., the first signal line 20 is a data cable, and the first driving signal is a data signal.

[0074] For example, as shown in FIG. 4, the first direction D1 and the second direction D2 are the column direction and the row direction of the display substrate 01, respectively, the first signal line 20 and the second signal line 30 are the data cable and the gate line of the display substrate 01, respectively, and the first driving signal and the second driving signal are the data signal and the gate scanning signal, respectively.

[0075] 4 and 5A, at least one first signal line 20 is arranged to drive a first light-emitting element 411 and a third light-emitting element 431 arranged in parallel along the first direction D1, i.e., the first light-emitting element 411 and the third light-emitting element 431 driven by the same first signal line 20 are provided in the same column of the display substrate 01. For example, at least one first signal line 20 is arranged to drive the first light-emitting element 411, the second light-emitting element 421, and the third light-emitting element 431 arranged in parallel along the first direction D1, i.e., the first light-emitting element 411, the second light-emitting element 421, and the third light-emitting element 431 driven by the same first signal line 20 are located in the same column of the display area of ​​the display substrate 01.

[0076] In addition, the display substrate further includes a third signal line (e.g., a data cable) and a fourth signal line (e.g., a gate line), where the third signal line extends along a first direction D1 and the fourth signal line extends along a second direction D2, and the third signal line and the fourth signal line are both straight line segments and do not overlap with (i.e., do not pass through) the first display area 11.

[0077] 4 and 5A, the first body portion 21 includes a first sub-portion 211 and a second sub-portion 212 that are separated by the first display area 11 (i.e., the first sub-portion 211 and the second sub-portion 212 are located on either side of the first display area 11 in the first direction D1), and the first sub-portion 211 and the second sub-portion 212 are electrically connected via a first winding portion 22. The first winding portion 22 is wired offset from a virtual connection line that is located between the first sub-portion 211 and the second sub-portion 212 and extends along the first direction D1 (i.e., a virtual extension line 213 of the first body portion 21 along the first direction D1). For example, both the first sub-portion 211 and the second sub-portion 212 are straight line segments.

[0078] For example, as shown in Figures 4 and 5A, by wiring the first winding portion 22 away from the virtual extension line along the first direction D1 of the first main body portion 21, it is possible to prevent the first signal line 20 from overlapping with the first light-emitting element 411 driven by the first signal line 20 and its surrounding area, and in this way, it is possible to increase the transmittance of the display area 10 near the first light-emitting element 411 driven by the first signal line 20.

[0079] 4 and 5A, the second display region 12 has an inner edge 121 and an outer edge 122. For example, as shown in Figures 4 and 5A, the inner edge 121 of the second display region 12 is formed by the boundary of the pixel circuits (e.g., the first pixel circuit 412 and the second pixel circuit 422) located innermost in the second display region 12 that are close to the first display region 11, i.e., the inner edge 121 of the second display region 12 is formed by the boundary of the pixel circuits located in the second display region 12 and closest to the first display region 11 that are close to the first display region 11.

[0080] For example, as shown in Figures 4 and 5A, the inner edge 121 of the second display area 12 surrounds the first winding portion 22, and in this case, the first winding portion 22 can be prevented from being short-circuited with the pixel circuits (e.g., the first pixel circuit 412 and the second pixel circuit 422) located in the second display area 12.

[0081] In a first example, the inner edge 121 of the second display area 12 surrounds the first winding portion 22, and the first winding portion 22 surrounds the first display area 11. In this case, not only can the first winding portion 22 avoid blocking of the optical signal incident on the first display area 11 and transmitted toward the sensor 02, but also the first winding portion 22 can avoid blocking of the light emitted from the first light-emitting element 411 located in the first display area 11, thereby improving the signal-to-noise ratio of the image output by the sensor 02 and avoiding diffraction by the first winding portion 22, and also improving the display quality of the first display area 11.

[0082] In a second example, the inner edge 121 of the second display area 12 surrounds the first winding portion 22, and the first winding portion 22 surrounds the effective boundary of the first display area 11. In this case, it is possible to avoid shading by the first winding portion 22 of optical signals that enter the effective boundary of the first display area 11 and are transmitted toward the sensor 02, thereby improving the signal-to-noise ratio of the image output by the sensor 02 and the display quality of the first display area 11. For example, the effective boundary of the first display area 11 is formed by the outer boundary of the first light-emitting element 411 that is located at the outermost side of the first display area 11. In this case, it is possible to avoid shading by the first winding portion 22 of light emitted from the first light-emitting element 411 in the first display area 11, thereby improving the display quality of the first display area 11. Also, for example, the effective boundary of the first display area 11 is configured from the outer boundary of the first light-emitting element 411 located in the first display area 11 and located on the second outer side (i.e., the outermost light-emitting element among the remaining first light-emitting elements 411 after removing the first light-emitting element 411 located on the outermost side of the first display area 11), in which case the first winding section 22 can at least partially overlap with the first light-emitting element 411 located on the outermost side of the first display area 11, thereby increasing the wiring space for the first winding section 22 while slightly reducing the effective area of ​​the first display area 11.

[0083] 5A , the first display area 11 has a rectangular shape, and the first winding portion 22 includes a first line segment 221, a second line segment 222, and a third line segment 223 that are connected in sequence, where the end of the first line segment 221 that is not connected to the second line segment 222 is connected to the end of the first sub-portion 211 that is closer to the second sub-portion 212, the end of the third line segment 223 that is not connected to the second line segment 222 is connected to the end of the second sub-portion 212 that is closer to the first sub-portion 211, the second line segment 222 extends along a first direction D1, and the first line segment 221 and the third line segment 223 extend along a second direction D2 that intersects with the first direction D1. For example, the first line segment 221, the second line segment 222, and the third line segment 223 are all straight line segments.

[0084] For example, as shown in Figures 4 and 5A, in the second direction D2, the second line segment 222 can be located between the pixel circuit located at the innermost side of the second display area 12 (i.e., the side closest to the first display area 11) and the pixel circuit located at the outermost side of the first display area 11.

[0085] For example, as shown in FIGS. 4 and 5A, the display substrate 01 may further include a second winding portion 23. For example, at least a portion of the second winding portion 23 is wired along a direction intersecting (e.g., perpendicular to) the first direction D1. For example, a first end of the second winding portion 23 is electrically connected to the second sub-portion 212, and a second end of the second winding portion 23 is electrically connected to a corresponding first pixel circuit 412. For example, as shown in FIGS. 4 and 5A, the second end of the second winding portion 23 may be electrically connected to a first pixel circuit 412 in the same column (e.g., a first pixel circuit 412 in the same column that is directly adjacent to the second wire portion 232 of the second winding portion 23).

[0086] For example, as shown in FIGS. 4 and 5A, the second winding portion 23 includes a first wire portion 231 and a second wire portion 232 connected in sequence. The end of the first wire portion 231 that is not connected to the second wire portion 232 becomes the first end of the second winding portion 23, and the end of the second wire portion 232 that is not connected to the first wire portion 231 becomes the second end of the second winding portion 23. The first wire portion 231 extends along the second direction D2, and the second wire portion 232 extends along the first direction D1 and is arranged in parallel with the second sub-portion 212 in the second direction D2. For example, the second wire portion 232 is a straight segment. For example, the first wire portion 231 may be a straight segment. Alternatively, for example, the first wire portion 231 may have a curved structure and extend as a whole along the second direction D2.

[0087] For example, by including the second winding portion 23 in the first signal line 20, the same first signal line 20 can be used to connect pixel circuits in different columns for driving the first light-emitting element 411 and the third light-emitting element 431 in the same column, respectively. In this case, the data signal transmitted by the data drive circuit 50 can directly correspond to the position of the light-emitting element. Therefore, there is no need to change the algorithm for transmitting the data signal or the settings of the data drive circuit 50, and there is no need to install a separate data drive circuit on the data cable having the winding portion. As a result, the amount of calculation of the data drive circuit 50 or the associated controller and processor can be reduced. For example, by including the second winding portion 23 in the first signal line 20, there is no need to adjust the first signal line providing a data signal to a first pixel circuit configured to drive a first light-emitting element from a first signal line in the same column of the first light-emitting element (the portion of the first signal line in the third display region is in the same column as the first light-emitting element) to a first signal line in the same column of the first pixel circuit (the portion of the first signal line in the third display region is in the same column as the first pixel circuit).

[0088] For example, during operation, the current in the second line portion 232 flows in the opposite direction to the current in the main body portion 21. For example, the current in the first main body portion 21 flows from the lower side of the display substrate 01 (the side where the data driving circuit 50 is provided) to the upper side of the display substrate 01, and the current in the second line portion 232 flows from the upper side of the display substrate 01 to the lower side of the display substrate 01.

[0089] Figure 5B is a second schematic diagram showing a portion of the first display region 11, the second display region 12, and the peripheral region 14 of the display substrate 01 shown in Figure 4, and Figure 5C is a third schematic diagram showing a portion of the first display region 11, the second display region 12, and the peripheral region 14 of the display substrate 01 shown in Figure 4. Figure 5B is the upper half of Figure 5C.

[0090] Figure 5C is similar to Figure 5A, and the difference between Figure 5C and Figure 5A is that Figure 5C shows more first light-emitting elements 411, connecting wiring 60, first pixel circuits 412, first signal lines 20, second light-emitting elements 421 and second pixel circuits 422, and Figure 5C also shows a fifth signal line 71 (e.g., a data cable) electrically connected to the second pixel circuit 422.

[0091] 5B and 5C, the fifth signal line 71 also has a winding portion. For example, the fifth signal line 71 also has a winding portion that surrounds the effective boundary of the first display area 11, and the inner edge of the second display area 12 surrounds the winding portion of the fifth signal line 71.

[0092] For example, as shown in Figures 5A to 5C, the display substrate 01 includes a plurality of first signal lines 20, and a plurality of first line portions 231 included in the plurality of first signal lines 20 are arranged in parallel in the first direction D1 (i.e., at least partially overlapping in the first direction D1).

[0093] For example, as shown in Figures 5A to 5C, in the second direction D2, the lengths of the multiple first line portions 231 included in the multiple first signal lines 20 are equal to each other, and as a result, the uniformity of the driving currents of the first line portions 231 can be further improved (for example, when the data signals are equal to each other).

[0094] For example, the first main body portion 21, the first winding portion 22 and the second wire portion 232 are located on the first electrode layer of the display substrate 01, the first wire portion 231 is located on the second electrode layer of the display substrate 01, the first electrode layer and the second electrode layer overlap in the normal direction of the display surface of the display substrate 01, and the first wire portion 231 is electrically connected to the second sub-portion 212 and the second wire portion 232 via the first via hole and the second via hole in the insulating layer between the first electrode layer and the second electrode layer, respectively.

[0095] For example, it is possible to avoid short-circuiting the first wire portion 231 of the second winding portion 23 of each first signal line 20 with other portions of each first signal line 20 (e.g., the second wire portion 232 and the second sub-portion 212), and the first wire portion 231 of the second winding portion 23 of each first signal line 20 with other first signal lines 20.

[0096] For example, the first electrode layer and the second electrode layer are both made of a metal material, which may be selected from silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), an aluminum alloy, or other suitable materials.

[0097] Hereinafter, with reference to Figures 5D to 5G, an illustrative description will be given of the specific structures of the first light-emitting element 411, the first pixel circuit 412, the second pixel unit 42, and the third pixel unit 43, as well as the relationship between each part of the first signal line 20 and each component of the thin-film transistor of the pixel circuit.

[0098] 5D shows a schematic diagram of a stacked structure of a first light-emitting element 411 and a first pixel circuit 412 for driving the first light-emitting element 411 provided by at least one embodiment of the present disclosure. For example, the first pixel circuit 412 includes structures such as a thin film transistor 412T and a storage capacitor 412C. The first light-emitting element 411 includes a first anode structure 4111, a first cathode structure 4113, and a first light-emitting layer 4112 between the first anode structure 4111 and the first cathode structure 4113. The first anode structure 4111 is electrically connected to the thin film transistor 412T included in the first pixel circuit 412 through a via hole. For example, the first anode structure 4111 may include multiple anode sub-layers, such as an ITO / Ag / ITO three-layer structure (not shown). The embodiments of the present disclosure are not limited to a specific form of the first anode structure 4111. For example, the first cathode structure 4113 may be a structure formed on the entire surface of the display substrate 01, and the first cathode structure 4113 may include a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), etc. For example, the first cathode structure 4113 may be formed as a very thin layer, so that the first cathode structure 4113 has good light transmittance.

[0099] For example, the thin film transistor 412T includes structures such as an active layer 4121, a gate 4122, a source electrode, and a drain electrode (i.e., a source 4123 and a drain 4124), and the storage capacitor 412C includes a first electrode plate 4125 and a second electrode plate 4126. For example, the active layer 4121 is disposed on the base substrate 74, a first gate insulating layer 741 is disposed on one side of the active layer 4121 away from the base substrate 74, the gate 4122 and the first electrode plate 4125 are disposed on the same layer and are located on one side of the first gate insulating layer 741 away from the base substrate 74, a second gate insulating layer 742 is disposed on one side of the gate 4122 and the first electrode plate 4125 away from the base substrate 74, and the second electrode plate 4126 is disposed on one side of the second gate insulating layer 742 away from the base substrate 74. An interlayer insulating layer 743 is provided on one side of the second electrode plate 4126 away from the base substrate 74, and a source electrode and a drain electrode are provided on one side of the interlayer insulating layer 743 away from the base substrate 74 and are electrically connected to the active layer 4121 through via holes located in the first gate insulating layer 741, the second gate insulating layer 742 and the interlayer insulating layer 743. A planarizing layer 744 for planarizing the first pixel circuit 412 is provided on one side of the source electrode and the drain electrode away from the base substrate 74.

[0100] For example, the planarization layer 744 has a via hole, and the first anode structure 4111 is electrically connected to the source 4123 or the drain 4124 of the thin film transistor 412T through the via hole in the planarization layer 744 .

[0101] For example, the first display region 11 further includes a transparent support layer 78 positioned on the base substrate 74, and the first light emitting element 11 is provided on one side of the transparent support layer 78 away from the base substrate 74. Therefore, the first light emitting element 411 in the first display region 11 is at approximately the same height as the second light emitting element 421 in the second display region 12 and the third light emitting element 431 in the third display region 13 relative to the base substrate 74, thereby improving the display effect of the display substrate.

[0102] 5E shows a schematic diagram of a stacked structure of a second pixel unit 42 provided by at least one embodiment of the present disclosure. As shown in FIG. 5E, the second pixel unit 42 includes a second light-emitting element 421 and a second pixel circuit 422 that drives the second light-emitting element 421. For example, the second pixel circuit 422 includes structures such as a thin film transistor 422T and a storage capacitor 422C. The second light-emitting element 421 includes a second anode structure 4211, a second cathode structure 4213, and a second light-emitting layer 4212 located between the second anode structure 4211 and the second cathode structure 4213. The second anode structure 4211 is electrically connected to the thin film transistor 422T included in the second pixel circuit 422 through a via hole 744A. For example, the second anode structure 4211 may include multiple anode sub-layers, such as an ITO / Ag / ITO three-layer structure (not shown), and the embodiments of the present disclosure are not limited to a specific form of the second anode structure 4211.

[0103] For example, the thin film transistor 422T includes structures such as an active layer 4221, a gate 4222, a source electrode, and a drain electrode (i.e., a source 4223 and a drain 4224), and the storage capacitor 422C includes a first electrode plate 4225 and a second electrode plate 4226. For example, the active layer 4221 is disposed on a base substrate 74, a first gate insulating layer 741 is disposed on one side of the active layer 4221 away from the base substrate 74, a gate 4222 and the first electrode plate 4225 are disposed on the same layer and on one side of the first gate insulating layer 741 away from the base substrate 74, a second gate insulating layer 742 is disposed on one side of the gate 4222 and the first electrode plate 4225 away from the base substrate 74, and a second electrode plate 4226 is disposed on one side of the second gate insulating layer 742 away from the base substrate 74. An interlayer insulating layer 743 is provided on one side of the second electrode plate 4226 away from the base substrate 74, and a source electrode and a drain electrode are provided on one side of the interlayer insulating layer 743 away from the base substrate 74 and are electrically connected to the active layer 4221 through via holes located in the first gate insulating layer 741, the second gate insulating layer 742, and the interlayer insulating layer 743. A planarization layer 744 for planarizing the second pixel circuit 422 is provided on one side of the source electrode and the drain electrode away from the base substrate 74.

[0104] For example, the planarization layer 744 has a via hole 744A, and the second anode structure 4211 is electrically connected to the source 4223 or the drain 4224 of the thin film transistor 422T through the via hole 744A in the planarization layer 744.

[0105] For clarity, FIG. 5E shows only one second light-emitting element 421 and one second pixel circuit 422 included in the second pixel unit 42, and only one thin film transistor 422T and one storage capacitor 422C included in the second pixel circuit 422, but the embodiments of the present disclosure are not limited thereto.

[0106] For example, FIG. 5F shows a schematic diagram of a stacked structure of a third pixel unit 43 provided by at least one embodiment of the present disclosure. As shown in FIG. 5F, each third sub-pixel includes a third light-emitting element 431 and a third pixel circuit 432 electrically connected to the third light-emitting element, and the third pixel circuit 432 is configured to drive the third light-emitting element 431. The third light-emitting element 431 includes a third anode structure 4311, a third cathode structure 4313, and a third light-emitting layer 4312 located between the third anode structure 4311 and the third cathode structure 4313, and the third anode structure 4311 is electrically connected to the third pixel circuit 432 through a via hole. For example, the third anode structure 4311 may include multiple anode sub-layers, such as an ITO / Ag / ITO three-layer structure (not shown), although the embodiments of the present disclosure are not limited to a specific form of the third anode structure 4311.

[0107] For example, the third pixel circuit 432 includes structures such as a thin film transistor 432T and a storage capacitor 432C. For example, the thin film transistor 432T includes structures such as an active layer 4321, a gate 4322, a source electrode and a drain electrode (i.e., a source 4323 and a drain 4324), and the storage capacitor 432C includes a first electrode plate 4325 and a second electrode plate 4326. For example, the active layer 4321 is disposed on a base substrate 74, a first gate insulating layer 741 is disposed on one side of the active layer 4321 away from the base substrate 74, the gate 4322 and the first electrode plate 4325 are in the same layer and are disposed on one side of the first gate insulating layer 741 away from the base substrate 74, a second gate insulating layer 742 is disposed on one side of the gate 4322 and the first electrode plate 4325 away from the base substrate 74, and the second electrode plate 4326 is disposed on one side of the second gate insulating layer 742 away from the base substrate 74. An interlayer insulating layer 743 is provided on one side of the second electrode plate 4326 away from the base substrate 74, and a source electrode and a drain electrode are provided on one side of the interlayer insulating layer 743 away from the base substrate 74 and are electrically connected to the active layer 4321 through via holes in the first gate insulating layer 741, the second gate insulating layer 742 and the interlayer insulating layer 743. A planarizing layer 744 for planarizing the third pixel circuit 432 is provided on one side of the source electrode and the drain electrode away from the base substrate 74.

[0108] For example, a via hole 744B is provided in the planarization layer 744, and the third anode structure 4311 is electrically connected to the source 4323 or the drain 4324 of the thin film transistor 432T through the via hole 744B in the insulating layer 745.

[0109] For clarity, FIG. 5F shows only one third light-emitting element 431 and one third pixel circuit 432 included in the third pixel unit 43, and only one thin film transistor 432T and one storage capacitor 432C included in the third pixel circuit 432, but the embodiments of the present disclosure are not limited thereto.

[0110] For example, the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 are provided in the same layer, and therefore can be formed by the same patterning process in the manufacturing process. For example, the first gate insulating layer 741, the second gate insulating layer 742, the interlayer insulating layer 743, and the planarizing layer 744 are provided in the same layer in the first display region 11, the second display region 12, and the third display region 13, and in some embodiments, are integrally connected (i.e., are integrally formed and connected to each other), and therefore are denoted by the same reference numerals in the drawings.

[0111] For example, in some embodiments, the display substrate further includes structures such as a pixel definition layer 746 and an encapsulation layer 747, where, for example, the pixel definition layer 746 is provided on the first anode structure and includes a plurality of openings to define different pixels or sub-pixels, and the first light-emitting layer is formed in the openings of the pixel definition layer 746. For example, the encapsulation layer 747 can include a single-layer or multi-layer encapsulation structure, where the multi-layer encapsulation structure includes, for example, a stacked structure of an inorganic encapsulation layer and an organic encapsulation layer, thereby improving the sealing effect of the display substrate.

[0112] For example, the pixel definition layers 746 in the first display area 11, the second display area 12 and the third display area 13 are provided in the same layer, and the sealing layers 747 in the first display area 11, the second display area 12 and the third display area 13 are provided in the same layer and, in some embodiments, are integrally connected, and therefore the same reference numerals are used in the accompanying drawings.

[0113] For example, in each embodiment of the present disclosure, the base substrate 74 may be a glass substrate, a quartz substrate, a metal substrate, a resin substrate, or the like, and may be a rigid substrate or a flexible substrate, although the embodiments of the present disclosure are not limited thereto.

[0114] For example, the first gate insulating layer 741, the second gate insulating layer 742, the interlayer insulating layer 743 and the planarizing layer 744, the insulating layer 745, the pixel defining layer 746, the encapsulating layer 747, and the insulating layer 748 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin. The embodiments of the present disclosure do not particularly limit the materials of the above functional layers.

[0115] For example, the material of the active layer 4121 / 4221 / 4321 can include a semiconductor material such as polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide). For example, portions of the active layer 4121 / 4221 / 4321 can be made conductive by a conduction process such as doping to provide higher electrical conductivity.

[0116] For example, in each of the above examples, the materials of the gate 4122 / 4222 / 4322, the first plate 4125 / 4225 / 4325 and the second plate 4126 / 4226 / 4326 can include metal materials or alloy materials such as molybdenum, aluminum, and titanium.

[0117] For example, the material of the source 4123 / 4223 / 4323 and the drain 4124 / 4224 / 4324 can include a metal material or an alloy material, such as a metal single layer or multilayer structure formed of molybdenum, aluminum, and titanium, for example, the multilayer structure is a multilayer metal stack, such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti).

[0118] For example, the display substrate provided by the embodiments of the present disclosure may be a display substrate such as an organic light-emitting diode (OLED) display substrate or a quantum dot light-emitting diode (QLED) display substrate, and the embodiments of the present disclosure are not limited to a specific type of display substrate.

[0119] For example, when the display substrate is an organic light-emitting diode display substrate, the light-emitting layer 4111 / 4211 / 4311 may include a small molecule organic material or a polymer molecule organic material, may be a fluorescent material or a phosphorescent material, and may emit red light, green light, blue light, or white light, etc. Furthermore, according to actual needs, in different examples, the light-emitting layer 4111 / 4211 / 4311 may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0120] For example, if the display substrate is a quantum dot light-emitting diode (QLED) display substrate, the light-emitting layer 4111 / 4211 / 4311 can include quantum dot materials such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, and indium arsenic quantum dots, and the particle size of the quantum dots is 2 to 20 nm.

[0121] 5G is a schematic diagram of a stacked structure of the second pixel unit 42, the first line portion 231 of the second winding portion 23, and the second sub-portion 212 of the first body portion 21 provided by at least one embodiment of the present disclosure. For example, as shown in FIG. 5G, the second sub-portion 212 of the first body portion 21, the source 4223, and the drain 4224 are located on the first electrode layer 251 of the display substrate 01, and the first sub-portion 211 of the first body portion 21, the first winding portion 22, and the second line portion 232 of the second winding portion 23 are also provided on the first electrode layer 251. For example, as shown in FIG. 5F, the first line portion 231 of the second winding portion 23, the gate 4222, and the first electrode plate 4225 are provided on the second electrode layer 252 of the display substrate 01. 5G, the first line portion 231 is electrically connected to the second sub-portion 212 and the second line portion 232 through a first via hole 254 and a second via hole 255 in the insulating layer between the first electrode layer 251 and the second electrode layer 252, respectively. That is, the first signal line 20 may employ a jumper wiring design, for example, a multiple-jumper wiring design. In some examples, the first line portion 231 and the second electrode plate 4226 of the second winding portion 23 are located on the second electrode layer 252 of the display substrate 01, which is omitted here. For example, the second body portion 32 of the second signal line 30 is also located on the second electrode layer 252 of the display substrate 01.

[0122] 5H shows a schematic diagram of another stacked structure of the second pixel unit 42 provided by at least one embodiment of the present disclosure. As shown in FIG. 5H, the second pixel unit 42 includes a second light-emitting element 421 and a second pixel circuit 422 that drives the second light-emitting element 421. For example, the second pixel circuit 422 includes structures such as a thin film transistor 422T and a storage capacitor 422C. The second light-emitting element 421 includes a second anode structure 4211, a second cathode structure 4213, and a second light-emitting layer 4212 located between the second anode structure 4211 and the second cathode structure 4213. The second anode structure 4211 is electrically connected to a transfer electrode 749 through a via hole 744A, and the transfer electrode 749 is electrically connected to the thin film transistor 422T included in the second pixel circuit 422 through a via hole 744B. For example, the second anode structure 4211 can include multiple anode sub-layers, such as an ITO / Ag / ITO three-layer structure (not shown), and the embodiments of the present disclosure do not limit the specific form of the second anode structure 4211. For example, the transfer electrode 749 can be made of a transparent conductive material. For example, the transparent conductive material can be selected from transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0123] For example, the thin film transistor 422T includes structures such as an active layer 4221, a gate 4222, a source electrode and a drain electrode (ie, a source 4223 and a drain 4224), and the storage capacitor 422C includes a first plate 4225 and a second plate 4226. For example, an active layer 4221 is provided on a base substrate 74, a first gate insulating layer 741 is provided on one side of the active layer 4221 remote from the base substrate 74, a gate 4222 and a first electrode plate 4225 are in the same layer and are provided on one side of the first gate insulating layer 741 remote from the base substrate 74, a second gate insulating layer 742 is provided on one side of the gate 4222 and the first electrode plate 4225 remote from the base substrate 74, a second electrode plate 4226 is provided on one side of the second gate insulating layer 742 remote from the base substrate 74, an interlayer insulating layer 743 is provided on one side of the second electrode plate 4226 remote from the base substrate 74, and a source electrode and a drain electrode are provided on the base substrate of the interlayer insulating layer 743. A passivation layer 748 is provided on one side of the source electrode and drain electrode away from the base substrate 74, and a first planarization layer 744 for planarizing the second pixel circuit 422 is provided on one side of the passivation layer 748 away from the base substrate 74. A transfer electrode 749 is provided on one side of the first planarization layer 7441 away from the base substrate 74, and a second planarization layer 7442 is provided on one side of the transfer electrode 749 away from the base substrate 74.

[0124] For example, the first planarization layer 7441 has a via hole 744B, and the transfer electrode 749 is electrically connected to the source 4223 or the drain 4224 of the thin film transistor 422T through the via hole 744B in the first planarization layer 7441. For example, the planarization layer 744 has a via hole 744A, and the second anode structure 4211 is electrically connected to the transfer electrode 749 through the via hole 744A in the second planarization layer 7442, so that the second anode structure 4211 can be electrically connected to the source 4223 or the drain 4224 of the thin film transistor 422T.

[0125] 5H , the display substrate further includes structures such as a pixel definition layer 746 and an encapsulation layer 747. For example, the pixel definition layer 746 is provided on the first anode structure and includes a plurality of openings for defining different pixels or sub-pixels, and the first light-emitting layer is formed in the openings of the pixel definition layer 746. For example, the encapsulation layer 747 includes a first encapsulation layer 7471, a second encapsulation layer 7472, and a third encapsulation layer 7473, which are sequentially arranged on the second cathode structure 4213 in a direction perpendicular to the display substrate. For example, the first encapsulation layer 7471, the second encapsulation layer 7472, and the third encapsulation layer 7473 are an inorganic encapsulation layer, an organic encapsulation layer, and an inorganic encapsulation layer, respectively.

[0126] For clarity, FIG. 5H shows only one second light-emitting element 421 and one second pixel circuit 422 included in the second pixel unit 42, and only one thin film transistor 422T and one storage capacitor 422C included in the second pixel circuit 422, but the embodiments of the present disclosure are not limited thereto.

[0127] In addition, when the second pixel unit 42 provided by at least one embodiment of the present disclosure uses the structure shown in Figure 5H, the third pixel unit 43 provided by at least one embodiment of the present disclosure, and the first light-emitting element 411 and the first pixel circuit 412 driving the first light-emitting element 411 provided by at least one embodiment of the present disclosure can also use the structure shown in Figure 5H, and will be omitted here.

[0128] 5I is a schematic cross-sectional view taken along line HH' shown in FIG. 5A. For example, as shown in FIG. 5I, the second sub-portion 212 of the first body portion 21 and the second wire portion 232 of the second winding portion 23 are located on one side of the interlayer insulating layer 743 away from the base substrate 74. That is, the second sub-portion 212 of the first body portion 21 and the second wire portion 232 of the second winding portion 23 are provided on the same electrode layer (e.g., the first electrode layer 251) as the source electrode and drain electrode (e.g., the source 4223 and the drain 4224) of the thin film transistor. For example, the first sub-portion 211 of the first body portion 21 and the first winding portion 22 are also located on the same electrode layer (e.g., the first electrode layer 251).

[0129] For example, as shown in FIG. 5I, the first wire portion 231 of the second winding portion 23 is located between the first gate insulating layer 741 and the second gate insulating layer 742. That is, the first wire portion 231, the gate 4222, and the first electrode plate 4225 of the second winding portion 23 are located on the same electrode layer (e.g., the second electrode layer 252 of the display substrate 01). For example, as shown in FIG. 5I, the first wire portion 231 is electrically connected to the second sub-portion 212 and the second wire portion 232 through the first via hole 254 and the second via hole 255, respectively, in the insulating layer between the first electrode layer 251 and the second electrode layer 252. That is, the first signal line 20 adopts a jumper wiring design, for example, a multiple-jumper wiring design can be used. For example, the second body portion 32 of the second signal line 30 is also located on the second electrode layer 252 of the display substrate 01. In some examples, the first wire portion 231 and the second electrode plate 4226 of the second winding portion 23 are located on the same electrode layer (e.g., the second electrode layer 252 of the display substrate 01), and the gate 4222 is not located on the same electrode layer (e.g., the second electrode layer 252 of the display substrate 01).

[0130] 4, 5A to 5C, and 5G, the first line portion 231 is located as a whole in the peripheral region 14 and is arranged in parallel with the second display region 12 in the first direction D1. For example, since no pixel circuits (first pixel circuit 412 to third pixel circuit 432) are provided in the peripheral region 14, the difficulty of wiring the first line portion 231 can be reduced.

[0131] 4 and 5A to 5C, the first line portion 231 is located as a whole on one side of the second display area 12 that is away from the third display area 13 in the first direction D1. For example, as shown in FIGS. 4 and 5A to 5C, the first line portion 231 is located as a whole on the upper edge of the display substrate 01.

[0132] 4, 5A to 5C, and 5G are located entirely in the peripheral region 14, but the embodiments of the present disclosure are not limited thereto. According to actual application requirements, the first line portion 231 may also be located entirely in the second display region 12, or the first line portion 231 may be located simultaneously in both the peripheral region 14 and the second display region 12. An illustrative description will be given below with reference to FIGS. 6, 7A to 7B, 8, and 9A to 9B.

[0133] Fig. 6 is a second example of the display substrate 01 shown in Fig. 2A. Fig. 7A is a first schematic diagram showing a portion of the first display region 11, the second display region 12, and the peripheral region 14 of the display substrate 01 shown in Fig. 6, and Fig. 7B is a second schematic diagram showing a portion of the first display region 11, the second display region 12, and the peripheral region 14 of the display substrate 01 shown in Fig. 6.

[0134] 6 and 7A to 7B, the first line portion 231 is located entirely within the second display area 12 and is arranged parallel to the first display area 11 in the first direction D1. For example, as shown in FIGS. 6 and 7A to 7B, the first line portion 231 is located on one side of the first display area 11 that is away from the third display area 13 in the first direction D1.

[0135] In one example, all of the multiple first line portions 231 included in the multiple first signal lines 20 are straight (i.e., straight line segments). In another example, at least some of the first line portions 231 included in the multiple first signal lines 20 may have a curved structure to prevent a part of the first line portion 231 from overlapping with the second light-emitting element 421 and blocking light emitted from the second light-emitting element 421.

[0136] For example, by disposing the entire first line portion 231 in the second display area 12, the size of the peripheral area 14 of the display substrate 01 can be reduced, thereby facilitating a narrow frame or full screen design of the display substrate 01.

[0137] Note that the other structures and specific implementation methods of the display substrate 01 shown in FIG. 6 are the same as or similar to the other structures and specific implementation methods of the display substrate 01 shown in FIG. 4, and the same or similar points will be omitted.

[0138] 7A and other related schematic plan views are used to illustrate the arrangement and connection of the elements of the display substrate 01 in a plane parallel to the base substrate of the display substrate 01, and do not limit the arrangement or relative positional relationship of the elements of the display substrate 01 in a direction perpendicular to the base substrate of the display substrate 01. The arrangement and relative positional relationship of the elements of the display substrate 01 in a direction perpendicular to the base substrate of the display substrate 01 can be determined by referring to the schematic diagrams of the stacked structure shown in FIGS. 5D to 5H and the schematic cross-sectional view shown in FIG. 5I, and are therefore omitted here.

[0139] Fig. 8 is a third example of the display substrate 01 shown in Fig. 2A. Fig. 9A is a first schematic diagram showing a portion of the first display region 11, the second display region 12, and the peripheral region 14 of the display substrate 01 shown in Fig. 8, and Fig. 9B is a second schematic diagram showing a portion of the first display region 11, the second display region 12, and the peripheral region 14 of the display substrate 01 shown in Fig. 8.

[0140] For example, as shown in FIG. 8 and FIGS. 9A to 9B, the first line portion 231 includes a first portion 2311, a second portion 2312, and a third portion 2313 that are connected in sequence, the first portion 2311 of the first line portion 231 is electrically connected to the second sub-portion 212, the third portion 2313 of the first line portion 231 is electrically connected to the second line portion 232, the first portion 2311 of the first line portion 231 is provided in the peripheral region 14, and the first direction The first line portion 231 is arranged in parallel with the second display area 12 in the direction D1, the second part 2312 of the first line portion 231 extends from the peripheral area 14 to the second display area 12 along the first direction D1, the third part 2313 of the first line portion 231 is located in the second display area 12, and a virtual extension line of the third part 2313 of the first line portion 231 extending along the second direction D2 is arranged in parallel with the first display area 11 in the first direction D1.

[0141] In some examples, the third portion 2313 of the first line portion 231 is electrically connected to the second sub-portion 212, and the first portion 2311 of the first line portion 231 is electrically connected to the second line portion 232, i.e., the electrically connected portion between the first line portion 231 and the second sub-portion 212 is located in the second display area 12, and the electrically connected portion between the first line portion 231 and the second line portion 232 is located in the peripheral area 14, which will be omitted here.

[0142] Note that other structures and specific mounting methods of the display substrate 01 shown in FIG. 8 are the same as or similar to other structures and specific mounting methods of the display substrate 01 shown in FIG. 4, and the same or similar points will be omitted.

[0143] 4, 6, and 8, the second winding portion 23 of the display substrate 01 is wound in the first direction D1 from the second sub-portion 212 of the first body portion 21 to a position parallel to the second sub-portion 212 of the first body portion 21 (parallel to the second direction D2), passing through one side of the first display region 11 away from the third display region 13, but the embodiments of the present disclosure are not limited thereto. In some examples, the second winding portion 23 may be wound in the first direction D1 from the first sub-portion 211 of the first body portion 21 to a position parallel to the second sub-portion 212 of the first body portion 21 (parallel to the second direction D2), passing through one side of the first display region 11 closer to the third display region 13, as will be described below with reference to FIG. 10.

[0144] 10 is a fourth example of the display substrate 01 shown in FIG. 2A. The display substrate 01 shown in FIG. 10 is similar to the display substrate 01 shown in FIG. 6, and only the differences between the two will be described here, omitting the commonalities. The difference between the display substrate 01 shown in FIG. 10 and the display substrate 01 shown in FIG. 6 is that the first line portion 231 of the display substrate 01 shown in FIG. 10 is located on one side of the first display area 11 closer to the third display area 13 in the first direction D1, and during operation, the current in the second line portion 232 of the display substrate 01 shown in FIG. 10 flows in the same direction as the current in the main body.

[0145] In some examples, in the first direction D1, at least a portion (e.g., all) of the first line portion 231 is arranged parallel to the first display area 11 and is located at one end of the third display area 13 close to the first display area 11, which is omitted here.

[0146] 4, 6, 8, and 10, the first signal lines 20 of the display substrate 01 are wound in the first direction D1 from one side of the first display region 11 to a position parallel to the first main body portion 21 (parallel to the second direction D2), but the embodiments of the present disclosure are not limited to this. In some examples, the first signal lines 20 of the display substrate 01 may be wound in the first direction D1 from both sides of the first display region 11 to a position parallel to the first main body portion 21 (parallel to the second direction D2). An illustrative description will be given below with reference to FIG. 11 and FIGS. 12A to 12C.

[0147] Fig. 11 is a fifth example of the display substrate 01 shown in Fig. 2A. Fig. 12A is a first schematic diagram showing the first display region 11, the second display region 12, and a portion of the peripheral region 14 of the display substrate 01 shown in Fig. 11, Fig. 12B is a second schematic diagram showing the first display region 11, the second display region 12, and a portion of the peripheral region 14 of the display substrate 01 shown in Fig. 11, and Fig. 12C is a schematic plan view of a partial region REG_E corresponding to Fig. 12B.

[0148] The display substrate 01 shown in Fig. 11 is similar to the display substrate 01 shown in Fig. 4, and only the differences between the two will be described here, omitting the similarities. The difference between the display substrate 01 shown in Fig. 11 and the display substrate 01 shown in Fig. 4 is that the display substrate 01 further includes a third winding portion 24. For example, at least a portion of the third winding portion 24 is wired in a direction intersecting (e.g., perpendicular to) the first direction D1.

[0149] For example, as shown in Figures 11 and 12A to 12B, a first end of the third winding portion 24 is electrically connected to the first sub-portion 211, and a second end of the third winding portion 24 is electrically connected to a corresponding first pixel circuit 412, and the first pixel circuit 412 connected to the second winding portion 23 is different from the first pixel circuit 412 connected to the third winding portion 24.

[0150] 11 and 12A to 12B, the first pixel circuit 412 connected to the second winding portion 23 and the first pixel circuit 412 connected to the third winding portion 24 are located in the same column, that is, the first pixel circuit 412 connected to the second winding portion 23 and the first pixel circuit 412 connected to the third winding portion 24 are arranged in the first direction D1. For example, the first pixel circuit 412 connected to the second winding portion 23 is the first pixel circuit 412 in the upper half of the first pixel circuits 412 in the same column, and the first pixel circuit 412 connected to the second winding portion 23 is the first pixel circuit 412 in the lower half of the first pixel circuits 412 in the same column.

[0151] For example, by further including a third winding portion 24 in the first signal line 20, the data cable can be used to bidirectionally drive pixel circuits (first pixel circuit 412 and second pixel circuit 422) in the area of ​​the second display area 12 parallel to the first display area 11 in the second direction D2, i.e., data signals can be input to the pixel circuits in the area from above and below the area of ​​the second display area 12 parallel to the first display area 11 in the second direction D2, and in this case, the opening of the second display area 12 (e.g., the inner edge 121 of the second display area 12) has a larger size.

[0152] For example, as shown in FIGS. 11 and 12A-12B, the third winding portion 24 includes a third wire portion 241 and a fourth wire portion 242 connected in sequence. The end of the third wire portion 241 that is not connected to the fourth wire portion 242 becomes the first end of the third winding portion 24, and the end of the fourth wire portion 242 that is not connected to the third wire portion 241 becomes the second end of the third winding portion 24. The third wire portion 241 extends along the second direction D2 and is arranged in parallel with the first wire portion 231 in the first direction D1. The fourth wire portion 242 extends along the first direction D1 and is arranged in parallel with the first sub-portion 211 in the second direction D2. During operation, the current in the fourth wire portion 242 flows in the same direction as the current in the main body portion. For example, the fourth wire portion 242 is a straight line segment. For example, the third wire portion 241 is a straight line segment. Furthermore, for example, the third line portion 241 may have a curved structure and extend along the second direction D2 as a whole.

[0153] For example, the fourth line portion 242 is located on the first electrode layer of the display substrate 01, and the third line portion 241 is located on the second electrode layer of the display substrate 01, and the third line portion 241 is electrically connected to the first sub-portion 211 and the fourth line portion 242, respectively, through the third via hole and the fourth via hole in the insulating layer between the first electrode layer and the second electrode layer.

[0154] For example, it is possible to avoid short-circuiting the first wire portion 231 of the second winding portion 23 and the third wire portion 241 of the third winding portion 24 of each first signal line 20 with other portions of each first signal line 20 (e.g., the fourth wire portion 242 and the first sub-portion 211), and the first wire portion 231 of the second winding portion 23 and the third wire portion 241 of the third winding portion 24 of each first signal line 20 with other first signal lines 20.

[0155] For example, as shown in FIG. 12C , the first display region 11 includes only a plurality of transparent wirings and an anode structure 4111 arranged in parallel, thereby increasing the transmittance of the first display region 11. For example, as shown in FIG. 12C , the plurality of transparent wirings arranged in parallel include connecting wirings 60 and dummy wirings 601. For example, the dummy wirings 601 have open sections, which make the dummy wirings 601 discontinuous. For example, providing the dummy wirings 601 with open sections can improve the etching uniformity of the first display region 11. Note that the lines indicated by arrows in FIG. 12C are shaded and not actual wirings.

[0156] 11 and 12A to 12B is not limited to being located in the peripheral region 14, and the third line portion 241 is not limited to being arranged parallel to the first display region 11 in the first direction D1 and located at one end of the third display region 13 close to the first display region 11. In one example, both the first line portion 231 and the third line portion 241 may be located in the second display region 12, and the first line portion 231 may be located on one side of the first display region 11 away from the third display region 13 in the first direction D1, and the third line portion 241 may be located between the first display region 11 and the third display region 13 in the first direction D1. In another example, the first line portion 231 may be located in both the peripheral region 14 and the second display region 12 at the same time, and the third line portion 241 may be located in both the third display region 13 and the second display region 12 at the same time.

[0157] Although the shapes of the first display region 11 of the display substrate 01 shown in FIGS. 4, 6, 8, 10, and 11 are all rectangular, the embodiments of the present disclosure are not limited thereto. For example, according to actual application requirements, the shape of the first display region 11 may be circular or other applicable shapes, and the shape of the first winding portion 22 may be adaptively changed accordingly. For example, the shape of the first winding portion 22 may match the shape of the first display region 11 to reduce the influence of the first winding portion 22 on elements in the first display region 11 and the second display region 12. An exemplary description will now be provided with reference to FIGS. 13A to 13D.

[0158] Fig. 13A is a schematic plan view of a sixth example of the display substrate 01 shown in Fig. 2A, Fig. 13B is another schematic plan view of the sixth example of the display substrate 01 shown in Fig. 2A, Fig. 13C is yet another schematic plan view of the sixth example of the display substrate 01 shown in Fig. 2A, and Fig. 13D is a schematic plan view corresponding to the partial region REG_B shown in Fig. 13C.

[0159] For clarity, Figure 13A shows only a portion of the second display area 12 and a portion of the peripheral area 14 of the display substrate 01, and Figures 13B and 13C show only a portion of the first display area 11, a portion of the second display area 12 and a portion of the peripheral area 14 of the display substrate 01.

[0160] The display substrate 01 shown in Figures 13A to 13C is similar to the display substrate 01 shown in Figures 4 and 5A to 5C, and only the differences between the two are described here, with the same points omitted. The difference between the display substrate 01 shown in Figures 13A to 13C and the display substrate 01 shown in Figures 4 and 5A to 5C is that the shape of the first display region 11 and the shape of the first winding portion 22 of the display substrate 01 shown in Figures 13A to 13C are different.

[0161] 13A to 13C, the shape of the first display area 11 is circular, the first winding portion 22 is an arcuate wire, a first end of the arcuate wire is connected to an end of the first sub-portion 211 that is closer to the second sub-portion 212, and a second end of the arcuate wire is connected to an end of the second sub-portion 212 that is closer to the first sub-portion 211. For example, the curvature of the arcuate wire and the curvature of the circle match (e.g., are equal to) each other.

[0162] According to actual application requirements, the shape of the first display area 11 of the display substrate 01 shown in Figures 6, 8, 10 and 11 can be changed to a circle, and the first winding portion 22 can be changed to an arc line, which will be omitted here.

[0163] 13C and 13D, the peripheral region 14 further includes a plurality of wirings 2911 and a plurality of wirings 2921, where the plurality of wirings 2911 are located in the electrode layer 291 and the plurality of wirings 2921 are located in the electrode layer 292. For example, the electrode layer 291 and the electrode layer 292 are different electrode layers in a direction perpendicular to the display substrate. For example, the plurality of wirings 2911 and the plurality of wirings 2921 are alternately arranged in a direction perpendicular to the extension direction of the wiring 2911. For example, by alternately arranging the plurality of wirings 2911 and the plurality of wirings 2921 in a direction perpendicular to the extension direction of the wiring 2911 and providing the wirings 2911 and 2921 in different electrode layers, the arrangement density of the wirings (the wirings 2911 and the wirings 2921 as a whole) can be increased.

[0164] For example, second sub-portion 212 of first signal line 20 and multiple wirings 2911 are located on different electrode layers, and second sub-portion 212 of first signal line 20 and multiple wirings 2921 are located on different electrode layers. For example, gate 4222 and first plate 4225 shown in FIG. 5H are also located on electrode layer 291, second plate 4226 shown in FIG. 5H is also located on electrode layer 292, and second sub-portion 212 of first signal line 20 is located on the same electrode layer as source 4223 and drain 4224 shown in FIG. 5H.

[0165] 13C and 13D , the second sub-portion 212 of the first signal line 20 passing through the second pixel circuit 422 is electrically connected to the corresponding wiring 2911 or the corresponding wiring 2921 (for example, electrically connected through a via hole), so that the signal of the second sub-portion 212 of the first signal line 20 is changed to the corresponding wiring 2911 or the corresponding wiring 2921 and transmitted. For example, the wiring 2911 or the wiring 2921 electrically connected to the second sub-portion 212 of the first signal line 20 is referred to as the first line portion 231. For example, the second sub-portion 212 of the first signal line 20 passing through the second pixel circuit 422 is electrically connected to the corresponding wiring 2911 or the corresponding wiring 2921.

[0166] For example, the first signal line (located in the SD layer) from each pixel unit is changed to the Gat1 (electrode layer 291) or Gat2 layer (electrode layer 292) by changing the layer. For example, when the longitudinal lead and the lateral lead cross each other, the longitudinal lead (the second sub-portion 212 of the first signal line 20) uses the SD layer, and the distance between the SD layer and the Gat layer (electrode layer 291 or 292) is greater than the distance between the Gat1 (electrode layer 291) and the Gat2 layer (electrode layer 292), thereby reducing the capacitive coupling.

[0167] Although the shapes of the second display area 12 of the display substrate 01 shown in Figures 4, 6, 8, 10, 11, and 13A to 13C are all rectangular, the embodiments of the present disclosure are not limited thereto. For example, according to actual application requirements, the shape of the second display area 12 may also be circular or other applicable shapes, which will not be discussed here.

[0168] 4, 6, 8, 10, 11, and 13A to 13C are wound with two or more winding portions in a position parallel to the first main body portion 21 (parallel in the second direction D2), but the embodiments of the present disclosure are not limited to this. For example, depending on actual application requirements, the first signal line 20 of the display substrate 01 may be wound with only one winding portion in a position parallel to the first main body portion 21 (parallel in the second direction D2), and an exemplary description will be given below with reference to FIG. 14.

[0169] 14 is a schematic plan view of a seventh example of the display substrate 01 shown in FIG. 2A. The display substrate 01 shown in FIG. 14 is similar to the display substrate 01 shown in FIG. 14, and only the differences between the two will be described here, and the same points will be omitted. The differences between the display substrate 01 shown in FIG. 14 and the display substrate 01 shown in FIG. 4 include that the display substrate 01 shown in FIG. 14 has only the first winding portion 22 and does not have the second winding portion 23.

[0170] 14, the first winding portion 22 surrounds the first display area 11 and is located as a whole in the second display area 12. For example, as shown in FIG. 14, the first winding portion 22 includes a fifth wire portion 271, a sixth wire portion 272, and a seventh wire portion 273 that are connected in sequence, the fifth wire portion 271 is electrically connected to the first sub-portion 211, the seventh wire portion 273 is electrically connected to the second sub-portion 212, the sixth wire portion 272 extends along a first direction D1, the fifth wire portion 271 and the seventh wire portion 273 extend along a second direction D2 that intersects with the first direction D1, and the sixth wire portion 272 extends along a second direction D2 that intersects with the first direction D1. 272 is located between the first sub-portion 211 and the second sub-portion 212 and is arranged in parallel in the first direction D1 to the virtual connecting line extending along the first direction D1, the sixth line portion 272 at least partially overlaps (or is located in the same column and closely adjacent to but not overlapping with) the first pixel circuit 412 electrically connected to the sixth line portion 272, and during operation, the current in the sixth line portion 272 flows in the same direction as the current in the first body portion 211. For example, the fifth line portion 271, the sixth line portion 272 and the seventh line portion 273 are all straight line segments.

[0171] For example, the data driving circuit 50 can be implemented as a driving chip. For example, the driving chip can be coupled to the display substrate 01 via a flexible circuit board, and provide display data signals to multiple data cables via the flexible circuit to drive the display substrate 01 to achieve a display function. For example, a gate driving chip may also be provided in the peripheral region 14, or a gate driving circuit (GOA, not shown) may be formed on the array substrate, with multiple output terminals of the gate driving chip or GOA connected to multiple gate lines respectively to transmit gate scanning signals to the multiple gate lines. Note that the display substrate 01 is not limited to being driven by a single data driving circuit. In some examples, the display substrate 01 can be driven by two data driving circuits, and the two data driving circuits are located on both sides of the display substrate 01 (e.g., on both sides of the display substrate 01 in the first direction D1).

[0172] Figure 15 is a schematic plan view of an eighth example of the display substrate 01 shown in Figure 2A, and Figure 16 is another schematic plan view of the eighth example of the display substrate 01 shown in Figure 2A. For clarity, Figure 15 shows only a portion of the first display region 11 and the second display region 12 of the display substrate 01.

[0173] The display substrate 01 shown in Fig. 15 is similar to the display substrate 01 shown in Fig. 4, and only the differences between the two will be described here, omitting the same points. The differences between the display substrate 01 shown in Fig. 15 and the display substrate 01 shown in Fig. 4 include that the first direction D1 of the display substrate 01 shown in Fig. 15 is the row direction of the display panel, the connection wiring 60 of the display substrate 01 shown in Fig. 15 extends along the column direction, the first signal line 20 of the display substrate 01 shown in Fig. 15 is a gate line, the second signal line 30 of the display substrate 01 shown in Fig. 15 is a data cable, and the structures of the winding portions of the first signal line 20 and the second signal line 30 of the display substrate 01 shown in Fig. 15 are different from the structures of the winding portions of the first signal line 20 and the second signal line 30 of the display substrate 01 shown in Fig. 4, respectively.

[0174] 15 , the first winding portion 22 surrounds the first display area 11 and is located in the second display area 12 as a whole. The first winding portion 22 includes an eighth wire portion 281 and a ninth wire portion 282 connected sequentially. The eighth wire portion 281 is electrically connected to the first body portion 21 and extends along the second direction D2. The ninth wire portion 282 extends along the first direction D1 and is arranged in parallel with an imaginary extension line of the first body portion 21 in the first direction D1. In operation, a current in the ninth wire portion 282 flows in the same direction as the current in the body portion. The ninth wire portion 282 is electrically connected to a first pixel circuit 412 configured to drive a first number of first light-emitting elements 411 arranged in parallel along the first direction D1 in the first display area 11. For example, both the eighth wire portion 281 and the ninth wire portion 282 are straight line segments.

[0175] In some examples, the first body portion 21 includes a first sub-portion 211 and a second sub-portion 212 (not shown), and the first winding portion 22 further includes a tenth wire portion (not shown), a first end of which is connected to the ninth wire portion 282, a second end of which is connected to the second sub-portion 212, and the tenth wire portion extends along the second direction D2.

[0176] 15 , the second signal line 30 includes a second body portion 32, a fourth winding portion 33, and a fifth winding portion 34. The fourth winding portion 33 is arranged offset from an imaginary extension line of the second body portion 32 along the second direction D2. The second body portion 32 includes a third sub-portion 321 and a fourth sub-portion 322 separated by the first display area 11. The third sub-portion 321 and the fourth sub-portion 322 are electrically connected via the fourth winding portion 33. The fourth winding portion 33 is located between the third sub-portion 321 and the fourth sub-portion 322 and arranged offset from an imaginary connection line extending along the second direction D2. For example, at least a portion of the fourth winding portion 33 extends in a direction intersecting the second direction D2. For example, at least a portion of the fifth winding portion 34 extends in a direction intersecting the second direction D2. For example, the third sub-portion 321 and the fourth sub-portion 322 are both straight line segments.

[0177] 15 , the fourth winding portion 33 includes a fourth line segment 331, a fifth line segment 332, and a sixth line segment 333 connected in sequence, the end of the fourth line segment 331 not connected to the fifth line segment 332 is connected to an end of the third sub-portion 321 that is closer to the fourth sub-portion 322, the end of the sixth line segment 333 not connected to the fifth line segment 332 is connected to an end of the fourth sub-portion 322 that is closer to the third sub-portion 321, the fourth line segment 331 and the sixth line segment 333 extend along the first direction D1, and the fifth line segment 332 extends along the second direction D2. For example, the fourth line segment 331, the fifth line segment 332, and the sixth line segment 333 are all straight line segments.

[0178] 15, a first end of the fifth winding portion 34 is electrically connected to the second sub-portion 212, and a second end of the fifth winding portion 34 is electrically connected to a corresponding first pixel circuit 412. For example, as shown in FIG. 15, the second end of the fifth winding portion 34 can be electrically connected to a first pixel circuit 412 in the same column (e.g., a first pixel circuit 412 in the same column that is directly adjacent to the second wire portion 232 of the second winding portion 23).

[0179] 15 , the fifth winding portion 34 includes a seventh line segment 341 and an eighth line segment 342 connected in sequence, with the end of the seventh line segment 341 not connected to the eighth line segment 342 being the first end of the fifth winding portion 34, and the end of the eighth line segment 342 not connected to the seventh line segment 341 being the second end of the fifth winding portion 34, the seventh line segment 341 extending along the first direction D1, the eighth line segment 342 extending along the second direction D2, and being arranged in parallel with the second sub-portion 212 in the first direction D1, and during operation, the current in the eighth line segment 342 flows in the opposite direction to the current in the second sub-portion 212. For example, the seventh line segment 341 and the eighth line segment 342 are both straight line segments.

[0180] 15, a first light-emitting element 411 and a first pixel circuit 412 for driving the first light-emitting element 411 are located in adjacent columns of the display panel. For example, as shown in FIG. 15, at least one second signal line 30 is configured to drive the first light-emitting element 411 and the second light-emitting element 421 arranged in parallel along the second direction D2, i.e., the first light-emitting element 411 and the third light-emitting element 431 driven by the same second signal line 30 are located in the same column of the display substrate 01.

[0181] In some examples, the first light-emitting element 411 and the first pixel circuit 412 for driving the first light-emitting element 411 may be located in the same column of the display panel, i.e., the first light-emitting element 411 and the first pixel circuit 412 for driving the first light-emitting element 411 are arranged in parallel in the column direction.

[0182] For example, as shown in FIG. 15, the first direction D1 is the row direction of the display panel, the second direction D2 is the column direction of the display panel, the first signal lines 20 are gate lines, and the second signal lines 30 are data cables.

[0183] Note that the connection wiring 60 of the display substrate 01 shown in FIG. 15 extends along the column direction, and the connection wiring 60 of the display substrate 01 is not limited to being straight (i.e., the connection wiring 60 of the display substrate 01 is not limited to being a straight line segment), and in some examples, the connection wiring 60 of the display substrate 01 shown in FIG. 15 further includes a portion extending along the row direction.

[0184] For example, the source / drain, first winding, and second signal line are all located on the first electrode layer, and the first body, gate, and first plate are located on the second electrode layer.Alternatively, for example, the first winding and second signal line are all located on the first electrode layer, and the first body and second plate of the storage capacitor are located on the second electrode layer.

[0185] FIG. 16 is similar to FIG. 15, except that FIG. 16 shows more of the first signal line 20, and FIG. 6 does not show the fifth winding portion 34 of the second signal line 30, which is omitted here.

[0186] 17 illustrates a pixel circuit 921 provided by at least one embodiment of the present disclosure and a light-emitting element 920 driven by the pixel electrode. For example, at least one (e.g., all) of the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 provided by at least one embodiment of the present disclosure may be implemented as the pixel circuit 921 illustrated in FIG.

[0187] 17 , the pixel circuit 921 further includes a first light-emitting control circuit 923 and a second light-emitting control circuit 924. The drive circuit 922 includes a control end, a first end, and a second end, and is configured to provide a drive current to the organic light-emitting element 920 to drive the organic light-emitting element 920 to emit light. For example, the first light-emitting control circuit 923 is connected to the first end and the first voltage end VDD of the drive circuit 922 and is configured to establish or disconnect communication between the drive circuit 922 and the first voltage end VDD, and the second light-emitting control circuit 924 and the second end of the drive circuit 922 are electrically connected to the first electrode of the organic light-emitting element 920 and are configured to establish or disconnect communication between the drive circuit 922 and the organic light-emitting element 920.

[0188] 17 , the pixel circuit 921 further includes a data writing circuit 926, a memory circuit 927, a threshold compensation circuit 928, and a reset circuit 929. The data writing circuit 926 is electrically connected to a first end of the driving circuit 922 and configured to write a data signal to the memory circuit 927 under the control of a scanning signal. The memory circuit 927 is electrically connected to a control end and a first voltage end VDD of the driving circuit 922 and configured to store the data signal. The threshold compensation circuit 928 is electrically connected to a control end and a second end of the driving circuit 922 and configured to perform threshold compensation for the driving circuit 922. The reset circuit 929 is electrically connected to the control end of the driving circuit 922 and a first electrode of the organic light emitting element 920 and configured to reset the control end of the driving circuit 922 and the first electrode of the organic light emitting element 920 under the control of a reset control signal.

[0189] For example, as shown in FIG. 17, the driving circuit 922 includes a driving transistor T1, the control end of the driving circuit 922 includes the gate of the driving transistor T1, the first end of the driving circuit 922 includes the first pole of the driving transistor T1, and the second end of the driving circuit 922 includes the second pole of the driving transistor T1.

[0190] For example, as shown in FIG. 17, the data write circuit 926 includes a data write transistor T2, the memory circuit 927 includes a capacitor C, the threshold compensation circuit 928 includes a threshold compensation transistor T3, the first light-emitting control circuit 923 includes a first light-emitting control transistor T4, the second light-emitting control circuit 924 includes a second light-emitting control transistor T5, the reset circuit 929 includes a first reset transistor T6 and a second reset transistor T7, and the reset control signal can include a first sub-reset control signal and a second sub-reset control signal.

[0191] For example, as shown in FIG. 17, the first electrode of the data write transistor T2 is electrically connected to the first electrode of the driving transistor T1, the second electrode of the data write transistor T2 is electrically connected to the data cable Vd to receive the data signal, the gate of the data write transistor T2 is electrically connected to the first scanning signal line Ga1 to receive the scanning signal, the first electrode of the capacitor C is electrically connected to the first power supply terminal VDD, the second electrode of the capacitor C is electrically connected to the gate of the driving transistor T1, the first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1, the gate of the threshold compensation transistor T3 is electrically connected to the second scanning signal line Ga2 to receive the compensation control signal, the first electrode of the first reset transistor T6 is electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal, and the second electrode of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1. a first electrode of the second reset transistor T7 electrically connected to the second reset control signal line Rst1 to receive a first sub-reset control signal; a first electrode of the second reset transistor T7 electrically connected to the second reset power supply terminal Vinit2 to receive a second reset signal; a second electrode of the second reset transistor T7 electrically connected to the first electrode of the organic light emitting element 920; a gate of the second reset transistor T7 electrically connected to the second reset control signal line Rst2 to receive a second sub-reset control signal; a first electrode of the first light emitting control transistor T4 electrically connected to the first power supply terminal VDD; a second electrode of the first light emitting control transistor T4 electrically connected to the first electrode of the driving transistor T1; a gate of the first light emitting control transistor T4 electrically connected to the first light emitting control signal line EM1 to receive a first light emitting control signal; a first electrode of the second light emitting control transistor T5 electrically connected to the second electrode of the driving transistor T1;The gate of the second light-emitting control transistor T5 is electrically connected to the second light-emitting control signal line EM2 to receive the second light-emitting control signal, and the first electrode of the organic light-emitting element 920 is electrically connected to the second power supply terminal VSS.

[0192] For example, one of the first power supply terminal VDD and the second power supply terminal VSS1 is a high-voltage terminal and the other is a low-voltage terminal. For example, in the embodiment shown in Figure 17, the first power supply terminal VDD may be a voltage source that outputs a constant first voltage, where the first voltage is a positive voltage, and the second power supply terminal VSS may be a voltage source that outputs a constant second voltage, where the second voltage is a negative voltage, etc. For example, in some examples, the second power supply terminal VSS may be grounded.

[0193] 17, the scanning signal and the compensation control signal may be the same, i.e., the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 may be electrically connected to the same signal line, e.g., the first scanning signal line Ga1, to receive the same signal (e.g., scanning signal). In this case, the second scanning signal line Ga2 may not be provided on the display substrate 1000 to reduce the number of signal lines. Also, for example, the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 may be electrically connected to different signal lines, i.e., the gate of the data writing transistor T2 is electrically connected to the first scanning signal line Ga1, and the gate of the threshold compensation transistor T3 is electrically connected to the second scanning signal line Ga2, and the first scanning signal line Ga1 and the second scanning signal line Ga2 transmit the same signal.

[0194] In addition, the scanning signal and the compensation control signal may also be different, so that the gate of the data writing transistor T2 and the threshold compensation transistor T3 can be controlled separately, which increases the flexibility of controlling the pixel circuit.

[0195] 17, the first light-emitting control signal and the second light-emitting control signal may be the same. That is, the gate of the first light-emitting control transistor T4 and the gate of the second light-emitting control transistor T5 may be electrically connected to the same signal line, for example, the first light-emitting control signal line EM1, to receive the same signal (e.g., the first light-emitting control signal). In this case, the display substrate 1000 does not need to be provided with the second light-emitting control signal line EM2, so as to reduce the number of signal lines. Also, for example, the gate of the first light-emitting control transistor T4 and the gate of the second light-emitting control transistor T5 may be electrically connected to different signal lines. That is, the gate of the first light-emitting control transistor T4 is electrically connected to the first light-emitting control signal line EM1, and the gate of the second light-emitting control transistor T5 is electrically connected to the second light-emitting control signal line EM2, so that the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 transmit the same signal.

[0196] In addition, if the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are different types of transistors, for example, if the first light-emitting control transistor T4 is a P-type transistor and the second light-emitting control transistor T5 is an N-type transistor, the first light-emitting control signal and the second light-emitting control signal may be different, and the embodiments of the present disclosure are not limited to this.

[0197] For example, the first sub-reset control signal and the second sub-reset control signal may be the same, i.e., the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may be electrically connected to the same signal line, e.g., the first reset control signal line Rst1, to receive the same signal (e.g., the first sub-reset control signal). In this case, the display substrate 1000 may not have the second reset control signal line Rst2 to reduce the number of signal lines. Also, for example, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may be electrically connected to different signal lines, i.e., the gate of the first reset transistor T6 is electrically connected to the first reset control signal line Rst1, and the gate of the second reset transistor T7 is electrically connected to the second reset control signal line Rst2, and the first reset control signal line Rst1 and the second reset control signal line Rst2 transmit the same signal. Note that the first sub-reset control signal and the second sub-reset control signal may be different.

[0198] For example, in some examples, the second sub-reset control signal may be the same as the scanning signal, i.e., the gate of the second reset transistor T7 may be connected to the first scanning signal line Ga1 to receive the scanning signal as the second sub-reset control signal.

[0199] For example, the gate of the first reset transistor T6 and the source of the second reset transistor T7 are connected to the first reset power terminal Vinit1 and the second reset power terminal Vinit2, respectively, which may be DC reference voltage terminals to output a constant DC reference voltage. The first reset power terminal Vinit1 may be the same as the second reset power terminal Vinit2, for example, the gate of the first reset transistor T6 and the source of the second reset transistor T7 are connected to the same reset power terminal. The first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be a high-voltage terminal or a low-voltage terminal, and the present disclosure is not limited thereto as long as they can provide a first reset signal and a second reset signal to reset the gate of the driving transistor T1 and the first electrode of the light-emitting element 920.

[0200] It should be noted that the driving circuit 922, the data writing circuit 926, the memory circuit 927, the threshold compensation circuit 928, and the reset circuit 929 in the pixel circuit shown in FIG. 17 are merely examples, and the specific structures of circuits such as the driving circuit 922, the data writing circuit 926, the memory circuit 927, the threshold compensation circuit 928, and the reset circuit 929 can be set according to actual application requirements, and are not particularly limited in the embodiments of the present disclosure.

[0201] For example, according to the characteristics of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor. For clarity, the embodiments of the present disclosure will describe the technical solution of the present disclosure in detail using the transistor as a P-type transistor (e.g., a P-type MOS transistor). That is, in the description of the present disclosure, the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light-emitting control transistor T4, the second light-emitting control transistor T5, the first reset transistor T6, and the second reset transistor T7, etc., can all be P-type transistors. However, the transistors in the embodiments of the present disclosure are not limited to P-type transistors. Those skilled in the art can use N-type transistors (e.g., N-type MOS transistors) to realize the functions of one or more transistors in the embodiments of the present disclosure according to actual needs.

[0202] The transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors. The source and drain of a transistor may be symmetrical in structure, so the source and drain cannot be distinguished from each other in terms of physical structure. In the embodiments of the present disclosure, to distinguish between transistors, one pole is directly described as a first pole and the other pole as a second pole, except for the gate as a control electrode. Therefore, in the embodiments of the present disclosure, the first pole and second pole of all or part of a transistor may be interchangeable as needed.

[0203] It should be noted that the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 provided by at least one embodiment of the present disclosure are not limited to being implemented as pixel circuits including seven transistors and one capacitor (i.e., the 7T1C pixel circuit shown in FIG. 17 ). The first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 provided by at least one embodiment of the present disclosure may include an appropriate number of transistors and an appropriate number of capacitors. For example, according to actual application requirements, the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 provided by at least one embodiment of the present disclosure may be a 7T2C pixel circuit, a 6T1C pixel circuit, a 6T2C pixel circuit, or a 9T2C pixel circuit.

[0204] Fig. 18 is a structural schematic diagram of the 7T1C pixel circuit shown in Fig. 17. The positions of the first transistor T1 to the seventh transistor T7 included in the 7T1C pixel circuit are as shown in Fig. 18, and are omitted here.

[0205] FIG. 19 is a schematic diagram illustrating a structure of a subpixel according to an embodiment of the present disclosure. FIGS. 20 to 23 are schematic diagrams illustrating layouts of specific layers within a subpixel according to some embodiments of the present disclosure. FIG. 20 is a schematic plan view illustrating an LTPS layer (low-temperature polysilicon layer) of a subpixel according to an embodiment of the present disclosure. FIG. 21 is a schematic plan view illustrating an SD layer (source-drain electrode layer) of a subpixel according to an embodiment of the present disclosure. FIG. 22 is a schematic plan view illustrating a Gat1 layer (first gate layer) of a subpixel according to an embodiment of the present disclosure. FIG. 23 is a schematic plan view illustrating a Gat2 layer (second gate layer) of a subpixel according to an embodiment of the present disclosure. FIG. 24 is a schematic diagram illustrating a stacked layout of the layers shown in FIGS. 20, 22, and 23 in a subpixel according to an embodiment of the present disclosure. FIG. 25 is a schematic diagram illustrating a stacked layout of the layers shown in FIGS. 20 to 23 in a subpixel according to an embodiment of the present disclosure. For example, the LTPS layer (low-temperature polysilicon layer), Gat1 layer (first gate layer), Gat2 layer (second gate layer), and SD layer (source-drain electrode layer) are arranged in order from bottom to top in a direction perpendicular to the subpixel. After the data cable of the SD layer (source-drain electrode layer) is pulled out, it is switched to the Gat1 layer (first gate layer) and Gat2 layer (second gate layer).

[0206] 19, a subpixel may include a light-emitting element D, a first transistor T1, a capacitor C, a second transistor T2, and a third transistor T3. The light-emitting element D includes an anode D1 and a cathode D2. In some implementations, the light-emitting element D may be an OLED. Here, the first transistor T1 may be referred to as a switching transistor, the second transistor T2 may be referred to as a driving transistor, and the third transistor T3 may be referred to as a reset transistor.

[0207] The first transistor T1 is configured to transmit a data signal from the data cable Dat to the second transistor T2 in response to a scanning signal from the gate line Gat when the first transistor T1 is connected. The second transistor T2 is configured to transmit a driving current Id to the light-emitting element D to drive the light-emitting element D to emit light. The third transistor T3 is configured to reset the voltage of the gate G2 of the second transistor T2 to the voltage of the initialization voltage line Vinit when the third transistor T3 is connected in response to a reset signal from the reset line Rese when the third transistor T3 is connected.

[0208] In various embodiments, as shown in FIG. 19 , a subpixel may include one or more of a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Here, the fourth transistor T4 may be referred to as a compensation transistor, the fifth transistor T5 may be referred to as a drive control transistor, the sixth transistor T6 may be referred to as an emission control transistor, and the seventh transistor T7 may be referred to as a bypass transistor. For example, the fourth transistor T4 is configured to place the second transistor T2 in a diode-connected state when it is connected in response to a scan signal on a scan line Gat. For example, the fifth transistor T5 and the sixth transistor T6 are configured to allow an emission current Id to flow to the light-emitting element D when it is connected in response to a control signal on a control line EM. For example, the seventh transistor T7 is configured to allow a portion of the drive current Id to flow as a bypass current Ibp when it is connected in response to a reset signal on a reset line Rese. 19, the third gate G3 of the third transistor T3 and the seventh gate G7 of the seventh transistor T7 are both connected to the same reset line Rese, but are not limited to this. For example, in some embodiments, the seventh gate G7 of the seventh transistor T7 may be connected to a different reset line from the reset line Rese.

[0209] In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-channel thin-film transistors. In other embodiments, one or more of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be N-channel thin-film transistors.

[0210] For example, the active layer of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is as shown in FIG. 20. The material of the active layer may include, for example, polysilicon, such as low-temperature polysilicon. The active layer of each transistor includes two electrode regions and a channel region located between the two electrode regions. Here, one of the two electrode regions is a source region, and the other is a drain region. It should be understood that the doping concentration of the two electrode regions is greater than the doping concentration of the channel region. In other words, each of the two electrode regions is a conductive region, and the channel region is a semiconductor region.

[0211] 19 and 20, the first transistor T1 includes a first active layer ACT1 and a first gate G1 connected to the scan line Gat. In some embodiments, the scan line Gat and the first gate G1 may be integrally disposed. As shown in FIG. 20, the first active layer ACT1 includes a first electrode region ACT11, a second electrode region ACT12, and a first channel region ACT13 located between the first and second electrode regions. Here, the first electrode region ACT11 is connected to the data cable Dat, and the second electrode region ACT12 is connected to the power cable VDD. For example, the first electrode region ACT11 may be connected to the data cable Dat through a via hole V1 shown in FIG. 25. In some embodiments, the second electrode region ACT12 may be connected to the power cable VDD through a fifth active layer ACT5 of the fifth transistor T5. For example, the fifth active layer ACT5 may be connected to the power cable VDD through a via hole V2 shown in FIG. 25. In some embodiments, referring to FIG. 21, the data cable Dat and the power cable VDD may be located on the same layer.

[0212] In this specification, two components being located on the same layer means that the two components are formed by the same patterning process, i.e., by patterning the same material layer once, or that the two components are located on the same film layer and are in direct contact with the film layer.

[0213] The capacitor C includes a first electrode plate C1 and a second electrode plate C2 connected to a power cable VDD. For example, the second electrode plate C2 is connected to the power cable VDD through a via hole V3 shown in FIG.

[0214] The second transistor T2 includes a second active layer ACT2 and a second gate G2 connected to the first electrode plate C1. In some embodiments, the first electrode plate C1 and the second gate G2 may be integrally arranged. As shown in FIG. 20 , the second active layer ACT2 includes a third electrode region ACT21, a fourth electrode region ACT22, and a second channel region ACT23 located between the third electrode region ACT21 and the fourth electrode region ACT22. The third electrode region ACT21 is connected to the second electrode region ACT12, and the fourth electrode region ACT22 is connected to the anode D1. In some embodiments, the third electrode region ACT21 and the second electrode region ACT12 may be integrally arranged. In some embodiments, the third electrode region ACT21 may be connected to the power supply cable VDD via the fifth active layer ACT5 of the fifth transistor T5.

[0215] The third transistor T3 includes a third active layer ACT3 and a third gate G3 connected to the reset line Rese. In some embodiments, the reset line Rese and the third gate G3 may be integrally disposed. As shown in FIG. 20 , the third active layer ACT3 includes a fifth electrode region ACT31, a sixth electrode region ACT32, and a third channel region ACT33 located between the fifth electrode region ACT31 and the sixth electrode region ACT32. The fifth electrode region ACT31 is connected to the first electrode plate C1, and the sixth electrode region ACT32 is connected to the initialization voltage line Vinit. For example, the fifth electrode region ACT31 may be connected to the first connector CT1 through a via hole V4 shown in FIG. 25 , and the first electrode plate C1 may be connected to the first connector CT1 through a via hole V5 shown in FIG. 25 . For example, the sixth electrode region ACT32 may be connected to the second connector CT2 through a via hole V6 shown in FIG. 25 , and the initialization voltage line Vinit may be connected to the second connector CT2 through a via hole V7 shown in FIG. 25 . In some embodiments, referring to Fig. 21, the first connector CT1, the second connector CT2, the data cable Dat, and the power cable VDD may be located on the same layer. In some embodiments, referring to Fig. 22, the scan line Gat, the first electrode plate C1, and the reset line Rese may be located on the same layer. In some embodiments, referring to Fig. 23, the second electrode plate C2 and the initialization voltage line Vinit may be located on the same layer.

[0216] Referring to Figures 20 and 24, the first channel region ACT13 may be a region where the first active layer ACT1 and the scanning line Gat overlap, the second channel region ACT23 may be a region where the second active layer ACT2 and the first electrode plate C1 overlap, the third channel region ACT33 may be a region where the third active layer ACT3 and the reset line Rese overlap, and the fourth channel region ACT43 may be a region where the fourth active layer ACT4 and the scanning line Gat overlap.

[0217] 19 and 20, the light-emitting element D includes an anode D1 and a cathode D2. The first transistor T1 includes a first active layer ACT1 and a first gate G1 connected to the scan line Gat, the first active layer ACT1 includes a first electrode region ACT11, a second electrode region ACT12, and a first channel region ACT13 located between the first and second electrode regions, the first electrode region ACT11 is connected to the data cable Dat, and the second electrode region ACT12 is connected to the power cable VDD.

[0218] The capacitor C includes a first electrode plate C1 and a second electrode plate C2 connected to the power supply cable VDD. The second transistor T2 includes a second gate G2 connected to the second active layer ACT2 and the first electrode plate C1. The second active layer ACT2 includes a third electrode region ACT21, a fourth electrode region ACT22, and a second channel region ACT23 located between the third electrode region ACT21 and the fourth electrode region ACT22. The third electrode region ACT21 is connected to the second electrode region ACT12, and the fourth electrode region ACT22 is connected to the anode D1.

[0219] The third transistor T3 includes a third active layer ACT3 and a third gate G3 connected to a reset line Rese, and the third active layer ACT3 includes a fifth electrode region ACT31, a sixth electrode region ACT32, and a third channel region ACT33 located between the fifth electrode region ACT31 and the sixth electrode region ACT32, with the fifth electrode region ACT31 connected to the first electrode plate C1 and the sixth electrode region ACT32 connected to the initialization voltage line Vinit.

[0220] Hereinafter, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 will be described with reference to FIGS.

[0221] The fourth transistor T4 includes a fourth active layer ACT4 and a fourth gate G4 connected to the scanning line Gat. In some embodiments, the scanning line Gat and the fourth gate G4 may be integrally arranged. As shown in FIG. 20 , the fourth active layer ACT4 includes a seventh electrode region ACT41, an eighth electrode region ACT42, and a fourth channel region ACT43 located between the seventh electrode region ACT41 and the eighth electrode region ACT42. The seventh electrode region ACT41 is connected to the second gate G2, and the eighth electrode region ACT42 is connected to the fourth electrode region ACT22. For example, the seventh electrode region ACT41 may be connected to the first connector CT1 through a via hole V4 shown in FIG. 25, and the second gate G2 may be connected to the first connector CT1 through a via hole V5 shown in FIG. 25. In some embodiments, the seventh electrode region ACT41 and the fifth electrode region ACT31 may be integrally arranged. In some embodiments, the eighth electrode region ACT42 and the fourth electrode region ACT22 may be integrally arranged. In some embodiments, the fourth channel region ACT43 may include two spaced apart portions, ie, the fourth gate G4 may include two gates.

[0222] The fifth transistor T5 includes a fifth active layer ACT5 and a fifth gate G5 connected to a control line EM. As shown in FIG. 20, the fifth active layer ACT5 includes a ninth electrode region ACT51, a tenth electrode region ACT52, and a fifth channel region ACT53 located between the ninth electrode region ACT51 and the tenth electrode region ACT52. The ninth electrode region ACT51 is connected to a power cable VDD, and the tenth electrode region ACT52 is connected to the second electrode region ACT12. For example, the ninth electrode region ACT51 may be connected to the power cable VDD through a via hole V2 shown in FIG. 25. For example, the tenth electrode region ACT52 may be connected to the second electrode region ACT12 through a third electrode region ACT21. In some embodiments, referring to FIG. 22, the control line EM, the scan line Gat, the first electrode plate C1, and the reset line Rese may be located on the same layer.

[0223] The sixth transistor T6 includes a sixth active layer ACT6 and a sixth gate G6 connected to the control line EM. As shown in FIG. 20, the sixth active layer ACT6 includes an eleventh electrode region ACT61, a twelfth electrode region ACT62, and a sixth channel region ACT63 located between the eleventh electrode region ACT61 and the twelfth electrode region ACT62. The eleventh electrode region ACT61 is connected to the fourth electrode region ACT22, and the twelfth electrode region ACT62 is connected to the anode D1. In some embodiments, the eleventh electrode region ACT61 and the fourth electrode region ACT22 may be integrally disposed. In some embodiments, the twelfth electrode region ACT62 may be connected to a conductive layer M (e.g., a metal layer) through a via hole V8 shown in FIG. 25, and the conductive layer M may be connected to the anode D1 through another via hole. In some embodiments, referring to FIG. 21, the conductive layer M, the first connector CT1, the second connector CT2, the data cable Dat, and the power cable VDD may be located on the same layer.

[0224] The seventh transistor T7 includes a seventh active layer ACT7 and a seventh gate G7 connected to a reset line Rese. In some embodiments, the reset line Rese and the seventh gate G7 may be integrally arranged. As shown in FIG. 20 , the seventh active layer ACT7 includes a thirteenth electrode region ACT71, a fourteenth electrode region ACT72, and a seventh channel region ACT73 located between the thirteenth electrode region ACT71 and the fourteenth electrode region ACT72. The thirteenth electrode region ACT71 is connected to the twelfth electrode region ACT62, and the fourteenth electrode region ACT72 is connected to the initialization voltage line Vinit. For example, the fourteenth electrode region ACT72 may be connected to the second connector CT2 via a via hole V6 shown in FIG. 25, and the initialization voltage line Vinit may be connected to the second connector CT2 via a via hole V7 shown in FIG. 25. In some embodiments, the fourteenth electrode region ACT72 and the sixth electrode region ACT32 may be integrally arranged.

[0225] Referring to Figures 20 and 24, the fifth channel region ACT53 may be a region where the fifth active layer ACT5 and the control line EM overlap, the sixth channel region ACT63 may be a region where the sixth active layer ACT6 and the control line EM overlap, and the seventh channel region ACT73 may be a region where the seventh active layer ACT7 and the reset line overlap.

[0226] In some embodiments, referring to FIG. 20, the first active layer ACT1, the second active layer ACT2, the third active layer ACT3, the fourth active layer ACT4, the fifth active layer ACT5, the sixth active layer ACT6 and the seventh active layer ACT7 may be located in the same layer.

[0227] Hereinafter, a method for driving a sub-pixel according to some embodiments of the present disclosure will be described, assuming that the sub-pixel includes transistors T1, T2, T3, T4, T5, T6, and T7, and that the transistors T1, T2, T3, T4, T5, T6, and T7 are all P-channel transistors.

[0228] In the reset stage, the third transistor T3 is turned on in response to a reset signal on the reset line Rese, and the second gate G2 of the second transistor T2 is connected to the initialization voltage line Vinit through the third transistor T3, so that the voltage of the second gate G2 of the driving transistor T1 is reset to the voltage of the initialization voltage line Vinit.

[0229] During the compensation phase, the first transistor T1 and the fourth transistor T4 are turned on in response to the scan signal on the scan line Gat. In this case, the second transistor T2 is diode-connected and forward-biased. The voltage of the second gate G2 of the second transistor T2 is the sum of the voltage Vdata from the data signal on the data cable Dat and the threshold voltage Vth (negative quantity) of the second transistor T2, i.e., Vdata+Vth. At this time, the voltage of the first electrode plate C1 of the capacitor Cst is Vdata+Vth, and the voltage of the second electrode plate C2 of the capacitor Cst is the voltage ELVDD of the power cable VDD. The capacitor Cst is charged with a charge corresponding to the voltage difference between the first electrode plate C1 and the second electrode plate C2.

[0230] During the light-emitting stage, the fifth transistor T5 and the sixth transistor T6 are turned on in response to a control signal on the control line EM. A driving current Id is generated according to the voltage difference between the voltage of the second gate G2 of the second transistor T2 and the voltage of the power cable VDD, and the driving current Id is supplied to the light-emitting element D by the sixth transistor T6. During the light-emitting stage, the gate-source voltage Vgs of the second transistor T2 is maintained at (Vdata+Vth)-ELVDD. The driving current Id is proportional to (Vdata-ELVDD)2. Therefore, the driving current Id is independent of the threshold voltage Vth of the first transistor T1.

[0231] Furthermore, in the reset stage, the seventh transistor T7 is turned on in response to a reset signal on the reset line Rese. The seventh transistor T7 may be turned on simultaneously with the first transistor T1 and the fourth transistor T4. When the second transistor T2 is turned off, a portion of the driving current Id may flow out of the seventh transistor T7 as a bypass current Ibp to prevent the driving current Id from driving the light-emitting element D to emit light.

[0232] In addition, the display substrate 01 and other components of the display device 03 (e.g., image data encoding / decoding device, clock circuit, etc.) can use applicable components, which should be understood by those skilled in the art, and are omitted here and should not be considered as limitations on the present disclosure.

[0233] At least one embodiment of the present disclosure further provides a display device including any of the above-described display substrates of the present disclosure, which can be implemented as any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigation device.

[0234] Although the present disclosure has been described in detail above using general descriptions and specific embodiments, some modifications or improvements can be made based on the examples of the present disclosure, which are obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure fall within the scope of protection claimed by the present disclosure.

[0235] The above descriptions are merely exemplary embodiments of the present disclosure, but are not used to limit the protection scope of the present disclosure, which is determined by the appended claims. [Explanation of symbols]

[0236] 01 Display board 03 Display device 10 Display area 11 1st display area 12 Second display area 20 First signal line 21 First main body part 22 First winding section 60 Connection wiring 411 first light-emitting element 412 first pixel circuit D1 1st direction

Claims

1. a base substrate including a display area and a peripheral area surrounding at least a portion of the display area, the display area including a first display area, a second display area, and a third display area, the second display area surrounding the first display area, and the third display area surrounding at least a portion of the second display area; a plurality of first pixel units including a plurality of first light-emitting elements located in the first display region and a plurality of first pixel circuits located in the second display region, wherein the first pixel circuits and corresponding first light-emitting elements are electrically connected via connection wiring, the first pixel circuits are configured to drive the corresponding first light-emitting elements, and orthogonal projections of the plurality of first pixel circuits on the base substrate do not overlap with orthogonal projections of the plurality of first light-emitting elements on the base substrate; a plurality of third pixel units located in the third display area, each of the third pixel units including a third light-emitting element and a third pixel circuit, the third pixel circuit configured to drive a corresponding one of the third light-emitting elements, and an orthogonal projection of the third pixel circuit on the base substrate overlaps with an orthogonal projection of the corresponding one of the third light-emitting elements on the base substrate; at least one first signal line located at least in the second display area and the third display area, the first signal line including a first body portion, a first winding portion, and a second winding portion, the first body portion including a first sub-portion and a second sub-portion located on opposite sides of the first display area, the first winding portion located in the second display area and electrically connected to the first sub-portion and the second sub-portion, respectively, the second winding portion located in at least one of the second display area and the peripheral area and electrically connected to the first body portion, and the second winding portion electrically connected to a corresponding first pixel circuit; Including, Display board.

2. the first winding portion includes a first line segment, a second line segment, and a third line segment that are connected in sequence; an end of the first line segment that is not connected to the second line segment is connected to an end of the first sub-portion that is close to the second sub-portion, an end of the third line segment that is not connected to the second line segment is connected to an end of the second sub-portion that is close to the first sub-portion, the second line segment extends along a first direction, and the first line segment and the third line segment extend along a second direction that intersects with the first direction; The display substrate according to claim 1 .

3. the at least one first signal line is further located in the peripheral region, and the second winding portion includes a first sub-line portion and a second sub-line portion that are sequentially connected; the first sub-line portion is located in the peripheral region and extends along the second direction, and the second sub-line portion extends from the peripheral region to the second display region along the first direction and is electrically connected to the first pixel circuit. The display substrate according to claim 2 .

4. the second winding section includes a first sub-wire section and a second sub-wire section that are connected in sequence; Both the first sub-line portion and the second sub-line portion are located in the second display area, the first sub-line portion extends along the second direction, and the second sub-line portion extends along the first direction and is electrically connected to the first pixel circuit. The display substrate according to claim 2 .

5. the at least one first signal line is further located in the peripheral region, and the second winding portion includes a first sub-line portion and a second sub-line portion that are sequentially connected; the first sub-line portion extends along the second direction, the second sub-line portion extends along the first direction and is electrically connected to the first pixel circuit, At least a part of the first sub-line portion is located in the peripheral region, and at least another part of the first sub-line portion is located in the second display region; At least a part of the second sub-line portion is located in the peripheral region, and at least another part of the second sub-line portion is located in the second display region. The display substrate according to claim 2 .

6. the plurality of first light-emitting elements and the first pixel circuits are in one-to-one correspondence, and each first pixel circuit is configured to drive one corresponding first light-emitting element; The display substrate according to claim 1 .

7. a plurality of second pixel units; the plurality of second pixel units are located in the second display area and include a plurality of second light-emitting elements and a plurality of second pixel circuits, the second pixel circuits are configured to drive corresponding second light-emitting elements, and orthogonal projections of the second pixel circuits on the base substrate and corresponding second light-emitting elements on the base substrate overlap; the plurality of first pixel circuits are located in gaps between the plurality of second pixel circuits, and the plurality of first pixel circuits and the plurality of second pixel circuits are arranged alternately. The display substrate according to claim 1 .

8. some second pixel circuits of the plurality of second pixel circuits are located in the second display area on opposite sides of the first display area, and the first sub-portion and the second sub-portion are electrically connected to the second pixel circuits located on opposite sides of the first display area, The display substrate according to claim 7 .

9. a distribution density per unit area of ​​the plurality of first light-emitting elements in the first display region is smaller than a distribution density per unit area of ​​the plurality of second light-emitting elements in the second display region; The display substrate according to claim 7 .

10. further including at least one second signal line; the at least one second signal line includes a second body portion extending along the second direction; a virtual extension line of the first body portion extending along the first direction and a virtual extension line of the second body portion extending along the second direction intersect within the first display area; a second body portion of the at least one second signal line electrically connected to at least one first pixel circuit so as to transmit a second drive signal, which is different from a first drive signal transmitted by the first signal line, to the at least one first pixel circuit; The display substrate according to claim 2 .

11. the first winding portion is an arcuate wire, a first end of the arcuate wire is connected to an end of the first sub-portion that is closer to the second sub-portion, and a second end of the arcuate wire is connected to an end of the second sub-portion that is closer to the first sub-portion; The display substrate according to claim 1 .

12. the at least one first signal line further includes a third winding portion; a first end of the third winding portion electrically connected to the first sub-portion, a second end of the third winding portion electrically connected to a corresponding first pixel circuit, and the first pixel circuit connected to the second winding portion is different from the first pixel circuit connected to the third winding portion; The display substrate according to claim 4 .

13. the third winding portion includes a third sub-wire portion and a fourth sub-wire portion that are connected in sequence; an end of the third sub-wire portion that is not connected to the fourth sub-wire portion becomes a first end of the third winding portion, and an end of the fourth sub-wire portion that is not connected to the third sub-wire portion becomes a second end of the third winding portion, the third sub-line portion extends along the second direction and is arranged in parallel with the first sub-line portion in the first direction; the fourth sub-line portion extends along the first direction and is arranged in parallel with the first sub-line portion in the second direction; The display substrate according to claim 12 .

14. the first body portion, the first winding portion, and the second sub-winding portion are located on a first electrode layer of the display substrate; the first sub-line portion is located on a second electrode layer of the display substrate; the first electrode layer and the second electrode layer overlap in a normal direction of a display surface of the display substrate, the first sub-line portion is electrically connected to the second sub-portion and the second sub-line portion through a first via hole and a second via hole in an insulating layer between the first electrode layer and the second electrode layer, respectively; The display substrate according to claim 3 .

15. each of the at least one first pixel circuit includes a thin film transistor; the thin film transistor includes a gate, a source, and a drain; the source and the drain are located on the first electrode layer, and the gate is located on the second electrode layer; The display substrate according to claim 14 .

16. the at least one second signal line further includes a fourth winding portion, the fourth winding portion being wired so as to deviate from an imaginary extension line of the second body portion along the second direction; the second body portion includes a third sub-portion and a fourth sub-portion separated by the first display area, the third sub-portion and the fourth sub-portion being electrically connected via the fourth winding portion; the fourth winding portion is wired offset from a virtual connecting line extending along the second direction and located between the third sub-portion and the fourth sub-portion. The display substrate according to claim 10 .

17. Each of the at least one first pixel circuit includes a thin film transistor, the thin film transistor including a gate, a source, and a drain; the source, the drain, the first winding portion and the second signal line are all located on a first electrode layer of the display substrate, and the first body portion and the gate are located on a second electrode layer of the display substrate. The display substrate according to claim 16.

18. a portion of the connection wiring in the first display area is a transparent wiring; The display substrate according to claim 1 .

19. A display device comprising the display substrate according to claim 1 . Display device.

20. a sensor provided on a non-display side of the display substrate, overlapping the first display area in a direction normal to a display surface of the display substrate, and configured to receive and process an optical signal passing through the first display area; 20. The display device according to claim 19.

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