Semiconductor Devices

Abstract

To enable reduction of VF of a FWD and recovery loss in a RC-IGBT.SOLUTION: A semiconductor device includes a semiconductor substrate having a first surface and a second surface, and an insulated gate bipolar transistor (IGBT) and a diode formed on the semiconductor substrate, and the diode includes a first conductivity type drift layer formed in the semiconductor substrate so as to have a first region on the first surface side, a second conductivity type first body layer formed above the drift layer and having a second region adjacent to the first region, a second conductivity type first floating layer formed above the drift layer and having a third region adjacent to the first region, a first trench electrode formed in a region above the drift layer and adjacent to the first floating layer, and a first control gate formed above the first region.SELECTED DRAWING: Figure 4A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an insulated gate bipolar transistor (IGBT). [Background technology]

[0002] Trench-gate IGBTs are widely used as IGBTs with low on-resistance, i.e., low forward saturation voltage Vce(sat). RC-IGBTs (Reverse-Conducting IGBTs) have also been developed, which combine an IGBT and an FWD (Free Wheeling Diode) on a single chip.

[0003] Although RC-IGBTs have the advantage of being integrated into a single chip, there is a problem in that there is a limit to how much FWD performance can be improved. Specifically, this is due to the deterioration of FWD recovery loss and VF (forward voltage drop). To reduce FWD recovery loss, it is possible to introduce a lifetime killer. However, introducing a lifetime killer will worsen VF. Furthermore, introducing a lifetime killer will also worsen IGBT performance. Improvement measures other than lifetime killers are needed.

[0004] Patent Document 1 discloses a technique for suppressing the phenomenon of an increase in the VF of an FWD by providing a second FWD, thereby suppressing an increase in switching loss. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2018-182254 Summary of the Invention [Problem to be solved by the invention]

[0006] RC-IGBTs are required to achieve both VF reduction and recovery loss reduction without requiring a lifetime killer.

[0007] Other objects and novel features will become apparent from the description of this specification and the drawings. [Means for solving the problem]

[0008] A semiconductor device according to one embodiment includes a semiconductor substrate having a first surface and a second surface, an insulated gate bipolar transistor (IGBT) and a diode formed on the semiconductor substrate, and the diode includes: a drift layer of a first conductivity type formed in the semiconductor substrate to have a first region on the first surface side; a first body layer of a second conductivity type formed above the drift layer to have a second region adjacent to the first region; a first floating layer of the second conductivity type formed above the drift layer to have a third region adjacent to the first region; a first trench electrode formed above the drift layer in a region adjacent to the first floating layer; and a first control gate formed above the first region. [Effects of the Invention]

[0009] In the semiconductor device according to one embodiment, it is possible to reduce the VF of the FWD and the recovery loss. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view of a semiconductor chip according to a first embodiment. [Figure 2] FIG. 2 is a plan view of the semiconductor chip according to the first embodiment. [Figure 3A] FIG. 3A is a plan view of an IGBT region of the semiconductor chip according to the first embodiment. [Figure 3B] FIG. 3B is a cross-sectional view of the IGBT region of the semiconductor chip according to the first embodiment. [Figure 4A] FIG. 4A is a plan view of a diode region of a semiconductor chip according to the first embodiment. [Figure 4B]FIG. 4B is a cross-sectional view of the diode region of the semiconductor chip according to the first embodiment.

[0011] [Figure 5] FIG. 5 is a circuit diagram for explaining the operation of the semiconductor chip according to the first embodiment. [Figure 6] FIG. 6 is a timing chart for explaining the operation of the semiconductor chip according to the first embodiment. [Figure 7] FIG. 7 is a diagram for explaining the operation of the semiconductor chip according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view of a diode region of the semiconductor chip according to the first embodiment. [Figure 9] FIG. 9 is a timing chart for explaining the operation of the semiconductor chip according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a diode region of a semiconductor chip according to the first embodiment. [Figure 11] FIG. 11 is a timing chart for explaining the operation of the semiconductor chip according to the second embodiment. [Figure 12] FIG. 12 is a timing chart for explaining the operation of the semiconductor chip according to the second embodiment. [Figure 13] FIG. 13 is a timing chart for explaining the operation of the semiconductor chip according to the third embodiment. [Figure 14] FIG. 14 is a timing chart for explaining the operation of the semiconductor chip according to the third embodiment. [Figure 15] FIG. 15 is a plan view of a diode region of a semiconductor chip according to the fourth embodiment. [Figure 16] FIG. 16 is a plan view of a diode region of a semiconductor chip according to the fifth embodiment. [Figure 17] FIG. 17 is a plan view of a diode region of a semiconductor chip according to the sixth embodiment. [Figure 18] FIG. 18 is a plan view of a semiconductor chip according to the seventh embodiment. [Figure 19] FIG. 19 is a cross-sectional view of a semiconductor chip according to the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] A semiconductor device according to one embodiment will be described in detail below with reference to the drawings. In the specification and drawings, identical or corresponding components are designated by the same reference numerals, and duplicate explanations will be omitted. For the sake of convenience, some components may be omitted or simplified in the drawings. At least some of the embodiments may be combined with each other in any desired manner.

[0013] [Embodiment 1] (Configuration of semiconductor device) FIG. 1 is a plan view of a semiconductor chip (RC-IGBT) 100, which is a semiconductor device according to the first embodiment. In FIG. 1, the insulating film is shown as being transparent for ease of understanding. As shown in FIG. 1, most of the front surface (first surface) of the semiconductor chip 100 is covered with an emitter electrode 1, and a gate electrode 2 is formed on the outer periphery of the emitter electrode 1. In addition, a collector electrode (also used as a cathode electrode) 3 is formed on the back surface (second surface) of the semiconductor chip 100. An emitter potential is supplied to the emitter electrode 1, and a gate potential is supplied to the gate electrode 2.

[0014] Fig. 2 is an enlarged view of region 4 in Fig. 1. Region 5 is a region where an IGBT is formed. Region 6 is a region where a diode (FWD) is formed.

[0015] FIG. 3A is an enlarged view of the IGBT region (region 5). FIG. 3B is a cross-sectional view taken along line A-A' in FIG. 3A. The IGBT of the first embodiment is a GE-S type (GE type shrink structure) IGBT, which is a type of IE type IGBT. As shown in FIGS. 3A and 3B, the IGBT region includes an emitter electrode 1, a collector electrode (cathode electrode) 3, a p++ type collector layer 15, an n+ type field stop layer 16, and an n- type drift layer 11 formed on a semiconductor substrate. The IGBT region further includes a gate potential trench electrode (also referred to as a gate potential trench gate) 7 to which a gate potential is supplied, and an emitter potential trench electrode (also referred to as an emitter potential trench gate) 9 to which an emitter potential is supplied. An n+ type hole barrier layer 17 is formed between the gate potential trench electrode 7 and the emitter potential trench electrode 9. The region formed by the gate potential trench electrode 7, the emitter potential trench electrode 9, and the hole barrier layer 17 is an active cell region. Between the two active cell regions, a p+ type floating layer 8 (non-active cell region) is formed.

[0016] The emitter potential trench electrode 9 is connected to the emitter electrode 1 via a contact hole. The emitter electrode 1 is connected to a p+ type latch-up prevention layer 21 via a contact hole and a body contact. An n+ type emitter layer 14 and a p+ type body layer 20 are formed between the gate potential trench electrode 7 and the contact hole of the emitter electrode 1. The emitter layer 14 and the body layer 20 are connected to the emitter electrode 1 via a contact hole. In FIG. 3A, 10 denotes a body contact Si (Silicon) trench, 12 denotes a p+ type impurity layer, and 13 denotes an FC-GATE (Floating layer Control GATE). In FIG. 3B, 18 denotes a gate insulating film, and 19 denotes an interlayer insulating film.

[0017] As shown in FIG. 3A , the gate potential trench electrode 7 has a shape with a straight portion extending in the Y-axis direction (first direction) and a bent portion extending in the X-axis direction (second direction), or more simply, an L-shape (referred to as the first shape or first gate potential trench electrode). Furthermore, the gate potential trench 7 has a shape (referred to as the second shape or second gate potential trench electrode) that is symmetrical to the first shape with respect to a line parallel to the X-axis. An n-type drift layer 11 and a p+ type impurity layer 12 are formed in the region sandwiched between the first and second shapes. Furthermore, an FC-GATE 13 is formed on top of the n-type drift layer 11 and the p+ type impurity layer 12 in the region sandwiched between the first and second shapes. The FC-GATE 13 is made of Polycrystalline Silicon (Poly-Si) and is connected to the gate electrode 2.

[0018] FIG. 4A is an enlarged view of the diode region (region 6). FIG. 4B is a cross-sectional view taken along line CC' in FIG. 4A. As shown in FIGS. 4A and 4B, the diode region includes an emitter electrode 1, a cathode electrode (also serving as a collector electrode) 3, an n++-type cathode layer 22, an n+-type field-stop layer 16, and an n--type drift layer 11 formed on a semiconductor substrate. Similarly to the IGBT region, the diode region also includes a gate potential trench electrode 7, an emitter potential trench electrode 9, a body contact Si groove 10, a p+-type floating layer 8, an n+-type hole barrier layer 17, a gate insulating film 18, an interlayer insulating film 19, a p+-type body layer 20, a p+-type latch-up prevention layer 21, an FC-GATE 13, and a p+-type impurity layer 12.

[0019] (Operation of semiconductor device) Next, the operation of the semiconductor chip 100 (RC-IGBT) according to the first embodiment will be described with reference to FIGS.

[0020] Before describing the operation of the diode (diode region), which is a feature of the first embodiment, the operation of the IGBT (IGBT region) will be described first. When the IGBT is turned off, a negative voltage (e.g., −15 V) is applied to the gate. When a negative voltage is applied to the gate, a negative voltage is also applied to FC-GATE 13. The upper view of FIG. 7 is a cross-sectional view taken along line B-B′ in FIG. 3A. Note that the upper view of FIG. 7 also serves as a cross-sectional view taken along line D-D′ in FIG. 4A. As shown in FIG. 7, an n-type drift layer 11 is also formed in a region (fourth region) on the surface of the semiconductor substrate. The impurity layer 12 and the body layer 20 are both p+ type, and therefore are collectively referred to as a body layer. The p+ type body layer is formed in a region (fifth region) on the surface of the semiconductor substrate adjacent to the region (fourth region) on the surface of the drift layer 11. The p+ type floating layer 8 is formed in a region (sixth region) on the surface of the semiconductor substrate adjacent to the region (fourth region) on the surface of the drift layer 11.

[0021] When a negative voltage is applied to FC-GATE 13, as shown in the upper diagram of Figure 7, holes gather on the surface of n- type drift layer 11, forming a hole path from p+ type floating layer 8 to p+ type body layer 20. When the hole path is formed, carriers (holes) in floating layer 8 are discharged to emitter electrode 1. Therefore, at the time of turn-off, the discharge of carriers is promoted, enabling high-speed turn-off.

[0022] On the other hand, when the IGBT is turned on, a positive voltage (e.g., +15 V) is applied to the gate. When a positive voltage is applied to the gate, a positive voltage is also applied to the FC-GATE 13. When a positive voltage is applied to the FC-GATE 13, the hole path described above is not formed. Therefore, the carrier discharge suppression function (carrier accumulation function) of the floating layer 8 functions, and the IE effect can be obtained. The IE effect improves switching loss when the IGBT is turned on.

[0023] Next, the operation of the diode (diode region), which is a feature of the first embodiment, will be described. As shown in Fig. 7, in the diode region, n- type drift layer 11 is also formed in a region (first region) on the surface of the semiconductor substrate. A p+ type body layer is formed in a region (second region) on the surface of the semiconductor substrate adjacent to the region (first region) on the surface of drift layer 11. A p+ type floating layer 8 is formed in a region (third region) on the surface of the semiconductor substrate adjacent to the region (first region) on the surface of drift layer 11.

[0024] Fig. 5 is a circuit diagram for explaining the operation of RC-IGBT. As shown in Fig. 5, RC-IGBT1 is arranged on the high side and RC-IGBT2 is arranged on the low side. RC-IGBT1 and RC-IGBT2 have the structure of the RC-IGBT described above.

[0025] First, a case where the RC-IGBT2 is changed from the on state to the off state will be described. Fig. 6 is a timing chart for explaining the operation of the RC-IGBT1 and the RC-IGBT2.

[0026] When RC-IGBT2 is in the on state, a positive voltage (+15 V) is applied to the gate of RC-IGBT2. At this time, RC-IGBT1 is in the off state, and 0 V is applied to the gate of RC-IGBT1. Current flows through coil L via RC-IGBT2. Next, when a negative voltage is applied to the gate of RC-IGBT2, RC-IGBT2 turns off. When RC-IGBT2 turns off, current flows from coil L to Diode 1, which is the FWD of RC-IGBT1. In the first embodiment, a negative voltage is applied to the gate of RC-IGBT1 just before RC-IGBT2 turns off. When a negative voltage is applied to the gate of RC-IGBT1, a negative voltage is also applied to FC-GATE 13 of RC-IGBT1. When a negative voltage is applied to FC-GATE 13, the IGBT of RC-IGBT1 turns off. The operation of Diode 1 when a negative voltage is applied to FC-GATE 13 is as follows. As shown in the upper diagram of Figure 7, holes gather on the surface (first region) of the drift layer 11 in the diode region, forming a p-type inversion layer. When the p-type inversion layer is formed, the p+ floating layer 8, p+ impurity layer 12, and p+ body layer 20 in the diode region are connected, and the floating layer 8 functions as an anode layer. Therefore, the p+ floating layer 8 (anode layer) and the n- drift layer (cathode layer) in the diode region function as a diode (FWD) (the diode in Figure 4B). The entire floating layer 8 functions as an anode layer, increasing the diode area and reducing the VF when current flows. The p+ body layer 20 also functions as an anode, but an n+ hole barrier layer 17 is formed below the body layer 20. Because no hole barrier layer is formed below the floating layer 8, the carrier injection amount can be increased compared to the body layer 20 (contributing to a reduced VF). Therefore, more current flows through the diode formed by the floating layer 8 (the lower diagram of Figure 7 and Figure 8).

[0027] Next, a case where the RC-IGBT2 is changed from the OFF state to the ON state will be described. Fig. 9 is a timing chart for explaining the operation of the RC-IGBT1 and the RC-IGBT2.

[0028] When the gate voltage of the RC-IGBT2 is changed from a negative voltage to a positive voltage, the RC-IGBT2 changes from an off state to an on state. When the RC-IGBT2 is turned on, a current flows through the coil L via the RC-IGBT2. Also, no current flows through the diode 1. In the first embodiment, before the RC-IGBT2 is turned on, the gate voltage of the RC-IGBT1 is changed from a negative voltage to 0 V. When the gate voltage of the RC-IGBT1 becomes 0 V, the FC-GATE 13 of the RC-IGBT1 also becomes 0 V. When the FC-GATE 13 becomes 0 V, the inversion layer formed on the surface of the drift layer 11 in the diode region disappears. The floating layer 8 in the diode region no longer functions as an anode layer, and the body layer 20 in the diode region functions as an anode layer (FIG. 10). Therefore, the amount of carrier accumulation due to the floating layer 8 decreases, and the recovery loss of the diode can be reduced.

[0029] (effect) As described above, in the semiconductor chip (RC-IGBT) 100 according to the first embodiment, the FC-GATE 13 is provided in the diode region, making it possible to control whether the floating layer 8 functions as an anode layer. This makes it possible to reduce the VF of the FWD and the recovery loss.

[0030] [Embodiment 2] (Configuration of semiconductor device) The configuration of the semiconductor chip (RC-IGBT) according to the second embodiment is the same as that of the first embodiment, except for the method of controlling the RC-IGBT.

[0031] (Operation of semiconductor device) The operation of the RC-IGBT according to the second embodiment will be described with reference to FIGS. 11 and 12. FIG. 11 shows a case where the RC-IGBT2 is changed from the on state to the off state. The difference from the first embodiment is the voltage applied to the FC-GATE 13 of the RC-IGBT1 immediately before the RC-IGBT2 is changed to the off state. The negative voltage applied to the FC-GATE 13 is larger than that in the first embodiment (for example, −15 V). This puts the surface of the drift layer 11 in the diode region surrounded by the FC-GATE 13 into a strong inversion state. The connection between the floating layer 8 and the body layer 20 in the diode region is strengthened, making it possible to further reduce the VF compared to the first embodiment.

[0032] 12 shows the case where the RC-IGBT2 is changed from the OFF state to the ON state. The difference from the first embodiment is that a positive voltage pulse is applied to the FC-GATE 13 of the RC-IGBT1 immediately before the RC-IGBT2 is turned ON. This improves the ability to break the connection between the floating layer 8 and the body layer 20 in the diode region, making it possible to further reduce recovery loss compared to the first embodiment.

[0033] (effect) As described above, in the semiconductor chip (RC-IGBT) according to the second embodiment, it is possible to further reduce the VF of the FWD and the recovery loss compared to the first embodiment.

[0034] [Embodiment 3] (Configuration of semiconductor device) In the first and second embodiments, the FC-GATE 13 is connected to the gate electrode, but in the third embodiment, the FC-GATE 13 is connected to an electrode independent of the gate electrode.

[0035] (Operation of semiconductor device) The operation of the RC-IGBT according to the third embodiment will be described with reference to FIGS. 13 and 14. FIG. 13 shows a case where the RC-IGBT 2 is changed from an on state to an off state. The difference from the first and second embodiments is the voltage applied to the FC-GATE 13 of the RC-IGBT 1. A larger negative voltage (e.g., −20 V) is applied to the FC-GATE 13 than in the second embodiment. This further strengthens the connection between the floating layer 8 and the body layer 20 in the diode region, enabling a further reduction in VF than in the second embodiment.

[0036] FIG. 14 shows the case where the RC-IGBT2 is changed from the OFF state to the ON state. The difference from the first and second embodiments is the voltage applied to the FC-GATE 13 of the RC-IGBT1 immediately before the RC-IGBT2 is turned ON. A higher voltage (e.g., +20 V) is applied to the FC-GATE 13 than in the first and second embodiments. This further improves the ability to break the connection between the floating layer 8 in the diode region and the body layer 20, making it possible to further reduce recovery loss than in the first and second embodiments. Note that the FC-GATE 13 is independent of the gate electrode, so applying +20 V to the FC-GATE 13 does not cause the RC-IGBT1 to turn ON.

[0037] The voltage applied to FC-GATE 13 depends on the guaranteed voltage of the gate structure. If the guaranteed voltage is high (e.g., ±30 V), it becomes possible to further reduce VF and recovery loss.

[0038] (effect) As described above, in the semiconductor chip (RC-IGBT) according to the third embodiment, the FC-GATE 13 can be controlled independently of the gate electrode. This makes it possible to further reduce the VF of the FWD and the recovery loss compared to the first and second embodiments.

[0039] [Embodiment 4] (Configuration of semiconductor device) 15 is an enlarged view of the diode region (region 6) of the semiconductor chip according to the fourth embodiment. The differences from the first embodiment are the gate potential trench electrode 7 and the FC-GATE 13. Compared to the first embodiment, the distance E between the first and second shapes of the gate potential trench electrode 7 is wider. By widening the distance E, the amount of carrier conduction increases when the floating layer 8 in the diode region operates as an anode layer, and the VF of the FWD is reduced.

[0040] (effect) As described above, in the semiconductor chip (RC-IGBT) according to the fourth embodiment, the VF of the FWD can be further reduced compared to the first embodiment.

[0041] [Embodiment 5] (Configuration of semiconductor device) 16 is an enlarged view of the diode region (region 6) of the semiconductor chip according to the fifth embodiment. As shown in FIG. 16, a plurality of gate potential trench electrodes 7 are formed to extend in the X-axis direction. FC-GATE 13 is formed on the plurality of gate potential trench electrodes 7 and the drift layer 11 between the gate potential trench electrodes 7.

[0042] (Operation of semiconductor device) The operation of the semiconductor chip according to the fifth embodiment is the same as that of the first to fourth embodiments, except that a plurality of hole paths are generated between the gate potential trench electrodes 7.

[0043] In the fifth embodiment, the gate capacitance of the FC-GATE 13 differs between the IGBT region and the diode region. If the gate capacitance differs, the switching timing of the IGBT and the diode may differ from what is expected. To address this issue, it is desirable to make the FC-GATE 13 controllable independently of the gate electrode (third embodiment).

[0044] (effect) As described above, in the semiconductor chip (RC-IGBT) according to the fifth embodiment, similarly to the first embodiment, it is possible to reduce the VF of the FWD and the recovery loss.

[0045] [Embodiment 6] (Configuration of semiconductor device) 17 is an enlarged view of the diode region (region 6) of the semiconductor chip according to the sixth embodiment. As shown in FIG. 17, in the sixth embodiment, the gate potential trench electrode 7 is not formed in the diode region. The FC-GATE 13 is formed in the upper part of the drift layer 11 between the floating layer 8 and the p+ type impurity layer 12. The structure is the same as that of the first embodiment, except that the gate potential trench electrode is not formed in the diode region.

[0046] (Operation of semiconductor device) The operation of the semiconductor chip according to the sixth embodiment is the same as that of the first to fifth embodiments, except that a hole path is formed over the entire surface of the drift layer 11 in the diode region surrounded by the FC-GATE 13 .

[0047] (effect) As described above, in the semiconductor chip (RC-IGBT) according to the sixth embodiment, similarly to the first embodiment, it is possible to reduce the VF of the FWD and the recovery loss.

[0048] [Embodiment 7] (Configuration of semiconductor device) In the first to sixth embodiments, the IGBT region and the diode region are separated in the X-axis direction of the semiconductor chip. In the seventh embodiment, the IGBT region and the diode region are separated in the Y-axis direction of the semiconductor chip. FIG. 18 is an enlarged view of the surface of the semiconductor chip according to the seventh embodiment. FIG. 19 is a cross-sectional view taken along line F-F' in FIG. 18. As shown in FIGS. 18 and 19, the IGBT region and the diode region are alternately formed in the Y-axis direction of the semiconductor chip.

[0049] 18, the IGBT region is formed in the linear portion of the gate potential trench electrode 7 in the Y-axis direction. Moreover, the FC-GATE 13 is not formed in the IGBT region. Since the elements constituting the IGBT are the same as those in the first embodiment, details are omitted.

[0050] 18, the diode region is formed in the bent portion of the gate potential trench electrode 7 in the X-axis direction. Also, an FC-GATE 13 similar to that in the first embodiment is formed in the diode region. Since the elements forming the diode are similar to those in the first embodiment, details are omitted.

[0051] (Operation of semiconductor device) Next, an operation of the semiconductor chip (RC-IGBT) according to the seventh embodiment will be described. In the seventh embodiment, the FC-GATE 13 is not formed in the IGBT region. Therefore, the IGBT region of the seventh embodiment operates in the same manner as a general IGBT.

[0052] In the diode region of the seventh embodiment, the same FC-GATE 13 as in the first embodiment is formed. Therefore, the diode region operates in the same manner as in the first embodiment.

[0053] (effect) As described above, in the semiconductor chip (RC-IGBT) according to the seventh embodiment, similarly to the first embodiment, it is possible to reduce the VF of the FWD and the recovery loss.

[0054] The present invention is not limited to the above-described embodiments and may be modified in various ways without departing from the spirit of the present invention. For example, in the first embodiment, a GE-S type IGBT is used, but this is not limiting. GGEE type, EGE type, and the like can also be used. Furthermore, for example, the gate potential trench electrode 7 is L-shaped, but it may have a P-loop shape. [Explanation of symbols]

[0055] 100 Semiconductor chips (RC-IGBT) 1 Emitter electrode 2 gate electrode 3 Collector electrode (cathode electrode) 5 IGBT area 6 Diode Region 7 Gate potential trench 8 p+ type floating layer 9 Emitter potential trench electrode 10 Body contact silicon groove 11 n-type drift layer 12 p+ type impurity layer 13 FC-GATE 14 n+ type emitter layer 15 p++ type collector layer 16 n+ type field stop layer 17 n+ type hole barrier layer 18 Gate insulating film 19 Interlayer insulating film 20 p+ type body layer 21 p+ type latch-up prevention layer 22 n++ type cathode layer

Claims

1. a semiconductor substrate having a first surface and a second surface; an insulated gate bipolar transistor (IGBT) and a diode formed on the semiconductor substrate; The diode is a drift layer of a first conductivity type formed in the semiconductor substrate so as to have a first region on the first surface side; a first body layer of a second conductivity type formed on the drift layer of the first conductivity type to have a second region adjacent to the first region; a first floating layer of the second conductivity type formed on the drift layer of the first conductivity type to have a third region adjacent to the first region; a first trench electrode formed in an upper portion of the first conductivity type drift layer and in a region adjacent to the second conductivity type first floating layer; a first control gate formed over the first region; The IGBT is second and third trench electrodes formed on the first surface side above the first conductivity type drift layer; a hole barrier layer of the first conductivity type formed on the drift layer of the first conductivity type and between the second and third trench electrodes; a second body layer of the second conductivity type formed on the hole barrier layer of the first conductivity type; an emitter layer of the first conductivity type formed on the first surface side of the second body layer of the second conductivity type, Semiconductor device.

2. 2. The semiconductor device according to claim 1, a first electrode formed on the first surface; a second electrode formed on the second surface, the first and second body layers of the second conductivity type and the emitter layer of the first conductivity type are electrically connected to the first electrode; Semiconductor device.

3. 3. The semiconductor device according to claim 2, The diode further includes fourth trench electrodes formed to sandwich the first region. Semiconductor device.

4. 3. The semiconductor device according to claim 2, the first, second, and third trench electrodes extend in a first direction in a plan view; the diode and the IGBT are formed adjacent to each other in a second direction in a plan view. Semiconductor device.

5. 3. The semiconductor device according to claim 2, the IGBT further comprises a second floating layer of the second conductivity type and a second control gate; the first conductivity type drift layer is formed to have a fourth region on the first surface side, the second body layer of the second conductivity type is formed to have a fifth region adjacent to the fourth region; the second floating layer of the second conductivity type is formed to have a sixth region adjacent to the fourth region, the second control gate is formed on the fourth region. Semiconductor device.

6. 6. The semiconductor device according to claim 5, the second trench electrode has portions sandwiching the fourth region; Semiconductor device.

7. 7. The semiconductor device according to claim 6, further comprising a third electrode formed on the first surface; the second and fourth trench electrodes and the first and second control gates are electrically connected to the third electrode; Semiconductor device.

8. 3. The semiconductor device according to claim 2, When a negative voltage is applied to the first control gate, the first floating layer of the second conductivity type operates as an anode. Semiconductor device.

9. 9. The semiconductor device according to claim 8, When a positive voltage is applied to the first control gate, the first floating layer of the second conductivity type does not function as an anode. Semiconductor device.

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