Plasma processing apparatus and plasma processing method

Abstract

In order to provide a plasma-processing method capable of suppressing the adhesion of charged foreign matter to a sample in plasma etching processing and thereby reducing the amount of foreign matter, the present invention provides a plasma-processing method comprising: providing a plasma-processing chamber for processing a sample using plasma, a high-frequency power supply for supplying high-frequency power for generating the plasma, an electrostatic adsorption electrode for applying a voltage to the sample and electrically adsorbing and securing the sample in place, and a DC power supply for applying a voltage to the electrostatic adsorption electrode; an ignition step for generating plasma using the high-frequency power supply for the sample placed on the electrostatic adsorption electrode; a plasma discharge step for etching the sample after the ignition step; and a static elimination step for canceling the adsorption fixing by static elimination after the plasma discharge step, wherein, for the sample, during the period from the ignition step to the static elimination step, the voltage applied to the electrostatic adsorption electrode is greater than 0 V.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device manufacturing technology, and more particularly to a plasma processing apparatus and a plasma processing method suitable for suppressing adhesion of foreign matter during plasma etching processing. [Background technology]

[0002] Recent semiconductor device development has been moving toward ever-increasing circuit miniaturization and higher integration, as evidenced by roadmaps such as the International Roadmap for Devices and Systems (IRDS). Amid this trend, semiconductor manufacturing equipment is required to meet ever-higher specifications in terms of both processing precision and mass productivity. One of the requirements is the prevention of foreign matter adhesion to sample substrates (wafers). As the pitch width of semiconductor devices shrinks, small particles that were previously ignored are now attracting attention as a cause of processing defects. Specifically, it is predicted that non-electrically active particles with a diameter of 7 nm or greater will become critical particles by 2025. Therefore, measures to prevent the adhesion of these particles to wafers will become increasingly important.

[0003] The above-mentioned contaminant issue is particularly important in plasma etching, a process used to etch samples in semiconductor manufacturing. In plasma etching, a wafer is placed on a sample stage inside a processing chamber, electrostatically attracted to prevent misalignment, and then exposed to plasma. By adjusting various processing conditions, such as the gas species introduced into the processing chamber and the high-frequency power applied to the wafer, specific laminated films on the wafer are selectively removed, forming fine circuit patterns on the wafer. If contaminants adhere to the wafer during the plasma processing, they can cause wiring breaks or short circuits, potentially resulting in fatal defects in semiconductor devices. Therefore, reducing contaminant concentrations is currently required to improve yield.

[0004] In response to the above-mentioned situation, several technologies have been proposed to prevent the adhesion of charged particles to the wafer surface, which is prone to occur in plasma processing equipment. For example, Patent Document 1 proposes an electrostatic adsorption method that prevents the attraction of charged particles to the wafer by adjusting the voltage applied to the wafer from the electrostatic adsorption electrode to a constant value and keeping the wafer surface potential close to ±0 V. However, with this electrostatic adsorption method, the wafer may become negatively charged due to the inflow of stray charges to the wafer during the etching process, and the charge state may not return to ±0 V after the plasma discharge is stopped. Because the wafer charging can attract charged particles in the sample chamber to the wafer, potentially reducing yield, it is desirable to eliminate the negative charge on the wafer. Patent Document 2 proposes an electrostatic adsorption method for preventing negative charging on wafers during plasma etching processes.

[0005] Patent Document 2 describes that the inflow of stray charges into the wafer during plasma processing of the wafer causes the wafer surface potential to change in the negative direction, and that after the plasma processing is completed, the wafer surface potential tends not to return to the state of ±0 V before the processing started. In response to this, the document discloses a technology in which, during the plasma discharge processing step of the wafer, the voltage applied to the wafer is shifted in the negative direction by a first shift amount so that the magnitude of the change in wafer potential due to the inflow of stray charges is equal to the amount of change in wafer potential due to the inflow of stray charges, and after the plasma discharge processing is completed, the DC voltage, which has been shifted in the negative direction by the first shift amount, is shifted in the positive direction by a second shift amount, thereby canceling out the charging of the wafer caused by the stray charges. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2009 / 013803 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-213358 Summary of the Invention [Problem to be solved by the invention]

[0007] In Patent Document 1, the applied voltage for electrostatically attracting the wafer is changed during the plasma etching process, but this control method does not take into account the current generation within the wafer that occurs due to abrupt fluctuations in the applied voltage. During the plasma etching process, abrupt fluctuations in the current within the wafer can cause the plasma generation state to become unstable. If the plasma state becomes unstable, it can induce abnormal discharge, causing the generation of foreign matter. Therefore, it is undesirable to suddenly change parameters such as the applied voltage.

[0008] Furthermore, although the technology described in Patent Document 2 can cancel out the charge on the wafer caused by floating charges, the inventors have found that the effect of suppressing adhesion of foreign matter is not sufficient.

[0009] An object of the present invention is to provide a plasma processing apparatus and a plasma processing method that can suppress the adsorption of charged foreign particles to a wafer while maintaining a stable plasma generation state, thereby reducing the adhesion of foreign particles to the wafer. [Means for solving the problem]

[0010] The present invention uses plasma wafer a processing chamber in which the plasma is processed; a high frequency power source that supplies high frequency power for generating the plasma; wafer of an electrostatic chucking electrode having a first electrode and a second electrode for electrostatically chucking the wafer; a sample stage on which the sample is placed; The first electrode, the second electrode To the electrode , the first voltage of opposite polarity, the second Voltage each A DC power supply is applied, and the plasma is ignited and wafer The period until the sample is released from the sample stage, the sum of the first voltage and the second voltage is positive so as to generate an average positive charge on the surface of the wafer; The plasma processing apparatus is provided with a control device that controls the DC power supply. [Effects of the Invention]

[0011] It is possible to provide a plasma processing apparatus and a plasma processing method that can suppress the adsorption of charged foreign matter to the wafer while maintaining a stable plasma generation state, thereby reducing the adhesion of foreign matter to the wafer. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic diagram showing a configuration of a plasma processing apparatus according to the present invention; [Figure 2] 4 is a time chart of a process according to the first embodiment of the present invention. [Figure 3] 1 is a time chart showing a first conventional example. [Figure 4] 1 shows the results of an investigation into the effect of reducing foreign matter adhesion to wafers according to Example 1. [Figure 5] 10 is a time chart of a process according to a second embodiment of the present invention. [Figure 6] 10 is a time chart of a process according to a development example of the second embodiment of the present invention. [Figure 7] 10 shows the results of an investigation into the effect of reducing foreign matter adhesion to wafers according to Example 2. [Figure 8] 10 is a time chart of a process according to a third embodiment of the present invention. [Figure 9] 10 shows the results of an investigation into the effect of reducing adhesion of foreign matter to wafers according to Example 3. [Figure 10] 10 is a time chart of a process according to a fourth embodiment of the present invention. [Figure 11] 10 is a time chart showing a second conventional example. [Figure 12] 10 shows the results of an investigation into the effect of reducing adhesion of foreign matter to wafers according to Example 4. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Note that the following is merely an embodiment, and the scope of the present application is not limited to the embodiment. [Example]

[0014] A first embodiment of the present invention will be described with reference to Figures 1 to 4. First, a plasma processing apparatus for carrying out the present invention will be described with reference to Figure 1. Figure 1 is a schematic diagram showing the configuration of a plasma processing apparatus according to the present invention.

[0015] In the plasma processing apparatus used in this embodiment, a wafer 1, which is a semiconductor substrate serving as a sample, is carried into a processing chamber 3, which is a vacuum processing chamber, through a gate 2 for wafer transport, and is placed on a sample stage 4 for placing the wafer.

[0016] This plasma processing apparatus includes a plasma generating mechanism comprising a solenoid coil 5, a high-frequency power supply 6 for generating microwaves, a microwave oscillator 7, a resonator 8, and a gas supply 9. Within the processing apparatus, a magnetic field is generated by the solenoid coil 5. The microwaves generated by the microwave oscillator 7 using high-frequency power from the high-frequency power supply 6 are introduced into the processing chamber 3 via the resonator 8. The microwaves impart energy to electrons within the magnetic field generated by the solenoid coil 5. These electrons ionize the gas supplied from the gas supply 9, thereby generating plasma.

[0017] During the plasma processing, a cooling gas is supplied to the backside of the wafer 1 to adjust the temperature of the wafer 1. To prevent the wafer 1 from shifting due to the cooling gas, the wafer 1 is attracted to the sample stage 4 by bipolar electrostatic chucking electrodes 10 and 11, which are electrodes with opposite polarities. The electrostatic chucking electrodes 10 and 11 are arranged concentrically, with one electrode 10 on the inside and the other electrode 11 on the outside.

[0018] Electrostatic chucking electrodes (hereinafter sometimes referred to as ESC) 10 and 11 are connected to independent DC power supplies 12 and 13, respectively. The DC power supply 12 is connected to the inner electrostatic chucking electrode 10, and the DC power supply 13 is connected to the outer electrostatic chucking electrode 11.

[0019] Although there is insulation between the electrostatic attraction electrode and the wafer, when a positive voltage is applied to the electrostatic attraction electrode, a negative charge is generated on the backside of the wafer near the electrode, and the wafer is attracted to the electrode by Coulomb force. Conversely, when a negative voltage is applied, a positive charge is generated on the backside of the wafer.

[0020] When a negative charge is generated on the back surface of the wafer, a positive charge is generated on the front surface of the wafer opposite the back surface, and the potential of the entire wafer becomes zero. Conversely, when a positive charge is generated on the back surface of the wafer, a negative charge is generated on the front surface of the wafer opposite the back surface.

[0021] Voltages of opposite polarities are applied from the respective DC power supplies to the electrostatic chucking electrodes 10 and 11. For example, a voltage of +800 V is applied to the inner electrostatic chucking electrode 10 from a DC power supply 12, and a voltage of −200 V is applied to the outer electrostatic chucking electrode 11 from a DC power supply 13.

[0022] As a result of investigations, the inventors have found that adhesion of foreign matter to the wafer surface can be suppressed by applying voltages to the electrostatic chucking electrodes under conditions such that the total value of the voltages applied to the electrostatic chucking electrodes (in the above case, (+800 V) + (-200 V) = (+600 V). Hereinafter, this voltage will be defined as the sum of the applied voltages) is positive. The theory is that a positive charge proportional to +800 V is generated on the wafer surface facing the inner electrostatic chucking electrode 10, and a negative charge proportional to -200 V is generated on the wafer surface facing the outer electrostatic chucking electrode 11, so that on average a positive charge is generated on the wafer surface, and foreign particles, which are often positively charged, are forced away from the wafer surface by Coulomb force. The results of experiments conducted by the present inventors are described below.

[0023] This plasma processing apparatus is equipped with a control device 14 for controlling the output values ​​of the DC power supplies 12 and 13. The variable DC voltages 12 and 13 are connected to the control device 14, and the voltage output values ​​are controlled by the control device 14. The control device 14 is also connected to the high frequency power supply 6 for generating μ-waves, and controls the power output value from the high frequency power supply 7 and the timing of output switching.

[0024] As described above, in this exemplary configuration of the plasma processing apparatus, a bipolar electrostatic chucking electrode is used to electrostatically chuck the wafer using two different DC power supplies. However, a monopolar electrostatic chucking electrode, in which one electrode is connected to ground, may also be used. Using a monopolar chucking electrode can further simplify the apparatus configuration, reducing the design difficulty and manufacturing costs of the plasma processing apparatus. Alternatively, a multipolar electrostatic chucking electrode, which uses three or more DC power supplies to electrostatically chuck the wafer, may also be used. Using a multipolar electrostatic chucking electrode makes it possible to locally control the voltage applied to the wafer, thereby adjusting the plasma distribution.

[0025] FIG. 2 is a time chart of a process according to Example 1 of the present invention. The contents of the present invention will be explained using the time chart. The plasma processing process shown in FIG. 2 is composed of three steps: an ignition step carried out between t2-1 and t2-3, a plasma discharge step carried out between t2-3 and t2-4, and a static elimination step carried out between t2-4 and t2-6. In addition, the "microwave incident power" in FIG. 2 is the high-frequency power from the high-frequency power supply located at the top of the processing chamber, the "ESC voltage (+)" is the positive voltage output from the DC power supply 12, and the "ESC voltage (-)" is the negative voltage output from the DC power supply 13.

[0026] 2, first, the wafer 1 is carried into the processing chamber 3 and placed on the sample stage 4. Next, at the timing of t2-1, a positive voltage and a negative voltage are simultaneously output from the DC power supplies 12 and 13 to the electrostatic chucking electrodes 10 and 11, respectively, to chuck the wafer 1 onto the sample stage 4.

[0027] The inventors have found that a net applied voltage of +1 V or greater to the electrostatic chucking electrode can reduce foreign matter. Furthermore, to stably chuck the wafer, the potential difference between the electrodes is preferably 1000 V or greater, from the viewpoint of maintaining the electrostatic chucking force of the wafer. In this embodiment, the ESC voltage (+) is set to +800 V and the ESC voltage (-) to -200 V, i.e., a net applied voltage of +600 V. Next, at the start of the ignition step at t2-2, a power of 1000 W is supplied from the high-frequency power supply 6 and a current is passed through the solenoid coil 5, thereby generating plasma in the processing chamber 3. Note that the supplied power here is set higher than that used in a typical plasma etching process to prevent plasma ignition failure. Next, at t2-3, the power supplied from the high-frequency power supply is changed to 800 W, and the plasma discharge step is initiated.

[0028] Next, at the start of the static elimination step at t2-4, the power supplied from the high-frequency power supply is changed to 450 W, gradually reducing the plasma discharge output. Next, at t2-5, the voltage supplied from the DC power supply to the electrostatic chucking electrode is changed to 0 V, stopping electrostatic chucking. Finally, at t2-6, the power supplied from the high-frequency power supply is changed to 0 W, completing the static elimination step (hereinafter sometimes referred to as the dechucking step).

[0029] Here, we will explain the plasma treatment process of Conventional Example 1 for comparing the level of foreign matter reduction effect with that of the above-mentioned Example 1. Fig. 3 shows a time chart of the conventional treatment corresponding to Conventional Example 1. Conventional Example 1 is a plasma treatment process in which the voltage values ​​of the ESC voltage (+) and the ESC voltage (-) are set to +500 V and -500 V, respectively, during the period from t3-1 to t3-6, and the net applied voltage during electrostatic attraction is changed to ±0 V.

[0030] An experiment was conducted to evaluate the number of foreign particles adhering to wafers after plasma etching for Example 1 and Conventional Example 1. In the experiment, the pressure inside the processing chamber 3 was set to 0.5 Pa, and a mixed gas of Ar and O2 was continuously supplied into the chamber from the start of the ignition step to the end of the neutralization step. The flow rates of Ar and O2 were set to 100 mL / min and 30 mL / min, respectively. The temperature of the sample stage 4 was set to 50°C, and He was used as the backside gas for cooling the wafer. The gas supply was maintained so that the backside pressure was maintained at 2 kPa.

[0031] In this experiment, the above plasma etching process was performed more than 30 times under each set of conditions, the number of particles adhering to the wafer in each run was tallied, and the median number of particles adhering under each set of conditions was compared. Note that in this experiment, the target particle size was set to 0.025 μm or larger.

[0032] Fig. 4 shows the results of an investigation into the effect of reducing the adhesion of foreign matter to wafers in Example 1. The vertical axis in Fig. 4 represents the converted value of the number of foreign matter adhesions when the number of foreign matter adhesions in Conventional Example 1 is normalized to 100%. In Fig. 4, in order to show the correlation between the voltage applied to the wafer and the number of foreign matter adhesions, two cases are shown: one in which the ESC voltage (+) between t2-1 and t2-5 is +600V and the ESC voltage (-) is -400V, i.e., the net applied voltage is +200V, and the other in which the ESC voltage (+) is +700V and the ESC voltage (-) is -300V, i.e., the net applied voltage is + 4 The results of the investigation in the case where the net applied voltage was set to +600V are also shown. As can be seen from these results, in the plasma treatment process of Example 1, in which the total value of the applied voltage for electrostatic attraction is maintained at a positive value between t2-1 and t2-5, the number of foreign particles decreased as the net applied voltage increased. Furthermore, in the results of Comparative Example 1, in which the net applied voltage was set to +600V, the number of foreign particles was reduced to less than half of that in Conventional Example 1. [Example]

[0033] FIG. 5 is a time chart of processing according to Example 2 of the present invention. The second example of the present invention will be described while noting the differences in configuration from Example 1. In FIG. 5, during the period from t5-3 to t5-4, the total value of the net applied voltage to the electrostatic chucking electrodes is changed to 0 V, which is different from the +600 V value adopted in Example 1 described above. The operating conditions during the period before t5-3 and the period after t5-4 in FIG. 5 are the same as those during the period before t2-3 and the period after t2-4 in the plasma processing process (FIG. 2) according to Example 1 described above, and therefore will not be described again.

[0034] As shown in FIG. 5, in this embodiment, at timing t5-3, the voltage value for electrostatic attraction is changed so that the net voltage applied to the electrostatic attraction electrodes from the DC power supplies 12 and 13 becomes 0 V. example In this example, to prevent a decrease in the electrostatic adsorption force of the wafer, the ESC voltage (+) and ESC voltage (-) are set to +600 V and -600 V, respectively, and the potential difference between the two electrodes is maintained at 1200 V. This control of the applied voltages can prevent the sudden parameter changes that occurred in the process employed in Patent Document 2, thereby suppressing fluctuations in the etching process due to changes in plasma distribution accompanying changes in wafer potential. Next, at timing t5-4, the total value of the net applied voltage to the electrostatic adsorption electrodes is changed again to a positive value, thereby preventing the adhesion of charged foreign matter, as described above.

[0035] In this embodiment, the total net voltage applied to the electrostatic chucking electrode during the plasma discharge step from t5-3 to t5-4 is set to 0 V. However, the plasma potential of the wafer may shift in the negative direction due to the inflow of stray charges during this period. In response to this, as an extension of the second embodiment, the net voltage applied to the electrostatic chucking electrode during this period may be set to a value shifted in the negative direction by the amount of the shift in the plasma potential. Figure 6 shows a time chart of a process according to an extension of the second embodiment of the present invention. Below, this extension will be described while taking into account the differences in configuration from the second embodiment.

[0036] 6, in the period from t6-3 to t6-4, the total value of the net applied voltage to the electrostatic chucking electrodes is changed to a value equal to or less than 0 V, which is different from the 0 V adopted in the above-described Example 2. The operating conditions in the period before t6-3 and the period after t6-4 in FIG. 6 are the same as the operations in the period before t5-3 and the period after t5-4 in the plasma processing process (FIG. 5) according to the above-described Example 2, and therefore a description thereof will be omitted.

[0037] 6, in this development, at timing t6-3, the total value of the net voltages applied to the electrostatic chucking electrodes from DC power supplies 12 and 13 is changed to a value equal to or less than 0 V so as to be equal to the amount of negative shift in the wafer's plasma potential during plasma discharge. To prevent a decrease in the electrostatic chucking force of the wafer, the applied voltages are set so that the potential difference between the two electrodes is 1000 V or more. This allows fluctuations in the wafer's plasma potential to be offset by changes in the voltage applied to the electrostatic chucking electrodes, thereby preventing a decrease in the wafer's chucking force and preventing the wafer from shifting position.

[0038] In this embodiment, the total net voltage applied to the electrostatic chucking electrode during the static elimination step from t5-4 to t5-6 is set to +600 V, the same as in the first embodiment shown in Fig. 2. However, the net applied voltage during the period from t5-4 to t5-6 may be set to the same value as during the period from t5-3 to t5-4. In this case, it is possible to suppress abrupt fluctuations in the chucking force that accompany changes in the net applied voltage between the plasma discharge step and the static elimination step, thereby further suppressing the occurrence of wafer positional deviation.

[0039] For the above-mentioned Example 2, an evaluation experiment was carried out to evaluate the number of foreign matter particles adhering to a wafer after plasma etching processing. Note that Conventional Example 1 is used here as a comparison condition for comparing the levels of the number of foreign matter particles adhering. Furthermore, as for the experimental conditions, during the period from t3-1 to t3-6, the voltage values ​​of the ESC voltage (+) and the ESC voltage (-) were set to +600 V and -600 V, respectively, and the potential difference between both electrodes was maintained at 1200 V. Note that the other experimental conditions were the same as those in the evaluation test of the above-mentioned Example 1, and therefore a description thereof will be omitted.

[0040] FIG. 7 shows the results of an investigation into the effect of reducing foreign matter adhesion to wafers in Example 2. The vertical axis in FIG. 7 represents the converted value of the number of foreign matter adhesions when the number of foreign matter adhesions in Conventional Example 1 is normalized to 100%. As shown in the results, in the plasma processing process of FIG. 5, in which the total value of the net applied voltage applied to the electrostatic chucking electrode is changed between t5-3 and t5-4, the number of foreign matter adhesions was reduced to about half that of Conventional Example 1. Furthermore, this example is useful in that it is possible to minimize the influence on changes in the plasma state compared to Example 1. [Example]

[0041] FIG. 8 is a time chart of processing according to Example 3 of the present invention. The third example of the present invention will be described while noting the differences in configuration from Examples 1 and 2. In FIG. 8, during the period from t8-1 to t8-3, the total value of the net applied voltage to the electrostatic chucking electrodes is changed to 0 V, which is different from the +600 V value adopted in Example 2 described above. The behavior of each parameter during the period from t8-3 onward in FIG. 8 is similar to the behavior of each parameter during the period from t5-3 onward in the plasma processing process (FIG. 5) according to Example 2 described above, and therefore will not be described again.

[0042] In this embodiment, as shown in FIG. 8 , first, at timing t8-1, the applied voltages from the DC power supplies 12 and 13 to the electrostatic chucking electrodes are changed so that the net applied voltage becomes 0 V. In this embodiment, to prevent a decrease in the electrostatic chucking force of the wafer, the ESC voltage (+) and the ESC voltage (-) are set to +600 V and −600 V, respectively, and the potential difference between the two electrodes is maintained at 1200 V. Next, at timing t8-2 when the plasma ignition step starts, 1000 W of power is supplied from the high-frequency power supply 6 and current is passed through the solenoid coil 5, thereby generating plasma in the processing chamber. Next, at timing t8-3 when the plasma discharge step starts, the power supplied from the high-frequency power supply 6 is changed to 800 W, and plasma etching is performed. In this way, by keeping the supply voltages from the DC power supplies 12 and 13 constant during the period from t8-1 to t8-4, it is possible to suppress abrupt fluctuations in the clamping force that accompany changes in the net applied voltage to the electrostatic clamping electrodes, and thus to suppress the occurrence of wafer positional deviation.

[0043] An evaluation experiment was conducted on the number of foreign particles adhering to the wafer after plasma etching processing for Example 3. Conventional Example 1 was used as a comparison condition for comparing the levels of the number of foreign particles adhering. The experimental conditions were the same as those for the evaluation test for Example 2 described above, and therefore a description thereof will be omitted.

[0044] 9 shows the results of a survey on the effect of reducing the adhesion of foreign matter to wafers according to Example 3. The vertical axis of FIG. 9 shows the number of foreign matter adhesions in Conventional Example 1, which is set to 100%. death 8, in which the net applied voltage to the electrostatic chucking electrode is changed between t8-1 and t8-3, the number of particles was reduced to 60% compared to Conventional Example 1. Furthermore, Example 3 is advantageous over Examples 1 and 2 in that it is possible to minimize the influence of the plasma state and the wafer chucking force on the change. [Example]

[0045] FIG. 10 is a time chart of processing according to Example 4 of the present invention. This example will be described while noting the differences in configuration from Examples 1 to 3. In FIG. 10, in the period from t10-1 to t10-2, the timing of the start of the ignition step is changed to be before the electrostatic attraction of the wafer, which is the reverse of the order of execution in Example 1 described above. Furthermore, the behavior of each parameter in the period from t10-2 onwards in FIG. 10 is the same as the behavior of each parameter from t2-2 onwards in the plasma processing process (FIG. 2) according to Example 1 of the present invention described above, and therefore a description thereof will be omitted.

[0046] 10, in this embodiment, at timing t10-1, the power supply from the high-frequency power supply at timing t2-2 in FIG. 2 is started, and the amount of supplied power is increased to 1000 W. Subsequently, at timing t10-2, the supply of the applied voltage for electrostatic attraction, which was carried out at timing t2-1 in FIG. 2, is started, and the net applied voltage from DC power supplies 12 and 13 is controlled to be +600 V. By changing the timing of wafer attraction in the plasma ignition step in this way, plasma formation is carried out before the change in wafer potential, and the plasma captures charged foreign particles that fly up from the backside of the wafer when the supply of the applied voltage is started, thereby further suppressing the adhesion of foreign particles to the wafer.

[0047] A plasma processing process of Conventional Example 2 will now be described for comparison of the level of foreign matter reduction effect with that of Example 4. Fig. 11 shows a time chart of conventional processing corresponding to Conventional Example 2, which is an embodiment for comparison with Example 4. Conventional Example 2 is a plasma processing process in which, during the period from t11-2 to t11-6, the voltage values ​​of the ESC voltage (+) and the ESC voltage (-) are set to +600 V and -600 V, respectively, and the net applied voltage to the electrostatic chucking electrode is changed to 0 V.

[0048] An evaluation experiment was carried out on the number of foreign particles adhering to wafers after plasma etching processing for the above-mentioned Example 4 and Conventional Example 2. The experimental conditions were the same as those for the evaluation tests of Examples 1 to 3 described above, and therefore a description thereof will be omitted.

[0049] Fig. 12 shows the results of an investigation into the effect of reducing foreign matter adhesion to wafers in Example 4. The vertical axis of Fig. 12 represents the converted value of the number of foreign matter adhesions when the number of foreign matter adhesions in Conventional Example 2 is normalized to 100%. As shown in this result, the plasma processing process of Fig. 10, in which the timing of plasma generation is changed between t10-1 and t10-2, was able to reduce the number of foreign matters compared to Conventional Example 2 (0 V).

[0050] As described in the above examples, it has been found that in the plasma processing according to the present invention, the adhesion of foreign matter to the wafer can be significantly reduced by changing the net voltage applied to the electrostatic chucking electrode in the positive direction and maintaining constant control parameters for the wafer in the plasma etching process.

[0051] Furthermore, by changing the net voltage applied to the electrostatic attraction electrode in a positive direction only in either or both of the ignition step and the discharge step, and keeping the net voltage applied to the electrostatic attraction electrode at 0 V in the other steps, it is possible to both suppress the adhesion of foreign matter and improve the stability of the wafer attracting force.

[0052] Furthermore, by changing the timing at which electrostatic attraction to the wafer begins from before the ignition step to during the ignition step, it is possible to reduce the adhesion of foreign particles that are blown up due to a sudden change in the potential of the wafer. As a result of the synergistic effect of these effects, the present invention can prevent the adhesion of foreign particles to the wafer and improve the yield of device manufacturing.

[0053] The present invention is realized by specifying a positive shift in the net voltage applied to the electrostatic chucking electrode for the wafer and maintaining constant values ​​of the control parameters during the plasma discharge step as shown in any one of FIGS. 2, 5, 6, 8, and 10, thereby suppressing the adhesion of foreign matter.

[0054] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. For example, in the above-described embodiments 1 to 4, the ignition step is performed first, but the present invention also applies to plasma processing processes in which the ignition step is deleted from each embodiment.

[0055] Furthermore, each of the above processing configurations may be implemented in hardware, for example, by designing a part or all of them as an integrated circuit. Each of the above processing configurations may also be implemented in software, with a processor interpreting and executing a program that implements each function. Information such as the programs, tables, and files that implement each function may be stored in a memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC card, SD card, or DVD.

[0056] In addition, the control lines shown are those considered necessary for the explanation, and not all control lines in the product are necessarily shown. In reality, it can be assumed that almost all components are interconnected. [Explanation of symbols]

[0057] 1...wafer, 2...gate, 3...processing chamber, 4...sample stage, 5...solenoid coil, 6...high frequency power supply, 7...microwave oscillation source, 8...resonator, 9...gas supply unit, 10...first electrostatic chucking electrode, 11...second electrostatic chucking electrode, 12...first DC power supply, 13...second DC power supply, 14...control unit.

Claims

1. a processing chamber in which a wafer is plasma-processed using plasma; a high frequency power source that supplies high frequency power for generating the plasma; a sample stage on which the wafer is placed, the sample stage including an electrostatic chucking electrode having a first electrode and a second electrode for electrostatically chucking the wafer; a DC power supply that applies a first voltage and a second voltage having different polarities to the first electrode and the second electrode, respectively; a control device that controls the DC power supply so that the sum of the first voltage and the second voltage is positive, so that an average positive charge is generated on the surface of the wafer during a period from ignition of the plasma to removal of the wafer from the sample stage.

2. 2. The plasma processing apparatus according to claim 1, The plasma processing apparatus is characterized in that the first voltage and the second voltage are substantially the same value during the period from the ignition of the plasma to the removal of the wafer from the sample stage.

3. a processing chamber in which a wafer is plasma-processed using plasma; a high frequency power source that supplies high frequency power for generating the plasma; a sample stage on which the wafer is placed, the sample stage including an electrostatic chucking electrode having a first electrode and a second electrode for electrostatically chucking the wafer; a DC power supply that applies a first voltage and a second voltage having different polarities to the first electrode and the second electrode, respectively; a control device that controls the DC power supply so that the sum of the first voltage and the second voltage is positive, so as to generate an average positive charge on the surface of the wafer during a processing period for igniting the plasma or a processing period for removing the wafer from the sample stage.

4. 4. The plasma processing apparatus according to claim 3, the sum of the first voltage and the second voltage during the plasma treatment is equal to or less than 0 V; The plasma processing apparatus according to claim 1, wherein the magnitude of the sum of the first voltage and the second voltage during the plasma processing period is equal to the shift of the plasma potential during the plasma processing period.

5. 5. The plasma processing apparatus according to claim 1, 10. The plasma processing apparatus according to claim 9, wherein the sum of the first voltage and the second voltage before the ignition of the plasma is a positive value.

6. 5. The plasma processing apparatus according to claim 1, The plasma processing apparatus is characterized in that the sum of the first voltage and the second voltage after the ignition of the plasma and before the start of the plasma processing is a positive value.

7. A plasma processing method for plasma processing a wafer placed on a sample stage equipped with an electrostatic attraction electrode having a first electrode and a second electrode for electrostatically attracting the wafer, the method comprising: a first voltage and a second voltage having opposite polarities and a positive sum are applied to the first electrode and the second electrode, respectively, so as to generate an average positive charge on the surface of the wafer during a period from ignition of the plasma to removal of the wafer from the sample stage.

8. A plasma processing method for plasma processing a wafer placed on a sample stage equipped with an electrostatic attraction electrode having a first electrode and a second electrode for electrostatically attracting the wafer, the method comprising: a first voltage and a second voltage having opposite polarities and a positive sum are applied to the first electrode and the second electrode, respectively, so as to generate an average positive charge on the surface of the wafer during a period of processing to ignite the plasma or a period of processing to remove the wafer from the sample stage.

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