Power semiconductor device, power module and power conversion device

Abstract

A power semiconductor device (2) comprises: a sub-mount substrate (10); a power semiconductor element (20) made of gallium oxide; and a conductive bonding member (28). The sub-mount substrate (10) has a first main surface (11) and a second main surface (12) on the opposite side from the first main surface (11). The sub-mount substrate (10) includes a first penetrating conductor (14) extending from the first main surface (11) to the second main surface (12). The power semiconductor element (20) is flip-chip-mounted on the first main surface (11). The power semiconductor element (20) includes a first main current electrode (25) opposite the first main surface (11), and a second main current electrode (27) disposed on the opposite side from the first main current electrode (25). The first main current electrode (25) is joined to the first penetrating conductor (14) by the conductive bonding member (28).

Description

[Technical Field]

[0001] The present disclosure relates to a power semiconductor device, a power module, and a power conversion device. [Background technology]

[0002] Japanese Patent Application Laid-Open Publication No. 2022-163881 (Patent Document 1) discloses a semiconductor module including a semiconductor element made of gallium oxide. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-163881 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide a power semiconductor device, a power module, and a power conversion device with improved reliability. [Means for solving the problem]

[0005] The power semiconductor device of the present disclosure includes a submount substrate, a power semiconductor element made of gallium oxide, and a conductive bonding member. The submount substrate has a first main surface and a second main surface opposite the first main surface. The submount substrate includes a first through conductor extending from the first main surface to the second main surface. The power semiconductor element is flip-chip mounted on the first main surface. The power semiconductor element includes a first main current electrode facing the first main surface and a second main current electrode disposed opposite the first main current electrode. The first main current electrode is bonded to the first through conductor by the conductive bonding member.

[0006] The power module of the present disclosure includes the power semiconductor device of the present disclosure and an insulating circuit board. The insulating circuit board includes an insulating layer and a circuit pattern disposed on the insulating layer. The first through conductor is electrically connected to the circuit pattern.

[0007] The power conversion device of the present disclosure includes a power module of the present disclosure, a main conversion circuit that converts input power and outputs it, and a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit. [Effects of the Invention]

[0008] The power semiconductor device, power module, and power conversion device of the present disclosure have improved reliability. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view of a power module according to a first embodiment. [Figure 2] 2 is a schematic enlarged plan view of the power semiconductor device of the first embodiment, as viewed in the direction of the arrow II shown in FIG. [Figure 3] FIG. 10 is a schematic cross-sectional view of a power module according to a second embodiment. [Figure 4] FIG. 10 is a schematic cross-sectional view of a power module according to a third embodiment. [Figure 5] FIG. 10 is a schematic cross-sectional view of a power module according to a fourth embodiment. [Figure 6] FIG. 13 is a schematic cross-sectional view of a power module according to a first modified example of the fourth embodiment. [Figure 7] FIG. 13 is a schematic cross-sectional view of a power module according to a second modified example of the fourth embodiment. [Figure 8] FIG. 10 is a block diagram showing the configuration of a power conversion system according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described. Note that the same reference numerals are used to designate the same components, and the description thereof will not be repeated.

[0011] Embodiment 1 A power module 1 according to a first embodiment will be described with reference to Figures 1 and 2. The power module 1 mainly includes a power semiconductor device 2, an insulating circuit board 3, a base plate 40, a case 42, terminals 44 and 45, conductive wires 47, 48 and 49, and a sealing member 50.

[0012] The power semiconductor device 2 includes a submount substrate 10, a power semiconductor element 20, and conductive bonding members 28 and 29.

[0013] The submount substrate 10 has a first main surface 11 and a second main surface 12 opposite to the first main surface 11. The first main surface 11 and the second main surface 12 extend in the x direction and in the y direction perpendicular to the x direction. The submount substrate 10 includes an insulating substrate 13 and a first through conductor 14. The submount substrate 10 may further include a main current wiring 16, a signal wiring 17, a wiring 19, and bonding pads 18 and 18b.

[0014] The insulating substrate 13 is made of an insulating inorganic material such as silicon oxide, or a composite material such as glass epoxy resin.

[0015] The first penetrating conductor 14 extends from the first main surface 11 to the second main surface 12, and penetrates the insulating substrate 13 in a thickness direction (z direction) of the insulating substrate 13 that is perpendicular to the x and y directions. The first penetrating conductor 14 is, for example, a conductive pillar 15. The cross-sectional area of ​​the first penetrating conductor 14 is larger than the cross-sectional area of ​​the conductive wire 47. The cross-sectional area of ​​the first penetrating conductor 14 is, for example, 10 times or more the cross-sectional area of ​​the conductive wire 47. The cross-sectional area of ​​the first penetrating conductor 14 is the area of ​​the first penetrating conductor 14 in a cross section perpendicular to the longitudinal direction (z direction) of the first penetrating conductor 14. The cross-sectional area of ​​the conductive wire 47 is the area of ​​the conductive wire 47 in a cross section perpendicular to the longitudinal direction of the conductive wire 47.

[0016] The main current wiring 16 is connected to the first through conductor 14. The main current wiring 16 is disposed on the second main surface 12 side of the submount substrate 10, and extends along the second main surface 12.

[0017] The signal wiring 17 and the wiring 19 are arranged on the first main surface 11 side of the submount substrate 10 and extend along the first main surface 11. The signal wiring 17 is electrically isolated from the first through conductor 14 by the insulating substrate 13. The wiring 19 is electrically isolated from the first through conductor 14 and the signal wiring 17 by the insulating substrate 13.

[0018] When the first main surface 11 is seen in plan view, the bonding pads 18 and 18b are exposed from the power semiconductor element 20.

[0019] The bonding pad 18 is connected to the signal wiring 17. The width of the bonding pad 18 is greater than the width of the signal wiring 17. The width of the bonding pad 18 means the length of the bonding pad 18 in a direction (y direction) perpendicular to the longitudinal direction (x direction) of the signal wiring 17 in a plan view of the first main surface 11. The width of the signal wiring 17 means the length of the signal wiring 17 in a direction (y direction) perpendicular to the longitudinal direction (x direction) of the signal wiring 17 in a plan view of the first main surface 11.

[0020] The bonding pad 18b is connected to the wiring 19. The width of the bonding pad 18b is greater than the width of the wiring 19. The width of the bonding pad 18b means the length of the bonding pad 18b in a direction (y direction) perpendicular to the longitudinal direction (x direction) of the wiring 19 in a plan view of the first main surface 11. The width of the wiring 19 means the length of the wiring 19 in a direction (y direction) perpendicular to the longitudinal direction (x direction) of the wiring 19 in a plan view of the first main surface 11.

[0021] The first through conductor 14, the main current wiring 16, the signal wiring 17, the wiring 19, and the bonding pads 18, 18b are formed of a conductive material such as copper (Cu). For example, the first through conductor 14, the main current wiring 16, the signal wiring 17, the wiring 19, and the bonding pads 18, 18b may be formed by press-fitting a conductive member into the insulating substrate 13.

[0022] The power semiconductor element 20 is, for example, a transistor such as an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET), or a diode. The power semiconductor element 20 is made of gallium oxide (β-Ga2O3). The power semiconductor element 20 includes an element body 21, a first main current electrode 25, and a second main current electrode 27. The power semiconductor element 20 may further include a signal electrode 26 and a detection electrode 26b.

[0023] The element body 21 is mainly made of gallium oxide. The element body 21 has a main surface 22 and a main surface 23 opposite to the main surface 22. The main surface 22 faces the first main surface 11 of the submount substrate 10. The element body 21 includes an active region 24. For example, if the power semiconductor element 20 is a transistor, the active region 24 is a channel region of the transistor. For example, if the power semiconductor element 20 is a diode, the active region 24 is a pn junction of the diode. The active region 24 is formed closer to the main surface 22 than to the main surface 23.

[0024] First main current electrode 25 is disposed on main surface 22 and faces first main current electrode 11 of submount substrate 10. Second main current electrode 27 is disposed on the opposite side to first main current electrode 25. Specifically, second main current electrode 27 is disposed on main surface 23. A main current to be controlled by power semiconductor element 20 flows between first main current electrode 25 and second main current electrode 27. For example, if power semiconductor element 20 is a transistor, first main current electrode 25 is an emitter electrode, and second main current electrode 27 is a collector electrode. For example, if power semiconductor element 20 is a diode, first main current electrode 25 is an anode electrode, and second main current electrode 27 is a cathode electrode.

[0025] The signal electrode 26 and the detection electrode 26b are disposed on the main surface 22 and face the first main surface 11 of the submount substrate 10. The signal electrode 26 and the detection electrode 26b are spaced apart from the first main current electrode 25. For example, if the power semiconductor element 20 is a transistor, the signal electrode 26 is a gate electrode, and the detection electrode 26b is an electrode for detecting the potential of the emitter.

[0026] The power semiconductor element 20 is flip-chip mounted on the first main surface 11 of the submount substrate 10. That is, the active region 24 is disposed in a portion of the power semiconductor element 20 close to the first main surface 11. The first main current electrode 25 is joined to the first through conductor 14 by a conductive bonding member 28 and is electrically and thermally connected to the first through conductor 14. The signal electrode 26 is joined to the signal wiring 17 by a conductive bonding member 29 and is electrically and thermally connected to the signal wiring 17. The detection electrode 26b is joined to the wiring 19 by a conductive bonding member (not shown) and is electrically and thermally connected to the wiring 19. The conductive bonding members 28, 29 are, for example, solder, a metal fine particle sintered body such as a silver nanoparticle sintered body, or a conductive adhesive such as a silver paste.

[0027] 2, in a plan view of the first main surface 11, the area of ​​the first penetrating conductor 14 is larger than the area of ​​the signal electrode 26. For example, in a plan view of the first main surface 11, the width of the first penetrating conductor 14 is larger than a first width of the signal electrode 26. The width of the first penetrating conductor 14 means the length of the first penetrating conductor 14 in a second direction (y direction) perpendicular to a first direction (x direction) in which the first penetrating conductor 14 and the signal electrode 26 are spaced apart from each other in a plan view of the first main surface 11. The first width of the signal electrode 26 means the length of the signal electrode 26 in the second direction in a plan view of the first main surface 11.

[0028] In a plan view of the first main surface 11, the area of ​​the signal electrode 26 is smaller than the area of ​​each of the bonding pads 18, 18b. For example, in a plan view of the first main surface 11, the second width of the signal electrode 26 is larger than the width of each of the bonding pads 18, 18b. The second width of the signal electrode 26 means the length of the signal electrode 26 in a direction (y direction) perpendicular to the longitudinal direction (x direction) of the signal wiring 17 in a plan view of the first main surface 11. The width of each of the bonding pads 18, 18b means the length of each of the bonding pads 18, 18b in a direction (y direction) perpendicular to the longitudinal direction (x direction) of the signal wiring 17 in a plan view of the first main surface 11. In the present embodiment, the second width of the signal electrode 26 is equal to the first width of the signal electrode 26.

[0029] Referring to FIG. 1, insulating circuit board 3 includes insulating layer 30, circuit pattern 33, and conductive pattern .

[0030] The insulating layer 30 is formed of, for example, a ceramic material such as alumina (Al2O3), aluminum nitride (AlN), or silicon nitride (Si3N4), an insulating resin, or a filler-containing insulating resin. The insulating layer 30 has a main surface 31 and a main surface 32 opposite to the main surface 31.

[0031] The circuit pattern 33 is disposed on the main surface 31 and bonded to the main surface 31. The conductive pattern 36 is disposed on the main surface 32 and bonded to the main surface 32. The circuit pattern 33 and the conductive pattern 36 are formed of a metal such as copper (Cu) or aluminum (Al). The insulating circuit board 3 is, for example, a DBC (Direct Bonded Copper) board in which a copper layer is bonded to a ceramic board.

[0032] The first through conductor 14 and the main current wiring 16 are joined to the circuit pattern 33 by a conductive bonding member 37, and are electrically and thermally connected to the circuit pattern 33. The conductive bonding member 37 is, for example, solder, a metal fine particle sintered body such as a silver nanoparticle sintered body, or a conductive adhesive such as silver paste.

[0033] The base plate 40 supports the insulating circuit board 3. The insulating circuit board 3 is fixed to the base plate 40 at a joint 41. For example, the conductive pattern 36 is joined to the base plate 40 at the joint 41. The joint 41 may be formed of, for example, solder, a metal microparticle sintered body such as a silver microparticle sintered body, or a resin containing a conductive filler, or may be liquid phase diffusion bonding between the conductive pattern 36 and the base plate 40. The base plate 40 is formed of, for example, copper (Cu) or a silicon carbide particle reinforced aluminum composite (AlSiC). The base plate 40 may be provided with a cooling fin (not shown).

[0034] The case 42 surrounds the insulating circuit board 3 and the power semiconductor device 2. The case 42 is fixed to the base plate 40 using an adhesive (not shown). The insulating circuit board 3 and the power semiconductor device 2 are arranged in an internal space defined by the base plate 40 and the case 42. The base plate 40 and the case 42 house the insulating circuit board 3 and the power semiconductor device 2. The case 42 is formed of an insulating resin such as an epoxy resin or a polyphenylene sulfide resin.

[0035] The terminals 44, 45 are fixed to the case 42. One end of each of the terminals 44, 45 is disposed inside the case 42 and is exposed from the case 42. A portion of each of the terminals 44, 45 extends to the outside of the case 42. The terminals 44, 45 are formed of a conductive material such as copper (Cu) or aluminum (Al). A coating layer (not shown) such as a nickel (Ni) layer or a gold (Au) layer may be formed on the surface of the terminals 44, 45.

[0036] 1 and 2, the conductive wires 47, 48, and 49 are made of a conductive material such as aluminum (Al) or copper (Cu). The conductive wire 47 is bonded to the terminal 44 and the second main current electrode 27. A main current is supplied to the power semiconductor element 20 (second main current electrode 27) through the terminal 44 and the conductive wire 47, or is extracted from the power semiconductor element 20 (second main current electrode 27) to the outside of the power module 1 through the terminal 44 and the conductive wire 47. The conductive wire 48 is bonded to the terminal 45 and the bonding pad 18. A signal for controlling the power semiconductor element 20 is supplied to the power semiconductor element 20 (signal electrode 26) through the terminal 45, the conductive wire 48, the bonding pad 18, and the signal wiring 17. The conductive wire 49 is bonded to the bonding pad 18b. For example, the emitter potential of the power semiconductor element 20 is output from the power semiconductor element 20 (detection electrode 26b) through the wiring 19, the bonding pad 18b, and the conductive wire 49 to the outside of the power semiconductor element 20.

[0037] Because the main current flows through the conductive wire 47, the cross-sectional area and diameter of the conductive wire 47 are large. For example, the diameter of the conductive wire 47 is 100 μm or more. The diameter of the conductive wire 47 may be 200 μm or more, or even 300 μm or more. In contrast, because the current flowing through each of the conductive wires 48 and 49 is smaller than the main current flowing through the conductive wire 47, the cross-sectional area and diameter of each of the conductive wires 48 and 49 may be smaller than the cross-sectional area and diameter of the conductive wire 47, respectively. To improve the efficiency of the bonding operation of the conductive wires 47, 48, and 49, the cross-sectional area and diameter of each of the conductive wires 48 and 49 may be equal to the cross-sectional area and diameter of the conductive wire 47, respectively.

[0038] 1, the sealing member 50 seals the power semiconductor element 20. The sealing member 50 may seal the power semiconductor device 2, the insulating circuit board 3, and the conductive wires 47, 48, and 49. The sealing member 50 may be disposed in an internal space defined by the base plate 40 and the case 42. The base plate 40 and the case 42 may be omitted, and the sealing member 50 may be formed by transfer molding or the like. The sealing member 50 is formed, for example, from a thermosetting resin such as an epoxy resin, a silicone gel, or an insulating resin containing a filler.

[0039] The operation of this embodiment will be described. During operation of the power semiconductor element 20, heat is generated in the active region 24 and its vicinity. The power semiconductor element 20 is made of gallium oxide. The thermal conductivity of gallium oxide is one-fifth or less of that of silicon (Si) and one-tenth or less of that of silicon carbide (SiC). Therefore, the power semiconductor element 20 made of gallium oxide is more susceptible to temperature rise and thermal damage than power semiconductor elements made of Si and power semiconductor elements made of SiC.

[0040] In this embodiment, the power semiconductor element 20 made of gallium oxide is flip-chip mounted on the first main surface 11 of the submount substrate 10, and the first main current electrode 25 of the power semiconductor element 20 is joined to the first penetrating conductor 14 by the conductive bonding member 28. The cross-sectional areas of the first penetrating conductor 14 and the conductive bonding member 28 are larger than the cross-sectional areas of the conductive wires 47. Therefore, heat generated in the power semiconductor element 20 is efficiently dissipated to the outside of the power module 1 through the first penetrating conductor 14 and the conductive bonding member 28. The power semiconductor element 20 made of gallium oxide is prevented from being thermally damaged. The reliability of the power semiconductor device 2 and the power module 1 is improved.

[0041] Furthermore, since the conductive wire 47 and the conductive wire 48 can be bonded to the second main current electrode 27 and the bonding pad 18, respectively, the same wire bonding as that for Si power semiconductor elements and SiC power semiconductor elements can be applied to the power semiconductor device 2 of this embodiment, thereby reducing the cost of the power module 1.

[0042] The effects of the power semiconductor device 2 and the power module 1 of this embodiment will be described. The power semiconductor device 2 of this embodiment includes a submount substrate 10, a power semiconductor element 20 made of gallium oxide, and a conductive bonding member 28. The submount substrate 10 has a first main surface 11 and a second main surface 12 opposite to the first main surface 11. The submount substrate 10 includes a first through conductor 14 extending from the first main surface 11 to the second main surface 12. The power semiconductor element 20 is flip-chip mounted on the first main surface 11. The power semiconductor element 20 includes a first main current electrode 25 facing the first main surface 11 and a second main current electrode 27 disposed on the opposite side to the first main current electrode 25. The first main current electrode 25 is bonded to the first through conductor 14 by the conductive bonding member 28.

[0043] Heat generated in the power semiconductor element 20 is efficiently dissipated to the outside of the power module 1 through the first through conductor 14 and the conductive bonding member 28. Even if the power semiconductor element 20 is made of gallium oxide, which has low thermal conductivity, the power semiconductor element 20 is prevented from being thermally damaged. The reliability of the power semiconductor device 2 and the power module 1 is improved.

[0044] Moreover, it becomes possible to apply wire bonding similar to that for Si power semiconductor elements and SiC power semiconductor elements to the power semiconductor device 2 of this embodiment. According to the power semiconductor device 2 of this embodiment, it becomes possible to reduce the cost of the power module 1.

[0045] In the power semiconductor device 2 of this embodiment, the submount substrate 10 includes a main current wiring 16 that is connected to the first through conductor 14 and extends along the second main surface 12.

[0046] The heat generated in the power semiconductor element 20 is spread in the direction (x direction) in which the main current wiring 16 extends. The heat generated in the power semiconductor element 20 is efficiently dissipated to the outside of the power module 1. The reliability of the power semiconductor device 2 and the power module 1 is improved.

[0047] In the power semiconductor device 2 of the present embodiment, the power semiconductor element 20 includes a signal electrode 26 facing the first main surface 11. In a plan view of the first main surface 11, the area of ​​the first through conductor 14 is larger than the area of ​​the signal electrode 26.

[0048] The heat generated in the power semiconductor element 20 is efficiently dissipated to the outside of the power module 1 through the first through conductor 14, which has a larger area. The heat is further efficiently dissipated to the outside of the power module 1 through the signal electrode 26 and the signal wiring 17. The power semiconductor element 20 is prevented from being thermally damaged. The reliability of the power semiconductor device 2 and the power module 1 is improved. Furthermore, a three-terminal element such as a transistor can be used as the power semiconductor element 20.

[0049] In the power semiconductor device 2 of this embodiment, the submount substrate 10 includes a signal wiring 17 and a bonding pad 18. The signal wiring 17 is electrically isolated from the first through conductor 14 and extends along the first main surface 11. The bonding pad 18 is connected to the signal wiring 17 and is exposed from the power semiconductor element 20 in a plan view of the first main surface 11. The signal electrode 26 is electrically connected to the signal wiring 17.

[0050] The heat generated in the power semiconductor element 20 is spread in the direction (x direction) in which the signal wiring 17 extends. The heat generated in the power semiconductor element 20 is efficiently dissipated to the outside of the power module 1. The reliability of the power semiconductor device 2 and the power module 1 is improved.

[0051] Moreover, it becomes possible to apply wire bonding similar to that for Si power semiconductor elements and SiC power semiconductor elements to the power semiconductor device 2 of this embodiment. According to the power semiconductor device 2 of this embodiment, it becomes possible to reduce the cost of the power module 1.

[0052] In the power semiconductor device 2 of this embodiment, the area of ​​the signal electrode 26 is smaller than the area of ​​the bonding pad 18 in a plan view of the first main surface 11.

[0053] The signal electrode 26 is miniaturized, and the power semiconductor element 20 made of expensive gallium oxide is miniaturized, thereby reducing the cost of the power semiconductor device 2.

[0054] The power module 1 of this embodiment includes a power semiconductor device 2 and an insulating circuit board 3. The insulating circuit board 3 includes an insulating layer 30 and a circuit pattern 33 disposed on the insulating layer 30. The first through conductor 14 is electrically connected to the circuit pattern 33.

[0055] The heat generated in the power semiconductor element 20 is spread in the directions in which the circuit pattern 33 extends (x direction and y direction). The heat generated in the power semiconductor element 20 is efficiently dissipated to the outside of the power module 1 through the first through conductors 14 and the circuit pattern 33. The power semiconductor element 20 is prevented from being thermally damaged. The reliability of the power module 1 is improved.

[0056] The power module 1 of this embodiment further includes a sealing member 50 that seals the power semiconductor element 20 .

[0057] The sealing member 50 protects the power semiconductor elements 20, and therefore the reliability of the power module 1 is improved.

[0058] Embodiment 2 The power module 1 of the second embodiment will be described with reference to Fig. 3. The power module 1 of the present embodiment has a similar configuration to the power module 1 of the first embodiment, but differs mainly in the following respects.

[0059] The power semiconductor device 2 of this embodiment further includes an underfill material 51. The underfill material 51 is filled in the gap between the power semiconductor element 20 and the submount substrate 10. The underfill material 51 is in contact with the conductive bonding members 28, 29 and the power semiconductor element 20. The underfill material 51 reinforces the conductive bonding members 28, 29 and supports the power semiconductor element 20. The underfill material 51 is formed of, for example, an epoxy-based resin.

[0060] The power semiconductor device 2 of this embodiment has the following effects in addition to the effects of the power semiconductor device 2 of the first embodiment.

[0061] The power semiconductor device 2 of this embodiment further includes an underfill material 51. The underfill material 51 is filled in the gap between the power semiconductor element 20 and the submount substrate 10, and is in contact with the conductive bonding member 28.

[0062] The underfill material 51 reinforces the conductive bonding member 28 and prevents cracks from occurring in the conductive bonding member 28. Furthermore, although the power semiconductor element 20 made of gallium oxide is more fragile than a power semiconductor element made of Si, the underfill material 51 supports the power semiconductor element 20 made of gallium oxide and mechanically reinforces the power semiconductor element 20 made of gallium oxide. Therefore, the reliability of the power semiconductor device 2 and the power module 1 is improved.

[0063] Embodiment 3 The power module 1 of the third embodiment will be described with reference to Fig. 4. The power module 1 of the present embodiment has a similar configuration to the power module 1 of the first embodiment, but differs mainly in the following respects.

[0064] In the power semiconductor device 2 of this embodiment, the first penetrating conductor 14 is a plurality of through-hole conductors 52. The cross-sectional area of ​​each of the plurality of through-hole conductors 52 is smaller than the cross-sectional area of ​​the conductive pillar 15 (see FIG. 1). The cross-sectional area of ​​the plurality of through-hole conductors 52 is approximately equal to the cross-sectional area of ​​the conductive pillar 15 (see FIG. 1). The through-hole conductors 52 can be formed by sputtering or plating a metal such as copper (Cu) on the surface of the insulating substrate 13 that defines the through hole.

[0065] The power semiconductor device 2 and the power module 1 of this embodiment have the following advantages in addition to the advantages of the power semiconductor device 2 and the power module 1 of the first embodiment.

[0066] In the power semiconductor device 2 and the power module 1 of this embodiment, the first penetrating conductors 14 are a plurality of through-hole conductors 52.

[0067] The cross-sectional area of ​​each of the plurality of through-hole conductors 52 is smaller than the cross-sectional area of ​​the conductive pillar 15 (see FIG. 1). Therefore, the plurality of through-hole conductors 52 can also be formed by sputtering, plating, or the like. This improves the productivity of the power semiconductor device 2 and the power module 1.

[0068] Embodiment 4 A power module 1 according to a fourth embodiment will be described with reference to Fig. 5. The power module 1 according to this embodiment has a similar configuration to the power module 1 according to the third embodiment, but differs mainly in the following respects.

[0069] The submount substrate 10 includes second through conductors 53 instead of the signal wiring 17 and bonding pads 18 shown in FIG. 1 . The second through conductors 53 extend from the first main surface 11 to the second main surface 12 and penetrate the insulating substrate 13. In the present embodiment, the second through conductors 53 are a plurality of through-hole conductors 54. The plurality of through-hole conductors 54 can be formed by a method similar to that for the plurality of through-hole conductors 52. The second through conductors 53 may be conductive pillars 15 (see FIG. 1 ). The second through conductors 53 are electrically separated from the first through conductors 14 by the insulating substrate 13. In a plan view of the first main surface 11 of the submount substrate 10, the second through conductors 53 overlap the power semiconductor elements 20 and are covered by the power semiconductor elements 20.

[0070] The signal electrode 26 is joined to the second through conductor 53 by a conductive joining member 29, and is electrically and thermally connected to the second through conductor 53.

[0071] The circuit pattern 33 includes a first circuit pattern layer 34 and a second circuit pattern layer 35 separated from the first circuit pattern layer 34. The first through conductors 14 are joined to the first circuit pattern layer 34 by a conductive bonding member 37 and are electrically and thermally connected to the first circuit pattern layer 34. The second through conductors 53 are joined to the second circuit pattern layer 35 by a conductive bonding member 38 and are electrically and thermally connected to the second circuit pattern layer 35. The conductive bonding member 38 is, for example, solder, a metal fine particle sintered body such as a silver nanoparticle sintered body, or a conductive adhesive such as silver paste.

[0072] The conductive wire 48 is bonded to the terminal 45 and the second circuit pattern layer 35. A signal for controlling the power semiconductor element 20 is supplied to the power semiconductor element 20 through the terminal 45, the conductive wire 48, the second circuit pattern layer 35, and the second through conductor 53.

[0073] A power module 1 according to a first modified example of the present embodiment will be described with reference to FIG. The submount substrate 10 further includes a third penetrating conductor 55. The third penetrating conductor 55 extends from the first main surface 11 to the second main surface 12 and penetrates the insulating substrate 13. In the present embodiment, the third penetrating conductor 55 is a plurality of through-hole conductors 56. The plurality of through-hole conductors 56 can be formed by a method similar to that for the plurality of through-hole conductors 52. The third penetrating conductor 55 may be a conductive pillar 15 (see FIG. 1 ). The third penetrating conductor 55 is electrically isolated from the first penetrating conductor 14 and the second penetrating conductor 53 by the insulating substrate 13. In a plan view of the first main surface 11 of the submount substrate 10, the third penetrating conductor 55 is exposed from the power semiconductor element 20.

[0074] The third through conductor 55 is joined to the second circuit pattern layer 35 by a conductive bonding member 39 and is electrically and thermally connected to the second circuit pattern layer 35. The conductive wire 48 is bonded to the terminal 45 and the third through conductor 55. A signal for controlling the power semiconductor element 20 is supplied to the power semiconductor element 20 through the terminal 45, the conductive wire 48, the third through conductor 55, the second circuit pattern layer 35 and the second through conductor 53.

[0075] A power module 1 according to a second modified example of the present embodiment will be described with reference to FIG. In the power semiconductor device 2 of this embodiment, the submount substrate 10 includes a semiconductor substrate 60 and an insulating film 61 instead of the insulating substrate 13 (see FIG. 5).

[0076] The semiconductor substrate 60 is made of a semiconductor material having a thermal conductivity greater than that of gallium oxide. The semiconductor substrate 60 is made of, for example, silicon carbide (SiC), silicon (Si), gallium nitride (GaN), or diamond. A through-hole is provided in the semiconductor substrate 60. An insulating film 61 is formed on the surface of the semiconductor substrate 60 that defines the through-hole. The insulating film 61 is made of, for example, an insulating material such as silicon oxide or silicon nitride. The insulating film 61 may be formed by thermally oxidizing the surface of the semiconductor substrate 60 that defines the through-hole, or may be formed on the surface by a chemical vapor deposition (CVD) method.

[0077] The first through conductors 14 (plurality of through-hole conductors 52) and the second through conductors 53 (plurality of through-hole conductors 54) are arranged in through holes provided in the semiconductor substrate 60. The first through conductors 14 (plurality of through-hole conductors 52) and the second through conductors 53 (plurality of through-hole conductors 54) are electrically insulated from the semiconductor substrate 60 by an insulating film 61.

[0078] The power semiconductor device 2 and the power module 1 of this embodiment have the following effects in addition to the effects of the power semiconductor device 2 and the power module 1 of the third embodiment.

[0079] In the power semiconductor device 2 of this embodiment, the submount substrate 10 includes a semiconductor substrate 60 having a through hole formed therein, and an insulating film 61 formed on the surface that defines the through hole. The first through conductor 14 is disposed in the through hole, and is electrically insulated from the semiconductor substrate 60 by the insulating film 61. The semiconductor substrate 60 is formed of a semiconductor material having a thermal conductivity greater than that of gallium oxide.

[0080] The heat generated in the power semiconductor element 20 is spread by the semiconductor substrate 60. The heat generated in the power semiconductor element 20 is efficiently dissipated to the outside of the power module 1. The reliability of the power semiconductor device 2 and the power module 1 is improved.

[0081] In the power semiconductor device 2 of this embodiment, the submount substrate 10 includes a second penetrating conductor 53 extending from the first main surface 11 to the second main surface 12. The second penetrating conductor 53 is electrically isolated from the first penetrating conductor 14 and overlaps the power semiconductor element 20 in a plan view of the first main surface 11. The signal electrode 26 is electrically connected to the second penetrating conductor 53.

[0082] The heat generated in the power semiconductor element 20 is efficiently dissipated to the outside of the power module 1 through the first through conductor 14 and the second through conductor 53. Furthermore, the power semiconductor device 2 is miniaturized, and the power module 1 can be miniaturized.

[0083] In the power semiconductor device 2 of this embodiment, the submount substrate 10 includes a third penetrating conductor 55 extending from the first main surface 11 to the second main surface 12. The third penetrating conductor 55 is electrically isolated from the first penetrating conductor 14 and the second penetrating conductor 53, and is exposed from the power semiconductor element 20 in a plan view of the first main surface 11.

[0084] The heat generated in the power semiconductor element 20 is efficiently dissipated to the outside of the power module 1 through the first through conductor 14, the second through conductor 53, and the third through conductor 55. This prevents the power semiconductor element 20 from being thermally damaged. This improves the reliability of the power semiconductor device 2 and the power module 1.

[0085] The power module 1 of this embodiment includes a power semiconductor device 2 of this embodiment or a first modified example of this embodiment, and an insulating circuit board 3. The insulating circuit board 3 includes an insulating layer 30 and a circuit pattern 33 disposed on the insulating layer 30. The circuit pattern 33 includes a first circuit pattern layer 34 and a second circuit pattern layer 35 separated from the first circuit pattern layer 34. The first through conductor 14 is electrically connected to the first circuit pattern layer 34. The second through conductor 53 is electrically connected to the second circuit pattern layer 35.

[0086] The heat generated in the power semiconductor element 20 is efficiently dissipated to the outside of the power module 1 through the first through conductor 14 and the first circuit pattern layer 34, and through the second through conductor 53 and the second circuit pattern layer 35. Furthermore, the power semiconductor device 2 is miniaturized, and the power module 1 can be miniaturized.

[0087] The power module 1 of this embodiment includes a power semiconductor device 2 of the first modified example of this embodiment and an insulating circuit board 3. The insulating circuit board 3 includes an insulating layer 30 and a circuit pattern 33 disposed on the insulating layer 30. The circuit pattern 33 includes a first circuit pattern layer 34 and a second circuit pattern layer 35 separated from the first circuit pattern layer 34. The first through conductor 14 is electrically connected to the first circuit pattern layer 34. The second through conductor 53 and the third through conductor 55 are electrically connected to the second circuit pattern layer 35.

[0088] Heat generated in the power semiconductor element 20 is efficiently dissipated to the outside of the power module 1 through the first through conductor 14 and the first circuit pattern layer 34, and through the second through conductor 53, the second circuit pattern layer 35, and the third through conductor 55. The power semiconductor element 20 is prevented from being thermally damaged. The reliability of the power semiconductor device 2 and the power module 1 is improved. Furthermore, the power semiconductor device 2 is miniaturized, and the power module 1 can be miniaturized.

[0089] Embodiment 5. In this embodiment, the power module 1 according to any one of the above-described first to fourth embodiments and their modifications is applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, the following will describe, as a fifth embodiment, a case in which the power module 1 according to any one of the first to fourth embodiments and their modifications is applied to a three-phase inverter.

[0090] The power conversion system shown in Fig. 8 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 is not particularly limited, and may be composed of, for example, a DC system, a solar cell, or a storage battery, or may be composed of a rectifier circuit or an AC / DC converter connected to an AC system. The power supply 100 may be composed of a DC / DC converter that converts DC power output from the DC system into a predetermined power.

[0091] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 8 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0092] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0093] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes a switching element (not shown) and a freewheeling diode (not shown). The switching element switches the voltage supplied from the power supply 100, thereby converting DC power supplied from the power supply 100 into AC power and supplying it to the load 300. The main conversion circuit 201 may have a variety of specific circuit configurations. However, the main conversion circuit 201 of this embodiment is a two-level three-phase full-bridge circuit that may be configured with six switching elements and six freewheeling diodes connected in anti-parallel to each switching element. The power semiconductor elements included in the power module 1 of any of the first to fourth embodiments and their modifications may be applied to each switching element and each freewheeling diode of the main conversion circuit 201. The power module 202 constituting the main conversion circuit 201 may be applied to any of the power modules 1 of the first to fourth embodiments and their modifications. The six switching elements are connected in series with each other to form upper and lower arms, and each upper and lower arm constitutes one phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201, are connected to a load 300.

[0094] The main conversion circuit 201 also includes a drive circuit (not shown) that drives each switching element. The drive circuit may be built into the power module 202 or may be provided external to the power module 202. The drive circuit generates drive signals that drive the switching elements included in the main conversion circuit 201 and supplies the drive signals to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203, the drive circuit outputs a drive signal that turns the switching element on and a drive signal that turns the switching element off to the control electrodes of each switching element.

[0095] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output to the load 300. Then, it outputs a control command (control signal) to a drive circuit provided in the main conversion circuit 201 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0096] In the power conversion device 200 of this embodiment, the power module 1 of any one of the first to fourth embodiments and their modifications is applied as the power module 202 included in the main conversion circuit 201. Therefore, the power conversion device 200 of this embodiment has improved reliability.

[0097] In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level power conversion device or a multi-level power conversion device may also be used. When the power conversion device supplies power to a single-phase load, the present disclosure may be applied to a single-phase inverter. When the power conversion device supplies power to a DC load or the like, the present disclosure may be applied to a DC / DC converter or an AC / DC converter.

[0098] The power conversion device to which the present disclosure is applied is not limited to cases where the load is an electric motor, and may be incorporated, for example, into a power supply device for an electric discharge machine or a laser processing machine, or a power supply device for an induction heating cooker or a contactless power supply system. The power conversion device to which the present disclosure is applied may also be used as a power conditioner for a solar power generation system, a power storage system, or the like.

[0099] The presently disclosed embodiments 1 to 5 and their modifications should be considered to be illustrative in all respects and not restrictive. Unless there is a contradiction, at least two of the presently disclosed embodiments 1 to 5 and their modifications may be combined. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0100] 1 power module, 2 power semiconductor device, 3 insulating circuit board, 10 submount substrate, 11 first main surface, 12 second main surface, 13 insulating substrate, 14 first through conductor, 15 conductive pillar, 16 main current wiring, 17 signal wiring, 18, 18b bonding pad, 19 wiring, 20 power semiconductor element, 21 element body, 22, 23 main surface, 24 active region, 25 first main current electrode, 26 signal electrode, 26b detection electrode, 27 second main current electrode, 28, 29 conductive bonding member, 30 insulating layer, 31, 32 main surface, 33 circuit pattern, 34 first circuit pattern layer, 35 second circuit pattern layer, 36 conductive pattern, 37, 38, 39 conductive bonding member, 40 base plate, 41 joint, 42 case, 44, 45 terminal, 47, 48, 49 Conductive wire, 50 sealing member, 51 underfill member, 52 through-hole conductor, 53 second through-hole conductor, 54 through-hole conductor, 55 third through-hole conductor, 56 through-hole conductor, 60 semiconductor substrate, 61 insulating film, 100 power supply, 200 power conversion device, 201 main conversion circuit, 202 power module, 203 control circuit, 300 load.

Claims

1. a submount substrate having a first major surface and a second major surface opposite the first major surface; a power semiconductor element made of gallium oxide flip-chip mounted on the first main surface; a first conductive bonding member; a second conductive bonding member; a conductive wire; the submount substrate includes a first through conductor extending from the first main surface to the second main surface and a second through conductor extending from the first main surface to the second main surface, the second through conductor being electrically isolated from the first through conductor and overlapping the power semiconductor element in a plan view of the first main surface; the power semiconductor element includes a first main current electrode facing the first main surface, a second main current electrode disposed on an opposite side to the first main current electrode, and a signal electrode facing the first main surface, the first main current electrode is joined to the first through conductor by the first conductive joining member; the conductive wire is bonded to the second main current electrode; The signal electrode is joined to the second through conductor by the second conductive joining member.

2. 2. The power semiconductor device according to claim 1, further comprising an underfill material filled in a gap between said power semiconductor element and said submount substrate and in contact with said first conductive bonding material.

3. 2. The power semiconductor device according to claim 1, wherein said submount substrate includes a main current wiring connected to said first through conductor and extending along said second main surface.

4. The power semiconductor device according to claim 1 , wherein the first penetrating conductors are a plurality of through-hole conductors.

5. the submount substrate includes a semiconductor substrate having a through hole formed therein and an insulating film formed on a surface that defines the through hole; the first through conductor is disposed in the through hole and is electrically insulated from the semiconductor substrate by the insulating film; 5. The power semiconductor device according to claim 4, wherein the semiconductor substrate is formed of a semiconductor material having a thermal conductivity greater than that of gallium oxide.

6. A power semiconductor device as described in claim 1, wherein, in the planar view of the first main surface, the area of ​​the first penetrating conductor is larger than the area of ​​the signal electrode.

7. the submount substrate includes a third through conductor extending from the first main surface to the second main surface; 2 . The power semiconductor device according to claim 1 , wherein the third through conductor is electrically isolated from the first through conductor and the second through conductor, and is exposed from the power semiconductor element in the planar view of the first main surface.

8. The power semiconductor device according to claim 1 ; an insulating circuit board including an insulating layer and a circuit pattern disposed on the insulating layer; the circuit pattern includes a first circuit pattern layer and a second circuit pattern layer separated from the first circuit pattern layer; the first through conductor is electrically connected to the first circuit pattern layer; The second through conductor is electrically connected to the second circuit pattern layer.

9. The power semiconductor device according to claim 7 ; an insulating circuit board including an insulating layer and a circuit pattern disposed on the insulating layer; the circuit pattern includes a first circuit pattern layer and a second circuit pattern layer separated from the first circuit pattern layer; the first through conductor is electrically connected to the first circuit pattern layer; The second through conductor and the third through conductor are electrically connected to the second circuit pattern layer.

10. The power module according to claim 8 , further comprising a sealing member that seals the power semiconductor element.

11. a main conversion circuit including the power module according to any one of claims 8 to 10, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit.

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