Bidirectional isolated DC / DC converter control device

Abstract

To maintain balance of DC voltage between DC / DC converters in a bidirectional insulation type DC / DC converter.SOLUTION: An adder 85 adds a power command value P* and a unit power command value P11. A phase difference / pulse width calculation part 81 calculates unit pulse width command values Wp11, Ws11 of a primary side single-phase inverter and a secondary side single-phase inverter of a unit and a phase difference θFF1. A cell pulse width command value calculation part 86 calculates cell pulse width command values for the primary side single-phase inverter and the secondary side single-phase inverter from the unit pulse width command values Wp11, Ws11. A gate signal generation part 83 generates a gate signal for a representative cell by a phase difference command value θ1 which is a difference between a phase command value θFB1 and a phase difference θFF1 and by the cell pulse width command value. A gate signal of k-th cell is generated by a phase difference command value θ(k) which is a difference between a phase difference command value of the k-th cell θFB(k) and the phase difference θFF1, and by the cell pulse width command value.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to voltage balance control in a series connection of dual active bridge (DAB) type bidirectional isolated DC / DC converters, in which DC power is converted to AC power by an inverter, isolated using a transformer, and then converted back to DC by another inverter. [Background technology]

[0002] Because the input and output sides of a DAB converter are insulated, multiple units can be connected in series and parallel. By designing a single DAB converter cell using low-voltage devices, mass-producing it, and connecting multiple units in series on one side and in parallel on the other, it is possible to convert DC power into low-voltage, high-current power, or vice versa, while still providing isolation.

[0003] In this way, by configuring a unit with multiple cells and connecting both sides (primary side and secondary side) of this unit in series as shown in Figure 7, it is possible to step up / down and insulate high-voltage DC power. However, in this case, maintaining an even DC voltage balance between each unit becomes a challenge. In some cases, damping control is added to suppress current control, voltage control, and DC voltage oscillation and resonance when a separate reactor is connected.

[0004] Furthermore, Non-Patent Documents 1 and 2 discuss capacitor voltage balance control and output voltage control in a configuration in which three or more DAB converters are connected in series and parallel.

[0005] In a DC / DC converter equipped with multiple DAB converters, a conventional technique for determining the pulse width of a semiconductor switching element in each converter is described, for example, in Non-Patent Document 3, and a conventional technique for generating a gate signal for the semiconductor switching element from a pulse width command value, a phase command value, etc. is described, for example, in Patent Document 1.

[0006] Furthermore, multiple units each consisting of multiple DAB converters, one connected in series and the other in parallel, may be connected in series on both sides. This configuration makes it possible to convert very high voltage DC power into high current high voltage DC power, or vice versa, while still providing isolation. Patent Document 2 discloses such a configuration and its control method. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 6785304 [Patent Document 2] WO2017 / 163508 [Non-patent literature]

[0008] [Non-Patent Document 1] P. Zumel et al., “Modular Dual-Active Bridge Converter Architecture,” in IEEE Transactions on Industry Applcations, vol, 52, no. 3, pp. 2444-2455.2016 [Non-patent document 2] F. Deng. X. Znang. [Non-patent document 3] B. Zhao, Q. Song, W. Liu and Y. Sun. “Overview of Dual-Active-Bridge Isolated Bidirectional DC-DC Converter for High-Frequency-Link Power-Conversion System” in IEEE Transactions on Power Electronics.vol.29.no.8.pp.4091-4106.Aug.2014 [Non-patent document 4] Tsuboi, Tsuji, and Yamada, "Instability Phenomena and Countermeasures for Chopper Systems with Input LC Filters," Journal of Electrical Engineering D, Vol. 120, No. 10, pp. 1171-1181 (2000) Summary of the Invention [Problem to be solved by the invention]

[0009] However, in Non-Patent Documents 1 and 2, when current control is applied, simply replacing the voltage control installed in each DAB converter with current control requires high-response current control when the current command value or detected value suddenly changes, so information on the current command value and detected value must be communicated at high speed between the DAB converters.Even in applications where a slow response speed of current control is acceptable, high-speed communication or a large filter is required if current ripple needs to be reduced.

[0010] In Patent Document 2, a separate auxiliary converter is required to maintain the balance of the DC voltage between the units connected in series, which increases the cost and weight accordingly.

[0011] As described above, when controlling equipment consisting of multiple bidirectional isolated DC / DC converters, the challenges are maintaining a balance of DC voltages between the DC / DC converters and reducing the communication load and large filters. Another challenge is maintaining a balance of DC voltages between each unit connected in series without using an auxiliary converter. [Means for solving the problem]

[0012] The present invention has been devised in view of the above-mentioned problems of the prior art, and one aspect thereof is a DAB (Dual Active Brake System) including a primary-side single-phase inverter having an AC side connected to a primary winding of an isolation transformer, a secondary-side single-phase inverter having an AC side connected to a secondary winding of the isolation transformer, a primary-side capacitor connected between positive and negative terminals of the DC side of the primary-side single-phase inverter, and a secondary-side capacitor connected between positive and negative terminals of the DC side of the secondary-side single-phase inverter. a control device for a bidirectional isolated DC / DC converter in which a plurality of DAB converters are provided, the plurality of DAB converters are hierarchically arranged into first to m (m = an integer of 2 or more) stages, the components of the first stage are the cells, a group of a predetermined number of first stage elements is a unit which is a component of the second stage, a group of a predetermined number of second stage elements is a device which is a component of the third stage, and stages 4 and onwards are higher-level devices which are groups of a predetermined number of the devices which are components of the previous stage, the positive and negative terminals of the primary-side single-phase inverters of each of z (z = an integer of 2 or more) cells are connected in series and the positive and negative terminals of each of the secondary-side single-phase inverters are connected in parallel, the primary and secondary sides of the components of the second stage and onwards are connected in series within the group, and the control device is a current control unit that outputs a phase command value which causes the primary-side DC current or the secondary-side DC current to follow a set current command value; a capacitor voltage balance control unit that outputs a phase command value that reduces the deviation between the primary capacitor voltage of the kth (k=an integer from 1 to z) cell and the primary capacitor voltage of a representative cell in the unit, or an average voltage value obtained by dividing the primary DC voltage of the unit by the number of cells in the unit; a unit power command value calculation unit that outputs a unit power command value that controls the power command value between the primary and secondary sides of each component so that the DC voltages upstream of the power transmission in each component are equal within the assembly in the second stage and thereafter; an adder that adds the power command value and the unit power command value; and a unit pulse width command value of the primary single-phase inverter and the secondary single-phase inverter of the unit that is determined by the primary capacitor voltage of the representative cell or each cell, the secondary capacitor voltage, the turns ratio of the primary winding and the secondary winding of the isolation transformer, and the output of the adder,The k-th cell includes a cell pulse width command value calculation unit provided in a representative cell or in each cell, which calculates a cell pulse width command value for the primary-side single-phase inverter and the secondary-side single-phase inverter of a cell, and a gate signal generation unit which generates gate signals for the primary-side single-phase inverter and the secondary-side single-phase inverter based on the cell pulse width command value or the unit pulse width command value, and a phase command value determined by feedback control or a value obtained by adding the phase command value to the unit power command value, wherein the gate signal generation unit generates a gate signal for the representative cell based on the cell pulse width command value and a value obtained by adding the phase command value fed back from the current control unit and the unit power command value, and generates a gate signal for the k-th cell based on the cell pulse width command value or the unit pulse width command value and a value obtained by adding the unit power command value to the phase command value fed back from the capacitor voltage balance control unit or the phase command value fed back from capacitor voltage balance control.

[0013] In another aspect, a DAB (Dual Active Brake System) is provided, which includes a primary single-phase inverter having an AC side connected to a primary winding of an isolation transformer, a secondary single-phase inverter having an AC side connected to a secondary winding of the isolation transformer, a primary capacitor connected between the positive and negative terminals of the DC side of the primary single-phase inverter, and a secondary capacitor connected between the positive and negative terminals of the DC side of the secondary single-phase inverter. a control device for a bidirectional isolated DC / DC converter in which a plurality of DAB converters are provided, the plurality of DAB converters are layered into 1st to m (m = an integer of 2 or more) stages, the components of the first stage are the cells, a group of a predetermined number of the first stage elements is a unit which is a component of the second stage, a group of a predetermined number of the second stage elements is a device which is a component of the third stage, and the fourth stage and onwards are higher-level devices which are groups of a predetermined number of the devices which are the components of the previous stage, the positive and negative terminals of the primary side single-phase inverters of each of z (z = an integer of 2 or more) cells are connected in series and the positive and negative terminals of each of the secondary side single-phase inverters are connected in parallel, the primary and secondary sides of the components of the second stage and onwards are connected in series within the group, the control device comprises a current control unit which outputs a phase command value that makes the primary side DC current or the secondary side DC current follow a set current command value, and a current control unit which outputs a phase command value that makes the primary side DC current or the secondary side DC current follow a set current command value a capacitor voltage balance control unit that outputs a phase command value that reduces the deviation between the primary capacitor voltage of the kth (k=an integer from 1 to z) cell and the average voltage value obtained by dividing the primary capacitor voltage or the primary DC voltage of the unit by the number of cells in the unit; a unit power command value calculation unit that outputs a unit power command value that controls the power command value between the primary and secondary sides of each component so that the DC voltages on the upstream side of the power transmission in each component are equal within the assembly in the second stage and thereafter; an adder that adds the power command value and the unit power command value; a phase difference / pulse width calculation unit that calculates a unit pulse width command value and a phase difference of the primary single-phase inverter and the secondary single-phase inverter of the unit based on the primary capacitor voltage, the secondary capacitor voltage of each cell, the turns ratio of the primary winding and the secondary winding of the isolation transformer, and the output of the adder;The system includes a cell pulse width command value calculation unit that calculates cell pulse width command values ​​for the primary single-phase inverter and the secondary single-phase inverter of a cell, and a gate signal generation unit that generates gate signals for the primary single-phase inverter and the secondary single-phase inverter of each cell based on the cell pulse width command value and a phase difference command value obtained by subtracting a phase command value determined by feedback control from the phase difference calculated by the phase difference / pulse width calculation unit, wherein the gate signal generation unit generates a gate signal for a representative cell based on the phase difference command value, which is the difference between the phase command value fed back from the current control unit and the phase difference calculated by the phase difference / pulse width calculation unit, and the cell pulse width command value, and generates a gate signal for the kth cell based on the phase difference command value, which is the difference between the phase command value fed back from the capacitor voltage balance control unit and the phase difference calculated by the phase difference / pulse width calculation unit, and the cell pulse width command value.

[0014] In another aspect, a DAB (Dual Active Brake System) is provided, which includes a primary single-phase inverter having an AC side connected to a primary winding of an isolation transformer, a secondary single-phase inverter having an AC side connected to a secondary winding of the isolation transformer, a primary capacitor connected between the positive and negative terminals of the DC side of the primary single-phase inverter, and a secondary capacitor connected between the positive and negative terminals of the DC side of the secondary single-phase inverter. a control device for a bidirectional isolated DC / DC converter in which a plurality of DAB converters are provided, the plurality of DAB converters are layered into 1st to m (m=an integer of 2 or more) stages, the components of the first stage being the cells, a group of a predetermined number of the first stage elements being a unit which is a component of the second stage, a group of a predetermined number of the second stage elements being a device which is a component of the third stage, and the fourth stage and thereafter being a higher-level device which is a group of a predetermined number of the devices which are the components of the previous stage, and a configuration in which the positive and negative pole terminals of the primary side single-phase inverters of each of z (z=an integer of 2 or more) cells are connected in series and the positive and negative pole terminals of each of the secondary side single-phase inverters are connected in parallel is defined as a unit, and the primary and secondary sides of the components of the second stage and thereafter are connected in series within the group, the control device a capacitor voltage balance control unit that outputs a phase command value that reduces the deviation between an average voltage value obtained by dividing the primary DC voltage of the unit or the primary DC voltage of the unit by the number of cells in the unit and the primary capacitor voltage of the kth (k=an integer from 1 to z) cell; a unit power command value calculation unit that outputs a unit power command value that controls a power command value between the primary and secondary sides of each component so that the DC voltages on the upstream side of the power transmission in each component are equal within the assembly in the second stage and thereafter; an adder that adds the power command value and the unit power command value; a phase difference / pulse width calculation unit that calculates a unit pulse width command value and a phase difference of the primary single-phase inverter and the secondary single-phase inverter of the unit using the average voltage value obtained by dividing the primary DC voltage of the unit by the number of cells in the unit, the secondary DC voltage in the unit, the turns ratio of the primary winding and the secondary winding of the isolation transformer and the output of the adder;The system includes a cell pulse width command value calculation unit that calculates cell pulse width command values ​​for the primary single-phase inverter and the secondary single-phase inverter of a cell, and a gate signal generation unit that generates gate signals for the primary single-phase inverter and the secondary single-phase inverter of each cell based on the cell pulse width command value and a phase difference command value obtained by subtracting a phase command value determined by feedback control from the phase difference calculated by the phase difference / pulse width calculation unit, wherein the gate signal generation unit generates a gate signal for a representative cell based on a phase difference command value that is the difference between the phase command value of a representative cell fed back from the current control unit and the phase difference calculated by the phase difference / pulse width calculation unit, and the cell pulse width command value, and generates a gate signal for the kth cell based on a phase difference command value that is the difference between the phase command value of the kth cell fed back from the capacitor voltage balance control unit and the phase difference calculated by the phase difference / pulse width calculation unit, and the cell pulse width command value.

[0015] In one aspect, the unit power command value calculation unit controls the unit power command value of a specific component in the second or subsequent stage so that the DC voltage upstream of the power transmission of the specific component is reduced when the energy stored in the primary DC capacitor and secondary DC capacitor of the specific component is greater than that of the other components in the assembly, and controls the unit power command value of the specific component so that the DC voltage upstream of the power transmission of the specific component is increased when the energy stored in the primary DC capacitor and secondary DC capacitor of the specific component in the second or subsequent stage is smaller than that of the other components in the assembly.

[0016] In one aspect, the control device is characterized in that, when the energy stored in the primary side DC capacitor and the secondary side DC capacitor of a specific component in the second stage or later is other than the smallest among all the components, the control device reduces the operating power factor of the component.

[0017] In one aspect, the control device is characterized in that, when the energy stored in the primary side DC capacitor and the secondary side DC capacitor of a specific component in the second stage or later is other than the smallest among all the components, the control device increases the DC component of the current output by the component. [Effects of the Invention]

[0018] According to the present invention, in a control device for a bidirectional isolated DC / DC converter, it is possible to maintain the balance of DC voltages between the DC / DC converters while reducing the communication load. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a diagram showing an isolated bidirectional DC / DC converter according to first to third embodiments. [Figure 2] This is an operational waveform diagram of the pulse width control method for the semiconductor switching elements of the primary-side single-phase inverter and the secondary-side single-phase inverter in Figure 1. [Figure 3] FIG. 2 is a block diagram showing a control device according to the first embodiment. [Figure 4] FIG. 10 is a block diagram showing a control device according to a second embodiment. [Figure 5] FIG. 11 is a block diagram showing a control device according to a third embodiment. [Figure 6] FIG. 3 is a block diagram showing a control unit in each embodiment. [Figure 7] FIG. 10 is a diagram showing a bidirectional isolated DC / DC converter according to a fourth embodiment. [Figure 8] FIG. 10 is a block diagram showing a control device according to a fourth embodiment. [Figure 9] FIG. 4 is a block diagram showing a unit power command value calculation unit. [Figure 10] FIG. 4 is a block diagram showing a cell pulse width command value calculation unit. [Figure 11] FIG. 10 is a diagram showing a bidirectional isolated DC / DC converter according to a fifth embodiment. [Figure 12] FIG. 2 is a block diagram showing the i-th device voltage control deviation calculation unit. [Figure 13]FIG. 10 is a block diagram showing the i-th device energy deviation calculation unit. [Figure 14] FIG. 10 is a block diagram showing a case where the fourth and fifth embodiments are applied to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, first to fifth embodiments of the control device for a bidirectional isolated DC / DC converter according to the present invention will be described in detail with reference to FIGS.

[0021] [Embodiment 1] FIG. 1 shows the configuration of a bidirectional isolated DC / DC converter according to the first embodiment.

[0022] In Figure 1(a), which shows a configuration in which an inductor (L) is connected to the secondary side, 1 is a primary-side single-phase inverter in which semiconductor switching elements S11, S21, S31, and S41 are bridge-connected, and 2 is a secondary-side single-phase inverter in which semiconductor switching elements S51, S61, S71, and S81 are bridge-connected.

[0023] The connection point of semiconductor switching elements S11 and S21 is connected via reactor L1 and primary winding 31 of insulating transformer 3 to the connection point of semiconductor switching elements S31 and S41.

[0024] The connection point of semiconductor switching elements S51 and S61 is connected via reactor L2 and secondary winding 32 of insulating transformer 3 to the connection point of semiconductor switching elements S71 and S81.

[0025] The primary winding 31 and secondary winding 32 of the insulating transformer 3 are insulated from each other, and the turns ratio thereof is N1:N2.

[0026] The semiconductor switching elements S11, S21, S31, S41, S51, S61, S71, and S81 are configured by, for example, IGBTs, and switching control is performed by gate signals generated by a gate signal generating unit of the control device, which will be described later.

[0027] V acp1 is the voltage at the connection point of semiconductor switching elements S11 and S21, V acs1 indicates the voltage at the connection point of the semiconductor switching elements S51 and S61, respectively.

[0028] Between the positive and negative terminals of the DC side of the primary single-phase inverter 1, a primary side capacitor C in is connected, and a secondary-side capacitor C is connected between the positive and negative terminals of the DC side of the secondary-side single-phase inverter 2. out is connected.

[0029] V in1 is the primary side capacitor C in voltage, V out is the secondary capacitor C out The voltages shown are:

[0030] The primary side single-phase inverter 1, the primary side capacitor C in , isolation transformer 3, secondary single-phase inverter 2, secondary capacitor C out The first DAB converter 101 is configured as above, and n DAB converters 101, . . . , 10 n is provided.

[0031] 11 is a first DC power supply, and n DAB converters 101 to 102 are connected between its positive and negative terminals. n The positive and negative terminals of the primary side single-phase inverters 1 are connected in series in this order.

[0032] 12 is a second DC power supply, and n DAB converters 101 to 102 are connected between its positive and negative terminals. n The positive and negative terminals of the secondary side single-phase inverters 2 are connected in parallel.

[0033] An inductor 22 (L) is connected between the positive terminal of the secondary-side single-phase inverter 2 of the first DAB converter 101 and the positive terminal of the second DC power supply 12. Note that the second DC power supply 12 is connected to, for example, a load (not shown).

[0034] V cc is the voltage of the first DC power supply 11, V load indicates the voltage of the second DC power supply 12.

[0035] In Figure 1(b), which shows a configuration in which an inductor (L) is connected to the primary side, instead of the inductor 22 in Figure 1(a), an inductor 21(L) is connected between the positive terminal of the primary side single-phase inverter 1 of the first DAB converter 101 and the positive terminal of the first DC power source 11, and the other parts are configured in the same way as in Figure 1(a).

[0036] The inductors 21 and 22 may not be connected.

[0037] In the following description, the DAB converters 101, 102, 103, 104, 105, 106, 107, 108, 109, 110A, 110B, 111C, 111D, 111E, 111F, 111G, 111H, 111I, 111J ... n Each of these units is sometimes called a cell. The current and voltage of each part in Figures 1(a) and 1(b) are detected by a current detector and a voltage detector, respectively, not shown.

[0038] 2 shows the operation waveforms of the pulse width control method in the control device of the first embodiment. n The period during which the output voltage is zero is set by simultaneously turning on two upper arm semiconductor switching elements (S11 and S31 on the primary side as an example) or two lower arm semiconductor switching elements (S21 and S41 on the primary side as an example) of the primary side single-phase inverter 1 and secondary side single-phase inverter 2. When the upper left and lower right switching elements of each inverter (S11 and S41 on the primary side as an example) are simultaneously turned on, the output voltage becomes positive, and the pulse widths W11 and W21 can be adjusted by the length of the ON time. When the lower left and upper right switching elements of each inverter (S21 and S31 on the primary side as an example) are simultaneously turned on, a negative voltage can be output.

[0039] A method is being considered for expanding the soft switching range using this pulse width control even when the difference between the DC voltages on the primary and secondary sides is large. The control of this embodiment 1 can be applied to square wave control in which there is no period when the output voltage of both inverters is zero, or when pulse width control is performed on only one inverter, or on both inverters.

[0040] In the control of the first embodiment, the control system is divided for each DAB converter.

[0041] The control device in the first embodiment includes the control blocks shown in Figs. 3 and 6. In Fig. 3, 30 includes n DAB converters 101 to 10 n The pulse width command value W of the primary side single-phase inverter 1 and the secondary side single-phase inverter 2 1(n) ,W 2(n) and a phase command value θ determined by feedback control, which will be described later. FB(n) Based on each DAB converter 101,~,10 n Gate signal S1 of the primary side single-phase inverter 1 and the secondary side single-phase inverter 2 (n) ,S2 (n) ,S3 (n) ,S4 (n) ,S5 (n) ,S6 (n) ,S7 (n) ,S8 (n) The gate signal generator generates the gate signal.

[0042] The pulse width command value W 1(n) ,W 2(n) is the input voltage of the nth cell of each DAB converter (primary side capacitor C in Voltage V in(n) ), output voltage (secondary capacitor C out Voltage)V out , is determined from the turns ratio N1 / N2 of the insulating transformer 3 and the power command value P* by the method described in Non-Patent Document 3, for example.

[0043] The phase command value θ determined by the feedback control FB(n)is generated by the control block in Figure 6. Figure 6(a) applies to the device in Figure 1(a) with inductor 22 connected to the secondary side, and Figure 6(b) applies to the device in Figure 1(b) with inductor 21 connected to the primary side.

[0044] In FIG. 6(a), 61 indicates the current (secondary DC current) flowing through the inductor 22. load The detected value and the set current command value I load * is used as an input, and the phase command value θ is used to make the detected value follow the current command value by performing PI control on the difference. acr The current control unit outputs

[0045] 62 is the secondary capacitor C of the first DAB converter 101 out Voltage V out is used as the input, and the inductor 22 and secondary capacitor C out The phase difference θ that suppresses the resonance caused by dump1 The damping control unit outputs

[0046] The input of the damping control unit 62 is the current (secondary DC current) I load may also be used.

[0047] The damping control section 62 and a damping control section 66 described later use, for example, the damping circuit shown in FIG. 2 of Non-Patent Document 4.

[0048] 63 is the output of the current control unit 61 (phase command value θ acr ) to the output of the damping control unit 62 (phase difference θ dump1 ) is subtracted to obtain the phase command value θ for the first cell. FB1 is a subtractor that outputs

[0049] If there is no inductor 22 and there is no risk of resonance, or if resonance is tolerable, the damping control section 62 may be omitted.

[0050] 64 is the primary side capacitor C of the DAB converter 101 of the first cell (representative cell) that serves as the reference in Voltage V in1 is used as the command value, and the nth cell of the DAB converter 10 n The primary side capacitor C in Voltage V in(n) is input as the detected value of the controlled object, and the deviation between them is amplified by the controller, and the capacitor voltage V of the nth cell is calculated. in(n) The first cell capacitor voltage V in1 The phase command value θ required to follow FB(n) (=phase difference θ bal(n) ) is a capacitor voltage balance control unit that outputs

[0051] In addition, the primary side capacitor C of the first cell in Voltage V in1 Instead, the primary side DC voltage V of the first DC power supply 11 cc The average voltage value (V cc / N cell ) may be used as input.

[0052] In FIG. 6(b), 65 is the current (primary DC current) flowing through the inductor 21. in The detected value and the set current command value I in * is used as an input, and the phase command value θ is used to make the detected value follow the current command value by performing PI control on the deviation. acr The current control unit outputs

[0053] 66 is the primary side capacitor C of the first DAB converter 101 in Voltage V in1 is used as the input, and the inductor 21 and the primary side capacitor C in The phase difference θ that suppresses the resonance caused by dump1 The damping control unit outputs

[0054] The input of the damping control unit 66 is the current (primary side DC current) I inや Voltage (input voltage) V of the first DC power supply 11cc Either one or both of these may be used.

[0055] 67 is the output of the current control unit 65 (phase command value θ acr ) to the output of the damping control unit 66 (phase difference θ dump1 ) is subtracted to obtain the phase command value θ for the first cell. FB1 is a subtractor that outputs

[0056] If there is no inductor 21 and there is no risk of resonance, or if resonance is tolerable, the damping control section 66 may be omitted.

[0057] Reference numeral 64 denotes a capacitor voltage balance control section having the same configuration as the capacitor voltage balance control section 64 in FIG. 6(a).

[0058] The subtraction output θ of the subtractors 63 and 67 FB1 (phase command value) and the output θ of the capacitor voltage balance control unit 64 FB(n) (phase command value) is the phase command value (θ FB(n) ) is input to the gate signal generating unit 30.

[0059] In controlling the first cell (DAB converter 101), the outputs of current control units 61 and 65 (because the power supply voltage is considered constant in this embodiment 1) that control the input power or output power, and the outputs of damping control units 62 and 66 that suppress LC resonance are applied.

[0060] That is, the gate signal generating unit 30 generates a phase command value θ output from the current control unit 61 or 65. acr The phase difference θ output from the damping control unit 62 or 66 dump1 is subtracted by the subtractor 63 or 67 to obtain the feedback phase command value θ FB1 and the pulse width command value W 1(n) ,W 2(n) A gate signal for the DAB converter 101 of the first cell is generated by the above.

[0061] In the control of the second cell and thereafter (the DAB converter 102 and thereafter), the balance control of the capacitor voltage of each cell is applied. That is, the gate signal generating unit 30 controls the phase command value θ FB(n) and the pulse width command value W 1(n) ,W 2(n) By nth cell DAB converter 10 n Generates a gate signal for

[0062] By dividing the control among the cells as described above, the only communication required between the cells to achieve the desired control is the input voltage value and the detected capacitor voltage value. Because only the first cell performs current control, high-speed communication of information on the current command value and detected value between the cells is not required. Furthermore, when the input is capacitive, the input voltage value does not change at high speed, reducing the communication load between the cells.

[0063] Furthermore, this embodiment 1 can be applied regardless of the number of installed cells, and there are few changes to control when the number of cells is changed, making it possible to shorten design time. Furthermore, this embodiment 1 can be applied not only to power control on the parallel side but also to power control on the series side.

[0064] As described above, according to the first embodiment, the signals communicated between cells are input / output voltages and capacitor voltages that do not fluctuate suddenly, so the communication load can be reduced. Therefore, the control system can be constructed using optical cables or wireless communication, which are difficult to use when the communication load is high, and wiring can be reduced.

[0065] [Embodiment 2] The control device in the second embodiment includes the control blocks shown in Figures 4 and 6. The second embodiment is characterized in that command values ​​for the pulse width and phase difference are calculated in advance in order to improve the responsiveness of power control.

[0066] In FIG. 4, 41 denotes a plurality of DAB converters 101, 102, 103, 104, 105, 106, 107, 108, 109, 110A, 111B, 111C, 111D, 111E, 111F, 111H ... n Input voltage (primary capacitor C in Voltage)V in(n), output voltage (secondary capacitor C out Voltage)V out , the power command value P* and the turns ratio N1 / N2 of the isolation transformer 3 are used to determine the pulse width command value W 1(n) ,W 2(n) (The pulse width W 11 ,W 21 ) and the phase difference θ FF(n) This is the phase difference and pulse width calculation section that calculates

[0067] The phase difference / pulse width calculation unit 41 performs calculations using the technique of Non-Patent Document 3, for example.

[0068] 42 is the phase difference θ calculated by the phase difference / pulse width calculation unit 41 FF(n) From the above, the phase command value θ determined by the feedback control of each control unit in FIG. FB(n) is subtracted to obtain the phase difference command value θ (n) is a subtractor that outputs

[0069] In this way, the phase command value θ of the feedback control is subtracted from the subtractor 42. FB(n) and the phase difference θ calculated by the phase difference / pulse width calculation unit 41 FF By taking the difference, the error between the transmission power and the power command value P* due to deviations in the circuit constants, detection errors, etc. is corrected.

[0070] 43 is the pulse width command value W calculated by the phase difference / pulse width calculation unit 41 1(n) ,W 2(n) and the phase difference command value θ output from the subtractor 42. (n) Based on each DAB converter 101,~,10 n Gate signal S1 of the primary side single-phase inverter 1 and the secondary side single-phase inverter 2 (n) ,S2 (n) ,S3 (n) ,S4 (n) ,S5 (n) ,S6 (n) ,S7 (n) ,S8 (n) The gate signal generator generates the gate signal.

[0071] The subtraction output θ of the subtractors 63 and 67 in FIG. FB1 (phase command value) and the output θ of the capacitor voltage balance control unit 64 FB(n) (Phase command value) is the phase command value θ determined by feedback control. FB(n) 4 as the phase difference θ FF(n) The difference is taken from

[0072] In the control of the first cell (DAB converter 101), the outputs of the current control units 61 and 65 and the outputs of the damping control units 62 and 66 are applied in the same manner as in the first embodiment.

[0073] That is, the gate signal generator 43 calculates the phase command value θ FB1 and the phase difference θ calculated by the phase difference / pulse width calculation unit 41 FF(n) The difference between the phase difference command value θ and the phase difference command value θ is calculated by the subtractor 42. (n) and the pulse width command value W 1(n) ,W 2(n) A gate signal for the DAB converter 101 of the first cell is generated by the above.

[0074] In the control of the second cell and thereafter (the DAB converter 102 and thereafter), the balance control of the capacitor voltage of each cell is applied. That is, the gate signal generator 43 controls the phase command value θ FB(n) and the phase difference θ calculated by the phase difference / pulse width calculation unit 41 FF(n) The difference between the phase difference command value θ and the phase difference command value θ is calculated by the subtractor 42. (n)と , pulse width command value W 1(n) ,W 2(n) By nth cell DAB converter 10 n Generates a gate signal for

[0075] As described above, the phase difference / pulse width calculation unit 41 calculates the pulse width and phase difference in a feedforward manner, thereby improving the responsiveness of power control. However, due to cell loss, dead time, gate driver delays, and the like, the pulse width and phase difference are not output as calculated, and the actual output power contains an error relative to the command value. In the second embodiment, feedback control is performed only for this error (current control units 61, 65). Therefore, compared to the first embodiment, there is no need to speed up the feedback control response.

[0076] As described above, according to the second embodiment, the addition of a phase difference / pulse width calculation unit improves the responsiveness of power control. Furthermore, the pulse width of each cell is changed in accordance with the capacitor voltage imbalance rate (in accordance with the output of the capacitor voltage balance control unit 64), improving the power conversion efficiency in the transient state of capacitor voltage balance control. However, although it is necessary to communicate the power command value P* between each cell compared to the first embodiment, the increase in communication load is slight for applications that do not require a high response speed.

[0077] [Embodiment 3] The control device in the third embodiment includes the control blocks shown in FIGS. 5 and 6. In the third embodiment, some of the input parameters of the phase difference / pulse width calculation unit 41 in the second embodiment are changed to obtain the pulse width command W 11 , W 21 and phase difference θ FF1 Calculate the pulse width command W for the first cell. 11 , W 21 and phase difference θ FF1 is used to control the DAB converters from the second cell onwards.

[0078] In FIG. 5(a) showing the control block of the first cell, 51 indicates the voltage V of the first DC power supply 11. cc The number of DAB converters installed is N cell Average voltage value divided by V cc / N cell (average input voltage), voltage V of the second DC power supply 12 load, the power command value P* and the turn ratio N1 / N2 of the primary winding and secondary winding of the isolation transformer 3 are input, and the pulse width command value W 11 ,W 21 and phase difference θ FF1 This is the phase difference and pulse width calculation section that calculates

[0079] 52 is the phase difference θ calculated by the phase difference / pulse width calculation unit 51 FF1 From the above, the phase command value θ determined by the feedback control of each control unit in FIG. FB1 and outputs the phase difference command value θ1.

[0080] 53 is the pulse width command value W calculated by the phase difference / pulse width calculation unit 51 11 ,W 21 and a gate signal generating unit that generates gate signals S11, S21, S31, S41, S51, S61, S71, and S81 for the primary side single-phase inverter 1 and the secondary side single-phase inverter 2 of the first cell DAB converter 101 based on the phase difference command value θ1 output from the subtractor 52.

[0081] In FIG. 5(b) showing the control block of the DAB converter for the second cell and thereafter, 54 is the phase difference θ of the first cell calculated by the phase difference / pulse width calculation unit 51 in FIG. 5(a). FF1 The phase command value θ from the second cell onwards determined by the feedback control of each control unit in Fig. 6 FB(n) The phase difference command value θ for the second cell and after is calculated by subtracting (n) is a subtractor that outputs

[0082] The gate signal generator 53 in FIG. 5(b) generates the pulse width command value W for the first cell calculated by the phase difference / pulse width calculator 51. 11 ,W 21 and the phase difference command value θ (n) Based on this, the DAB converters 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 12 n The gate signal (S1 (n), S2(n) ,S3 (n) ,S4 (n) ,S5 (n) ,S6 (n) ,S7 (n) ,S8 (n) Generate.

[0083] During transient operation of the capacitor voltage balance control unit 64 in Fig. 6, there is a deviation in the capacitor voltage, which causes the pulse width and phase difference to change. Since the change in pulse width acts as a disturbance to the capacitor voltage balance control and damping control, when the capacitor voltage fluctuates significantly, the responsiveness of the capacitor voltage balance control and damping control deteriorates.

[0084] To solve this problem, in this embodiment 3, the phase difference and pulse width are calculated using the first cell capacitor voltage V in1 Instead, the input voltage average value (V cc / N cell ) is used as the input, and the same phase difference θ FF1 , pulse width command value W 11 ,W 21 This reduces disturbances to the capacitor voltage balance control section 64 and the damping control sections 62 and 66 due to fluctuations in the capacitor voltage, thereby improving responsiveness.

[0085] In this way, the response of the voltage balance control is improved, so the input capacitor capacity can be reduced, and the device can be made smaller. However, compared to the second embodiment, the signal to be communicated between cells is changed from the power command value P* to W 11 ,W 21 ,θ FF1 However, the voltage Vcc of the first DC power supply 11 and the voltage Vload of the second DC power supply 12 to which the capacitor is connected do not change suddenly. As for the remaining power command value P*, if the application does not require a high response speed as in the second embodiment, the 11 ,W 21 ,θ FF1 These three factors change only slowly, so the third embodiment can be applied even to low-speed communications.

[0086] [Embodiment 4] The first to third embodiments are methods for controlling a unit consisting of multiple DAB converters, one connected in series and the other in parallel. The first to third embodiments are methods characterized by a reduction in communication load and wiring.

[0087] The first to third embodiments explain the control method for a single unit, and do not mention the control method when a plurality of units are connected in series on both sides.

[0088] In Fig. 7, a unit is made up of z (z = an integer of 2 or more) DAB converters (cells) with their primary sides connected in series and their secondary sides connected in parallel, and y (y = an integer of 2 or more) units are connected in series on both sides. This fourth embodiment is applied to the circuit in Fig. 7. In Fig. 7, one DAB converter is called a cell.

[0089] The main circuit configuration is explained hierarchically. The first-level component is the cell. The second-level component is the unit, which is an assembly of a certain number (z units) of cells, which are first-level components, connected in series on the primary side and in parallel on the secondary side. The third-level component is the device. The device is an assembly of a certain number (y units), which are second-level components, connected in series on both the primary and secondary sides.

[0090] In other words, the isolated bidirectional DC / DC converter of the fourth embodiment includes a first DC power supply DCP, a second DC power supply DCS, and one third-stage component between the first DC power supply DCP and the second DC power supply DCS. Inside the third-stage component are y second-stage components connected in series, namely, the 11th unit to the 1yth unit. Inside the second-stage component are z first-stage components, each with its primary side connected in series and its secondary side connected in parallel, and these are the 111th cell to the 11zth cell, respectively.

[0091] In Figure 7, DCP is the first DC power supply, DCS is the second DC power supply, Cp is the primary side capacitor, Cs is the secondary side capacitor, Vdcp is the primary side DC voltage of the first DC power supply DCP, and Vdcs is the secondary side DC voltage of the second DC power supply DCS.

[0092] Furthermore, Vdcp111 is the primary-side capacitor voltage, Vdcs111 is the secondary-side capacitor voltage, ip111 is the primary-side AC current detection value, and is111 is the secondary-side AC current detection value. The three-digit alphanumeric character at the end of each symbol indicates the cell number, and the two-digit alphanumeric character indicates the unit number. For example, Vdcp111 indicates the primary-side capacitor voltage of the 111th cell of the 11th unit, and Vdcp11 indicates the primary-side DC voltage of the 11th unit (the sum of the primary-side capacitor voltages of the 111th cells to the 11zth cells of the 11th unit).

[0093] The semiconductor switching elements S11 to S81, the primary side single-phase inverter 1, and the secondary side single-phase inverter 2 are the same as those in the first to third embodiments.

[0094] One end of a reactor L1 is connected to the connection point of semiconductor switching elements S11 and S21. One end of a reactor L2 is connected to the connection point of semiconductor switching elements S31 and S41. One end of a reactor L3 is connected to the connection point of semiconductor switching elements S51 and S61. One end of a reactor L4 is connected to the connection point of semiconductor switching elements S71 and S81.

[0095] The primary winding of an isolation transformer Tr is connected between the other end of reactor L1 and the other end of reactor L2. The secondary winding of an isolation transformer Tr is connected between the other end of reactor L3 and the other end of reactor L4. The turns ratio of the isolation transformer Tr is 1:n.

[0096] 7, reactors L1 to L4 are connected in series between the primary-side single-phase inverter 1, the secondary-side single-phase inverter 2, and the isolation transformer Tr, but the reactors L1 to L4 may be replaced by the leakage inductance of the isolation transformer Tr, or both the reactors L1 to L4 and the leakage inductance of the isolation transformer Tr may be used.

[0097] 8 to 10 show block diagrams of the control device of the fourth embodiment.

[0098] In this fourth embodiment, the third embodiment is applied to voltage balance control of each cell in a unit. FIG. 8 shows the control block of the 11th unit. In this fourth embodiment, each unit has the control block of FIG. 8. Also, like the first to third embodiments, the fourth embodiment has the control block of FIG. 6. FIG. 8 differs from the third embodiment in the following respects.

[0099] FIG. 8(a) shows the control block of the representative cell (111th cell of the 11th unit).

[0100] The adder 85 adds the power command value P* to the unit power command value P of the 11th unit (described later). 11 Add.

[0101] The phase difference / pulse width calculation unit 81 receives Vdcp11 / z, which is the value obtained by dividing the primary side DC voltage Vdcp11 of the 11th unit by the number of cells z of the unit, the secondary side DC voltage Vdcs11 of the 11th unit, the output of the adder 85, and the turns ratio 1 / n of the isolation transformer Tr, and calculates the unit pulse width command values ​​Wp11, Ws11, and the phase difference θ FF1 Output.

[0102] The subtractor 82 calculates the phase difference θ FF1 to the phase command value θ FB1 is subtracted and output as the phase difference command value θ1.

[0103] The cell pulse width command value calculation unit 86 outputs cell pulse width command values ​​Wp111p, Wp111m, Ws111p, and Ws111m based on the unit pulse width command values ​​Wp11 and Ws11 of the 11th unit.

[0104] The gate signal generating unit 83 generates a gate signal based on the cell pulse width command values ​​Wp111p, Wp111m, Ws111p, and Ws111m of the 111th cell and the phase difference command value θ1, and generates a gate signal for the semiconductor switching element of the corresponding 111th cell.

[0105] 8(b) shows the control block of the 11k-th cell (2≦k≦z) of the 11th unit. The subtractor 84 calculates the phase difference θ FF1 to the phase command value θ FB(k) is subtracted, and the phase difference command value θ (k) The gate signal generating unit 83 outputs the cell pulse width command values ​​Wp111p, Wp111m, Ws111p, and Ws111m and the phase difference command value θ (k) A gate signal is generated based on the

[0106] In this fourth embodiment, voltage balance control of each unit is applied. Fig. 9 is a block diagram of a unit power command value (P1j) calculation section of the 1j unit.

[0107] The energy E1j stored in both the primary-side capacitor Cp and the secondary-side capacitor Cs of the 1j unit is calculated as follows (not shown):

[0108] The energy stored in the unit's primary-side capacitor Cp is determined by applying a low-pass filter (LPF) to the primary-side capacitor voltages Vdcp1j1 to Vdcp1jz of z cells, squaring the result, multiplying it by the primary-side capacitor capacitance Cp, and dividing the result by two. The sum of these two results is the energy stored in the unit's secondary-side capacitor Cs. Similarly, the low-pass filter (LPF) is applied to the secondary-side DC voltage Vdcs1j, squaring the result, multiplying it by the secondary-side capacitor capacitance Cs and the number of cells z in the unit, and dividing the result by two. The sum of these two results is the energy E1j.

[0109] That is, E1j=Cp / 2×(Vdcp1j1 2 +Vdcp1j2 2 +…Vdcp1jz 2)+zCs×Vdcs1j 2 / 2.

[0110] For simplicity, the energy stored in the primary capacitor Cp of the unit can be calculated approximately from the average value of the primary capacitor voltages Vdcp1j1 to Vdcp1jz of z cells. In this case, E1j ≒ Cp / 2 × (Vdcp1j / z) 2 +zCs×Vdcs1j 2 / 2.

[0111] E1avg is the average value of the energy stored in both the primary-side capacitor Cp and the secondary-side capacitor Cs of the 11th to 1yth units. A subtractor 91 calculates the deviation between the energy E1j and the average energy value E1avg.

[0112] An amplifier 92 amplifies the output of the subtractor 91 by multiplying it by a gain G2. The gain G2 may be a fixed value, or the value may be changed by a gain adjuster 93 based on the power command value P*, such as by decreasing it when the power command value P* is near zero as shown in the figure. The output of the amplifier 92 becomes the DC voltage imbalance command value Vdc1j of the 1j unit.

[0113] The low-pass filter LPF1 removes ripples and noises having a frequency twice that of the fundamental wave from the primary-side DC voltage Vdcp1j of the 1j unit.

[0114] The average primary DC voltage Vdcp1avg of the 11th to 1yth units is either the total of Vdcp11 to Vdcp1y or the primary DC voltage Vdcp divided by the number y of units.

[0115] The adder 94 calculates the deviation between the imbalance command value Vdc1j and the primary DC voltage average value Vdcp1avg, and then adds the primary DC voltage Vdcp1j of the 1j unit to the deviation. The output of the adder 94 is input to the upper terminal of the switch SW1.

[0116] The low-pass filter LPF2 removes ripples and noises having a frequency twice that of the fundamental wave from the secondary-side DC voltage Vdcs1j of the 1j unit.

[0117] Vdcs1avg is the average value of the secondary side DC voltages of the 11th to 1y units.

[0118] The adder 95 calculates the deviation between the unbalance command value Vdc1j and the secondary DC voltage average value Vdcs1avg, and further adds the secondary DC voltage Vdcs1j of the 1j unit to the deviation.

[0119] A multiplier 96 multiplies the output of the adder 95 by the reciprocal 1 / n of the transformer turns ratio of the insulating transformer Tr and inverts the sign. The output of the multiplier 96 is input to the lower terminal of the switch SW1.

[0120] P* is the power command value transmitted between the primary and secondary sides. If the power command value P* is positive, power is transmitted from the primary side to the secondary side, and if it is negative, power is transmitted from the secondary side to the primary side. The power command value P* can be given externally, or it can be obtained by voltage control or current control of either the primary side DC voltage Vdc1 or the secondary side DC voltage Vdc2.

[0121] Comparator 97 detects whether power command value P* is positive or not. Switch SW1 outputs the input to its upper terminal if power command value P* is positive, and outputs the input to its lower terminal if power command value P* is zero or negative.

[0122] In order to prevent frequent switching of the switch SW1, if the power command value P* is near zero, the immediately preceding switch state may be maintained to provide a hysteresis characteristic.

[0123] If the power command value P* is zero, the average value of the deviation of the primary DC voltage of the 1j unit and the deviation of the secondary DC voltage of the 1j unit may be output.

[0124] An adder 98 adds the device voltage control deviation Vd1 to the output of the switch SW1. In the fourth embodiment, Vd1=0.

[0125] An amplifier 99 amplifies the output of the adder 98 and outputs a unit power command value P1j for the 1j unit. In this example, the following two are used in combination: A proportional amplifier P1 outputs a value proportional to the output of the adder 98. A first-order lag filter 99a with gain amplifies the low-frequency components of the output of the adder 98. An adder 99b adds the outputs of the above two amplifiers and outputs a unit power command value P1j for the 1j unit. The unit power command value P1j for the 1j unit output from the amplifier 99 is input to the adder 85 in Figure 8.

[0126] Figure 10 shows a block diagram of the calculation unit for the cell pulse width command values ​​(Wp1jkp, Wp1jkm, Ws1jkp, Ws1jkm) of the 1jkth cell of the 1j unit. Figure 10 is composed of the following components.

[0127] A subtractor 101 subtracts a unit pulse width command value Ws1j from a unit pulse width command value Wp1j. A comparator 102 receives the output of the subtractor 101 and determines whether Wp1j>Ws1j. The comparator 102 may have a hysteresis characteristic to prevent frequent switching of a switch SW2, which will be described later.

[0128] The switch SW2 receives the unit pulse width command values ​​Wp1j and Ws1j and outputs the smaller one, while the switch SW3 receives the unit pulse width command values ​​Wp1j and Ws1j and outputs the larger one.

[0129] E1j is the energy stored in both the primary capacitor Cp and the secondary capacitor Cs of the 1j unit. E1min is the minimum value of the energy stored in both the primary capacitor Cp and the secondary capacitor Cs of each cell of the 11th to 1y units. Subtractor 103 subtracts minimum value E1min from energy E1j to obtain the deviation.

[0130] The adder 104 adds the device energy deviation Ed1 to the deviation (the output of the subtractor 103). In the fourth embodiment, the device energy deviation Ed1 is zero.

[0131] Amplifier 105 amplifies the output of adder 104. In this example, the following two amplifiers are used in combination. Proportional amplifier P2 outputs a value proportional to the output of adder 104. Gain-added first-order lag filter 105a amplifies the low-frequency components of the output of adder 104. Adder 105b adds the outputs of these two amplifiers. The gains of the two amplifiers may be fixed values, or may be variable so that they become larger the closer the power command value P* is to zero and smaller the further away it is from zero.

[0132] Adder 106 adds the output of amplifier 105 and the output of switch SW2.

[0133] The first limiter 107 limits the output of the adder 106. The upper limit of the first limiter 107 is usually 1, and the lower limit is a value greater than zero, such as 0.2. The upper limit may also be a value slightly smaller than 1.

[0134] Subtractor 108 finds the difference between the input and output of first limiter 107 and outputs the value that exceeds first limiter 107. Subtractor 109 subtracts the output of subtractor 108 from the output of switch SW3. Second limiter 110 limits the output of subtractor 109. The upper and lower limits of second limiter 110 are set in the same way as for first limiter 107.

[0135] The fourth switch SW4 receives the outputs of both the first limiter 107 and the second limiter 110, and if Wp1j>Ws1j, it outputs the output of the second limiter 110, otherwise it outputs the output of the first limiter 107. The value output by the fourth switch SW4 does not depend on the magnitude relationship between the unit pulse width command values ​​Wp1j and Ws1j, but is a value obtained by adding or subtracting the output of the amplifier 105 to or from the unit pulse width command value Wp1j.

[0136] The fifth switch SW5 inputs the outputs of both the first limiter 107 and the second limiter 110, and outputs the output of the first limiter 107 if Wp1j > Ws1j, and the output of the second limiter 110 otherwise. The value output by the fifth switch SW5 does not depend on the magnitude relationship between the unit pulse width command values Wp1j and Ws1j, but is the value obtained by adding and subtracting the output of the amplifier 105 to the unit pulse width command value Ws1j.

[0137] When Wp1j > Ws1j, the second and third switches SW2 and SW3 switch downwards, and the fourth and fifth switches SW4 and SW5 switch upwards. From the fourth switch SW4, a signal based on the unit pulse width command value Wp1j is output, and from the fifth switch SW5, a signal based on the unit pulse width command value Ws1j is output.

[0138] When Wp1j < Ws1j, the second and third switches SW2 and SW3 switch upwards, and the fourth and fifth switches SW4 and SW5 switch downwards. Even under this condition, from the fourth switch SW4, a signal based on the unit pulse width command value Wp1j is output, and from the fifth switch SW5, a signal based on the unit pulse width command value Ws1j is output.

[0139] The subtractor 111 calculates the difference between the input and output of the second limiter 110, and outputs the value exceeding the second limiter 110. The output of this subtractor 111 becomes the DC component command value of the alternating current. [[ID=十四]]

[0140] ip1jk is the primary side alternating current detection value of the first j unit, first jk cell. is1jk is the secondary side alternating current detection value of the first j unit, first jk cell. The multiplier 112 multiplies the secondary side alternating current detection value is1jk by the turns ratio n.

[0141] The low-pass filter LPF3 extracts the DC component from the primary side alternating current detection value ip1jk. The low-pass filter LPF4 extracts the DC component from the output n×is1jk of the multiplier 112.

[0142] A subtractor 113 subtracts the output of the low-pass filter LPF3 from the DC component command value to obtain a deviation. A subtractor 114 subtracts the output of the low-pass filter LPF4 from a value obtained by inverting the sign of the DC component command value to obtain a deviation. PI amplifiers 115 and 116 amplify the respective deviations.

[0143] Adder 117 adds the value obtained by amplifying the DC component of primary side AC current detection value ip1jk by PI amplifier 115 to the output of fourth switch SW4, and outputs the result as cell pulse width command value Wp1jkp. Subtractor 118 subtracts the value obtained by amplifying the DC component of primary side AC current detection value ip1jk by PI amplifier 115 from the output of fourth switch SW4, and outputs the result as cell pulse width command value Wp1jkm.

[0144] An adder 119 adds the value obtained by amplifying the DC component of the secondary-side AC current detection value is1jk by the PI amplifier 116 to the output of the fifth switch SW5, and outputs the result as a cell pulse width command value Ws1jkp. A subtractor 120 subtracts the value obtained by amplifying the DC component of the secondary-side AC current detection value is1jk by the PI amplifier 116 from the output of the fifth switch SW5, and outputs the result as a cell pulse width command value Ws1jkm.

[0145] In this embodiment 4, a configuration in which a total of z cells, 111th cell to 11zth cell of the 11th unit, are connected in series on the primary side and in parallel on the secondary side is regarded as the 11th unit, and control is performed by regarding the primary and secondary sides of this unit as y cells connected in series.

[0146] The voltage balance control of each cell in the unit is shown in FIG. 8, and the operation is the same as in the third embodiment.

[0147] In Figure 8, the representative cell 111 of the 11th unit inputs Vdcp11 / z, which is the primary DC voltage Vdcp11 of the 11th unit divided by the number of cells z of the unit, Vdcp11 / z, the secondary DC voltage Vdcs11 of the 11th unit, the power command value P* plus the unit power command value P11 of the 11th unit, and the turn ratio 1 / n, and calculates the appropriate unit pulse width command values ​​Wp11, Ws11 and phase difference θ FF1 Ask for.

[0148] Then, based on the unit pulse width command values ​​Wp11 and Ws11, a cell pulse width command value calculation unit 86 calculates cell pulse width command values ​​Wp111p, Wp111m, Ws111p, and Ws111m through the transformer bias magnetization suppression control and discharge control due to a decrease in power factor when there is no load, as shown in FIG. 10.

[0149] The subtractor 82 calculates the phase difference θ FF1 The phase command value θ fed back from the current control unit 61 FB1 is subtracted and the phase difference command value θ1 is output.

[0150] The gate signal generator 83 generates gate signals for the representative cell based on the cell pulse width command values ​​Wp111p, Wp111m, Ws111p, and Ws111m and the phase difference command value θ1. The gate signal generator 83 also generates gate signals for the representative cell based on the cell pulse width command values ​​Wp111p, Wp111m, Ws111p, and Ws111m and the phase difference θ1 for the other cells in the 11th unit. FF1 Distribute the following.

[0151] The 11k-th cell performs feedback control by the capacitor voltage balance control unit 64 in FIG. 6 so that the primary side DC voltage Vdcp11k is uniform within the 11th unit, and the phase command value θ FB(k) The phase difference θ given by the 111th cell is subtracted by the subtractor 84. FF1 to the phase command value θ FB(k) is subtracted, and the phase difference command value θ (k) Generate.

[0152] The gate signal generator 83 generates a phase difference command value θ (k) Gates are generated based on the distributed cell pulse width command values ​​Wp111p, Wp111m, Ws111p, and Ws111m.

[0153] The voltage balance control of each unit is shown in Figs. 9 and 10.

[0154] The unit power command value calculation unit outputs a unit power command value that controls the power command value between the primary and secondary sides of each second-stage component (unit) so that the DC voltage on the upstream side of power transmission in each second-stage component (unit) is equal within the third-stage component (device).

[0155] In Figure 9, when power flows from the primary side to the secondary side, the deviation between the primary side DC voltage Vdcp1j of the 1j unit and the average primary side DC voltage Vdcp1avg of all units is input to an amplifier 99 and output to the adder 85 in Figure 8 as a unit power command value P1j.

[0156] For example, if the primary DC voltage Vdcp11 of the 11th unit is greater than the primary DC voltage average value Vdcp1avg, then P*+P 11 is larger than the other units, and each cell of the 11th unit transfers larger power from the primary side to the secondary side, thereby lowering the primary side DC voltage Vdcp11 of the 11th unit.

[0157] The downstream side is balanced spontaneously without voltage balance control.

[0158] In addition, the unit power command value calculation unit controls the unit power command value of a specific second-stage component (unit) so that the DC voltage upstream of the power transmission of the specific second-stage component (unit) becomes smaller when the energy stored in the primary-side DC capacitor and secondary-side DC capacitor of the second-stage component (unit) is larger than that of other second-stage components (units) in the third-stage component (device).

[0159] The unit power command value calculation unit controls the unit power command value of a specific second-stage component (unit) so that the DC voltage upstream of the power transmission of the specific second-stage component (unit) becomes larger when the energy stored in the primary-side DC capacitor and secondary-side DC capacitor of the second-stage component (unit) is smaller than that of other second-stage components (units) in the third-stage component (device).

[0160] That is, for units with large stored energy, the unbalance command value Vdc1j increases, and the unit power command value P1j output from the amplifier 99 also increases, providing the function of significantly reducing the primary side DC voltage. This reduces the power received from the DC side, suppresses charging of the unit's stored energy, and reduces the difference in stored energy with other units.

[0161] In Figure 10, the positive and negative pulse widths of the AC voltage are changed according to the DC components of the primary AC current detection value ip1jk and secondary AC current detection value is1jk of the 1j unit 1jk cell, preventing magnetic saturation of the transformer.

[0162] The accumulated energy E1j of the 1j unit is compared with the minimum value E1min of the accumulated energies of the 11th to 1y units, and the obtained deviation is amplified. Depending on the result, the pulse width of the narrower pulse with a larger DC voltage is widened, and the pulse width of the wider pulse with a smaller DC voltage is narrowed.

[0163] If the energy stored in the primary side DC capacitor and secondary side DC capacitor of a specific component (unit) in the second stage or later is other than the smallest among the components (units), the operating power factor of the component (unit) is reduced.

[0164] In the "phase difference and pulse width calculation unit 81" in Figure 8, the AC side current is minimized by setting the power factor of the AC side with the larger DC voltage to 1. However, manipulating the pulse width reduces the power factor, and unnecessary current begins to flow on the AC side. This allows for intentionally increasing copper loss and conduction loss in cells with large stored energy to encourage discharge and equalize the unit DC voltage.

[0165] In addition, if the energy stored in the primary side DC capacitor and secondary side DC capacitor of a specific second-stage component (unit) is not the smallest among the other second-stage components (units), the DC component of the AC side current output by all first-stage components (cells) that make up the specific second-stage component (unit) is increased.

[0166] A DC component is intentionally superimposed on the primary side AC current detection value ip1jk and the secondary side AC current detection value is1jk according to the excess manipulated variable from the second limiter 110. This also increases copper loss and conduction loss, making the unit DC voltages uniform.

[0167] By reversing the sign of the superimposed DC component in the primary side AC current detection value ip1jk and the secondary side AC current detection value is1jk, it is possible to prevent DC from being superimposed on the excitation current and prevent magnetic saturation of the transformer.

[0168] In the fourth embodiment, the 111th cell, which is the representative cell of the 11th unit, needs to externally input the average value Vdcp11 / z of the primary side DC voltage, the power command value P*, and the unit power command value P11.

[0169] In addition, the 11th unit's 112th to 11zth cells have the cell pulse width command values ​​Wp111p, Wp111m, Ws111p, and Ws111m and the phase difference θ FF1 However, cells 112 to 11z of the 11th unit can operate without inputting any external signals, simply by communicating with the representative cell, cell 111 of the 11th unit.

[0170] Furthermore, cells 112 to 11z of the 11th unit calculate their own stored energy and transmit it to cell 111 of the 11th unit, and cell 111 of the 11th unit calculates the sum and transmits it to the unit control unit (the unit power command value calculation unit in FIG. 9 or the unit pulse width command value calculation unit in FIG. 10), so that the unit control unit can operate without knowing the state of each cell. If the stored energy is calculated approximately, cells 112 to 11z of the 11th unit do not need to transmit the stored energy. In this way, by applying this embodiment 4, the circuit shown in FIG. 7 can be operated with a small communication load.

[0171] As described above, according to the fourth embodiment, it is possible to operate a circuit in which a unit in which one side of a DAB converter cell is connected in series and the other side is connected in parallel is connected in series on both sides. Also, it is possible to interchange power between high-voltage DC power systems and to step up and down the voltage using low-voltage components, and further it is possible to insulate the primary and secondary sides.

[0172] Furthermore, the voltage balance between the series-connected cells and between the series-connected units can be kept equal, and the withstand voltage required for components can be reduced.

[0173] Furthermore, unlike Patent Document 2, an auxiliary converter is not required, which allows for cost reduction and miniaturization.

[0174] Moreover, the fourth embodiment can reduce the communication load.

[0175] [Embodiment 5] In this fifth embodiment, the primary and secondary sides of the device of the fourth embodiment are connected in series as shown in Fig. 11. The control of each cell unit is the same as in the fourth embodiment. This fifth embodiment is applied to the circuit of Fig. 11.

[0176] In this fifth embodiment, the first-stage components are cells, and an assembly of a predetermined number (z units) of first-stage cells is a unit, which is a second-stage component. An assembly of a predetermined number (y units) of second-stage units connected in series is a device, which is a third-stage component. From the fourth stage onwards, higher-level devices are further assembled, each consisting of a predetermined number (x (x = an integer equal to or greater than 2)) of third-stage devices connected in series.

[0177] In other words, the isolated bidirectional DC / DC converter of the fifth embodiment includes a first DC power supply DCP, a second DC power supply DCS, and first to x-th devices connected between the first DC power supply DCP and the second DC power supply DCS. The first to x-th devices include an 11th to 1yth unit. The 11th to 1yth units have a 111th to 11zth cell, respectively.

[0178] Furthermore, a single digit alphanumeric character at the end of each reference numeral in this embodiment 5 indicates the number of the device. For example, Vdcp1 indicates the primary side DC voltage of the first device.

[0179] The control device of the fifth embodiment has the control blocks of FIGS. 8, 9, and 10, and further calculates the device voltage deviation Vdi (Vd1) of FIG. 9 and the device energy deviation Edi (Ed1) of FIG. 10 using FIGS. 12 and 13.

[0180] Fig. 12 is a block diagram of the i-th (i=an integer from 1 to x) device voltage deviation (Vdi) calculation unit in embodiment 5. Fig. 12 differs from Fig. 9 in the following respects.

[0181] [Table 1]

[0182] The output device voltage deviation Vdi is input to the adder 98 in FIG.

[0183] That is, in the fifth embodiment, the power command value between the primary side and secondary side of each unit is controlled so that the DC voltages on the upstream side of the power transmission of each unit in each device are equalized within the device in Fig. 9. Also, in Fig. 12, the power command value between the primary side and secondary side of each device is controlled so that the DC voltages on the upstream side of the power transmission of each device are equalized.

[0184] Also, in FIG. 12, when the energy stored in the primary side DC capacitor and secondary side DC capacitor of a specific third-stage component (device) is larger than that of other third-stage components (devices) in the fourth-stage component (higher-level device), the unit power command value of the specific third-stage component (device) is controlled so that the DC voltage upstream of the power transmission of the specific third-stage component (device) becomes smaller.

[0185] In addition, when the energy stored in the primary side DC capacitor and secondary side DC capacitor of a specific third-stage component (device) is smaller than that of other third-stage components (devices) in the fourth-stage component (higher-level device), the unit power command value of the specific third-stage component (device) is controlled so that the DC voltage upstream of the power transmission of the specific third-stage component (device) becomes larger.

[0186] Figure 13 is a block diagram of the i-th device energy deviation (Edi) calculation unit. Figure 13 is composed of the following:

[0187] Ei is the total accumulated energy detection value of all y units belonging to the i-th device. Emin is the minimum value of the accumulated energy of the first to x-th devices. Subtractor 131 calculates the deviation between energy Ei and minimum energy value Emin.

[0188] The adder 132 adds 0 to the output of the subtractor 131. The adder 132 can be omitted. The divider 133 divides the output of the adder 132 by the number y of apparatus constituent units. The output of the divider 133 is the i-th apparatus energy deviation Edi.

[0189] In the fifth embodiment, control is performed assuming that x more devices of the fourth embodiment are connected in series.

[0190] Voltage balance control of equipment is shown in Figures 12 and 13. In Figure 12, the primary side DC voltage Vdcpi and secondary side DC voltage Vdcsi of the i-th equipment to be controlled are compared with the primary side DC voltage average value Vdcpavg and secondary side DC voltage average value Vdcsavg of x number of equipment. Then, depending on the direction of the power command value P*, the appropriate deviation is output from either the primary side or the secondary side and distributed to each unit as the equipment voltage deviation Vdi.

[0191] In the first unit, the unit voltage deviation Vdi is input as Vd1 in Figure 9, added to the output of switch SW1, and then amplified by amplifier 99. The control block in Figure 9 evens out the unit voltage balance on the side aligned with the direction of the power command value P*, and for units with small stored energy, the unit DC voltage on the side receiving power increases. Since the unit voltage deviation Vdi is input to y units of the i-th unit, it is multiplied by 1 / y in advance to prevent the manipulated variable from becoming excessive.

[0192] Figure 13 shows a control block that balances the DC voltage of the device by performing a discharge operation targeted at light load and no load conditions. In devices with large stored energy, the device energy deviation Edi becomes large, which is output as energy deviation Ed1 in Figure 10 and is amplified by amplifier 105 in Figure 10, causing an increase in loss in the y x z cells that make up the device.

[0193] A circuit with the same configuration can be operated by increasing the number of series units in embodiment 4 without applying embodiment 5. However, in embodiment 4, information on the DC voltage and stored energy of other units is required to control a unit, and increasing the number of series units increases the communication load and the wiring between units.

[0194] On the other hand, in the fifth embodiment, a unit can operate only with information from other units in the same device, and does not need information from other devices. The unit needs to transmit the total accumulated energy to the control block of the device (Figs. 12 and 13).

[0195] The control block of the device requires information on the device's stored energy, average value, and DC voltage, but can operate without knowing the state of each unit. By applying this embodiment 5, it is possible to reduce the communication load and wiring compared to the case in which the number of series units is increased in embodiment 4.

[0196] In this fifth embodiment, the 0 (adders 98, 132) added in Figures 12 and 13 is replaced with a higher voltage deviation, and by further connecting the configurations of the fifth embodiment in series, the number of series units can be increased and higher voltages can be handled.

[0197] As described above, according to the fifth embodiment, the communication load can be reduced compared to the fourth embodiment even when the number of units connected in series is increased.

[0198] Although the present invention has been described in detail above only with respect to the specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and variations fall within the scope of the claims.

[0199] Although the fourth and fifth embodiments have been described as examples applied to the third embodiment, they may also be applied to the first and second embodiments.

[0200] When applied to the first embodiment, as shown in FIG. 14, the cell pulse width command value calculation unit 86 calculates the voltage of the primary side capacitor of each of the DAB converters (each cell), the voltage of the secondary side capacitor, the turn ratio of the primary winding and the secondary winding of the insulating transformer, the power command value P*, and the unit power command value P 11 The unit pulse width command value W of the primary side single-phase inverter and the secondary side single-phase inverter of the unit's DAB converter, determined by the sum of 1(1) ,W 1(2) The cell pulse width command value 86 is input as the unit pulse width command value W 1(1) ,W 1(2) The cell pulse width command values ​​for the primary-side single-phase inverter and secondary-side single-phase inverter of the cell are calculated based on the calculated values. The cell pulse width command values ​​obtained by the calculation are input to the gate generators 30 of all cells in the corresponding unit, and the inverters of each cell are driven based on the converted gate signals.

[0201] Moreover, the communication load can be reduced by providing the cell pulse width command value calculation unit 86 only for the representative cell. In this case, the unit pulse width command value W 1(n) ,W 2(n) is input directly to the gate signal generator. However, this means that only the representative cell is discharged, which can cause problems such as it taking time for the voltage balance deviation to converge to zero and the heat load being concentrated on the representative cell. This problem can be solved by standardizing the design and components used for each unit of the device to prevent imbalance in losses.

[0202] In the gate signal generating unit 30, the representative cell is controlled by a cell pulse width command value and a phase command value θ FB(1) and the unit power command value P in Fig. 9 11 The gate signals of the primary side single-phase inverter and the secondary side single-phase inverter are generated based on the sum of the phase command value θ FB(n) The gate signal of the kth cell is generated according to the cell pulse width command value or unit pulse width command value, or the phase command value θ FB(n) The unit power command value P 11 The gate signal of the k-th cell may be generated using the value obtained by adding the above (output of the adder 87).

[0203] When applied to the second embodiment, the adders (in the 111th to 11zth cells) add the unit power command value P11 to the power command value P*.

[0204] The phase difference and pulse width command values ​​are calculated by calculating the unit pulse width command values ​​and phase difference of the unit's primary single-phase inverter and secondary single-phase inverter using the primary capacitor voltage, secondary capacitor voltage, turn ratio of the isolation transformer's primary and secondary windings of each cell, and the output of the adder.

[0205] The cell pulse width command value calculation unit calculates cell pulse width command values ​​for the primary side single-phase inverter and the secondary side single-phase inverter of the cell from the unit pulse width command value (in the 111th cell to the 11zth cell).

[0206] The gate signal generating unit generates gate signals for the primary side single-phase inverter and the secondary side single-phase inverter of each cell (in cells 111 to 11z) based on the cell pulse width command value and the phase difference command value obtained by subtracting the phase command value determined by feedback control from the phase difference calculated by the phase difference / pulse width calculating unit.

[0207] The gate signal generation unit generates a gate signal for the representative cell using a phase difference command value, which is the difference between the phase command value fed back from the current control unit and the phase difference calculated by the phase difference / pulse width calculation unit, and a cell pulse width command value, and generates a gate signal for the kth cell using a phase difference command value, which is the difference between the phase command value fed back from the capacitor voltage balance control unit and the phase difference calculated by the phase difference / pulse width calculation unit, and a cell pulse width command value. [Explanation of symbols]

[0208] 1...Primary side single-phase inverter 2...Secondary side single-phase inverter 3...Isolation transformer 30, 43, 53, 83...Gate signal generator 61, 65...Current control section 64...Capacitor voltage balance control section 41, 51, 81... Phase difference and pulse width calculation section 42, 52, 54, 82, 84...Subtractor 85...adder 86...Cell pulse width command value calculation unit

Claims

1. a plurality of DAB (Dual Active Bridge) converters are provided, each including a primary-side single-phase inverter having an AC side connected to a primary winding of an isolation transformer, a secondary-side single-phase inverter having an AC side connected to a secondary winding of the isolation transformer, a primary-side capacitor connected between positive and negative terminals of the DC side of the primary-side single-phase inverter, and a secondary-side capacitor connected between positive and negative terminals of the DC side of the secondary-side single-phase inverter; The plurality of DAB converters are layered into first to m (m = an integer of 2 or more) stages, the components of the first stage are cells, a predetermined number of first stage elements are aggregates of units that are components of the second stage, a predetermined number of second stage elements are aggregates of devices that are components of the third stage, and the fourth stage and onwards are aggregates of predetermined numbers of the devices that are components of the previous stage, which are higher-level devices, A control device for a bidirectional isolated DC / DC converter in which the unit is configured by connecting the positive and negative terminals of the primary-side single-phase inverters of z (z = an integer of 2 or more) cells in series and connecting the positive and negative terminals of the secondary-side single-phase inverters in parallel, and the primary and secondary sides of components from the second stage onwards are connected in series within an assembly, The control device a current control unit that outputs a first phase command value that causes the primary-side DC current or the secondary-side DC current to follow a set current command value; a capacitor voltage balance control unit that outputs a k-th phase command value that reduces the deviation between the primary capacitor voltage of the k-th cell (k=an integer from 2 to z) and an average voltage value obtained by dividing the primary capacitor voltage of a representative cell in the unit or the primary DC voltage of the unit by the number of cells in the unit; a unit power command value calculation unit that outputs a unit power command value that increases or decreases the power transmitted between the primary side and the secondary side of each component so that the DC voltages on the upstream side of the power transmission in each component are equal within the assembly, in the second stage and thereafter; an adder that adds a power command value, which is a command value for power transmitted between the primary side and the secondary side, to the unit power command value; a phase difference / pulse width calculation unit that calculates a unit pulse width command value and a phase difference of the primary-side single-phase inverter and the secondary-side single-phase inverter of a unit based on the primary-side capacitor voltage, the secondary-side capacitor voltage of each cell, the turns ratio between the primary winding and the secondary winding of the isolation transformer, and the output of the adder; a cell pulse width command value calculation unit that calculates cell pulse width command values ​​for the primary-side single-phase inverter and the secondary-side single-phase inverter of the cell from the unit pulse width command value; a gate signal generating unit that generates gate signals for the primary-side single-phase inverter and the secondary-side single-phase inverter of each cell based on the cell pulse width command value and a phase difference command value obtained by subtracting the first phase command value or the kth phase command value from the phase difference calculated by the phase difference / pulse width calculating unit, the gate signal generating unit generates a gate signal of a representative cell based on a phase difference command value which is a difference between the first phase command value and the phase difference calculated by the phase difference / pulse width calculating unit, and the cell pulse width command value, and generates a gate signal of the kth cell based on a phase difference command value which is a difference between the kth phase command value and the phase difference calculated by the phase difference / pulse width calculating unit, and the cell pulse width command value.

2. a plurality of DAB (Dual Active Bridge) converters are provided, each including a primary-side single-phase inverter having an AC side connected to a primary winding of an isolation transformer, a secondary-side single-phase inverter having an AC side connected to a secondary winding of the isolation transformer, a primary-side capacitor connected between positive and negative terminals of the DC side of the primary-side single-phase inverter, and a secondary-side capacitor connected between positive and negative terminals of the DC side of the secondary-side single-phase inverter; The plurality of DAB converters are layered into first to m (m = an integer of 2 or more) stages, the components of the first stage are cells, a predetermined number of first stage elements are aggregates of units that are components of the second stage, a predetermined number of second stage elements are aggregates of devices that are components of the third stage, and the fourth stage and onwards are aggregates of predetermined numbers of the devices that are components of the previous stage, which are higher-level devices, A control device for a bidirectional isolated DC / DC converter in which a unit is formed by connecting the positive and negative terminals of each of the primary-side single-phase inverters of z (z = an integer of 2 or more) cells in series and connecting the positive and negative terminals of each of the secondary-side single-phase inverters in parallel, and the primary and secondary sides of components from the second stage onwards are connected in series within an assembly, The control device a current control unit that outputs a first phase command value that causes the primary-side DC current or the secondary-side DC current to follow a set current command value; a capacitor voltage balance control unit that outputs a k-th phase command value that reduces the deviation between the primary capacitor voltage of the k-th cell (k=an integer from 2 to z) and an average voltage value obtained by dividing the primary capacitor voltage of a representative cell in the unit or the primary DC voltage of the unit by the number of cells in the unit; a unit power command value calculation unit that outputs a unit power command value that increases or decreases the power transmitted between the primary side and the secondary side of each component so that the DC voltages on the upstream side of the power transmission in each component are equal within the assembly, in the second stage and thereafter; an adder that adds a power command value, which is a command value for power transmitted between the primary side and the secondary side, to the unit power command value; a phase difference / pulse width calculation unit that calculates a unit pulse width command value and a phase difference of the primary single-phase inverter and the secondary single-phase inverter of the unit based on an average voltage value obtained by dividing the primary DC voltage of the unit by the number of cells in the unit, the secondary DC voltage of the unit, the turns ratio between the primary winding and the secondary winding of the isolation transformer, and the output of the adder; a cell pulse width command value calculation unit that calculates cell pulse width command values ​​for the primary-side single-phase inverter and the secondary-side single-phase inverter of the cell from the unit pulse width command value; a gate signal generating unit that generates gate signals for the primary-side single-phase inverter and the secondary-side single-phase inverter of each cell based on the cell pulse width command value and a phase difference command value obtained by subtracting the first phase command value or the kth phase command value from the phase difference calculated by the phase difference / pulse width calculating unit, the gate signal generating unit generates a gate signal of a representative cell based on a phase difference command value which is a difference between the first phase command value and the phase difference calculated by the phase difference / pulse width calculating unit, and the cell pulse width command value, and generates a gate signal of the kth cell based on a phase difference command value which is a difference between the kth phase command value and the phase difference calculated by the phase difference / pulse width calculating unit, and the cell pulse width command value.

3. The unit power command value calculation unit When the energy stored in the primary-side DC capacitor and the secondary-side DC capacitor of a specific component in the second or subsequent stage is larger than that of other components in the assembly, the unit power command value of the specific component is controlled so that the DC voltage on the upstream side of the power transmission of the specific component is reduced; 3. The control device for a bidirectional isolated DC / DC converter according to claim 1, wherein, when the energy stored in the primary-side DC capacitor and the secondary-side DC capacitor of a specific component in a second or subsequent stage is smaller than that of other components in the assembly, the unit power command value of the specific component is controlled so that the DC voltage on the upstream side of power transmission of the specific component is increased.

4. The control device 4. The control device for a bidirectional isolated DC / DC converter according to claim 1, wherein when the energy stored in the primary-side DC capacitor and the secondary-side DC capacitor of a specific component in the second stage or later is other than the smallest among all the components, the operating power factor of the component is reduced.

5. The control device 5. The control device for a bidirectional isolated DC / DC converter according to any one of claims 1 to 4, characterized in that, when the energy stored in the primary-side DC capacitor and the secondary-side DC capacitor of a specific component in the second stage or later is other than the smallest among all the components, the DC component of the current output by that component is increased.

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