circuit board

Abstract

A circuit board according to an embodiment includes an insulating layer including a first via hole and a first via arranged in the first via hole of the insulating layer, the first via including a first via part arranged in a first region of the first via hole and a second via part arranged in a second region of the first via hole other than the first region, the second region being a central region of the first via hole and the first region being an outer region surrounding the second region, the first via part and the second via part including a first surface in contact with other via parts and a second surface other than the first surface exposed on the insulating layer, the first surface having a first surface roughness and the second surface having a second surface roughness different from the first surface roughness.

Description

[Technical Field]

[0001] The embodiment relates to a circuit board. [Background technology]

[0002] As electronic components become increasingly smaller, lighter, and more integrated, circuit line widths are becoming finer. In particular, as semiconductor chip design rules become more integrated on a nanometer scale, the circuit line widths of package substrates or circuit boards on which semiconductor chips are mounted are becoming finer, down to a few micrometers or less.

[0003] Various processes have been proposed to increase the circuit integration density of circuit boards, i.e., to reduce the circuit line width. SAP (semi-additive process) and MSAP (modified semi-additive process) have been proposed to prevent loss of circuit line width during the etching step to form patterns after copper plating.

[0004] Since then, the Embedded Trace Substrate (ETS) method, which embeds copper foil in an insulating layer, has been used in the industry to achieve finer circuit patterns. The ETS method embeds copper foil circuits in the insulating layer instead of forming them on the surface of the insulating layer, eliminating circuit loss due to etching and making it advantageous for finer circuit pitches.

[0005] Meanwhile, to meet the recent demand for wireless data traffic, improved 5G (5G) th Efforts are underway to develop pre-5G (pre-5G) or ultra-high frequency (mmWave) bands (sub-6 GHz, 28 GHz, 38 GHz, or higher frequencies) to achieve high data transmission rates.

[0006] In order to mitigate path loss and increase the transmission distance of radio waves in the ultra-high frequency band, aggregation technologies such as beamforming, massive MIMO, and array antennas are being developed for 5G communication systems. Considering that these frequency bands are made up of hundreds of active antennas with wavelengths, the antenna system becomes relatively large.

[0007] Because these antennas and AP modules are patterned or mounted on a circuit board, low loss in the circuit board is very important, which means that the multiple boards that make up the active antenna system, i.e., antenna board, antenna feed board, transceiver board, and baseband board, must be integrated into one compact unit.

[0008] Recently, circuit boards including large-area vias have been developed to improve heat dissipation and shielding properties. Large-area vias can be formed by filling a large-diameter via hole with a metal material. However, it is not easy to fill the interior of a large-diameter via hole with a metal material. As a result, conventional large-area vias have a dimple area on one side that is recessed toward the interior of the via hole. Furthermore, the dimple area can affect via hole processing when additional lamination is performed, thereby affecting the reliability of the circuit board. Summary of the Invention [Problem to be solved by the invention]

[0009] In the embodiment, a circuit board including a via of a new structure and a manufacturing method thereof are provided.

[0010] In addition, in the embodiment, a circuit board including a via formed of a plurality of via parts arranged in a multi-layer structure inside a via hole, and a manufacturing method thereof are provided.

[0011] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0012] A circuit board according to an embodiment includes an insulating layer including a first via hole and a first via arranged in the first via hole of the insulating layer, the first via including a first via part arranged in a first region of the first via hole and a second via part arranged in a second region of the first via hole other than the first region, the second region being a central region of the first via hole and the first region being an outer region surrounding the second region, the first via part and the second via part including a first surface in contact with other via parts and a second surface other than the first surface exposed on the insulating layer, the first surface having a first surface roughness and the second surface having a second surface roughness different from the first surface roughness.

[0013] Furthermore, the first surface roughness is smaller than the second surface roughness.

[0014] Furthermore, each of the first via part and the second via part includes a first portion disposed in the first via hole and a second portion on the first portion that protrudes above the upper surface of the insulating layer, the first surface includes the interface between the first portion of the first via part and the first portion of the second via part, and the second surface includes the upper surface of the second portion of the first via part and the upper surface of the second portion of the second via part.

[0015] The height of the first surface decreases from the edge to the center.

[0016] The distance from the upper surface of the second portion of the first via part to the lowest point of the upper surface of the first portion of the first via part corresponds to 30% to 70% of the thickness of the first via.

[0017] The distance from the upper surface of the second portion of the second via part to the lowest point of the lower surface of the first portion of the second via part corresponds to 30% to 70% of the thickness of the first via.

[0018] Additionally, the upper surface of the first bead part is located on the same plane as the upper surface of the second bead part.

[0019] It also includes a first pad disposed on the lower surface of the insulating layer and exposed through the first via hole, a first portion of the first via part disposed on the first pad exposed through the first via hole, and a first portion of the second via part disposed on the first portion of the first via part.

[0020] The insulating layer includes a first insulating layer and a second insulating layer on the first insulating layer, and the first via hole is formed to penetrate both the first insulating layer and the second insulating layer.

[0021] The insulating layer may further include a second via disposed in a second via hole formed through the first insulating layer or the second insulating layer, the size of the second via being smaller than the size of the first via, and the second via having a single part disposed in the second via hole.

[0022] The second via part also includes a first sub-second via part that contacts the first via part and fills a portion of the second region of the first via hole, and a second sub-second via part that contacts the first sub-second via part and fills the remaining portion of the second region of the first via hole.

[0023] Meanwhile, a circuit board according to an embodiment includes a plurality of insulating layers, a first via disposed in a first via hole formed to commonly penetrate the plurality of insulating layers, a second via disposed in a second via hole formed to penetrate any one of the plurality of insulating layers, a first pad disposed on a lower surface of a lowest layer of the plurality of insulating layers and connected to the first via, and a second pad disposed on a lower surface of the lowest layer and connected to the second via, wherein the first via is disposed in the first via hole and includes a first via part and a second via part separated from each other by an interface, the second via is disposed in the second via hole to have a single part, and the size of the first via is larger than the size of the second via.

[0024] The first and second bead parts each include a first surface that contacts another bead part and a second surface other than the first surface that is exposed on the top surface of the uppermost layer of the plurality of insulating layers, and the first surface has a first surface roughness, and the second surface has a second surface roughness that is greater than the first surface roughness.

[0025] Furthermore, each of the first via part and the second via part includes a first portion disposed in the first via hole and a second portion on the first portion that protrudes above the upper surface of the insulating layer, the first surface includes the interface between the first portion of the first via part and the first portion of the second via part, the second surface includes the upper surface of the second portion of the first via part and the upper surface of the second portion of the second via part, and the height of the first surface decreases from the edge to the center.

[0026] Furthermore, the distance from the upper surface of the second portion of the first via part to the lowest point of the upper surface of the first portion of the first via part corresponds to 30% to 70% of the thickness of the first via, and the distance from the upper surface of the second portion of the second via part to the lowest point of the lower surface of the first portion of the second via part corresponds to 30% to 70% of the thickness of the first via.

[0027] Meanwhile, a method for manufacturing a circuit board according to an embodiment includes the steps of: preparing an insulating layer; forming a first pad on a lower surface of the insulating layer; forming a first via hole in the insulating layer to expose an upper surface of the first pad; disposing a first mask on an upper surface of the insulating layer, the first mask having a first opening exposing the first via hole and a portion of the upper surface of the insulating layer extending from the first via hole; performing a primary plating process on the upper surface of the first insulating layer exposed through the first opening of the first mask and into the first via hole; forming a first via part to fill a portion of the first via hole; primarily grinding the upper surface of the first via part; forming a second mask on the first mask, the second mask having a second opening that is narrower than the first opening while exposing a portion of the first opening; forming a second via part to fill the first via hole on the first via part exposed through the second opening of the second mask; removing the second mask; secondary grinding the upper surface of the second via part; removing the third mask; and tertiary grinding the upper surfaces of the first and second via parts to form a first via to fill the first via hole.

[0028] Furthermore, the first and second bead parts include a first surface in contact with other bead parts and a second surface other than the first surface that is exposed on the insulating layer, the first surface having a first surface roughness, and the second surface having a second surface roughness greater than the first surface roughness.

[0029] Furthermore, each of the first via part and the second via part constituting the first via includes a first portion disposed within the first via hole and a second portion on the first portion that protrudes above the upper surface of the insulating layer, the first surface includes the interface between the first portion of the first via part and the first portion of the second via part, the second surface includes the upper surface of the second portion of the first via part and the upper surface of the second portion of the second via part, and the height of the first surface decreases from the edge to the center.

[0030] Furthermore, the distance from the upper surface of the second portion of the first via part to the lowest point of the upper surface of the first portion of the first via part corresponds to 30% to 70% of the thickness of the first via, and the distance from the upper surface of the second portion of the second via part to the lowest point of the lower surface of the first portion of the second via part corresponds to 30% to 70% of the thickness of the first via.

[0031] Also, forming the second via part includes forming a first sub-second via part on the first via part to fill a portion of the first via hole, and forming a second sub-second via part on the first sub-second via part to fill the first via hole.

[0032] Further, preparing the insulating layer includes preparing the first insulating layer and a second insulating layer disposed on the first insulating layer, forming the first pad includes forming a second pad spaced apart from the first pad on the upper surface of the first insulating layer, forming the first via hole includes forming a second via hole exposing the second pad by penetrating the second insulating layer, disposing the first mask includes disposing a first mask having a third opening exposing the second via hole, forming the first via part includes forming a second via filling the second via hole exposed through the third opening, grinding the upper surface of the second via together with the upper surface of the first via part, the second mask is formed to cover the upper surface of the second via, and the tertiary grinding includes grinding the upper surface of the second via together with the upper surfaces of the first and second via parts.

[0033] According to the present embodiment, although limitations on plating large diameter via holes exist in the case of conventional large area vias, these limitations can be overcome by changing the plating method, thereby enabling stable plating of large diameter via holes. Furthermore, according to the present embodiment, it is possible to ensure uniformity of via plating compared to existing methods, and quality reliability can be ensured by improving the quality of the laser after additional lamination.

[0034] In addition, while there was a conventional limit to the ratio between the thickness of the insulating layer and the size of the via hole in order to stably achieve plating inside the via hole, according to the present embodiment, it is possible to eliminate the design constraints for achieving a highly reliable plating state inside the via hole, thereby increasing the degree of freedom in design. Furthermore, according to the present embodiment, by increasing the size of the via, it is possible to completely shield interference between circuits that occurs in areas where circuits are concentrated, and it is possible to improve heat dissipation characteristics in areas where heat dissipation is required.

[0035] Specifically, in the comparative example, the heat dissipation function is performed using multiple heat dissipation vias spaced at regular intervals horizontally, whereas in the embodiment, the heat dissipation function is performed using a single large-area via while ensuring uniformity of its plating, thereby improving the heat dissipation performance by increasing the via area compared to the comparative example. [Brief explanation of the drawings]

[0036] [Figure 1] FIG. 10 is a diagram showing the structure of a normal stack via in a first comparative example. [Figure 2] FIG. 10 is a diagram showing a rod-type via structure in a second comparative example. [Figure 3] FIG. 10 is a diagram showing a pyramidal via structure in a third comparative example. [Figure 4] FIG. 10 is a diagram showing a via formed according to a comparative example. [Figure 5] FIG. 2 is a diagram showing a circuit board according to the first embodiment. [Figure 6a] FIG. 6 is an enlarged view of a first via in FIG. 5. [Figure 6b] FIG. 6 is a diagram showing a plan view of the first via in FIG. 5. [Figure 7] FIG. 10 is a diagram showing the surface roughness of a first via according to an example. [Figure 8] FIG. 10 is a diagram showing the surface roughness of a first via according to an example. [Figure 9] 2A to 2C are diagrams showing a method for manufacturing a circuit board according to a first embodiment in the order of steps. [Figure 10] 2A to 2C are diagrams showing a method for manufacturing a circuit board according to a first embodiment in the order of steps. [Figure 11] 2A to 2C are diagrams showing a method for manufacturing a circuit board according to a first embodiment in the order of steps. [Figure 12] 2A to 2C are diagrams showing a method for manufacturing a circuit board according to a first embodiment in the order of steps. [Figure 13] 2A to 2C are diagrams showing a method for manufacturing a circuit board according to a first embodiment in the order of steps. [Figure 14] 2A to 2C are diagrams showing a method for manufacturing a circuit board according to a first embodiment in the order of steps. [Figure 15] 2A to 2C are diagrams showing a method for manufacturing a circuit board according to a first embodiment in the order of steps. [Figure 16] 2A to 2C are diagrams showing a method for manufacturing a circuit board according to a first embodiment in the order of steps. [Figure 17] 2A to 2C are diagrams showing a method for manufacturing a circuit board according to a first embodiment in the order of steps. [Figure 18] 2A to 2C are diagrams showing a method for manufacturing a circuit board according to a first embodiment in the order of steps. [Figure 19] FIG. 10 is a diagram showing a circuit board according to a second embodiment. [Figure 20a] 20 is a diagram for explaining the interfaces of the parts of the first via shown in FIG. 19. FIG. [Figure 20b] FIG. 20 is a plan view of the first via shown in FIG. [Figure 21] 10A to 10C are diagrams showing a method for manufacturing a circuit board according to a second embodiment in the order of steps. [Figure 22] 10A to 10C are diagrams showing a method for manufacturing a circuit board according to a second embodiment in the order of steps. [Figure 23] 10A to 10C are diagrams showing a method for manufacturing a circuit board according to a second embodiment in the order of steps. [Figure 24] 10A to 10C are diagrams showing a method for manufacturing a circuit board according to a second embodiment in the order of steps. MODE FOR CARRYING OUT THE INVENTION

[0037] Hereinafter, the embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Identical or similar components will be designated by the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "unit" used in the following description are assigned or used interchangeably for the sole purpose of facilitating the description, and do not have any distinct meanings or functions. Furthermore, in describing the embodiments disclosed herein, if a detailed description of related publicly known technology is deemed to obscure the gist of the embodiments disclosed herein, such detailed description will be omitted. Furthermore, the accompanying drawings are merely intended to facilitate understanding of the embodiments disclosed herein, and the accompanying drawings should not be construed as limiting the technical concept disclosed herein, and should be understood to include all modifications, equivalents, and alternatives within the concept and technical scope of the present invention.

[0038] Terms including ordinal numbers such as "second," "first," etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0039] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that the component may be directly coupled or connected to the other component, but that there may be other components in between. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no other components in between.

[0040] A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0041] In this application, the terms "comprise" or "have" and the like are intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof described in the specification, but are to be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0042] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0043] Prior to describing this embodiment, a comparative example to be compared with this embodiment will be described.

[0044] 1 to 3 are cross-sectional views illustrating via structures of circuit boards in comparative examples. Fig. 1 shows the structure of a normal stack via in a first comparative example, Fig. 2 shows the rod-type via structure in a second comparative example, and Fig. 3 shows the pyramid-type via structure in a third comparative example.

[0045] Referring to FIG. 1, the circuit board includes a plurality of insulating layers 1 connected to each other, inner layer pads 2 formed between different insulating layers, outer layer pads 3 formed on the surfaces of the top insulating layer and the bottom insulating layer, and a plurality of vias formed in each of the plurality of insulating layers 1.

[0046] The vias in the first comparative example include a first via 4, a second via 5, a third via 6, and a fourth via 7, which are spaced apart at regular intervals. The first to fourth vias 4, 5, 6, and 7 are commonly connected to the inner layer pad 2 and the outer layer pad 3, respectively.

[0047] Referring to Figure 2, the circuit board in the second comparative example includes a plurality of insulating layers 11 connected to each other, inner layer pads 12 formed between different insulating layers, outer layer pads 13 formed on the surfaces of the top insulating layer and the bottom insulating layer, and vias 14 formed respectively within the plurality of insulating layers 11.

[0048] The via 14 is formed to have a width wider than that of a general via. For example, the via 14 may have a width equivalent to the sum of the widths of the first to fourth vias 4, 5, 6, and 7 shown in FIG.

[0049] As shown in the bottom of FIG. 2, the via 14 has a shape corresponding to a cylindrical via hole having a wide width, which is formed by plating the inside of the via hole with a metal material.

[0050] Referring to Figure 3, the circuit board in the third comparative example includes a plurality of insulating layers 21 connected to each other, inner layer pads 22 formed between different insulating layers, outer layer pads 23 formed on the surfaces of the top insulating layer and the bottom insulating layer, and vias 24 formed respectively within the plurality of insulating layers 21.

[0051] The vias 24 formed in each insulating layer 21 have different widths. For example, a via formed in a central insulating layer has a first width, and as the vias move from the central insulating layer to the upper insulating layers, they have a second width wider than the first width. Thus, as the vias move from the central insulating layer to the lower insulating layers, they have a third width wider than the first width. In this case, the third width is wider than the second width.

[0052] However, as in the comparative example, rod-type or pyramid-type vias have a relatively large volume and a long shape compared to a general stack via, and therefore there is a very high possibility that dimples will occur during plating.

[0053] FIG. 4 shows a via formed by a comparative example.

[0054] Referring to FIG. 4, the via may have a concave shape D in which the height of the central region is lower than that of the edge region, and such a concave shape is called a dimple phenomenon.

[0055] Therefore, in the comparative example, the area of ​​the via is limited to minimize the above-mentioned dimple phenomenon. That is, in the comparative example, the size of the via is limited to an area at a level where the dimple phenomenon does not occur, which acts as a factor in reducing the heat dissipation characteristics of the via.

[0056] In particular, when the via hole size is processed to a diameter of 100 μm or more, via fill plating does not proceed smoothly, resulting in the formation of the above-mentioned concave dimple regions DP.

[0057] For example, in the comparative example, when the diameter of the via hole exceeds 100 μm, via fill plating does not proceed smoothly, and a dimple region D that is recessed downward is present above the via.

[0058] If the depth of the dimple region D is 10 μm or more, it will be judged as defective and unusable, or there will be a problem that via holes cannot be processed smoothly in that region when additional lamination is performed after the core layer of the circuit board is formed.

[0059] Recently, the size of via holes has been significantly increased to improve the performance of vias, which play a role in heat dissipation, shielding, and signal transmission, and the size of via holes and vias has also tended to increase accordingly. In the present embodiment, we aim to provide a circuit board with a new structure and a manufacturing method thereof, which enables uniform plating to be performed over the entire area of ​​a via hole, even in the case of a large via with an area of ​​10 μm or more, thereby eliminating the dimple area of ​​the via.

[0060] FIG. 5 is a diagram showing a circuit board according to a first embodiment, FIG. 6a is an enlarged view of a first via in FIG. 5, and FIG. 6b is a plan view of the first via in FIG.

[0061] Referring to Figures 5, 6a, and 6b, the circuit board may include the insulating layer 110, a first pad 140 and a second pad 120 arranged on the surface of the insulating layer 110, and a first via 170 and a second via 130 arranged through the insulating layer 110.

[0062] In the above, the first pad 140 may be in direct contact with the first via 170 and thus be part of a circuit pattern connected to the first via 170. Also, the second pad 120 may be in contact with the second via 130 and thus be part of a circuit pattern connected to the second via 130. In this case, the first via 170 may have a first cross-sectional area, and the second via 130 may have a second cross-sectional area smaller than the first cross-sectional area. For example, the first via 170 may be a heat dissipation via that performs a heat dissipation function, and the second via 130 may be a signal via that performs a signal transmission function, but is not limited thereto. Preferably, the first via 170 and the second via 130 have different cross-sectional areas, and therefore the first via 170 and the second via 130 may have different shapes. Here, different shapes do not mean the overall shape of the first via 170 and the overall shape of the second via 130, but may mean that the shapes of each via part constituting the first via 130 and the shapes of each via part constituting the second via 130 are different.

[0063] This will be explained in detail.

[0064] The circuit board includes an insulating layer 110. Preferably, the circuit board includes multiple insulating layers. For example, the circuit board can include, but is not limited to, a first insulating layer 111, a second insulating layer 112, a third insulating layer 113, and a fourth insulating layer 114. For example, the circuit board can have fewer than four layers, or alternatively, the circuit board can have more than four layers. However, the circuit board can include at least two insulating layers.

[0065] The insulating layer 110 may have a flat plate structure. The insulating layer 110 may be a printed circuit board (PCB). Here, the insulating layer 110 may be realized as a multi-layer board in which a plurality of insulating layers are continuously stacked, as described above.

[0066] A circuit pattern may be disposed on the surface of the insulating layer 110. For example, a circuit pattern may be disposed on each of the surfaces of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. In this case, the circuit pattern may include via pads connected to vias, connection pads connected to an external substrate, mounting pads on which electronic components are mounted, and traces serving as signal transmission lines between the pads. In this embodiment, FIG. 5 may show via pad portions connected to vias among the circuit patterns disposed on the surface of the insulating layer 110.

[0067] The insulating layer 110 is a substrate on which an electrical circuit with reversible wiring is organized, and can include any of a printed circuit board, a wiring board, and an insulating substrate made of an insulating material on which a circuit pattern can be formed on the surface of the insulating layer.

[0068] At least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may include a prepreg containing glass fiber. More specifically, at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may include an epoxy resin and a material in which glass fiber and a silicon filler are dispersed in the epoxy resin.

[0069] At least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may be rigid or flexible. For example, at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may include glass or plastic. More specifically, at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or may include reinforced or ductile plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or sapphire.

[0070] Also, at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may include an optical isotropic film. For example, at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optical isotropic polycarbonate (PC), optical isotropic polymethyl methacrylate (PMMA), or the like.

[0071] In addition, at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may be partially curved. For example, at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may be partially flat and partially curved. In particular, an end of at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may be curved or have a surface with a random curvature.

[0072] Also, at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may be a flexible substrate having flexibility.

[0073] Also, at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may be a curved or bent substrate.

[0074] The first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may each have a thickness of 20 μm to 500 μm. Preferably, at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may have a thickness of 40 μm to 400 μm. More preferably, at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may have a thickness of 60 μm to 250 μm. If the thickness of at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 is less than 20 μm, it may be difficult to form a circuit pattern on the surface of the insulating layer. If the thickness of at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 exceeds 500 μm, the overall thickness of the circuit board may increase.

[0075] A circuit pattern, for example, a first pad 140 and a second pad 120, may be disposed on the surface of each of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. The first pad 140 and the second pad 120 may be a part of the circuit pattern and may substantially refer to a portion of the entire area of ​​the circuit pattern disposed on the surface of each insulating layer that is connected to a via.

[0076] The first pad 140 and the second pad 120 may be patterns for transmitting electrical signals, or may be patterns for transmitting heat formed for the purpose of heat dissipation.

[0077] To this end, at least one of the first pad 140 and the second pad 120 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn).

[0078] At least one of the first pad 140 and the second pad 120 may be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which have excellent bonding strength. Preferably, at least one of the first pad 140 and the second pad 120 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0079] The first pad 140 and the second pad 120 can be formed using conventional circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and detailed description thereof will be omitted here.

[0080] The first pad 140 may be disposed on the surface of any one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. In other words, the first pad 140 may be connected to a large-area first via 170 that commonly penetrates the plurality of insulating layers. Thus, the first pad 140 may be disposed on the surface of a specific insulating layer that is disposed in the center of the plurality of insulating layers. For example, as shown in FIG. 5, the first pad 140 may be disposed on the lower surface of the first insulating layer 111, but is not limited thereto. However, the first pad 140 may be disposed at the interface between the plurality of insulating layers, with one end connected to a first via 170 disposed thereon and the other end connected to another first via 170 disposed thereunder.

[0081] The first pad 140 may have a first cross-sectional area. Preferably, the first pad 140 may have a first cross-sectional area that is larger than an upper cross-sectional area or a lower cross-sectional area of ​​the first via 170.

[0082] The second pads 120 may be disposed on the surfaces of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114, respectively. In other words, the second pads 120 may be connected to second vias 130 of normal size that penetrate the respective insulating layers. Thus, the second pads 120 may be disposed on the surfaces of the respective insulating layers.

[0083] The second pad 120 may have a second cross-sectional area. Preferably, the second pad 120 may have a second cross-sectional area larger than an upper cross-sectional area or a lower cross-sectional area of ​​the second via 130. In this case, the second cross-sectional area of ​​the second pad 120 may be smaller than the first cross-sectional area of ​​the first pad 140. That is, the size of the second pad 120 may be smaller than the size of the first pad 140.

[0084] The first pad 140 and the second pad 120 may have a thickness in the range of 5 μm to 50 μm. For example, the first pad 140 and the second pad 120 may have a thickness in the range of 10 μm to 40 μm. For example, the first pad 140 and the second pad 120 may have a thickness in the range of 15 μm to 35 μm. If the thickness of the first pad 140 and the second pad 120 is less than 5 μm, it may be difficult to form them. Furthermore, if the thickness of the first pad 140 and the second pad 120 exceeds 50 μm, the overall thickness of the circuit board may increase. Furthermore, if the thickness of the first pad 140 and the second pad 120 is outside the range of 5 μm to 50 μm, loss may occur during signal transmission.

[0085] The first via 170 and the second via 130 may be disposed to penetrate the insulating layer 110. In this case, the first via 170 and the second via 130 may have different shapes in their respective parts. This may occur because the first via 170 and the second via 130 have different sizes.

[0086] Preferably, the size of the first via 170 may be larger than the size of the second via 130. For example, the diameter of the first via 170 may be larger than 100 μm. And, the diameter of the second via 130 may be smaller than 100 μm. For example, the diameter of the first via 170 in the first direction may be larger than 500 μm. For example, the diameter of the first via 170 in the first direction may be larger than 1000 μm. For example, the diameter of the first via 170 in the first direction may be larger than 2000 μm. For example, the diameter of the first via 170 in the first direction may be larger than 2500 μm. For example, the diameter of the first via 170 in the second direction may be larger than 500 μm. For example, the diameter of the first via 170 in the second direction may be larger than 1000 μm. For example, the diameter of the first via 170 in the second direction may be larger than 2000 μm. For example, the diameter of the first via 170 in the first direction may be greater than 2500 μm.

[0087] In this case, the diameter of the first via 170 in the first direction may be the same as the diameter of the first via 170 in the second direction, but is not limited thereto. That is, the diameter of the first via 170 in the first direction and the diameter of the first via 170 in the second direction may be different from each other.

[0088] The second via 130 may be a signal transmission via included in a general circuit board, and therefore, a detailed description thereof will be omitted.

[0089] However, in this embodiment, the second via 130 can be formed together with the first via 170, and in this case, the first via 170 includes multiple via parts formed through multiple processes, while the second via 130 includes a single part.

[0090] The first via 170 and the second via 130 may be formed by filling the inside of a via hole (not shown) that penetrates at least one of the insulating layers with a conductive material.

[0091] The via hole may be formed by any one of mechanical, laser, and chemical processing methods. When the via hole is formed by mechanical processing, methods such as milling, drilling, and routing may be used. When the via hole is formed by laser processing, methods such as UV or CO2 laser may be used. When the via hole is formed by chemical processing, at least one of the insulating layers may be opened using a chemical containing aminosilane, ketones, etc.

[0092] On the other hand, laser processing is a cutting method that focuses optical energy on the surface to melt and vaporize part of the material to create the desired shape, and it can easily process complex shapes created by computer programs, as well as composite materials that are difficult to cut with other methods.

[0093] In addition, the laser processing has the advantage that the cutting diameter can be as small as 0.005 mm, and the range of thickness that can be processed is wide.

[0094] The laser processing drill is preferably a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper foil layer and the insulating layer, while the CO2 laser is a laser that can process only the insulating layer.

[0095] Once the via holes are formed, the interiors of the via holes may be filled with a conductive material to form the first via 170 and the second via 130. The metal material forming the first via 170 and the second via 130 may be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the conductive material may be filled by any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet printing, and dispensing.

[0096] The structure of the first via 170 will be specifically described below.

[0097] The first via 170 may include a first via part 150 filling a portion of a first via hole commonly penetrating a plurality of insulating layers, and a second via part 160 arranged to fill the remaining portion of the first via hole.

[0098] The first via part 150 may be formed in a first region of the first via hole. The second via part 160 may be formed in a second region of the first via hole excluding the first region. The second region may be a central region of an upper region of the first via hole excluding a lower region. The first region may be the remaining region excluding the second region. Preferably, the first region may be an outer region of the lower and upper regions of the first via hole.

[0099] That is, in the first embodiment, a part of the inside of the first via hole formed by commonly penetrating a plurality of insulating layers can be filled with the first via part 150 , and the remaining part can be filled with the second via part 160 .

[0100] Each of the first via part 150 and the second via part 160 may include a portion disposed within the first via hole and a portion disposed on the portion disposed within the first via hole and protruding above the surface of the insulating layer 110.

[0101] That is, the first via part 150 includes a first portion 151 disposed in a first region of the first via hole. The first portion 151 can also be referred to as a connection portion located within the first via hole. For example, the first portion 151 of the first via part 150 can form a part of the connection portion of the first via 170.

[0102] The first via part 150 may include a second part 152 disposed on the first part 151 and protruding above the top surface of the insulating layer 110. The second part 152 is located on the opposite side of the first pad 140 with the connection part of the first via 170 as the center and may be referred to as a via pad connected to the connection part. For example, the second part 152 of the first via part 150 may form a part of the pad of the first via 170.

[0103] The first portion 151 of the first via part 150 may be formed to fill only a first region corresponding to a portion of the first via hole, rather than the entire region of the first via hole.

[0104] Therefore, the upper surface of the first portion 151 of the first via part 150 may have a curved surface rather than a flat surface. Preferably, the upper surface of the first portion 151 of the first via part 150 may have a shape concave downward. As a result, the length of the upper surface of the first portion 151 of the first via part 150 may be greater than the upper width of the first via hole. That is, the length of the upper surface of the first portion 151 of the first via part 150 may be greater than the upper width corresponding to the linear distance of the upper region of the first via hole.

[0105] A portion of the upper surface of the first portion 151 of the first via part 150 may be located lower than the upper surface of the insulating layer 110. Here, the insulating layer 110 may refer to the uppermost insulating layer among a plurality of insulating layers in which a first via hole is formed. For example, the center point of the upper surface of the first portion 151 of the first via part 150 may be located lower than the upper surface of the insulating layer 110. In this case, the upper surface of the first portion 151 of the first via part 150 may gradually become lower from the periphery to the center. Therefore, the center point of the upper surface of the first portion 151 of the first via part 150 may be located lowest, and the edge point of the periphery may be located highest. As a result, a concave portion may be formed on the upper surface of the first portion 151 of the first via part 150. Meanwhile, the length of the lower surface of the first portion 151 of the first via 170 may be the same as the bottom width of the first via hole.

[0106] The second portion 152 of the first via part 150 may be located on the first portion 151. That is, the second portion 152 of the first via part 150 may be integrally formed with the first portion 151. That is, the second portion 152 of the first via part 150 may extend from the first portion 151 and protrude above the top surface of the insulating layer 110.

[0107] Meanwhile, the first via 170 may have a first thickness H1. The first thickness H1 of the first via 170 may refer to the vertical linear distance from the bottom surface of the first portion 151 of the first via part 150 to the top surface of the second portion 152.

[0108] At this time, the thickness of the recess of the first bead part 150 may have a second thickness H2. Here, the second thickness H2 of the recess of the first bead part 150 may refer to the vertical linear distance from the top surface of the second portion 152 of the first bead part 150 to the lowest point on the top surface of the first portion 151.

[0109] The second thickness H2 may be 30% to 70% of the first thickness H1. For example, the second thickness H2 may be 40% to 65% of the first thickness H1. For example, the second thickness H2 may be 50% to 60% of the first thickness H1. If the second thickness H2 is less than 30% of the first thickness H1, the thickness of the area removed by the polishing process during the formation of the first bead part 150 and the second bead part 160 increases, which may complicate the manufacturing process. Furthermore, if the second thickness H2 is more than 70% of the first thickness H1, a dimple area may occur on the second bead part 160 even after the second bead part 160 is formed.

[0110] Meanwhile, the first via hole may have a first width W1.

[0111] Preferably, the first width W1 of the first via hole may include the width of the first via hole in the first direction and the width of the first via hole in the second direction. The width of the first via hole in the first direction may be greater than 500 μm. For example, the width of the first via hole in the first direction may be greater than 1000 μm. For example, the width of the first via hole in the first direction may be greater than 2000 μm. For example, the width of the first via hole in the first direction may be greater than 2500 μm. For example, the width of the first via hole in the second direction may be greater than 500 μm. For example, the width of the first via hole in the second direction may be greater than 1000 μm. For example, the width of the first via hole in the second direction may be greater than 2000 μm. For example, the width of the first via hole in the second direction may be greater than 2500 μm.

[0112] In this case, the width of the first via hole in the first direction may be the same as its width in the second direction, but is not limited to this. That is, the diameter of the first via hole in the first direction and the diameter of the first via hole in the second direction may be different from each other, thereby forming a bar or ellipse shape.

[0113] On the other hand, if the width of the first via hole is smaller than the above range, it may be substantially the same size as the second via 130, and therefore only one single via part may be formed therein. That is, if the width of the via hole is smaller than the above-described range of the width of the first via hole, no dimple region will be formed even if the inside of the via hole is filled in one process.

[0114] Meanwhile, the second via part 160 includes a first portion 161 disposed in a second region of the first via hole. The first portion 161 can also be referred to as a connection portion located within the first via hole. For example, the first portion 161 of the second via part 160 can form a part of the connection portion of the first via 170.

[0115] That is, the first portion 161 of the second via part 160 may form a connection portion of the first via 170 together with the first portion 151 of the first via part 150 .

[0116] The second via part 160 is disposed on the first part 161 and may include a second part 162 protruding above the upper surface of the insulating layer 110. The second part 162 is located on the opposite side of the first pad 140, centered on the connection part of the first via 170, and may also be referred to as a via pad connected to the connection part. For example, the second part 162 of the second via part 160 may form a part of the pad of the first via 170. That is, the second part 162 of the second via part 160, together with the second part 152 of the first via part 150, may form the pad (specifically, the upper pad) of the first via part 150.

[0117] The first portion 161 of the second via part 160 may be formed to fill only a second region corresponding to a portion of the first via hole rather than the entire region of the first via hole. Specifically, the first portion 161 of the second via part 160 may be formed to fill a recess formed on the top surface of the first portion 151 of the first via part 150.

[0118] Therefore, the lower surface of the first portion 161 of the second via part 160 may have a curved surface rather than a flat surface. Preferably, the lower surface of the first portion 161 of the second via part 160 may have a downwardly convex shape. As a result, the length of the lower surface of the first portion 161 of the second via part 160 may be greater than each of the upper and lower widths of the first via hole. That is, the length of the lower surface of the first portion 161 of the second via part 160 may be greater than the upper width, which corresponds to the linear distance of the upper region of the first via hole.

[0119] A portion of the lower surface of the first portion 161 of the second via part 160 may be located lower than the upper surface of the insulating layer 110. Here, the insulating layer 110 may refer to the uppermost insulating layer among a plurality of insulating layers in which a first via hole is formed. For example, the center point of the lower surface of the first portion 161 of the second via part 160 may be located lower than the upper surface of the insulating layer 110. In this case, the lower surface of the first portion 161 of the second via part 160 may gradually become lower from the periphery to the center. Therefore, the center point of the lower surface of the first portion 161 of the second via part 160 may be located lowest, and the edge point of the periphery may be located highest. As a result, a convex portion may be formed on the lower surface of the first portion 161 of the second via part 160.

[0120] The second portion 162 of the second via part 160 may be located on the first portion 161. That is, the second portion 162 of the second via part 160 may be integrally formed with the first portion 161. That is, the second portion 162 of the second via part 160 may extend from the first portion 161 and protrude above the top surface of the insulating layer 110.

[0121] Meanwhile, the first via 170 may have a first thickness H1. The first thickness H1 of the first via 170 may refer to the vertical linear distance from the bottom surface of the first portion 151 of the first via part 150 to the top surface of the second portion 152.

[0122] In this case, the thickness of the convex portion of the second bead part 160 may have a second thickness H2. Here, the second thickness H2 of the convex portion of the second bead part 160 may refer to the vertical linear distance from the upper surface of the second portion 162 of the second bead part 160 to the lowest point on the lower surface of the first portion 161.

[0123] The second thickness H2 may be 30% to 70% of the first thickness H1. For example, the second thickness H2 may be 40% to 65% of the first thickness H1. For example, the second thickness H2 may be 50% to 60% of the first thickness H1. If the second thickness H2 is less than 30% of the first thickness H1, the thickness of the area removed by the polishing process during the formation of the first bead part 150 and the second bead part 160 increases, which may complicate the manufacturing process. Furthermore, if the second thickness H2 is more than 70% of the first thickness H1, a dimple area may occur on the second bead part 160 even after the second bead part 160 is formed.

[0124] In other words, the first portion 151 of the first via part 150 may be disposed around the first portion 161 of the second via part 160 disposed in the second region of the first via hole. Also, as shown in FIG. 6b, the second portion 152 of the first via part 150 may be disposed around the second portion 162 of the second via part 160 protruding above the upper surface of the insulating layer 110.

[0125] Meanwhile, the first bead part 150 and the second bead part 160 may have different surface roughnesses at different points on their surfaces.

[0126] 7 and 8 are diagrams showing the surface roughness of the first via according to the example.

[0127] The first bead part 150 may include an upper surface S1 of the first portion 151 and an upper surface S2 of the second portion 152. The surface roughness of the upper surface S1 of the first portion 151 of the first bead part 150 may be different from the surface roughness of the upper surface S2 of the second portion 152 of the first bead part 150.

[0128] 7, the surface roughness Ra of the upper surface S1 of the first portion 151 of the first bead part 150 may be 150 nm to 180 nm. The average value of the surface roughness Ra of the upper surface S1 of the first portion 151 of the first bead part 150 may be 165.41 nm. (a), (b), and (c) of FIG. 7 are diagrams illustrating the surface roughness Ra at different points on the upper surface S1 of the first portion 151 of the first bead part 150.

[0129] Furthermore, the surface roughness Ra of the upper surface S2 of the second portion 152 of the first bead part 150 may be greater than the surface roughness Ra of the upper surface S1 of the first portion 151 of the first bead part 150. That is, as shown in Fig. 8, the surface roughness Ra of the upper surface S2 of the second portion 152 of the first bead part 150 may be 170 nm to 205 nm. That is, the average value of the surface roughness Ra of the upper surface S2 of the second portion 152 of the first bead part 150 may be 193.53 nm. Figs. 8(a), (b), and (c) are diagrams showing the surface roughness Ra at different points on the upper surface S2 of the second portion 152 of the first bead part 150.

[0130] In this case, the upper surface S1 of the first portion 151 of the first bead part 150 corresponds to the lower surface of the first portion 161 of the second bead part 160, and thus the same reference numeral S1 is given to them. In other words, the upper surface S1 of the first portion 151 of the first bead part 150 or the lower surface of the first portion 161 of the second bead part 160 may refer to the boundary surface between the upper surface S1 of the first portion 151 of the first bead part 150 and the lower surface of the first portion 161 of the second bead part 160.

[0131] The second bead part 160 may include a lower surface S1 of the first portion 161 and an upper surface S3 of the second portion 162. The surface roughness of the lower surface S1 of the first portion 161 of the second bead part 160 may be different from the surface roughness of the upper surface S3 of the second portion 162 of the second bead part 160.

[0132] 7, the surface roughness Ra of the lower surface S1 of the first portion 161 of the second bead part 160 may be 150 nm to 180 nm. The average value of the surface roughness Ra of the lower surface S1 of the first portion 161 of the second bead part 160 may be 165.41 nm. (a), (b), and (c) of FIG. 7 can also be seen as showing the surface roughness Ra for different points on the lower surface S1 of the first portion 161 of the second bead part 160.

[0133] Furthermore, the surface roughness Ra of the upper surface S3 of the second portion 162 of the second bead part 160 may be greater than the surface roughness Ra of the lower surface S1 of the first portion 161 of the second bead part 160. That is, as shown in Fig. 8, the surface roughness Ra of the upper surface S3 of the second portion 162 of the second bead part 160 may be 170 nm to 205 nm. That is, the average value of the surface roughness Ra of the upper surface S3 of the second portion 162 of the second bead part 160 may be 193.53 nm. Figs. 8(a), (b), and (c) are diagrams showing the surface roughness Ra at different points on the upper surface S3 of the second portion 162 of the second bead part 160.

[0134] According to the present embodiment, although limitations on plating large diameter via holes exist in the case of conventional large area vias, these limitations can be overcome by changing the plating method, thereby enabling stable plating of large diameter via holes. Furthermore, according to the present embodiment, it is possible to ensure uniformity of via plating compared to existing methods, and to ensure quality reliability by improving laser quality after additional lamination.

[0135] In addition, while there was a conventional limit to the ratio between the thickness of the insulating layer and the size of the via hole in order to stably achieve plating inside the via hole, according to the present embodiment, it is possible to eliminate the design constraints for achieving a highly reliable plating state inside the via hole, thereby increasing the degree of freedom in design. Furthermore, according to the present embodiment, by increasing the size of the via, it is possible to completely shield interference between circuits that occurs in areas where circuits are concentrated, and it is possible to improve heat dissipation characteristics in areas where heat dissipation is required.

[0136] Specifically, in the comparative example, the heat dissipation function is performed using multiple heat dissipation vias spaced at regular intervals horizontally, whereas in the embodiment, the heat dissipation function is performed using a single large-area via while ensuring uniformity of its plating, thereby improving the heat dissipation performance by increasing the via area compared to the comparative example.

[0137] The method for manufacturing the circuit board according to the first embodiment shown in FIG. 5 will be specifically described below.

[0138] 9 to 18 are diagrams showing the manufacturing method of the circuit board according to the first embodiment in the order of steps.

[0139] 9, a base lamination process for manufacturing a circuit board may be performed first, where the base lamination process may include a process of laminating an insulating layer and a process of forming a circuit pattern before the first via 170 is formed.

[0140] To this end, first, a first insulating layer 111 is prepared, and then a process of forming a via hole VH1 for forming the second via 130 in the first insulating layer 111 may be performed.

[0141] After that, when the via hole VH1 is formed, a process of forming a second via 130 to fill the inside of the via hole VH1, and simultaneously forming a first pad 140 and a second pad 120 on the surface of the first insulating layer 111 may be performed.

[0142] In addition, a lamination process can be performed in which a second insulating layer 112 is formed on the lower surface of the first insulating layer 111, a fourth insulating layer 114 is formed on the lower surface of the second insulating layer 112, and a third insulating layer 113 is formed on the upper surface of the first insulating layer 111. Meanwhile, as described above, the number of layers constituting the insulating layer 110 may be changed depending on the embodiment, and the lamination order may also be changed.

[0143] In an embodiment, the insulating layer 110 can include, but is not limited to, a first insulating layer 111, a second insulating layer 112, a third insulating layer 113, and a fourth insulating layer 114. For example, the circuit board can have fewer than four layers, or alternatively, the circuit board could have more than four layers, but the circuit board can include at least two insulating layers.

[0144] In this embodiment, a process of forming a circuit pattern on the surface of the insulating layer 110 may be performed. For example, a process of forming a circuit pattern on the surfaces of the first insulating layer 111 and the second insulating layer 112 may be performed preferentially. In this case, the circuit pattern may include via pads connected to vias, connection pads connected to an external substrate, mounting pads on which electronic components are mounted, and traces serving as signal transmission lines between the pads.

[0145] For example, a process of forming a circuit pattern on the surfaces of the first insulating layer 111 and the second insulating layer 112 may be performed, which may include a first pad 140 and a second pad 120. The first pad 140 and the second pad 120 may be part of the circuit pattern formed on the surfaces of the first insulating layer 111 and the second insulating layer 112, and may substantially refer to the portion connected to the via of the entire area of ​​the circuit pattern disposed on the surface of each insulating layer.

[0146] The first pad 140 and the second pad 120 may be patterns for transmitting electrical signals, or may be patterns for transmitting heat for the purpose of heat dissipation.

[0147] The first pad 140 may be disposed on the lower surface of the first insulating layer 111, but is not limited to this. In other words, the first pad 140 may be connected to a large-area first via 170 that commonly penetrates a plurality of insulating layers. However, the first pad 140 may be disposed at the interface between a plurality of insulating layers, with one end connected to a first via 170 disposed thereover and the other end connected to another first via 170 disposed thereunder.

[0148] The first pad 140 may have a first cross-sectional area. Preferably, the first pad 140 may have a first cross-sectional area that is larger than an upper cross-sectional area or a lower cross-sectional area of ​​the first via 170.

[0149] The second pads 120 may be disposed on the surfaces of the first insulating layer 111 and the second insulating layer 112, respectively. In other words, the second pads 120 may be connected to the second vias 130 of normal size that penetrate the respective insulating layers. Thus, the second pads 120 may be disposed on the surfaces of the respective insulating layers.

[0150] Next, as shown in FIG. 10, a process for penetrating the insulating layer 110 may be performed to form via holes in the insulating layer 110. In this case, the via holes may include a first via hole and a second via hole. The first via hole may have a first area, and the second via hole may have a second area. The first area and the second area may be different from each other. For example, the via holes may include a first via hole VH2 for forming the first via 170 and a second via hole VH1 for forming the second via.

[0151] The first via hole VH2 may be formed to penetrate a plurality of insulating layers in common, and the second via hole VH1 may be formed to penetrate only one of the insulating layers.

[0152] That is, the first via hole VH2 may have a first width W1. Preferably, the first width W1 of the first via hole VH2 may include the width of the first via hole VH2 in the first direction and the width of the first via hole VH2 in the second direction. The width of the first via hole VH2 in the first direction may be greater than 500 μm. For example, the width of the first via hole VH2 in the first direction may be greater than 1000 μm. For example, the width of the first via hole VH2 in the first direction may be greater than 2000 μm. For example, the width of the first via hole VH2 in the first direction may be greater than 2500 μm. For example, the width of the first via hole VH2 in the second direction may be greater than 500 μm. For example, the width of the first via hole VH2 in the second direction may be greater than 1000 μm. For example, the width of the first via hole VH2 in the second direction may be greater than 2000 μm. For example, the width of the first via hole VH2 in the second direction may be greater than 2500 μm.

[0153] In this case, the width of the first via hole VH2 in the first direction may be the same as its width in the second direction, but is not limited to this. That is, the diameter of the first via hole VH2 in the first direction and the diameter of the first via hole VH2 in the second direction may be different from each other, thereby forming a bar or ellipse shape.

[0154] On the other hand, if the width of the first via hole VH2 is smaller than the above range, it may be substantially the same size as the second via hole VH1.

[0155] Here, the first via hole is designated VH2 and the second via hole is designated VH1 because the codes are assigned to the via holes in ascending order of size, and as a result, the first via hole, which is relatively larger in size, is named VH2.

[0156] Next, as shown in FIG. 11, a step of forming a first mask M1 on the surface of the insulating layer 110 can be performed.

[0157] The first mask M1 may include a plurality of openings.

[0158] Specifically, the first mask M1 may include a first opening OR2 exposing the first via hole VH2 formed in the insulating layer 110 and a second opening OR1 exposing the second via hole VH1.

[0159] In this case, the first opening OR2 may have a width greater than the top width of the first via hole VH2. In other words, the first opening OR2 may have a width greater than the top width of the first via hole VH2, rather than being equal to or smaller than the top width of the first via hole VH2. As a result, the first opening OR2 may expose not only the top region of the first via hole VH2 but also the top surface of the insulating layer 110 around the top region of the first via hole VH2. That is, the first opening OR2 may expose a region where a connection portion of the first via 170 is to be formed and a region where a pad of the first via 170 is to be formed. Here, the region where the connection portion is to be formed may be the first via hole VH2, and the region where the pad is to be formed may be the top region of the first via hole VH2 and an adjacent top region of the insulating layer 110.

[0160] The second opening OR1 may have a width greater than the top width of the second via hole VH1. In other words, the second opening OR1 may have a width greater than the top width of the second via hole VH1, rather than being equal to or smaller than the top width of the second via hole VH1. As a result, the second opening OR1 may expose not only the top region of the second via hole VH1 but also the top surface of the insulating layer 110 around the top region of the second via hole VH1. That is, the second opening OR1 may expose a region where a connection portion of the second via 130 is to be formed and a region where a pad of the second via 130 is to be formed. Here, the region where the connection portion of the second via 130 is to be formed may be the second via hole VH1, and the region where the pad of the second via 130 is to be formed may be the top region of the second via hole VH1 and an adjacent top region of the insulating layer 110.

[0161] Next, as shown in FIG. 12, once the first via hole VH2 and the second via hole VH1 are formed, the insides of the first via hole VH2 and the second via hole VH1 can be filled with a conductive material to form the first via 170 and the second via 130.

[0162] The metal material forming the first via 170 and the second via 130 may be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the filling of the conductive material may be any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet printing, and dispensing, or a combination thereof.

[0163] In this case, the first via hole VH2 and the second via hole VH1 have different sizes. The first via hole VH2 is a large-area via. Therefore, while it is possible to form a second via that fills the entire second via hole VH1 in a single process, it is difficult to form a first via that fills the entire first via hole VH2 in a single process.

[0164] Therefore, a primary plating process is performed to form the first via part 150 of the first via 170 that fills a portion of the first via hole VH2, and also to form the second via 130a that fills the entire second via hole VH1.

[0165] The second via 130 a includes a connecting portion 131 disposed in the second via hole VH 1 and a pad portion 132 protruding from the connecting portion 131 .

[0166] The upper surface of the pad portion 132 may not be flat. That is, the plating process of the second via hole VH1 is performed together with the plating process of the first via hole VH2. The plating process of the second via hole VH1 may be performed under conditions for forming the first via part 150 of the first via 170 in the first via hole VH2. Therefore, the pad portion 132 of the second via 130a formed at this time may protrude above the first mask M1 and have a curved upper surface.

[0167] In the above-described primary plating process, the first via part 150 of the first via 170 may be formed in the first via hole VH2.

[0168] The first via part 150 may include a first portion 151 disposed in the first via hole VH2 and a second portion 152 disposed on the first portion 151 and protruding above the top surface of the insulating layer 110. The top surface of the second portion 152 may have a curvature similar to the pad portion 132 of the second via 130a.

[0169] The first via part 150 may be formed in a first region of the first via hole. The first region may be an outer region excluding a central region. Preferably, the first region may be an outer region of a lower region and an upper region of the first via hole.

[0170] That is, in the first embodiment, a portion of the inside of the first via hole formed by commonly penetrating a plurality of insulating layers may be filled with the first via part 150 by the first plating process.

[0171] In addition, the formed first portion 151 of the first via part 150 can also be referred to as a connection portion located within the first via hole. For example, the first portion 151 of the first via part 150 can form a part of the connection portion of the first via 170.

[0172] The second portion 152 of the first via part 150 is located on the opposite side of the first pad 140 around the connection portion of the first via 170, and can be referred to as a via pad connected to the connection portion. For example, the second portion 152 of the first via part 150 can form a part of the pad of the first via 170.

[0173] The first portion 151 of the first via part 150 may be formed to fill only a first region corresponding to a portion of the first via hole, rather than the entire region of the first via hole.

[0174] Therefore, the upper surface of the first portion 151 of the first via part 150 may have a curved surface rather than a flat surface. Preferably, the upper surface of the first portion 151 of the first via part 150 may have a shape concave downward. As a result, the length of the upper surface of the first portion 151 of the first via part 150 may be greater than the upper width of the first via hole. That is, the length of the upper surface of the first portion 151 of the first via part 150 may be greater than the upper width corresponding to the linear distance of the upper region of the first via hole.

[0175] A portion of the upper surface of the first portion 151 of the first via part 150 may be located lower than the upper surface of the insulating layer 110. Here, the insulating layer 110 may refer to the uppermost insulating layer among a plurality of insulating layers in which a first via hole is formed. For example, the center point of the upper surface of the first portion 151 of the first via part 150 may be located lower than the upper surface of the insulating layer 110. In this case, the upper surface of the first portion 151 of the first via part 150 may gradually become lower from the periphery to the center. Therefore, the center point of the upper surface of the first portion 151 of the first via part 150 may be located lowest, and the edge point of the periphery may be located highest. As a result, a concave portion may be formed on the upper surface of the first portion 151 of the first via part 150. Meanwhile, the length of the lower surface of the first portion 151 of the first via 170 may be the same as the bottom width of the first via hole.

[0176] The second portion 152 of the first via part 150 may be located on the first portion 151. That is, the second portion 152 of the first via part 150 may be integrally formed with the first portion 151. That is, the second portion 152 of the first via part 150 may extend from the first portion 151 and protrude above the top surface of the insulating layer 110.

[0177] Next, a primary grinding step can be carried out as shown in FIG.

[0178] The primary grinding process may be a process of planarizing the upper surface of the second portion 152 of the first via part 150 of the first via 170 formed through the primary plating process. Also, the primary grinding process may be a process of planarizing the upper surface of the pad portion 132 of the second via 130a formed through the primary plating process.

[0179] Next, as shown in FIG. 14, a step of forming a second mask M2 on the first mask M1 can be performed.

[0180] The second mask M2 may include a third opening OR3. Preferably, the second mask M2 may have the third opening OR3 disposed on the upper surface of the first mask M1, covering the pad portion 132 of the second via 130a, thereby exposing the first via hole VH2.

[0181] The third opening OR3 may be smaller than the first opening OR2. Thus, the second mask M2 may be disposed to cover a portion of the top surface of the second portion 152 of the first via part 150 formed in the primary plating process. This is because if the size of the third opening OR3 were the same as the size of the first opening OR2 of the first mask M1, plating would be performed on the inside of the first via hole VH2 and on the second portion 152 of the first via part 150 in the subsequent secondary plating process. This would take a long time to fill the entire inside of the first via hole VH2 and also take a long time for the subsequent grinding process.

[0182] Next, as shown in FIG. 15, a secondary plating process can be performed within the first via hole VH2 exposed through the third opening OR3 of the second mask M2 to form the second via part 160 of the first via 170.

[0183] The second via part 160 includes a first portion 161 disposed in a second region of the first via hole. The first portion 161 may also be referred to as a connecting portion located within the first via hole. For example, the first portion 161 of the second via part 160 may form a part of the connecting portion of the first via 170.

[0184] That is, the first portion 161 of the second via part 160 may form a connection portion of the first via 170 together with the first portion 151 of the first via part 150 .

[0185] The second via part 160 is disposed on the first part 161 and may include a second part 162 protruding above the upper surface of the insulating layer 110. The second part 162 is located on the opposite side of the first pad 140, centered on the connection part of the first via 170, and may be referred to as a via pad connected to the connection part. For example, the second part 162 of the second via part 160 may form a part of the pad of the first via 170. That is, the second part 162 of the second via part 160, together with the second part 152 of the first via part 150, may form the pad (specifically, the upper pad) of the first via part 150.

[0186] The first portion 161 of the second via part 160 may be formed to fill only a second region corresponding to a portion of the first via hole rather than the entire region of the first via hole. Specifically, the first portion 161 of the second via part 160 may be formed to fill a recess formed on the top surface of the first portion 151 of the first via part 150.

[0187] Therefore, the lower surface of the first portion 161 of the second via part 160 may have a curved surface rather than a flat surface. Preferably, the lower surface of the first portion 161 of the second via part 160 may have a downwardly convex shape. As a result, the length of the lower surface of the first portion 161 of the second via part 160 may be greater than each of the upper and lower widths of the first via hole. That is, the length of the lower surface of the first portion 161 of the second via part 160 may be greater than the upper width, which corresponds to the linear distance of the upper region of the first via hole.

[0188] A portion of the lower surface of the first portion 161 of the second via part 160 may be located lower than the upper surface of the insulating layer 110. Here, the insulating layer 110 may refer to the uppermost insulating layer among a plurality of insulating layers in which a first via hole is formed. For example, the center point of the lower surface of the first portion 161 of the second via part 160 may be located lower than the upper surface of the insulating layer 110. In this case, the lower surface of the first portion 161 of the second via part 160 may gradually become lower from the periphery to the center. Therefore, the center point of the lower surface of the first portion 161 of the second via part 160 may be located lowest, and the edge point of the periphery may be located highest. As a result, a convex portion may be formed on the lower surface of the first portion 161 of the second via part 160.

[0189] At this time, the second portion 162 of the second via part 160 formed through the secondary plating process may be located on the first portion 161. That is, the second portion 162 of the second via part 160 is integrally formed with the first portion 161. That is, the second portion 162 of the second via part 160 may extend from the first portion 161 and protrude above the top surface of the insulating layer 110.

[0190] At this time, the upper surface of the second portion 162 of the second bead part 160 may have a curve, and a dimple phenomenon may occur in a specific area.

[0191] Next, as shown in FIG. 16, the second mask M2 is removed, and a secondary grinding process can be performed to flatten the top surface of the second portion 162 of the second bead part 160.

[0192] The upper surface of the second portion 162 of the second via part 160 may be planarized by the secondary grinding process, so that it can be positioned flush with the upper surface of the pad portion 132 of the second via 130a.

[0193] Next, as shown in FIG. 17, a third grinding process can be performed to polish the upper surface of the second portion 152 of the first via part 150, the upper surface of the second portion 162 of the second via part 160, and the upper surface of the pad portion 132 of the second via 130a.

[0194] That is, the second portion 152 of the first via part 150, the second portion 162 of the second via part 160, and the pad portion 132 of the second via 130a, which were formed in the previous process, have thicknesses greater than their actual design values. This is to improve plating deviations that may occur in the secondary plating process, and also to ensure that dimple regions that may occur in the secondary plating process are located in the ineffective portions of the first vias rather than the effective portions. The ineffective portions of the first vias may refer to the portions that are removed in the secondary and tertiary grinding processes.

[0195] Then, the third grinding process is performed to adjust the thickness of the second portion 152 of the first via part 150, the second portion 162 of the second via part 160, and the pad portion 132 of the second via 130a to the same level as the thickness of the first pad 140 or the thickness of the second pad 120.

[0196] Next, as shown in FIG. 18, a process of removing the first mask M1 is performed, thereby forming a circuit board including first and second vias having different structural shapes.

[0197] FIG. 19 is a diagram showing a circuit board according to a second embodiment, FIG. 20a is a diagram for explaining the interfaces of each part of the first via shown in FIG. 19, and FIG. 20b is a plan view of the first via shown in FIG. 19.

[0198] 19, 20a, and 20b, the circuit board according to the second embodiment has substantially the same structure as the circuit board according to the first embodiment shown in Fig. 5, except for the second via part of the first via. Therefore, the following description will focus on the structural features of the second via part of the first via in the circuit board according to the second embodiment.

[0199] The circuit board according to the second embodiment may include an insulating layer 210, a first pad 240 and a second pad 220 arranged on the surface of the insulating layer 210, and a first via 270 and a second via 230 arranged through the insulating layer 210.

[0200] Here, the insulating layer, the first pad, the second pad, and the first via have the same structure as the insulating layer, the first pad, the second pad, and the first via in the circuit board according to the first embodiment described with reference to FIG. 5, and therefore, description thereof will be omitted.

[0201] The first via 270 may include a first via part 250 that fills a portion of a first via hole that commonly penetrates a plurality of insulating layers, and a second via part 260 that is disposed to fill the remaining portion of the first via hole.

[0202] The first via part 250 may be formed in a first region of the first via hole. The second via part 260 may be formed in a second region of the first via hole excluding the first region. The second region may be a central region of an upper region of the first via hole excluding a lower region. The first region may be the remaining region excluding the second region. Preferably, the first region may be an outer region of the lower and upper regions of the first via hole.

[0203] That is, in the second embodiment, a portion of the inside of the first via hole formed by commonly penetrating a plurality of insulating layers may be filled with the first via part 250, and the remaining portion may be filled with the second via part 260.

[0204] Each of the first via part 250 and the second via part 260 may include a portion disposed within the first via hole and a portion disposed on the portion disposed within the first via hole and protruding above the surface of the insulating layer 210.

[0205] That is, the first via part 250 includes a first portion 251 disposed in a first region of the first via hole. The first portion 251 can also be referred to as a connection portion located within the first via hole. For example, the first portion 251 of the first via part 250 can form a part of the connection portion of the first via 270.

[0206] The first via part 250 may include a second part 252 disposed on the first part 251 and protruding above the top surface of the insulating layer 210. The second part 252 is located on the opposite side of the first pad 240 with the connection part of the first via 270 as the center and may be referred to as a via pad connected to the connection part. For example, the second part 252 of the first via part 250 may form a part of the pad of the first via 270.

[0207] The first portion 251 of the first via part 250 may be formed to fill only a first region corresponding to a portion of the first via hole, rather than the entire region of the first via hole.

[0208] Here, the first bead part 250 has substantially the same structure as the first bead part 150 described in the first embodiment, and therefore, detailed description thereof will be omitted.

[0209] The second via part 160 of the first via 270 is disposed in a second region of the first via hole.

[0210] In the first embodiment, the second region of the first via hole is formed by a single plating process, so that the second via part 160 in the first embodiment is formed as a single part.

[0211] In contrast, in the second embodiment, the second via part 260 is formed by performing at least two plating processes instead of one plating process.

[0212] Thus, the second via part 260 includes a first sub-second via part 260a whose outer surface contacts the first via part 250 and fills a portion of the second region of the first via hole. The second via part 260 also includes a second sub-second via part 260b whose outer surface contacts the inner surface of the first sub-second via part 260a.

[0213] That is, in the second embodiment, the first region of the first via hole is formed by performing multiple plating processes, and thus the second via part 260 may include a first sub-second via part 260a and a second sub-second via part 260b whose interfaces are separated from each other.

[0214] Accordingly, the first sub-second via part 260a may include a first portion 261a disposed within the first via hole and a second portion 262a disposed on the first portion 261a and protruding above the top surface of the insulating layer.

[0215] In addition, the second sub-second via part 260b may also include a first portion 261b disposed in the first via hole and a second portion 262b disposed on the first portion 261b and protruding above the top surface of the insulating layer.

[0216] As a result, in the first embodiment, the interfaces of the via parts that form the first via include only one interface between the first via part and the second via part.

[0217] In contrast, the interfaces of the via parts constituting the first via in the second embodiment may include a first interface BS1 between the first via part and the first sub-second via part 260a and a second interface BS2 between the first sub-second via part 260a and the second sub-second via part 260b.

[0218] The reason why the second via part 260 of the first via is plated in multiple steps is to minimize plating deviations that occur during the plating process. Furthermore, in order to form the second via part 260 in a single process, the current condition in the plating conditions may be higher than the limiting current of a general plating device. Therefore, the second via part 260 is formed in multiple steps under a current condition lower than the limiting current.

[0219] As a result, the outer surface of the first sub-second bead part 260a has characteristics corresponding to the outer surface of the second bead part 160 in the first embodiment.

[0220] In addition, a portion of the inner surface of the first sub-second via part 260a may be located lower than the upper surface of the insulating layer 210. Here, the insulating layer 210 may refer to the uppermost insulating layer among a plurality of insulating layers in which a first via hole is formed. For example, the center point of the inner surface of the first sub-second via part 260a may be located lower than the upper surface of the insulating layer 210. In this case, the inner surface of the first portion 261a of the first sub-second via part 260a may gradually become lower from the periphery to the center. Therefore, the center point of the inner surface of the first portion 261a of the first sub-second via part 260a may be located lowest, and the edge point of the periphery may be located highest. As a result, the outer surface of the first sub-second via part 260a may form a convex portion, and the inner surface thereof may form a concave portion.

[0221] 20b, the second portion 261b of the first sub-second bead part 260a may be disposed around the second portion 262b of the second sub-second bead part 260b, and the second portion 252 of the first bead part 250 may be disposed around the second portion 261b of the first sub-second bead part 260a.

[0222] 21 to 24 are diagrams for explaining the manufacturing method of the circuit board according to the second embodiment in the order of steps.

[0223] Referring to FIG. 21, the steps shown in FIGS. 9 to 14 can be carried out preferentially.

[0224] Then, in the first embodiment, a secondary plating process was performed at once to fill the entire remaining portion of the first via hole, but in the second embodiment, a first sub-second plating process is performed first to fill only a portion of the remaining portion of the first via hole, thereby forming the first sub-second via part 260a.

[0225] Next, referring to FIG. 22, a second sub-secondary plating process may be performed on the first sub-second via part 260a to fill the remaining portion of the first via hole, thereby forming a second sub-second via part 260b.

[0226] Next, the second mask M2 may be removed, and the upper surfaces of the second portions of the first sub-second via part 260a and the second sub-second via part 260b may be planarized.

[0227] Then, as shown in Figure 24, the pad portions of the first via and the second via (the second portion of the first via part, the second portion of the first sub-second via part, and the second portion of the second sub-second via part) can be ground to form the first via and the second via with pads having thicknesses corresponding to the actual design values.

Claims

1. a first insulating layer; a second insulating layer disposed on the first insulating layer; a first through electrode disposed in a first through hole that integrally penetrates the first insulating layer and the second insulating layer; a second through electrode disposed in a second through hole penetrating at least a partial region of the second insulating layer and overlapping the first through electrode along a horizontal direction; a third through electrode disposed in a third through hole penetrating at least a partial region of the first insulating layer and overlapping the first through electrode along the horizontal direction; an inner pad portion disposed between the second through electrode and the third through electrode and overlapping with the first through electrode along the horizontal direction; The first through electrode is a first part that contacts an inner wall of the first through hole; a second part disposed on the first part, the second through electrode includes a metal layer corresponding to the first part of the first through electrode; The width of the second through electrode is smaller than the width of the first through electrode.

2. an upper surface of the first part includes a first upper surface that contacts the second part and a second upper surface that does not contact the second part; the first upper surface has a first surface roughness; the second upper surface has a second surface roughness greater than the first surface roughness; a lower surface of the second part contacts the first upper surface of the first part; The upper surface of the second part is not in contact with the first part, a lower surface of the second part has the first surface roughness; The circuit board according to claim 1 , wherein an upper surface of the second part has the second surface roughness.

3. The first part comprises: a first portion disposed within the first through hole; a second portion on the first portion disposed on the second insulating layer; The second part is a third portion disposed within the first through hole and on the first portion of the first part; 3. The circuit board of claim 2, further comprising a fourth portion on said third portion disposed on said second insulating layer.

4. The first upper surface of the first part is recessed toward the lower surface of the first insulating layer, The lower surface of the second part is The circuit board according to claim 2 , wherein the first insulating layer has a convex portion corresponding to the first upper surface of the first part and convex toward the lower surface of the first insulating layer.

5. The circuit board according to claim 2 , wherein the first upper surface of the first part decreases in height as it moves away from the inner wall of the first through hole.

6. The vertical distance from the second upper surface of the first part to the lowest point of the first upper surface of the first part is The circuit board according to claim 4 , wherein the thickness of the first through-electrode is in the range of 30% to 70% of the total thickness of the first through-electrode.

7. The vertical distance from the upper surface of the second part to the lowest point of the lower surface of the second part is The circuit board according to claim 4 , wherein the thickness of the first through-electrode is in the range of 30% to 70% of the total thickness of the first through-electrode.

8. The circuit board according to claim 2 , wherein the second upper surface of the first part and the upper surface of the second part are located on the same plane.

9. a first pad disposed on a lower surface of the first insulating layer and vertically overlapping the first through hole; The circuit board according to claim 1 , wherein the first part is disposed on the first pad.

10. The circuit board according to claim 1 , wherein the first through-hole has a slope such that its width decreases from the upper surface of the second insulating layer toward the lower surface of the first insulating layer.

11. The first through electrode is The circuit board of claim 3 further comprising a third part disposed on the second part.

12. The third part is a fifth portion disposed within the first through hole and on the third portion of the second part; 12. The circuit board of claim 11, further comprising: a sixth portion on the fifth portion disposed on the second insulating layer.

13. The top surface of the second part is a third upper surface in contact with the third part; a fourth upper surface that is not in contact with the third part; The circuit board according to claim 12 , wherein the third upper surface of the second part has a surface roughness smaller than a surface roughness of the fourth upper surface of the second part.

14. a lower surface of the third part contacts the third upper surface of the second part; an upper surface of the third part is not in contact with the first part or the second part; The circuit board according to claim 13 , wherein a surface roughness of the upper surface of the third part is greater than a surface roughness of the lower surface of the third part.

15. The third upper surface of the second part is recessed toward the lower surface of the first insulating layer, The lower surface of the third part is The circuit board according to claim 14 , wherein the third upper surface of the second part corresponds to the third upper surface and is convex toward the lower surface of the first insulating layer.

16. The circuit board according to claim 14 , wherein the second top surface of the first part, the fourth top surface of the second part, and the top surface of the third part are located on the same plane as one another.

17. The circuit board according to claim 15 , wherein the third upper surface of the second part decreases in height as it moves away from the inner wall of the first through hole.

18. The circuit board according to claim 15 , wherein the lower surface of the third part decreases in height as it moves away from the inner wall of the first through hole.

Images