Method for forming a semiconductor device

Abstract

A method of semiconductor device manufacturing includes forming a vertical structure in a layer stack by processing a first side of a first die, the vertical structure having an end in a first layer. The first layer has a better etch selectivity to the layer stack than a second layer (S310). The method further includes replacing the first layer with a second layer by processing a second side of the first die opposite the first side (S320).

Description

[Technical Field]

[0001] The present invention generally describes embodiments relating to semiconductor device manufacturing processes. [Background technology]

[0002] Semiconductor manufacturers have developed vertical device technologies, such as three-dimensional (3D) NAND flash memory technology, to achieve higher transistor densities without requiring smaller transistors. In some examples, 3D NAND memory devices include an array of vertical memory cell strings. Each vertical memory cell string includes multiple memory cells connected in series. Increasing the number of memory cells in a vertical memory cell string can increase data array density. Summary of the Invention

[0003] Aspects of the present disclosure provide a method for semiconductor device fabrication. The method includes forming a vertical structure in a layer stack by processing a first side of a first die, the vertical structure having an edge in a first layer. The first layer has a better etch selectivity to the layer stack than a second layer. The method further includes replacing the first layer with a second layer by processing a second side of the first die opposite the first side.

[0004] In some examples, the first layer includes tungsten and the second layer includes a semiconductor layer, such as a polysilicon layer.

[0005] According to one aspect of the present disclosure, the vertical structure corresponds to a channel structure, and the initial first layer stack includes a first layer in a core region, and the layer stack corresponds to an initial second layer stack. Then, the method includes forming an initial second layer stack including alternating insulating layers and sacrificial gate layers on top of the initial first layer stack.

[0006] In some examples, the method includes forming a channel hole in the initial second layer stack, the channel hole having an end in the first layer, and forming a channel structure in the channel hole. Specifically, in some examples, the channel structure includes a channel layer surrounded by a blocking insulating layer, a charge storage layer, and a tunnel insulating layer. And, replacing the first layer with the second layer further includes removing the first layer by processing the second surface, and removing the blocking insulating layer, the charge storage layer, and the tunnel insulating layer from the end of the channel structure by processing the second surface.

[0007] In some examples, the method includes forming a second layer in contact with the channel layer at an end of the channel structure to replace the first layer with the second layer. For example, the method may include forming a semiconductor layer in contact with the channel layer at the end of the channel structure by processing the second surface. Specifically, in one example, the method includes forming a liner portion of the semiconductor layer. The liner portion contacts the channel layer at the end of the channel structure. Then, the method includes performing ion implantation to dope the liner portion and forming a bulk portion of the semiconductor layer. Furthermore, the method includes forming a pad structure on the second surface, the pad structure being conductively connected to the semiconductor layer.

[0008] According to another aspect of the present disclosure, the vertical structure corresponds to a dummy channel structure, and the initial first layer stack includes a first layer within a staircase region. In some examples, the layer stack corresponds to an initial second layer stack, and the method includes forming an initial second layer stack including alternating insulating layers and sacrificial gate layers on top of the initial first layer stack, and forming a staircase based on the initial second layer stack within the staircase region. The method further includes planarizing the staircase region using an insulating material. The method then includes forming a dummy channel hole in the insulating material and the initial second layer stack. The end of the dummy channel hole is within the first layer. The method then includes forming a dummy channel structure within the dummy channel hole.

[0009] According to another aspect of the present disclosure, the vertical structure corresponds to a gate line slit structure, and the initial first layer stack includes a first layer in the gate line slit region. The layer stack corresponds to a first second layer stack, and the method further includes forming an initial second layer stack including alternating insulating layers and sacrificial gate layers on top of the initial first layer stack. Then, the method includes forming a channel structure in the initial second layer stack, forming a trench in the initial second layer stack with an end in the first layer, replacing the sacrificial gate layer with a gate layer through the trench, and forming the gate line slit structure in the trench.

[0010] According to another aspect of the present disclosure, the method includes forming a punch-through contact structure in a punch-through region by processing a first side of a first die. In some examples, the method includes forming a bonding structure on the first side of the first die and bonding the first side to a second die before processing the second side of the first die. In one example, the method includes processing the second side of the first die to form a through-silicon contact. The through-silicon contact conductively connects the punch-through contact structure to a pad structure on the second side of the first die.

[0011] Aspects of the present disclosure provide a layout design for use in a method for semiconductor device manufacturing.

[0012] Aspects of the present disclosure provide semiconductor devices and memory device systems manufactured according to methods of semiconductor device manufacturing.

[0013] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, various features have not been drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration. [Brief explanation of the drawings]

[0014] [Figure 1A] 1 shows a cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure. [Figure 1B] 1 shows a cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure. [Figure 2A] 1 shows the layout of a pattern for defining a stop layer. [Figure 2B] 1 shows the layout of a pattern for defining a stop layer. [Figure 2C] 1 shows the layout of a pattern for defining a stop layer. [Figure 3] 3 shows a flowchart outlining a process 300 in some examples. [Figure 4A] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4B] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4C] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4D]1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4E] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4F] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4G] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4H] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4I] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4J] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4K] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4L] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4M] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4N] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4O] 1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 4P]1A-1D illustrate cross-sectional views of an array die in a semiconductor device at various intermediate steps in wafer-level manufacturing, according to some embodiments. [Figure 5] 1 illustrates a block diagram of a memory system apparatus according to some examples of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature on or above a second feature in the following description can include embodiments in which the first and second features are formed in direct contact with each other, and can also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact with each other. Furthermore, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations described.

[0016] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to facilitate describing the relative relationship of one element or feature to another, as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0017] According to some aspects of the present disclosure, vertical device technology forms vertical structures on a wafer, such as channel structures, dummy channel structures, and gate line slit structures in three-dimensional (3D) NAND flash memory. In some examples, the vertical structures can be formed in openings, such as holes or trenches, etched into a layer on the first surface, also known as the front surface, of the wafer. The etching process for forming the holes or trenches can affect the uniformity of the hole depth. As the height of the vertical structures increases (e.g., to increase the number of memory cells in a vertical memory cell string), it becomes difficult to control the depth of the holes or trenches, which can lead to poor uniformity of the hole or trench depth. If the uniformity of the hole or trench depth is poor, the edges of the vertical structures will have poor depth uniformity, which can cause large variations in the electronic characteristics of the device. Some semiconductor technologies use front and back surface processing to form structures on both sides of the wafer. Poor depth uniformity at the edges of the vertical structures can make back surface processing difficult.

[0018] Some aspects of the present disclosure provide techniques for improving depth control and depth uniformity at the edges of vertical structures, thus increasing processing margins and facilitating backside processing.

[0019] According to some aspects of the present disclosure, a stop layer can be formed below the layer stack in areas where vertical structures are to be formed. The vertical structures can be formed by etching holes or trenches in the layer stack and filling the holes or trenches with material for the vertical structures. The etching of the holes or trenches can be stopped at the stop layer. The etch characteristics of the stop layer can be used to control the depth of the edges of the vertical structures. In some examples using backside processing, the stop layer can be removed by backside processing and replaced with another layer that is functional but may have poorer etch characteristics than the stop layer.

[0020] For example, in three-dimensional (3D) NAND flash memory technology, a channel structure is formed in a layer stack with the channel structure terminating in a semiconductor layer. The semiconductor layer, in some examples, can be used to form an array common source. However, the etching characteristics of the semiconductor layer can result in poor depth control or poor uniformity during the etching process to form a hole in the layer stack for the channel structure. In some examples, a stop layer having better etching characteristics than the semiconductor layer, such as better etching selectivity to the layer stack than the semiconductor layer, can be formed below the layer stack. In one example, the semiconductor layer is a polysilicon layer, and the stop layer includes tungsten. Note that other suitable materials having better etching selectivity to the layer stack than the polysilicon layer can be used for the stop layer. The hole can be etched through the layer stack and terminate in the stop layer with better depth control and better depth uniformity. After the channel structure is formed, the stop layer can be replaced with a semiconductor layer using backside processing.

[0021] 1A-1B illustrate cross-sectional views of a semiconductor device 100 according to some embodiments of the present disclosure. Figure 1A illustrates a cross-sectional view of the semiconductor device 100 shown in Figure 1B along line A'A, and Figure 1B illustrates a cross-sectional view of the semiconductor device 100 shown in Figure 1A along line B'B. Note that for ease of illustration, features are not drawn to scale.

[0022] 1A and 1B, the semiconductor device 100 includes a plurality of regions and vertical structures formed in the plurality of regions. Specifically, the semiconductor device 100 includes a core region 101 and a channel structure 130 formed in the core region 101. The semiconductor device 100 includes a staircase region 102 and a dummy channel structure 150 formed in the staircase region 102. The semiconductor device 100 includes a gate line slit region 103 and a gate line slit structure 140 formed in the gate line slit region 103.

[0023] According to some aspects of the present disclosure, at least one type of vertical structure can be formed by utilizing a stop layer to achieve depth control and better depth uniformity within the vertical structure, after which the stop layer is replaced by a functional layer. In one example, a stop layer is formed in the core region 101 to achieve depth control and better depth uniformity of the channel structure 130. In another example, a stop layer is formed in the staircase region 102 to achieve depth control and better depth uniformity in the dummy channel structure 150. In another example, a stop layer is formed in the gate line slit region 103 to achieve depth control and better depth uniformity of the gate line slit structure 140.

[0024] In some examples, the stop layer is formed in multiple regions to achieve depth control and better depth uniformity in multiple types of vertical structures. In one example, stop layers are formed in the core region 101, the staircase region 102, and the gate line slit region 103 to achieve depth control and better depth uniformity in the channel structure 130, the dummy channel structure 150, and the gate line slit structure 140, respectively. Note that the following description illustrates depth control and uniformity control techniques for examples using stop layers in the core region 101, the staircase region 102, and the gate line slit region 103, but the described techniques can be adapted for use in other examples.

[0025] While FIG. 1A illustrates that semiconductor device 100 includes one die, it should be noted that semiconductor device 100 may include additional dies not shown. In some examples, semiconductor device 100 includes a first die shown in FIG. 1A and a second die (not shown) bonded face-to-face (e.g., front-to-front). For example, the first die (shown in FIGS. 1A and 1B) includes a memory cell array formed on the front side and may be referred to as an array die. The second die (not shown) includes peripheral circuitry formed on the front side and may be referred to as a peripheral die. In some examples, the peripheral circuitry is formed using complementary metal-oxide-semiconductor (CMOS) technology, and the peripheral die is also referred to as a CMOS die.

[0026] It should be noted that in some other embodiments, the semiconductor device can include multiple array dies and CMOS dies. The multiple array dies and CMOS dies can be stacked and bonded together. The CMOS die can be coupled to each of the multiple array dies and drive each of the array dies.

[0027] The semiconductor device 100 can be a device of any appropriate scale, such as wafer scale, chip scale, or package scale. In some examples (e.g., wafer scale), the semiconductor device 100 includes at least a first wafer and a second wafer bonded face-to-face. The array die is disposed with other array dies on the first wafer, and the CMOS die is disposed with other CMOS dies on the second wafer. The first and second wafers are bonded together, such that the array die on the first wafer is bonded with the corresponding CMOS die on the second wafer. In some examples (e.g., chip scale), the semiconductor device 100 is a chip in which at least the array die and the CMOS die are bonded together. In one example, the chip is diced from the bonded wafers. In another example (e.g., package scale), the semiconductor device 100 is a semiconductor package including one or more semiconductor chips assembled on a package substrate.

[0028] FIG. 1A shows a channel structure 130 in the core region 101 , a gate line slit structure 140 in the gate line slit region 103 , a dummy channel structure 150 in the staircase region 102 , and a punch-through contact structure 160 in the punch-through region 104 .

[0029] The channel structure 130 includes a body portion 132 formed in the second layer stack 120 and an end portion 131 in the first layer stack 110. The first layer stack 110 includes a semiconductor layer 111 formed by replacing a stop layer (not shown) using backside processing. The second layer stack 120 includes alternating gate layers 123 and insulating layers 121 on the front side of the array die. The front side is opposite the back side.

[0030] In some embodiments, the channel structure 130 has a pillar shape extending in the Z direction perpendicular to the XY plane of the main surface. In one embodiment, the channel structure 130 is formed of a circular (or elliptical or polygonal) material in the XY plane and extends in the Z direction. The channel structure 130 includes, for example, functional layers such as a blocking insulating layer 133 (e.g., silicon oxide), a charge storage layer 134 (e.g., silicon nitride), a tunnel insulating layer 135 (e.g., silicon oxide), a semiconductor layer 136, and an insulating layer 137, each of which has a circular (or elliptical or polygonal) shape in the XY plane and extends in the Z direction. In one example, after the blocking insulating layer 133 (e.g., silicon oxide) is formed on the sidewall of the channel hole of the channel structure 130, the charge storage layer 134 (e.g., silicon nitride), the tunnel insulating layer 135, the semiconductor layer 136, and the insulating layer 137 are sequentially stacked on the sidewall. The semiconductor layer 136 can be any suitable semiconductor material, such as polysilicon or single-crystal silicon, and the semiconductor material can be undoped or can include p-type or n-type dopants. In some examples, the semiconductor material is an undoped intrinsic silicon material. However, in some examples, due to defects, the intrinsic silicon material can have a carrier density on the order of 10 cm. The insulating layer 137 can be formed of an insulating material, such as silicon oxide and / or silicon nitride, and / or can be formed as an air gap.

[0031] According to some embodiments of the present disclosure, the channel structure 130 and the second layer stack 120 together form a vertical memory cell string. For example, the semiconductor layer 136 corresponds to the channel portion of a transistor in the memory cell string, and the gate layer 123 corresponds to the gate of a transistor in the vertical memory cell string. Generally, a transistor has a gate that controls the channel, and a drain and a source on either side of the channel. For simplicity, in the example of FIG. 1A, the upper side of the channel of the transistor in FIG. 1A is referred to as the drain, and the lower side of the channel of the transistor in FIG. 1A is referred to as the source. Note that the drain and source can be switched under certain driving configurations. In the example of FIG. 1A, the semiconductor layer 136 corresponds to the connecting channel of the transistor. For a particular transistor, the drain of the particular transistor is connected to the source of the upper transistor above the particular transistor, and the source of the particular transistor is connected to the drain of the lower transistor below the particular transistor. This connects the transistors in the vertical memory cell string in series.

[0032] In the example of FIG. 1A , end portion 131 includes semiconductor layer 136 and insulating layer 137. In some examples, blocking insulating layer 133, charge storage layer 134, and tunnel insulating layer 135 of end portion 131 are removed by backside processing. In some examples, an initial end portion corresponding to end portion 131 also includes blocking insulating layer 133, charge storage layer 134, and tunnel insulating layer 135. The initial end portion is formed in an initial first layer stack having a stop layer (not shown) in core region 101. The stop layer can be removed by backside processing. The blocking insulating layer 133, charge storage layer 134, and tunnel insulating layer 135 of the initial end portion can be removed by backside processing. Also, semiconductor layer 111 can be formed by backside processing.

[0033] According to some embodiments of the present disclosure, the semiconductor layer 136 of the end portion 131 corresponds to a source terminal of a vertical memory cell string, and the semiconductor layer 111 in the first stack 110 is configured to connect the source terminal of the array of vertical memory cell strings to an array common source (ACS) terminal, as indicated by P2. In the example of FIG. 1A , the semiconductor layer 111 includes a bulk portion 112 and a liner portion 113 (e.g., a conformal portion). The liner portion 113 is in contact with the semiconductor layer 136. In one example, the liner portion 113 can be doped by ion implantation to achieve a desired doping profile. In another example, the semiconductor layer 111 includes only the bulk portion 112 in contact with the semiconductor layer 136. In some examples, the semiconductor layer 111 is a silicon material such as doped polysilicon (e.g., N-type doped silicon, P-type doped silicon).

[0034] In the example of FIGS. 1A-1B, gate line slit (GLS) structures 140 are formed in the second layer stack 120 and have end portions in the first layer stack 110. The GLS structures 140 can be used to facilitate replacement of a sacrificial layer with the gate layer 123 in gate-last processing. In some examples, the GLS structures 140 are formed by filling trenches with one or more dielectric materials. In some examples, the GLS structures 140 extend through the second layer stack 120, and the GLS structures 140 can divide the vertical memory cell strings (corresponding to the channel structures 130) into separate blocks. In some examples, the vertical memory cell string rings are configured to be erased block by block. Additionally, the number and arrangement of the channel structures 130 between the GLS structures 140 can vary.

[0035] The end portion of the GLS structure 140 is in the first layer stack 110. In some examples, the end portion of the GLS structure 140 is formed in the initial first layer stack with a stop layer (not shown) in the gate line slit region 103. The stop layer can be removed by backside processing. Also, the semiconductor layer 111 can be formed by backside processing.

[0036] It should be noted that in some examples (not shown), the GLS structure 140 can include a conductive material (not shown) and can be configured to function as an ACS terminal.

[0037] 1A, in the staircase region 102, the gate layers 123 and insulating layers 121 are arranged in a staircase format. For example, each staircase may include one or more pairs of insulating layers 121 and gate layers 123. The staircase region 102 is also filled with insulating material 163 and planarized with the other regions. Gate contact structures (not shown) may be disposed on the staircase and connected to the respective gate layers 123. The gate contact structures are used to connect drive circuitry to the respective gate layers 123 and control the stacked memory cells and select gates.

[0038] In the example of FIGS. 1A-1B, the dummy channel structure 150 is formed in the staircase region 102 and has an end portion within the first stack 110. The dummy channel structure 150 can prevent the second layer stack 120 from collapsing during the replacement of the sacrificial layer with the gate layer 123 in a gate-last process. The dummy channel structure 150 can include one or more dielectric materials. In one example, the dummy channel structure 150 can be disposed in the staircase region 102 between the GLS structures 140. In another example, one or more dummy channel structures 150 can be disposed in the core region 101.

[0039] An end portion of the dummy channel structure 150 is in the first layer stack 110. In some examples, the end portion of the dummy channel structure 150 is formed in an initial first layer stack having a stop layer (not shown) in the staircase region 102. The stop layer can be removed by backside processing. Also, the semiconductor layer 111 can be formed by backside processing.

[0040] 1A-1B, punch-through contact structures 160 are formed in punch-through region 104. In the example of FIG. 1A, punch-through region 104 is filled with insulating material 163 and planarized with other regions. Punch-through contact structures 160 may extend from the front surface of the array die to the back surface of the array die, conductively interconnecting conductive structures on the front surface of the array die with conductive structures on the back surface of the array die.

[0041] In one example, the punch-through contact structure 160 extends through the cap layer 125, the insulating layer 163, and stops at the top etch stop layer 115. In some examples, the end of the punch-through contact structure 160 can abut a conductive layer 167, which is conductively connected to the pad structure P2. The conductive layer 167 can include one or more metallic materials, such as aluminum (Al), titanium (Ti), etc. The conductive layer 167 can be separated from the semiconductor layer 111 by a spacer layer 165, such as silicon oxide.

[0042] 2A-2C show layouts of patterns for defining a stop layer. Figure 2A shows a pattern 201 that can be used to form a stop layer in the core region 101 to achieve depth control and better depth uniformity of the channel structure 130.

[0043] FIG. 2B shows a pattern 203 that can be used to form a stop layer in the gate line slit region 103 to achieve depth control and better depth uniformity of the gate line slit structure 140.

[0044] FIG. 2C shows a pattern 202 that can be used to form a stop layer in the staircase region 102 to achieve depth control and better depth uniformity of the dummy channel structures 150.

[0045] In some instances, the stop layer is not patterned and no additional layout or mask is required.

[0046] 3 shows a flowchart outlining some example processes 300. Process 300 can be used to form semiconductor devices such as semiconductor device 100. Process begins at S301 and proceeds to S310.

[0047] In S310, processing of the first side of the wafer forms vertical structures in the layer stack, with edges of the vertical structures in a first layer that has a better etch selectivity to the layer stack than a second layer.

[0048] In the example of FIGS. 1A-1B, the initial first layer stack corresponding to the first stack 110 can include a stop layer that has a better etch selectivity to the upper layers of the initial first layer stack than the polysilicon layer. In one example, the stop layer includes tungsten (W). In the example of FIGS. 1A-1B, in the core region 101, the upper layers of the initial first layer stack can include alternating silicon oxide and silicon nitride layers, with tungsten having a better etch selectivity to the upper layers of the initial first stack than the polysilicon layer. A channel hole for the channel structure 130 is etched through the upper layers of the initial first stack, stopping at the stop layer. The channel structure 130 is formed in the channel hole that terminates in the stop layer in the core region 101.

[0049] In the staircase region 102, the upper layers of the initial first layer stack can include a subset of alternating silicon oxide and silicon nitride layers and additional insulating material 163, with tungsten having a better etch selectivity to the upper layers of the initial first stack than to the polysilicon layer. A dummy channel hole for the dummy channel structure 150 is etched through the upper layers of the initial first stack, stopping at the stop layer. The dummy channel structure 150 is formed in the dummy channel hole having an end in the stop layer in the staircase region 102.

[0050] In the gate line slit region 103, the upper layers of the initial first layer stack can include alternating silicon oxide and silicon nitride layers, with tungsten having a better etch selectivity to the upper layers of the initial first stack than to the polysilicon layers. The trenches of the gate line slit structures 140 are etched through the upper layers of the initial first stack, stopping at the stop layer. The gate line slit structures 140 are formed in the trenches whose ends are in the stop layer.

[0051] In S320, the first layer is replaced with a second layer by processing a second side of the wafer opposite the first side. In the example of FIGS. 1A-1B, backside processing is performed to remove several layers from the backside of the wafer, such as the substrate, oxide layer, stop layer, blocking insulating layer 133 at the end of channel structure 130, charge storage layer 134 at the end of channel structure 130, and tunnel insulating layer 135 at the end of channel structure 130. A semiconductor layer 111, such as a polysilicon layer, can then be formed on the backside of the wafer. In some examples, a through-silicon contact structure can be formed to conductively connect with punch-through contact structure 160.

[0052] Processing can continue until the end of the manufacturing process.

[0053] 4A-4P are cross-sectional views of an array die within a semiconductor device, such as an array die within semiconductor device 100, at various intermediate steps in wafer-level manufacturing according to some embodiments of the present disclosure.

[0054] 4A shows a cross-sectional view of semiconductor device 100 after depositing an initial first layer stack 110′ on substrate 171. In the example of FIG. 4A, initial first layer stack 110′ includes a first oxide layer 173, a stop layer 175, a second oxide layer 177, a top etch stop layer 115, and a third oxide layer 179, which are sequentially deposited on substrate 171. In one example, stop layer 175 includes tungsten and has a thickness to ensure that etching of channel holes to form channel structures, etching of dummy channel holes to form dummy channel structures, and etching of trenches to form gate line slit structures can be stopped within stop layer 175.

[0055] FIG. 4B shows a cross-sectional view of the semiconductor device 100 after a channel hole 183 for forming a channel structure has been etched through the initial second layer stack 120′. The etching of the channel hole 183 stops at the stop layer 175. For example, the initial second layer stack 120′ is formed on top of the initial first layer stack 110′. The initial second layer stack 120′ may include insulating layers 121 (e.g., silicon oxide) and sacrificial gate layers 122 (e.g., silicon nitride) alternately stacked in the Z direction. Next, a pattern of the channel hole is defined in a photoresist and / or hard mask layer using photolithography techniques, and the pattern is transferred to the initial second layer stack 120′ and the initial first layer stack 110′ using etching techniques, with the etching stopping at the stop layer 175. The stopping layer 175 has a relatively high etching selectivity with respect to the insulating layer 121 and the sacrificial gate layer 122, allowing for good control of the depth of the channel hole 183 in the stopping layer 175, and the channel hole 183 can have a relatively uniform depth.

[0056] 4C shows a cross-sectional view of the semiconductor device 100 after the channel structure 130 is formed. In one example, after a blocking insulating layer 133 (e.g., silicon dioxide) is formed on the sidewall of the channel hole, a charge storage layer 134 (e.g., silicon nitride), a tunnel insulating layer 135, a semiconductor layer 136, and an insulating layer 137 are sequentially stacked from the sidewall.

[0057] It should be noted that the channel structure 130 is not limited to a single-deck configuration as shown in FIG. 4C. In some examples (not shown), the channel structure 130 is formed using a multi-deck technique. For example, the channel structure 130 includes a lower channel structure in a lower deck and an upper channel structure in an upper deck. The lower and upper channel structures are suitably joined to form the channel structure 130.

[0058] 4D shows a cross-sectional view of the semiconductor device 100 after dummy channel holes 185 to form dummy channel structures have been etched through the layers in the staircase region. In some examples, the staircase region is appropriately formed with steps, filled with insulating material 163 (e.g., silicon oxide), and appropriately planarized. Photolithography techniques are then used to define a pattern for the dummy channel holes in a photoresist and / or hard mask layer, and etching techniques are used to transfer the pattern to the layers in the staircase region and to the etch stop in the stop layer 175. The stop layer 175 has a relatively high etch selectivity to the insulating material 163, the insulating layer 121, and the sacrificial gate layer 122, allowing for sufficient control over the depth of the dummy channel holes in the stop layer 175, and the dummy channel holes can have a relatively uniform depth.

[0059] 4E shows a cross-sectional view of semiconductor device 100 after dummy channel structures 150 have been formed. In some examples, one or more insulating layers are formed within the dummy channel holes. In one example, one or more insulating layers are deposited, and excess insulating material in areas outside the dummy channel holes can be removed, for example, by chemical mechanical polishing (CMP) and / or etching processes.

[0060] FIG. 4F shows a cross-sectional view of semiconductor device 100 after trenches 184 have been etched through layers in the gate line slit region to form gate line slit structures. The trenches 184 are also referred to as gate line slits or gate line cuts. In some examples, photolithography techniques are used to define a trench pattern in a photoresist and / or hard mask layer, and etching techniques are used to transfer the pattern to the initial second layer stack 120′ and the initial first layer stack 110′, with the etching stopping at stop layer 175. Stop layer 175 has a relatively high etch selectivity with respect to insulating layer 121 and sacrificial gate layer 122, allowing for good control of the depth of the trenches in stop layer 175 and allowing the trenches to have a relatively uniform depth.

[0061] FIG. 4G shows a cross-sectional view of the semiconductor device 100 after forming the gate-line slit structures 140 in the gate-line slit region 103.

[0062] In some examples, the trench can be used to replace the sacrificial gate layer 122 with the gate layer 123. In one example, an etchant is applied to the sacrificial gate layer 122 through the trench to remove the sacrificial gate layer. In one example, the sacrificial gate layer is made of silicon nitride, and hot sulfuric acid (H2SO4) is applied through the trench to remove the sacrificial gate layer. Further, a gate stack to the transistor in the array region is formed through the trench. In one example, the gate stack is formed from a high-k dielectric layer, an adhesive layer, and a metal layer. The high-k layer can include any suitable material that provides a relatively large dielectric constant, such as hafnium oxide (HfO), hafnium silicon dioxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (AlO), lanthanum oxide (LaO), tantalum oxide (TaO), yttrium oxide (YO), zirconium oxide (ZrO), strontium titanate oxide (SrTiO), zirconium silicon dioxide (ZrSiO), hafnium zirconium oxide (HfZrO), etc. The adhesion layer can include refractory metals such as titanium (Ti) and tantalum (Ta), and their nitrides such as TiN, TaN, WN, TiSiN, and TaSiN. The metal layer can include highly conductive metals such as tungsten (W) and copper (Cu).

[0063] The trenches can then be filled to form gate line slit structures 140. In some examples, one or more insulating layers are formed within the trenches. In one example, one or more insulating layers are deposited, and excess insulating material in areas outside the trenches can be removed, for example, by CMP and / or etching processes. In some examples, an array common source terminal can be formed within the gate line slit structures 140 using a conductive material such as tungsten.

[0064] 4H shows a cross-sectional view of semiconductor device 100 after punch-through holes 186 have been etched through layers in the punch-through region to form punch-through contact structures. For example, cap layer 125 is deposited and planarized. Further, photolithography techniques can be used to define a pattern for the punch-through holes in a photoresist and / or hard mask layer, and etching techniques can be used to transfer the pattern into cap layer 125 and insulating material 163, with etching stopping at top etch-stop layer 115. Note that etching can stop at other suitable layers. In some examples, punch-through holes 186 are formed simultaneously and by the same processing steps as other contact holes (not shown), such as word line contact holes, bit line contact holes, etc.

[0065] 4I shows a cross-sectional view of semiconductor device 100 after punch-through contact structures 160 have been formed in the punch-through holes. For example, a suitable liner layer (e.g., titanium / titanium nitride) and a metal layer (e.g., tungsten) can be filled into the punch-through holes to form the punch-through contact structures. In some examples, the punch-through contact structures are formed simultaneously and by the same processing steps with other contact structures, such as word line contact structures (also referred to as gate contact structures in some examples), bit line contact structures, etc.

[0066] In some embodiments, a bonding structure (not shown) is then formed on the front side of the array die. The array die is then bonded to an opposing CMOS die (not shown). Backside processing can then be performed on the array die.

[0067] 4J shows a cross-sectional view of semiconductor device 100 after stop layer 175 has been removed by backside processing. In some examples, substrate 171 is removed by a backside process, such as applying a CMP process and / or an etching process to the backside of the array die. Oxide layer 173 is then removed by a backside process, such as applying a CMP process and / or an etching process on the backside of the array die. Stop layer 175 is then removed by a backside process, such as applying a CMP process and / or an etching process on the backside of the array die.

[0068] This allows the ends of the channel structure 130, the gate line slit structure 140 and the dummy channel structure 150 to be exposed from the back surface of the array die.

[0069] 4K shows a cross-sectional view of semiconductor device 100 after the blocking insulating layer, charge storage layer, and tunnel insulating layer have been removed from the end of channel structure 130 by backside processing, including removing second oxide layer 177.

[0070] FIG. 4L shows a cross-sectional view of the semiconductor device 100 after the semiconductor layer 111 has been formed by backside processing. In some examples, the semiconductor layer 111 includes a bulk portion 112 and a liner portion 113 (e.g., a conformal portion). The liner portion 113 can be formed, for example, by atomic layer deposition and doped by ion implantation. The bulk portion 112 can then be formed, for example, by chemical vapor deposition (CVD) and planarized by CMP. The bulk portion 112 can be doped in situ during CVD or by ion implantation after CVD. A post-annealing step, such as laser annealing, can be performed to activate dopants and / or repair crystalline damage. In some examples, the semiconductor layer 111 includes only the bulk portion 112.

[0071] FIG. 4M shows a cross-sectional view of semiconductor device 100 after silicon through holes 187 have been formed in semiconductor layer 111 to expose the ends of punch-through contact structures 160 from the backside of the array die.

[0072] FIG. 4N shows a cross-sectional view of semiconductor device 100 after spacer layer 165 has been formed from the backside of the array die.

[0073] 4O shows a cross-sectional view of semiconductor device 100 after portions of spacer layer 165 have been removed. For example, spacer layer 165 is removed from the bottom of silicon through-hole 187 to expose punch-through contact structure 160. Note that a portion of spacer layer 165 above semiconductor layer 111 is removed to form opening 188.

[0074] 4P shows a cross-sectional view of semiconductor device 100 after a conductive layer 167 has been formed on the backside of the array die and patterned into pad structures, for example, as indicated by P1 and P2. In some examples, conductive layer 167 includes aluminum.

[0075] The semiconductor device 100 can be suitably used in a memory system.

[0076] 5 shows a block diagram of a memory system apparatus 500 according to some examples of the present disclosure. The memory system apparatus 500 includes one or more semiconductor memory devices, as shown by semiconductor memory devices 511-514, each configured similarly to the semiconductor device 100. In some examples, the memory system apparatus 500 is a solid-state drive (SSD).

[0077] The memory system apparatus 500 may include other suitable components. For example, the memory system apparatus 500 may include an interface 501 and a master controller 502 coupled to each other as shown in FIG. 5. The memory system apparatus 500 may include a bus 520 coupling the master controller 502 to the semiconductor memory devices 511-514. Furthermore, the master controller 502 is connected to each of the semiconductor memory devices 511-514 as indicated by respective control lines 521-524.

[0078] The interface 501 is mechanically and electrically configured appropriately to connect between the memory system device 500 and a host device, and the interface 501 can be used to transfer data between the memory system device 500 and the host device.

[0079] The master controller 502 is configured to connect each of the semiconductor memory devices 511-514 to the interface 501 for data transfer. For example, the master controller 502 is configured to provide enable / disable signals to the semiconductor memory devices 511-514, respectively, to activate one or more of the semiconductor memory devices 511-514 for data transfer.

[0080] The master controller 502 is responsible for completing various commands within the memory system device 500. For example, the master controller 502 may perform bad block management, error checking and correction, garbage collection, and the like.

[0081] The foregoing outlines some example features to enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages as the examples introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

[0082] The foregoing outlines features of some embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. 1. A method of semiconductor device manufacturing, comprising: processing a first surface of the first die to form a plurality of holes and / or trenches in the layer stack having ends in the first layer and filling the holes and / or trenches with a material to form a plurality of vertical structures; and replacing the first layer with a second layer by processing a second surface of the first die opposite the first surface, wherein a material of the first layer has a better etch selectivity to the layer stack than a material of the second layer; The etching selectivity indicates that the material is difficult to etch, the material of the first layer is tungsten, and the material of the second layer is polysilicon, different from the material of the first layer; The method comprises: processing the first surface of the first die to form a punch-through contact structure in a punch-through region; further comprising the layer stack includes an initial first layer stack and an initial second layer stack stacked on top of the initial first layer stack; the punch-through contact structure is not formed on the first second layer stack side of a boundary between the first layer stack and the first second layer stack; the vertical structure includes a channel structure, and the initial first layer stack includes the first layer in a core region; the second layer includes a semiconductor layer; replacing the first layer with the second layer; processing the second surface to form the semiconductor layer in contact with a channel layer of the channel structure at an end of the channel structure; further comprising the semiconductor layer includes a liner portion and a bulk portion; forming the semiconductor layer in contact with the channel layer, forming the liner portion in contact with the channel layer at the end of the channel structure in the semiconductor layer; performing ion implantation to dope the liner portion; forming the bulk portion of the semiconductor layer; further comprising The method comprises: forming a pad structure on the second surface that is conductively connected to the semiconductor layer; further comprising the channel structure is not directly connected to the pad structure but is connected via the bulk portion; a surface of the bulk portion opposite the first die is flat; A method for semiconductor device fabrication.

2. the layer stack includes a first second layer stack; The method comprises: forming the initial second stack of layers on top of the initial first stack of layers, the second stack of layers including alternating insulating layers and sacrificial gate layers; The method of claim 1 further comprising:

3. forming a channel hole in the initial second layer stack having an end in the first layer; forming the channel structure in the channel hole; The method of claim 2 further comprising:

4. The method of claim 3 , wherein the channel structure comprises the channel layer encased in a blocking insulating layer, a charge storage layer, and a tunnel insulating layer.

5. replacing the first layer with the second layer; treating the second surface to remove the first layer; treating the second surface to remove the blocking insulating layer, the charge storage layer, and the tunnel insulating layer from the end of the channel structure; The method of claim 4 further comprising:

6. replacing the first layer with the second layer; forming the second layer in contact with the channel layer at the end of the channel structure; The method of claim 5 further comprising:

7. The method of claim 1 , wherein the vertical structure includes a dummy channel structure and the initial first layer stack includes the first layer in a staircase region.

8. The method according to claim 7, forming the initial second stack of layers on top of the initial first stack of layers, the second stack of layers including alternating insulating layers and sacrificial gate layers; forming a staircase based on the initial second layer stack within the staircase region; planarizing the step region with an insulating material; The method of claim 7 further comprising:

9. forming a dummy channel hole in the insulating material and the initial second layer stack, the dummy channel hole having an end in the first layer; forming the dummy channel structure in the dummy channel hole; The method of claim 8 further comprising:

10. 2. The method of claim 1, wherein the vertical structure comprises a gate line slit structure, and the initial first layer stack comprises the first layer in a gate line slit region.

11. The method comprising: forming the initial second stack of layers on top of the initial first stack of layers, the second stack of layers including alternating insulating layers and sacrificial gate layers; The method of claim 10 further comprising:

12. forming the channel structure in the initial second layer stack; forming a trench in the initial second layer stack having an end in the first layer; replacing the sacrificial gate layer with a gate layer through the trench; forming the gate line slit structure in the trench; The method of claim 11 further comprising:

13. forming a bonding structure on the first surface of the first die; bonding the first surface of the first die to a second die prior to processing the second surface of the first die; The method of claim 1 further comprising:

14. 14. The method of claim 13, further comprising processing the second side of the first die to form a through silicon contact, the through silicon contact connecting the punch-through contact structure with a pad structure on the second side of the first die.

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