Semiconductor element manufacturing method

Abstract

To provide a light emitter having a base semiconductor portion including a nitride semiconductor and a compound semiconductor portion including a nitride semiconductor, which can improve light emission efficiency and reliability.SOLUTION: A light emitter includes a base semiconductor portion 8 including a nitride semiconductor, a compound semiconductor portion 9 including a nitride semiconductor and located above the base semiconductor portion, a first electrode E1 and a second electrode E2, the base semiconductor portion has a first portion and a second portion in which the density of threading dislocations extending in the thickness direction is lower than that of the first portion, at least a portion of the first electrode and at least a portion of the second electrode are located on the compound semiconductor portion, and at least a portion of the first electrode is located above the second portion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] In the nitride semiconductor laser described in Patent Document 1, an anode and a cathode are formed on one side of a chip including a semiconductor layer. If the current path from the anode to the cathode includes a portion parallel to the c-plane of the semiconductor layer, the light emission efficiency decreases. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2000-49415 Summary of the Invention

[0004] The light emitter according to the present disclosure comprises a base semiconductor portion including a nitride semiconductor, a compound semiconductor portion including a nitride semiconductor and located above the base semiconductor portion, a first electrode, and a second electrode, wherein the base semiconductor portion has a first portion and a second portion in which the density of threading dislocations extending in the thickness direction is lower than that of the first portion, and at least a portion of the first electrode and at least a portion of the second electrode are located on the compound semiconductor portion, and at least a portion of the first electrode is located above the second portion. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 2 is a perspective view showing the configuration of the light emitter according to the embodiment. [Figure 2] 1 is a schematic diagram illustrating a configuration of a light-emitting device according to an embodiment of the present invention. [Figure 3] 1 is a flowchart showing an example of a method for manufacturing a light-emitting body according to the present embodiment. [Figure 4] 1 is a block diagram showing an example of a manufacturing apparatus for a light-emitting body according to an embodiment of the present invention. [Figure 5] 1 is a perspective view showing the configuration of a light emitter according to Example 1. FIG. [Figure 6] FIG. 2 is a plan view showing the configuration of a compound semiconductor portion. [Figure 7] 1 is a cross-sectional view showing the configuration of a light emitter according to Example 1. FIG. [Figure 8] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 9] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 10] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 11] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 12] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 13] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 14] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 15] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 16] FIG. 2 is a perspective view showing another configuration of the light emitter of Example 1. [Figure 17] 17A and 17B are top and cross-sectional views of FIG. 16. [Figure 18] FIG. 2 is a perspective view showing another configuration of the light emitter of Example 1. [Figure 19] 19A and 19B are top and cross-sectional views of FIG. 18. [Figure 20] 1 is a cross-sectional view showing the configuration of a light-emitting element according to Example 1. FIG. [Figure 21] 1 is a perspective view showing the configuration of a light emitting element according to Example 1. FIG. [Figure 22] 4 is a cross-sectional view showing another configuration of the light-emitting device according to Example 1. FIG. [Figure 23] 4 is a cross-sectional view showing another configuration of the light-emitting device according to Example 1. FIG. [Figure 24] 4 is a cross-sectional view showing another configuration of the light-emitting device according to Example 1. FIG. [Figure 25]1 is a perspective view showing a configuration of a light emitting substrate (semiconductor laser array) according to Example 1. FIG. [Figure 26] FIG. 4 is a perspective view showing another configuration of the light emitting substrate according to the first embodiment. [Figure 27] 3 is a flowchart showing an example of a method for manufacturing a light-emitting device according to the first embodiment. [Figure 28] 28A to 28D are schematic cross-sectional views showing a method for manufacturing the light-emitting device of FIG. 27. [Figure 29] 28A to 28C are plan views illustrating a method for manufacturing the light-emitting device of FIG. 27. [Figure 30] 5 is a schematic cross-sectional view showing another example of the method for manufacturing the light-emitting device according to Example 1. FIG. [Figure 31] 5 is a schematic cross-sectional view showing another example of the method for manufacturing the light-emitting device according to Example 1. FIG. [Figure 32] 3 is a cross-sectional view showing an example of lateral growth of a base semiconductor portion (ELO semiconductor layer) in Example 1. FIG. [Figure 33] FIG. 10 is a cross-sectional view showing the configuration of a light emitter according to Example 2. [Figure 34] FIG. 10 is a perspective view showing the configuration of a light-emitting module according to a fourth embodiment. [Figure 35] FIG. 10 is a perspective view showing another configuration of the light emitting module of the fourth embodiment. [Figure 36] FIG. 10 is a schematic diagram illustrating a configuration of an electronic device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] [Light-emitting body] FIG. 1 is a perspective view showing the configuration of a light emitter according to this embodiment. As shown in FIG. 1, the light emitter 21 according to this embodiment includes a base semiconductor portion 8 containing a nitride semiconductor, a compound semiconductor portion 9 containing a nitride semiconductor and located above the base semiconductor portion 8, a first electrode E1, and a second electrode E2. The base semiconductor portion 8 has a first portion B1 and a second portion B2 in which the density of threading dislocations extending in the thickness direction (Z direction) is lower than that of the first portion B1. At least a portion of the first electrode E1 and at least a portion of the second electrode E2 are located on the compound semiconductor portion 9. At least a portion of the first electrode E1 may be located above the second portion B2. Hereinafter, the direction from the base semiconductor portion 8 to the compound semiconductor portion 9 is referred to as the upward direction. In the light emitter 21, the base semiconductor portion 8 may be a base semiconductor layer 8, and the compound semiconductor portion 9 may be a compound semiconductor layer 9. The light emitter 21 may be a light-emitting diode (LED) chip or a semiconductor laser chip.

[0007] The base semiconductor portion 8 of the light emitter 21 includes the second portion B2 (low-defect portion) with a low density of threading dislocations, which can improve the light-emitting efficiency and reliability in a configuration in which the first and second electrodes E1 and E2 are provided on one side of the chip, because threading dislocations cause heat generation.

[0008] In this embodiment, the second portion B2 of the base semiconductor portion 8 and the first electrode E1 may overlap in a plan view. "Two members overlap" means that at least a portion of one member overlaps the other member in a plan view (including a perspective plan view) seen in the thickness direction of each member, and these members may or may not be in contact with each other.

[0009] The nitride semiconductor included in the base semiconductor portion 8 and the compound semiconductor portion 9 can be expressed as, for example, AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The base semiconductor portion 8 may be doped (e.g., n-type containing donors) or undoped.

[0010] The base semiconductor portion 8 including a nitride semiconductor can be formed by ELO (Epitaxial Lateral Overgrowth). In the ELO method, for example, the base semiconductor portion 8 is grown laterally on a template substrate having a mask pattern (selective growth mask) including openings and mask portions (described later). In this way, a low-defect portion (second portion B2) with a low threading dislocation density can be formed on the mask portion. Since the number of threading dislocations (dislocations extending in the thickness direction) inherited by the compound semiconductor portion 9 (e.g., a GaN-based semiconductor layer) on the second portion B2 is reduced, the light-emitting efficiency can be improved.

[0011] [Light-emitting devices] 2 is a schematic diagram showing the configuration of a light emitting device according to this embodiment. The light emitting substrate 22 according to this embodiment includes a plurality of light emitting bodies 21 (chips) and a support substrate SK on which the plurality of light emitting bodies 21 are mounted. The light emitting element 23 according to this embodiment includes one or more light emitting bodies 21 and a support body ST on which the one or more light emitting bodies 21 are mounted. Hereinafter, the light emitting bodies 21, the light emitting substrate 22, the light emitting element 23, and a light emitting module described below may be collectively referred to as a light emitting device.

[0012] [Production of luminous body] Fig. 3 is a flowchart showing an example of a method for manufacturing a light-emitting device according to this embodiment. In the manufacturing method shown in Fig. 3, after a step of preparing a template substrate (substrate for ELO growth), a step of forming a base semiconductor portion 8 using the ELO method, a step of forming a compound semiconductor portion 9, and a step of forming first and second electrodes E1 and E2 are performed.

[0013] 4 is a block diagram showing an example of an apparatus for manufacturing a light-emitting body according to this embodiment. The apparatus 70 for manufacturing a light-emitting body shown in FIG. 4 includes a semiconductor forming unit 72 that forms a base semiconductor portion 8 and a compound semiconductor portion 9 on a template substrate, an electrode forming unit 73 that forms first and second electrodes E1 and E2, and a control unit 74 that controls the semiconductor forming unit 72 and the electrode forming unit 73.

[0014] The semiconductor forming unit 72 may include an MOCVD (Metal Organic Chemical Vapor Deposition) device, and the control unit 74 may include a processor and a memory. The control unit 74 may be configured to control the semiconductor forming unit 72 and the electrode forming unit 73 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network. The above program and a recording medium on which the above program is stored are also included in this embodiment.

[0015] Example 1 (composition) FIG. 5 is a perspective view showing the configuration of the light emitter according to Example 1. FIG. 6 is a plan view showing the configuration of the compound semiconductor section. FIG. 7 is a cross-sectional view showing the configuration of the light emitter according to Example 1. As shown in FIGS. 5 to 7, the light emitter 21 according to Example 1 includes a base semiconductor section 8, a compound semiconductor section 9 located on the base semiconductor section 8, a first electrode E1 which is an anode, and a second electrode E2 which is a cathode. The light emitter 21 can also be called a semiconductor laser chip.

[0016] The base semiconductor portion 8 and the compound semiconductor portion 9 are nitride semiconductor layers (for example, GaN-based semiconductor layers), and the base semiconductor portion 8 is an n-type semiconductor layer having donors. In FIG. 5 and other figures, the <11-20> direction of the base semiconductor portion 8 is the X direction, the <1-100> direction is the Y direction, and <0001> The direction is the Z direction (thickness direction).

[0017] The base semiconductor portion 8 is a free-standing layer without a support material, and the upper surface of the base semiconductor portion 8 is in contact with the compound semiconductor portion 9, while the lower surface 8U of the base semiconductor portion 8 is exposed (the lower surface 8U is exposed on a chip-by-chip basis, but may not be exposed after mounting).

[0018] The base semiconductor portion 8 includes a first portion B1 including threading dislocations KD extending in the Z direction, and a second portion B2 and a third portion B3 having a threading dislocation density lower than that of the first portion B1. The second portion B2, the first portion B1, and the third portion B3 are arranged in this order in the X direction, and the first portion B1 is located between the second portion B2 and the third portion B3. The first portion B1 is a portion that was located above the opening of the mask layer 6 when the base semiconductor portion 8 was formed by the ELO method (described later). The threading dislocation densities of the second portion B2 and the third portion B3 are 1 / 5 or less (for example, 5×10) of the threading dislocation density of the first portion B1. 6 / cm 2 (See below).

[0019] The compound semiconductor section 9 is formed by depositing, in this order, a first-type (n-type) semiconductor layer 9N having a donor, an active layer 9K, and a second-type (p-type) semiconductor layer 9P having an acceptor. The first-type semiconductor layer 9N is formed by depositing, in this order, a first contact layer 9A, a first cladding layer 9B, and a first optical guide layer 9C. The second-type semiconductor layer 9P is formed by depositing, in this order, an electron blocking layer 9D, a second optical guide layer 9E, a second cladding layer 9F, and a second contact layer 9G, and a first electrode E1 (anode) is formed on the second contact layer 9G.

[0020] The second electrode E2 is provided on the same side of the base semiconductor portion 8 as the first electrode E1. The second electrode E2 is in contact with the first contact layer 9A, and the first and second electrodes E1 and E2 do not have to overlap in a plan view. Specifically, a portion of the compound semiconductor portion 9 may be recessed down to the first contact layer 9A, and the second electrode E2 may be formed so as to contact the first contact layer 9A exposed in the recessed portion 9Q of the compound semiconductor portion 9. The first electrode E1 is located, for example, on the (0001) plane of the second-type semiconductor layer 9P (second contact layer 9G), and the second electrode E2 is located on the (0001) plane of the first-type semiconductor layer 9N (first contact layer 9A). Note that in Example 1, the region of the first contact layer 9A that contacts the second electrode E2 has the same thickness as the other regions, but the region of the first contact layer 9A that contacts the second electrode E2 may have a smaller thickness than the other regions. For example, a thin film portion having a smaller thickness than the surrounding area may be formed in the first contact layer 9A by digging out a portion of the first contact layer 9A, and the second electrode E2 (cathode) may be provided so as to be in contact with this thin film portion. The upper surface of the thin film portion (the surface in contact with the second electrode E2) may be the (0001) plane of the first contact layer 9A, which is, for example, a nitride semiconductor layer.

[0021] When the compound semiconductor portion 9 is recessed by etching or the like, the c-plane ((0001) plane) of the first contact layer 9A (e.g., an n-GaN layer) is exposed and the second electrode E2 (cathode) is brought into contact with the c-plane of the first contact layer 9A, thereby reducing the contact resistance (compared to contact with the -c-plane). Note that the c-plane is a gallium-polar plane, and the -c-plane is a nitrogen-polar plane.

[0022] In a plan view, the first electrode E1 and the second electrode E2 are aligned in the X direction (first direction). The first and second electrodes E1 and E2 are shaped such that their longitudinal direction is in the Y direction (second direction). The size WC of the second electrode E2 in the X direction may be smaller than the size W3 of the third portion B3 in the X direction. The size WC of the second electrode E2 in the X direction may be larger than the size of the first electrode E1 in the X direction.

[0023] 7, the first electrode E1 has a first region L1 in contact with the ridge portion RJ, and in plan view, the entire first region L1 may overlap with the second portion B2 (low-defect portion) of the base semiconductor portion 8. The size WR of the first region L1 in the X direction may be smaller than the size W2 of the second portion B2 in the X direction.

[0024] The compound semiconductor portion 9 has an optical resonator LK including a pair of resonator facets F1 and F2, and the resonator length K1, which is the distance between the pair of resonator facets F1 and F2, is 200 μm or less. The resonator length K1 may be 20 μm or more and 200 μm or less. Each of the resonator facets F1 and F2 is an m-plane of the compound semiconductor portion 9 and is included in a cleavage plane of the compound semiconductor portion 9. That is, each of the resonator facets F1 and F2 can be formed by m-plane cleavage of the compound semiconductor portion 9, which is a nitride semiconductor layer (e.g., a GaN-based semiconductor layer). At least one of the base semiconductor portion 8 and the compound semiconductor portion 9 may have scribe marks (marks of cleavage start points) for cleavage. The resonator facets F1 and F2 can also be formed by etching.

[0025] Each of the cavity facets F1 and F2 is covered with a reflector film UF (e.g., a dielectric film), and the optical reflectivity of the cavity facet F1 on the light-emitting surface side is, for example, 50% or higher. The optical reflectivity of the cavity facet F2 on the light-reflecting surface side is higher than that of the cavity facet F1. Although not shown in FIGS. 5 and 7, the reflector film UF can be formed on the entire cleavage planes (m-planes) of the base semiconductor portion 8 and the compound semiconductor portion 9.

[0026] The first electrode E1 overlaps the optical resonator LK in plan view and also overlaps the second portion B2 of the base semiconductor portion 8. The length of the first and second electrodes E1 and E2 in the Y direction may be shorter than the resonant length K1. In this way, the first and second electrodes E1 and E2 do not interfere with cleavage of the compound semiconductor portion 9.

[0027] The optical resonator LK includes a portion (portion overlapping with the first electrode E1 in plan view) of each of the first-type semiconductor layer 9N, the active layer 9K, and the second-type semiconductor layer 9P. For example, the optical resonator LK includes a portion (portion overlapping with the first electrode E1 in plan view) of each of the first cladding layer 9B, the first optical guide layer 9C, the active layer 9K, the second optical guide layer 9E, and the second cladding layer 9F.

[0028] In the optical resonator LK, the refractive index (optical refractive index) decreases in the order of the active layer 9K, the first optical guide layer 9C, and the first cladding layer 9B, and also decreases in the order of the active layer 9K, the second optical guide layer 9E, and the second cladding layer 9F. Therefore, light generated by the combination of holes supplied from the first electrode E1 and electrons supplied from the second electrode E2 in the active layer 9K is confined within the optical resonator LK (particularly the active layer 9K), and laser oscillation occurs due to stimulated emission and feedback in the active layer 9K. The laser light generated by laser oscillation is emitted from a light emission region EA of the resonator end facet F1 on the emission surface side.

[0029] Because the cavity facets F1 and F2 are formed by m-plane cleavage, they have excellent flatness and perpendicularity to the c-plane (parallelism of the cavity facets F1 and F2), resulting in high optical reflectivity. This reduces mirror loss, enabling stable laser oscillation even with a short cavity length of 200 μm or less, where it is difficult to reduce mirror loss. Because the cavity facets F1 and F2 are formed on the second portion B2, which is a low-dislocation region, the cleavage facets have excellent flatness, resulting in high optical reflectivity.

[0030] The compound semiconductor section 9 includes a ridge section (current confinement section) RJ that overlaps with the first electrode E1 in a planar view, and the ridge section RJ includes the second cladding layer 9F and a portion of the second optical guide layer 9E (portions that overlap with the first electrode E1 in a planar view). Insulating films DF are provided on both sides of the ridge section RJ. The refractive index of the insulating films DF may be smaller than the refractive indexes of the second optical guide layer 9E and the second cladding layer 9F. By providing the ridge section RJ and the insulating films DF, the current path between the first electrode E1 and the first-type semiconductor layer 9N is confined on the anode side, allowing efficient light emission within the resonator LK.

[0031] In plan view, the entire ridge portion RJ overlaps with the second portion B2 (low dislocation portion) of the base semiconductor portion 8 (the ridge portion RJ does not overlap with the first portion B1). In this way, the current path from the first electrode E1 through the active layer 9K to the first-type semiconductor layer 9N is formed in the portion (low dislocation portion) that overlaps with the second portion B2 in plan view, thereby improving the light emission efficiency of the active layer 9K. This is because threading dislocations hinder the movement of charges, resulting in a decrease in light emission efficiency.

[0032] In the first embodiment, the sum T1 of the thickness of the base semiconductor portion 8 and the thickness of the compound semiconductor portion 9 can be set to 50 μm or less. If this sum T1 of the thicknesses is too large, it becomes difficult to cleave the semiconductor so that the resonance length is 200 μm or less.

[0033] The base semiconductor portion 8 may include a base end facet (a cleavage plane of the base semiconductor portion 8) that is flush with the cavity end facet F1, and the density of dislocations in the base end facet (dislocations measured by CL on the cleavage plane, primarily basal plane dislocations) may be equal to or greater than the threading dislocation density in the second portion B2. Furthermore, the surface roughness of at least one of the pair of cavity end faces F1 and F2 (for example, the cavity end face F2 on the reflecting surface side) may be smaller than the surface roughness of the side face 9S (see FIG. 6 ), which is the a-plane of the compound semiconductor portion 9. The a-plane is the (11-20) plane of the compound semiconductor portion 9, which is a nitride semiconductor layer.

[0034] In Example 1, for example, 200 mW or less of power is supplied between the first and second electrodes E1 and E2, and a light emitter with low power consumption and low output can be realized due to the short resonance length of 200 μm or less. A configuration in which the first and second electrodes E1 and E2 are provided on one side of the chip generally has the disadvantage of a longer current path and higher electrical resistance, but this is hardly an issue in the case of a short resonance length (low output) such as in Example 1. Another advantage is that mounting (flip-chip mounting) on ​​a submount or the like can be easily performed.

[0035] The lower surface (rear surface) of the base semiconductor portion 8 may include a region 8C where the surface roughness is locally increased (a rough surface region where the surface is rougher than the surrounding area). The region 8C may have at least one of convex portions and concave portions. For example, a plurality of randomly shaped protrusions or a plurality of randomly shaped concave portions may be formed. The region 8C may be a region corresponding to the first portion B1 (for example, a central region). The region 8C may be formed so as not to overlap with the ridge portion RJ in a planar view. The region 8C may improve heat dissipation. A dielectric film made of the same material as the reflector film UF may be formed on at least a portion of the region 8C.

[0036] Fig. 8 is a cross-sectional view showing another configuration of the light emitter of Example 1. As shown in Fig. 8, the first electrode E1 may have a region other than the first region L1 overlapping with the first portion B1 in plan view. Furthermore, the region other than the first region L1 may be located on the insulating film DF.

[0037] 9 and 10 are cross-sectional views showing other configurations of the light emitter of Example 1. As shown in Fig. 9 and 10, the second electrode E2 located in the recessed portion 9Q of the compound semiconductor portion may overlap with the first portion B1 of the base semiconductor portion 8 in plan view.

[0038] Fig. 11 is a cross-sectional view showing another configuration of the light emitter of Example 1. As shown in Fig. 11, the thickness of the second electrode E2 may be greater than the thickness of the first electrode E1, and the top surfaces of the first electrode E1 and the second electrode E2 may be flush with each other. The first electrode E1 and the second electrode E2 may be made of different conductive materials.

[0039] Fig. 12 is a cross-sectional view showing another configuration of the light emitter of Example 1. As shown in Fig. 12, the compound semiconductor portion 9 has a bank portion BK, and the ridge portion RJ and the bank portion BK are at the same upper surface level, and a part of the second electrode E2 may be located on the bank portion BK. In a plan view, the bank portion BK may overlap the first portion B1 of the base semiconductor portion 8. This makes it easier to mount (flip-chip mount) on a submount or the like. The structures (layer configuration) of the ridge portion RJ and the bank portion BK may be the same.

[0040] 12, the second electrode E2 may have a second region L2 located on the first-type semiconductor layer 9N and a third region L3 located on the second-type semiconductor layer 9P. The third region L3 may overlap with the first portion B1 of the base semiconductor portion 8 in a plan view.

[0041] Fig. 13 is a cross-sectional view showing another configuration of the light emitter of Example 1. As shown in Fig. 13, at least a part of the second electrode E2 may be located on the compound semiconductor portion 9, specifically, on the first-type (n-type) semiconductor layer 9N of the compound semiconductor portion 9.

[0042] FIG. 14 is a cross-sectional view showing another configuration of the light emitter of Example 1. As shown in FIG. 14, the entire second electrode E2 may overlap the first portion B1 in a plan view. Alternatively, a first-type semiconductor layer 9N, an active layer 9K, a second-type semiconductor layer 9P (including a ridge portion RJ), and a first electrode E1 may be provided above the second portion B2 and the third portion B3 of the base semiconductor portion 8, respectively. Providing ridge portions in both the second portion B2 and the third portion B3 in this manner increases the number of light emitters that can be obtained, reduces the distance between the light-emitting points of both emitters when fabricated on a single chip, increases the light integration density, simplifies optical design, and provides a measure against speckle noise due to the difference in wavelength between the two emitters.

[0043] FIG. 15 is a cross-sectional view showing another configuration of the light emitter of Example 1. As shown in FIG. 15, the first electrode E1 may be located on the semi-polar plane PJ of the second-type semiconductor layer 9P, and the second electrode E2 may be located on the semi-polar plane NJ of the first-type semiconductor layer 9N. A semi-polar plane is, for example, an r-plane that is oblique to the c-plane, which is a polar plane. The first and second electrodes E1 and E2 may also be provided on non-polar planes (a-plane, m-plane) that are perpendicular to the c-plane.

[0044] FIG. 16 is a perspective view showing another configuration of the light emitter of Example 1. FIG. 17 is a top view and a cross-sectional view of FIG. 16. In the example shown in FIGS. 16 and 17, the second electrode E2 has a second region L2 located on the first contact layer 9A and a third region L3 located on the second-type semiconductor layer 9P. This reduces the difference in upper surface level between the first electrode E1 and the third region L3, making mounting easier. In this case, the second electrode E2 may have a recess UB on its surface.

[0045] FIG. 18 is a perspective view showing another configuration of the light emitter of Example 1. FIG. 19 is a top view and a cross-sectional view of FIG. 18. In the example shown in FIGS. 18 and 19, the compound semiconductor portion 9 has a bank portion BK, and the ridge portion RJ and the bank portion BK are at the same top surface level. The second electrode E2 has a second region L2 located on the first contact layer 9A and a third region L3 located on the bank BK. This makes the top surface levels of the first electrode E1 and the third region L3 the same, facilitating mounting. In this case, the second electrode E2 has a recess UB on its surface.

[0046] Figure 18 shows a case where the second-type (p-type) semiconductor layer is removed only near the sides of the ridge during ridge formation. The second electrode E2 is larger than the first electrode E1, and the area of ​​the third region L3 in particular is large. The larger the area of ​​the third region L3 (the larger the bonding area), the stronger the bonding to the support substrate and the easier handling in subsequent processes. An insulating film (silicon oxide, silicon nitride, etc.) is present on the sides of the ridge portion RJ where the first electrode E1 contacts. However, the adhesive strength between metal and insulating film is generally weak, so electrode peeling may occur at that location during peeling from the growth substrate (described later). Therefore, it is better to increase the area of ​​the third region L3 (the area of ​​the second electrode E2 without an insulating film) rather than increasing the area of ​​the first electrode E1. The shape of the first electrode E1 or the second electrode E2 may be a shape that can be used for alignment during bonding (e.g., a shape with an alignment mark).

[0047] In the third region L3, the contact resistance between the second electrode E2, which is the cathode, and the second-type (p-type) semiconductor layer 9P is sufficiently high, so that no current flows and the two are not short-circuited.

[0048] 20 is a cross-sectional view showing the configuration of a light-emitting device according to Example 1. The light-emitting device 23 includes a light emitter 21 including a base semiconductor portion 8 and a compound semiconductor portion 9, and a support ST that holds the light emitter 21. Examples of materials for the support ST include Si, SiC, and AlN. The support ST is disposed such that the compound semiconductor portion 9 and the first and second electrodes E1 and E2 are located between the support ST and the base semiconductor portion 8. In other words, the light emitter 21 is mounted on the support ST in a junction-down configuration.

[0049] The support ST includes conductive first and second pads P1 and P2. The first electrode E1 is connected to the first pad P1 via a first bonding portion A1, and the second electrode E2 is connected to the second pad P2 via a second bonding portion A2. The second bonding portion A2 is thicker than the first bonding portion A1, and the difference in thickness between the first and second bonding portions A1 and A2 is equal to or greater than the thickness of the compound semiconductor portion 9. This allows the first and second electrodes E1 and E2 to be connected to the first and second pads P1 and P2, which are located on the same plane. In other words, the light-emitting element 23 functions as a COS (chip on submount).

[0050] FIG. 21 is a perspective view showing the configuration of a light-emitting device according to Example 1. As shown in FIG. 21, the light-emitting device 23 includes a light emitter 21 and a support member ST. The support member ST has two wide portions SH having a width greater than the resonance length of the light emitter 21 and a mounting portion SB located between the two wide portions SH and having a width smaller than the resonance length. The light emitter 21 is located above the mounting portion SB so that the width direction (Y direction) of the mounting portion SB coincides with the direction of the resonance length. In plan view, a pair of resonance end faces F1 and F2 protrude from the mounting portion SB. In other words, the mounting portion SB is formed between two cutout portions C1 and C2 facing each other in the direction defining the resonance length (Y direction). The resonance end face F1 is located on the cutout portion C1, and the resonance end face F2 is located on the cutout portion C2. The cutout portions C1 and C2 may have a rectangular shape, for example, when viewed in the Z direction.

[0051] The support ST includes a T-shaped first pad P1 and a second pad P2. The first pad P1 is located on the wide portion SH and includes a mounting portion J1 whose length in the Y direction is greater than the resonance length K1, and a contact portion Q1 whose length in the Y direction is less than the resonance length K1, located on the mounting portion SB. The second pad P2 is located on the wide portion SH and includes a mounting portion J2 whose length in the Y direction is greater than the resonance length K1, and a contact portion Q2 whose length in the Y direction is less than the resonance length K1, located on the mounting portion SB. The contact portions Q1 and Q2 are aligned in the X direction on the upper surface of the mounting portion SB. A first joint portion A1 is formed on the contact portion Q1, and a second joint portion A2 is formed on the contact portion Q2. The first joint portion A1 contacts the first electrode E1 of the light emitter 21, and the second joint portion A2 contacts the second electrode E2 of the light emitter 21. The first and second joint portions A1 and A2 can be made of solder, such as AuSi or AuSn.

[0052] The cavity end faces F1 and F2 of the light emitter 21 are covered with a reflector film UF, but a dielectric film SF made of the same material as the reflector film UF may be formed on one of the side surfaces of the support ST that is parallel to the cavity end faces F1 and F2 (for example, the side surface of the mounting portion SB).

[0053] Fig. 22 is a cross-sectional view showing another configuration of the light-emitting element according to Example 1. In Fig. 21, the cutout portions C1 and C2 are rectangular in plan view in the Z direction, but this is not limited thereto. As shown in Fig. 22, the cutout portions C1 and C2 may be trapezoidal with the shorter side facing the mounting portion SB.

[0054] 23 and 24 are cross-sectional views showing another configuration of the light-emitting element according to Example 1. In the light-emitting element 23 of FIG. 23, a plurality of light-emitting bodies 21 may be arranged on a support ST in a direction (X direction) perpendicular to the direction defining the resonance length so that the resonance lengths are aligned, and first and second pads P1 and P2 may be provided corresponding to each light-emitting body 21. As shown in FIG. 24, an optical device such as a photodiode PD may be provided in a cutout portion C1 of the support ST. This allows feedback control of the light emission intensity of the light-emitting bodies 21.

[0055] 25 is a perspective view showing the configuration of a light emitting substrate (semiconductor laser array) according to Example 1. The light emitting substrate 22 includes a support substrate SK and a plurality of light emitters 21. In the light emitting substrate 22, the plurality of light emitters 21 are arranged in a matrix on the support substrate SK in a direction defining the resonance length (Y direction) and a direction perpendicular thereto (X direction) so that the directions of the resonance lengths are aligned, and first and second pads P1 and P2 and first and second bonding portions A1 and A2 may be provided corresponding to each light emitter 21.

[0056] The support substrate SK can be formed, for example, by providing a matrix of multiple recesses HL (rectangular in plan view) in a Si substrate, SiC substrate, etc., and providing multiple first pads P1, multiple second pads P2, multiple first bonding portions A1, and multiple second bonding portions A2 in the non-recessed portions.

[0057] Fig. 26 is a perspective view showing another configuration of the light emitting substrate according to Example 1. A two-dimensionally arranged light emitting substrate in which a plurality of light emitters 21 are arranged in a matrix as shown in Fig. 25 can also be divided horizontally (divided into rows extending in the X direction) to form a one-dimensionally arranged (bar-shaped) light emitting substrate 22 as shown in Fig. 26. The one-dimensionally arranged type makes it easier to form the reflector film UF on the pair of cavity end faces F1 and F2.

[0058] (Manufacturing method) Fig. 27 is a flowchart illustrating an example of a method for manufacturing the light emitting device according to Example 1. Fig. 28 is a schematic cross-sectional view illustrating a method for manufacturing the light emitting device of Fig. 27. Fig. 29 is a plan view illustrating a method for manufacturing the light emitting device of Fig. 27. 27 to 29 includes the steps of preparing a template substrate 7 including a base substrate UK and a mask layer 6, forming a first semiconductor layer S1 (and a third semiconductor layer S3) that will become the base semiconductor portion 8 by the ELO method (described later), forming a second semiconductor layer S2 (and a fourth semiconductor layer S4) that will become the compound semiconductor portion 9, forming a stacked body LB that has the first semiconductor layer S1, the second semiconductor layer S2 that includes a ridge portion, and a first electrode E1 and a second electrode E2, etc., bonding the stacked body LB to a support substrate SK and separating the first semiconductor layer S1 from the template substrate 7, cleaving the stacked body LB on the support substrate SK to form a pair of resonant cavity facets F1 and F2 (an optical resonator LK including the pair of resonant cavity facets F1 and F2), forming a reflector film UF on each of the pair of resonant cavity facets F1 and F2, and dividing the support substrate SK into a plurality of support bodies ST.

[0059] After the laminate LB is formed, the mask layer 6 is etched away, and the first and second bonding portions A1 and A2 (e.g., solder) of the support substrate SK are heated and melted while the laminate LB is bonded to the support substrate SK. This fractures the bonding portion (downward protrusion) on the back surface of the first semiconductor layer S1 with the base substrate UK, separating the first semiconductor layer S1 from the template substrate 7. The laminate LB is then cleaved on the support substrate SK (m-plane cleavage of the first and second semiconductor layers S1 and S2, which are nitride semiconductor layers) to form a pair of resonant cavity facets F1 and F2. This results in a two-dimensionally arranged light emitting substrate 22 (see FIG. 25). The two-dimensionally arranged light emitting substrate is then divided into rows to form one-dimensionally arranged (rod-shaped) light emitting substrates 22 (see FIG. 26). A reflector film UF is then formed on the resonant cavity facets F1 and F2 of the one-dimensionally arranged light emitting substrate 22. Thereafter, the support substrate SK is divided into a plurality of support members ST, and each support member ST holds one or more light emitters 21, thereby forming a plurality of light emitting elements 23. The reflector film UF (e.g., a dielectric film) may be formed not only on the cleavage planes (m-planes) of the base semiconductor portion 8 and the compound semiconductor portion 9, but also on the side surfaces of the support member ST (including the side surfaces of the mounting portion SB) that are parallel to the cavity facets F1 and F2.

[0060] 30 and 31 are schematic cross-sectional views showing another example of the method for manufacturing the light-emitting device according to Example 1. As shown in Fig. 30, it is also possible to stack a plurality of one-dimensionally arranged light-emitting substrates 22 (see Fig. 26) in the Z direction so that the back surfaces of the base semiconductor portions 8 face each other, and simultaneously form a reflector film UF on the cavity end faces F1 and F2 of each light-emitting substrate 22. Furthermore, as shown in Fig. 31, when dividing the support substrate SK into a plurality of support bodies ST, each support body ST can hold a plurality of light-emitting bodies 21, thereby forming the light-emitting element 23 shown in Fig. 23 etc.

[0061] (Base semiconductor part) FIG. 32 is a cross-sectional view showing an example of lateral growth of the base semiconductor portion (ELO semiconductor layer) in Example 1. As shown in FIG. 32, the base substrate UK includes a main substrate 1 and an underlayer 4 on the main substrate 1, and a seed layer 3, which is a surface layer of the underlayer 4, is exposed from an opening K in a mask portion 5. In the ELO method, an initial growth layer SL is first formed on the seed layer 3, and then a first semiconductor layer S1 can be grown laterally from the initial growth layer SL. The initial growth layer SL is the starting point for the lateral growth of the first semiconductor layer S1 and is part of the first portion B1 of the base semiconductor portion 8. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the first semiconductor layer S1 to either the Z direction (c-axis direction) or the X direction (a-axis direction).

[0062] Here, deposition of the initial growth layer SL can be stopped just before the edge of the initial growth layer SL rises onto the upper surface of the mask portion 5 (the stage where it touches the upper end of the side surface of the mask portion 5) or just after it rises onto the upper surface of the mask portion 5 (i.e., at this timing, the ELO deposition conditions are switched from c-axis deposition conditions to a-axis deposition conditions). In this way, lateral deposition is performed from a state in which the initial growth layer SL slightly protrudes from the mask portion 5, so that material is less likely to be consumed in the thickness direction growth of the first semiconductor layer S1, and the first semiconductor layer S1 can be grown laterally at a high speed. The initial growth layer SL may be formed to a thickness of, for example, 2.0 μm or more and 3.0 μm or less.

[0063] In Example 1, the first semiconductor layer S1, which is the basis of the base semiconductor portion 8, was an n-type GaN layer, and Si-doped GaN (gallium nitride) was deposited on the template substrate 7 by ELO using an MOCVD apparatus. Examples of ELO deposition conditions include a substrate temperature of 1120°C, growth pressure of 50 kPa, TMG (trimethylgallium) at 22 sccm, NH3 at 15 slm, and V / III=6000 (the ratio of the amount of Group V source material supplied to the amount of Group III source material supplied). The lateral growth of the first and third semiconductor layers S1 and S3, which grew laterally from both sides of the mask portion 5, was stopped before they merged.

[0064] The width of the mask portion 5 was 50 μm, the width of the opening K was 5 μm, the lateral width of the first semiconductor layer S1 was 53 μm, the width (size in the X direction) of the low-defect portions B2 and B3 was 24 μm, and the thickness of the first semiconductor layer S1 was 5 μm. The aspect ratio of the first semiconductor layer S1 was 53 μm / 5 μm=10.6, which was a high aspect ratio.

[0065] A heterogeneous substrate having a lattice constant different from that of the nitride semiconductor can be used for the main substrate 1 in Fig. 32. Examples of heterogeneous substrates include single-crystal silicon (Si) substrates, sapphire (Al2O3) substrates, and silicon carbide (SiC) substrates. The plane orientation of the main substrate 1 is, for example, the (111) plane of a silicon substrate, the (0001) plane of a sapphire substrate, or the 6H-SiC (0001) plane of a SiC substrate.

[0066] As the underlayer 4 in FIG. 32, a buffer layer 2 and a seed layer 3 can be provided in this order from the main substrate 1 side. For example, if a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed layer 3, the two (main substrate and seed layer) will melt together. Therefore, providing a buffer layer 2 including at least one of an AlN layer and a SiC (silicon carbide) layer reduces melting. The buffer layer 2 may have at least one of the effects of increasing the crystallinity of the seed layer 3 and alleviating the internal stress of the first semiconductor layer S1. If a main substrate 1 that does not melt together with the seed layer 3 is used, a configuration without providing the buffer layer 2 is also possible. Note that the configuration in FIG. 32 is not limited to one in which the seed layer 3 overlaps the entire mask portion 5. Since the seed layer 3 only needs to be exposed from the opening K, the seed layer 3 may be formed locally so as not to overlap part or all of the mask portion 5.

[0067] The openings K in the mask layer 6 function as growth initiation holes that expose the seed layer 3 and initiate the growth of the first semiconductor layer S1, and the mask portions 5 of the mask layer 6 function as selective growth masks that cause the first semiconductor layer S1 to grow laterally. The mask layer 6 may be a mask pattern that includes the mask portions 5 and the openings K.

[0068] The mask layer 6 may be, for example, a single layer film including one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000°C or higher), or a laminated film including at least two of these.

[0069] For example, a silicon oxide film having a thickness of about 100 nm to 4 μm (preferably about 150 nm to 2 μm) is formed on the entire surface of the underlayer 4 using a sputtering method, and a resist is applied to the entire surface of the silicon oxide film. The resist is then patterned using a photolithography method to form a resist with a plurality of stripe-shaped openings. Then, a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) is used to remove portions of the silicon oxide film to form the plurality of openings K, and the resist is then removed by organic cleaning to form the mask layer 6.

[0070] The openings K have a longitudinal shape (slit shape) and are periodically arranged in the a-axis direction (X direction) of the first semiconductor layer S1. The width of the openings K is approximately 0.1 μm to 20 μm. The smaller the width of each opening, the fewer the number of threading dislocations propagating from each opening to the first semiconductor layer S1. In addition, the width (size in the X direction) of the low-defect portions B2 and B3 can be increased.

[0071] While silicon oxide films decompose and evaporate in minute amounts during the formation of the ELO semiconductor layer and can become incorporated into the ELO semiconductor layer, silicon nitride films and silicon oxynitride films have the advantage of being less susceptible to decomposition and evaporation at high temperatures.

[0072] Therefore, the mask layer 6 may be a single layer film of a silicon nitride film or a silicon oxynitride film, or may be a laminated film in which a silicon oxide film and a silicon nitride film are formed in this order on the underlayer 4, or may be a laminated film in which a silicon nitride film and a silicon oxide film are formed in this order on the underlayer 4, or may be a laminated film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order on the underlayer.

[0073] When the base semiconductor portion 8 is formed using the ELO method, a template substrate 7 may be used that includes a main substrate 1 and a mask layer 6 (mask pattern) on the main substrate 1. The template substrate 7 may have a growth-inhibiting region (e.g., a region that inhibits crystal growth in the Z direction) corresponding to the mask portion 5, and a seed region corresponding to the opening K. For example, the growth-inhibiting region and the seed region may be formed on the main substrate 1, and the base semiconductor portion 8 may be formed on the growth-inhibiting region and the seed region using the ELO method.

[0074] (Compound Semiconductor Department, etc.) The compound semiconductor portion 9 can be formed using, for example, an MOCVD apparatus. The first contact layer 9A can be, for example, an n-type GaN layer, the first cladding layer 9B can be, for example, an n-type AlGaN layer, the first optical guide layer 9C can be, for example, an n-type GaN layer, the active layer 9K can be, for example, an MQW (Multi-Quantum Well) structure including an InGaN layer, the electron blocking layer 9D can be, for example, a p-type AlGaN layer, the second optical guide layer 9E can be, for example, a p-type GaN layer, the second cladding layer 9F can be, for example, a p-type AlGaN layer, and the second contact layer 9G can be, for example, a p-type GaN layer.

[0075] The thickness of each layer of the light emitter 21 can be expressed as base semiconductor portion 8>first cladding layer 9B>first optical guide layer 9C>active layer 9K, and base semiconductor portion 8>second cladding layer 9F>second optical guide layer 9E>active layer 9K. Furthermore, the refractive index of each layer of the compound semiconductor portion 9 (refractive index of light generated in the active layer 9K) can be expressed as first cladding layer 9B<first optical guide layer 9C<active layer 9K, and insulating film DF<second cladding layer 9F<second optical guide layer 9E<active layer 9K.

[0076] The first and second electrodes E1 and E2 and the first and second pads P1 and P2 may be formed of a single-layer or multi-layer film containing at least one of a metal film (which may be an alloy film) containing at least one of Ni, Rh, Pd, Cr, Au, W, Pt, Ti, and Al, and a conductive oxide film containing at least one of Zn, In, and Sn. The insulating film DF covering the ridge portion RJ may be formed of a single-layer or multi-layer film containing, for example, an oxide or nitride of Si, Al, Zr, Ti, Nb, or Ta.

[0077] The first semiconductor layer S1 (ELO semiconductor layer) that will become the base semiconductor portion 8 and the second semiconductor layer S2 that will become the compound semiconductor portion 9 can also be successively formed in the same film formation apparatus (for example, an MOCVD apparatus). The intermediate substrate on which the first semiconductor layer S1 has been formed can be temporarily removed from the film formation apparatus, and the second semiconductor layer S2 can be formed on the first semiconductor layer S1 using a different apparatus. In this case, the second semiconductor layer S2 can be formed after forming an n-type GaN layer (for example, with a thickness of about 0.1 μm to 3 μm) that will serve as a buffer during regrowth on the first semiconductor layer S1.

[0078] The reflector film UF covering the resonator facets F1 and F2 can be made of dielectric materials such as SiO2, Al2O3, AlN, AlON, Nb2O5, Ta2O5, and ZrO2. The reflector film UF may also be a multilayer film. The reflector film UF can be formed by electron beam evaporation, electron cyclotron resonance sputtering, chemical vapor deposition, or other methods.

[0079] In the first embodiment, a silicon substrate can be used for the main substrate 1 used for the ELO of the base semiconductor portion 8, as well as for the support substrate SK and the support body ST. This makes it difficult for bonding defects caused by differences in thermal expansion coefficients to occur during bonding, and also has advantages in terms of large diameter, heat dissipation, processability, and cost.

[0080] Because the light emitter 21 has a single-sided electrode structure in which the first and second electrodes E1 and E2 are provided on one side, the surface of the first-type semiconductor layer 9N connected to the second electrode E2 and the surface of the second-type semiconductor layer 9P connected to the first electrode E1 can both be the (0001) plane (c-plane) of a GaN-based semiconductor. In GaN-based semiconductor lasers, when the crystal growth substrate (e.g., a GaN substrate) is conductive, the semiconductor layer is fabricated so that the front surface is the (0001) plane, and the anode contact surface is the (0001) plane, and the cathode contact surface is the back surface of the crystal growth substrate, i.e., the (000-1) plane, resulting in a double-sided electrode structure. A single-sided electrode structure causes current to flow laterally between the anode and cathode, which can result in nonuniform current flow within the ridge portion (ridge waveguide), increasing the threshold current, or the current path being longer than in a double-sided electrode structure, resulting in an increased driving voltage. Therefore, the single-sided electrode structure of GaN-based semiconductor lasers has traditionally been used only when the crystal growth substrate is insulating and an electrode cannot be formed on the back side (for example, a sapphire substrate). It is known that when the (000-1) plane is used as the cathode connection surface, the contact resistance is higher than when the (0001) plane is used as the cathode connection surface, so a process is added in which the (000-1) plane of the crystal growth substrate is processed by etching or other methods to expose various planes on the surface.

[0081] In Example 1, even when a double-sided electrode structure can be adopted because the crystal growth substrate (main substrate) is conductive or the main substrate is removed and the conductive base semiconductor portion is located on the backside, there is an advantage to adopting a single-sided electrode structure. With a short resonance length, the drive current is inherently small, and in applications such as AR (augmented reality) glasses that do not require high optical output, the device is driven near the threshold current, so the increase in series resistance, which causes a voltage increase depending on the current value, is not a major problem. On the other hand, using the (0001) plane as the cathode connection surface has the advantage of reducing contact resistance (reducing power consumption) and also facilitating mounting on a submount (support substrate SK, etc.).

[0082] Example 2 FIG. 33 is a cross-sectional view showing the configuration of a light emitter according to Example 2. The light emitter 21 includes a base semiconductor portion 8, a compound semiconductor portion 9 located on the base semiconductor portion 8, a first electrode E1 serving as an anode, and a second electrode E2 serving as a cathode. The light emitter 21 can also be referred to as an LED (light-emitting diode) chip. The compound semiconductor portion 9 includes a first-type (n-type) semiconductor layer 9N having a donor, an active layer 9K, and a second-type (p-type) semiconductor layer 9P having an acceptor, formed in this order. At least a portion of the first electrode E1 is located on the (0001) plane of the second-type semiconductor layer 9P, and at least a portion of the second electrode E2 is located on the (0001) plane of the first-type semiconductor layer 9N.

[0083] In plan view, the entire first electrode E1 overlaps with the second portion B2 (low dislocation portion) of the base semiconductor portion 8 (the first electrode E1 does not overlap with the first portion B1). In this way, the current path from the first electrode E1 through the active layer 9K to the first-type semiconductor layer 9N is formed in the portion (low dislocation portion) that overlaps with the second portion B2 in plan view, thereby improving the light emission efficiency of the active layer 9K.

[0084] Example 3 In Examples 1 and 2, the base semiconductor portion 8 (ELO semiconductor layer) can be a GaN layer, but is not limited to this. An InGaN layer, which is a GaN-based semiconductor layer, can also be formed as the ELO semiconductor layer. Lateral deposition of the InGaN layer is performed at a low temperature, for example, below 1000°C. This is because at high temperatures, the vapor pressure of indium increases and it is not effectively incorporated into the film. Lowering the deposition temperature has the effect of reducing the mutual reaction between the mask portion 5 and the InGaN layer. Another effect is that the InGaN layer has a lower reactivity with the mask portion 5 than the GaN layer. When indium is incorporated into the InGaN layer at an In composition level of 1% or more, the reactivity with the mask portion 5 further decreases. Triethylgallium (TEG) can be used as the gallium source gas.

[0085] Example 4 FIG. 34 is a perspective view showing the configuration of a light-emitting module of Example 4. The light-emitting module 24 (light-emitting device) of FIG. 34 is a surface-mount package, and includes a housing 35 and a light-emitting element 23 (see, for example, FIG. 23). The light-emitting element 23 includes a plurality of light-emitting bodies 21, and is provided so that the side surface (surface parallel to the resonant cavity end face) of the support body ST faces the bottom surface 37 of the housing 35. Therefore, the emission surface (emission-side resonant cavity end face) of each light-emitting body 21 faces the top surface 34 (transparent plate) of the housing 35, and laser light is emitted from the top surface 34 of the housing 35. The light-emitting element 23 is connected to an external connection pin 33 via a wire 31.

[0086] Fig. 35 is a perspective view showing another configuration of the light emitting module of Example 4. The light emitting module 24 of Fig. 35 is a TO-can mounting type package, and includes a stem 38 and a light emitting element 23 (see, for example, Fig. 21). The light emitting element 23 is disposed on a heat block 36 that protrudes from the base of the stem 38. First and second pads P1 and P2 of the light emitting element 23 are connected to external connection pins 33 via wires 31.

[0087] In conventional technology, semiconductor laser chips must be individually die-bonded to a submount to form a CoS (Chip on Submount). However, in Examples 1 to 4, the support ST of the light-emitting element 23 functions as a submount, and the light-emitting element 23 itself has a CoS structure, eliminating the need for die-bonding to a submount. This eliminates the difficulty of handling when the resonance length is short or the chip width is narrow. Specifically, the light-emitting element 23 has first and second pads P1 and P2 that meet the size requirements for wire bonding on the support ST. These first and second pads P1 and P2 are electrically connected to the first and second electrodes (anode and cathode) of the light-emitting element 21 (semiconductor laser chip). Therefore, it is sufficient to electrically connect the external connection pins 33 of the package to the first and second pads P1 and P2 with wires 31.

[0088] Example 5 Fig. 36 is a schematic diagram showing the configuration of an electronic device according to Example 5. The electronic device 50 in Fig. 36 includes a light-emitting device GD (21-24) according to Examples 1-4, and a control unit 80 including a processor and controlling the light-emitting device GD. Examples of the electronic device 50 include a lighting device, a display device, a communication device, an information processing device, a medical device, and an electric vehicle (EV).

[0089] The above-described technical aspects are intended to be illustrative and explanatory, and not limiting. Many variations will be apparent to those skilled in the art based on these examples and descriptions.

[0090] [Additional Notes] The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-described embodiments. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure. [Explanation of symbols]

[0091] 7 Template substrate 8 Base Semiconductor Section 9 Compound Semiconductor Department 21 Light-emitting body (light-emitting device) 22 Light-emitting substrate (light-emitting device) 23 Light-emitting elements (light-emitting devices) 24 Light-emitting module (light-emitting device) S1 First semiconductor layer S2 Second semiconductor layer LK optical resonator RJ Ridge Club B1 Part 1 B2 Part 2 (low dislocation area) B2 Part 3 (low dislocation area) F1·F2 A pair of resonant end faces P1 1st pad P2 2nd pad E1 1st electrode E1 2nd electrode UF reflective mirror film ST support SB placement area SK support board

Claims

1. preparing a semiconductor substrate comprising: an underlying substrate; a plurality of mask portions located on the underlying substrate; and a base semiconductor portion extending from an area of ​​an upper surface of the underlying substrate that is exposed between the plurality of mask portions, the base semiconductor portion comprising a first portion extending upward from the exposed area and a second portion extending from the first portion onto one of the plurality of mask portions; forming a compound semiconductor portion on the base semiconductor portion; forming a first electrode and a second electrode above the base semiconductor portion such that at least a portion of the first electrode is located above the second portion; providing a support substrate having a first pad and a second pad; bonding a stack including the base semiconductor portion, the compound semiconductor portion, the first electrode, and the second electrode to a support substrate while connecting the first electrode to the first pad and while connecting the second electrode to the second pad, and separating the base semiconductor portion from the underlying substrate.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the threading dislocation density of the second portion is equal to or less than one-fifth of the threading dislocation density of the first portion.

3. The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of dividing the base semiconductor portion and the compound semiconductor portion.

4. The method for manufacturing a semiconductor device according to claim 3 , wherein the base semiconductor portion and the compound semiconductor portion are divided to form cavity facets of the semiconductor device.

5. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the base semiconductor portion includes a nitride semiconductor, and the base semiconductor portion has an elongated shape with the <1-100> direction of the nitride semiconductor as the longitudinal direction.

6. the base semiconductor portion and the compound semiconductor portion include nitride semiconductors, The method for manufacturing a semiconductor device according to claim 4 , further comprising the step of dividing the base semiconductor portion and the compound semiconductor portion so as to generate cross sections along an m-plane of the nitride semiconductor.

7. 7. The method for manufacturing a semiconductor element according to claim 1, wherein the first electrode and the second electrode are formed such that at least a portion of the first electrode and at least a portion of the second electrode are located on a (0001) plane of the compound semiconductor portion.

8. The plurality of mask portions are arranged in a first direction, 7. The method for manufacturing a semiconductor element according to claim 1, wherein the first electrode and the second electrode are aligned in the first direction in a plan view.

9. The plurality of mask portions are arranged in a first direction, 7. The method for manufacturing a semiconductor element according to claim 1, wherein the first electrode has a shape whose longitudinal direction is a second direction perpendicular to the first direction.

10. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the compound semiconductor portion includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer in this order.

11. the first electrode is in contact with a (0001) plane of the p-type semiconductor layer, The method for manufacturing a semiconductor device according to claim 10 , wherein the second electrode is in contact with a (0001) plane of the n-type semiconductor layer.

12. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the first electrode is an anode and the second electrode is a cathode.

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