Driver circuit and switch system

Abstract

To shorten turn on time without using a capacitor with high capacity.SOLUTION: A speed up circuit 14 is provided between a power source terminal 11 and a gate 21 of a semiconductor switch element 2. An impedance element 15 is provided between a node N1, which is between the speed up circuit 14 and the gate 21 of the semiconductor switch element 2, and a signal input terminal 13. In the speed up circuit 14, a second field effect transistor Q2 is connected in series to a first field effect transistor Q1 and is connected to the gate 21 of the semiconductor switch element 2. The impedance of the impedance element 15 is higher than the impedance of the speed up circuit 14 when both the first field effect transistor Q1 and the second field effect transistor Q2 are on.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a driver circuit and a switch system, and more particularly to a driver circuit for a current-driven semiconductor switch element and a switch system including the same. [Background technology]

[0002] BACKGROUND ART Conventionally, a gate drive circuit for a semiconductor element is known (Patent Document 1).

[0003] The semiconductor device described in Patent Document 1 is a gate-driven semiconductor device. The semiconductor device is driven based on a signal from a switching circuit. The switching circuit configures a gate drive circuit with a drive circuit and a parallel circuit of a gate resistor and a capacitor.

[0004] The drive circuit is composed of an NPN transistor and a PNP transistor. The gate-driven semiconductor element that constitutes the semiconductor element is a GIT (Gate Injection Transistor). In the gate drive circuit disclosed in Patent Document 1, high-speed switching is made possible by including a capacitor connected in parallel with the gate resistor, so it is necessary to include a capacitor with a large capacity. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-51165 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present disclosure is to provide a driver circuit and a switch system that can shorten the turn-on time of a semiconductor switch element without using a large-capacity capacitor. [Means for solving the problem]

[0007] A driver circuit according to one aspect of the present disclosure is a driver circuit for a current-driven semiconductor switch element having a gate and a source corresponding to the gate, the driver circuit comprising: a power supply terminal, a ground terminal, a signal input terminal, a speed-up circuit, and an impedance element. The ground terminal is connected to the source of the semiconductor switch element. The speed-up circuit is provided between the power supply terminal and the gate of the semiconductor switch element. The impedance element is provided between the signal input terminal and a node between the speed-up circuit and the gate of the semiconductor switch element. The speed-up circuit includes a first field-effect transistor and a second field-effect transistor. The second field-effect transistor is connected in series with the first field-effect transistor and to the gate of the semiconductor switch element. The impedance of the impedance element is higher than the impedance of the speed-up circuit when both the first field-effect transistor and the second field-effect transistor are in an on-state.

[0008] A driver circuit according to one aspect of the present disclosure is a driver circuit for a current-driven semiconductor switch element having a gate and a source corresponding to the gate, and includes a power supply terminal, a ground terminal, a signal input terminal, a first field-effect transistor, a second field-effect transistor, and an impedance element. The ground terminal is connected to the source of the semiconductor switch element. The first field-effect transistor is connected to the power supply terminal. The second field-effect transistor is connected in series with the first field-effect transistor and to the gate of the semiconductor switch element. The impedance element is provided between the signal input terminal and a node between the second field-effect transistor and the gate of the semiconductor switch element. When the second field effect transistor is on and the potential level of the signal input to the signal input terminal changes from a first potential level to a second potential level higher than the first potential level, the driver circuit turns on the first field effect transistor and causes a current larger than the current passing through the impedance element to flow to the gate of the semiconductor switch element, thereby increasing the gate voltage of the semiconductor switch element above a predetermined value larger than a threshold voltage, and then continues to cause a current to flow to the gate of the semiconductor switch element through the impedance element, thereby setting the gate voltage of the semiconductor switch element to the predetermined value.

[0009] A switch system according to one aspect of the present disclosure includes the driver circuit and the semiconductor switch element. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a circuit diagram of a switch system including a driver circuit according to a first embodiment. [Figure 2] FIG. 2 is a timing chart for explaining the operation of the driver circuit of the above embodiment. [Figure 3] FIG. 3 is a circuit diagram of a switch system including a driver circuit according to the second embodiment. [Figure 4]FIG. 4 is a circuit diagram of a switch system including a driver circuit according to the third embodiment. [Figure 5] FIG. 5 is a circuit diagram of a switch system including a driver circuit according to the fourth embodiment. [Figure 6] FIG. 6 is a circuit diagram of a switch system including a driver circuit according to the fifth embodiment. [Figure 7] FIG. 7 is a circuit diagram of a switch system including a driver circuit according to the sixth embodiment. [Figure 8] FIG. 8 is a diagram illustrating the operation of the constant current circuit in the driver circuit of the above embodiment. [Figure 9] FIG. 9 is a circuit diagram of a switch system including a driver circuit according to the seventh embodiment. [Figure 10] FIG. 10 is a timing chart for explaining the operation of the driver circuit of the above embodiment. [Figure 11] FIG. 11 is a circuit diagram of a switch system including a driver circuit according to the eighth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] (Embodiment 1) A driver circuit 1 according to the first embodiment and a switch system 3 including the driver circuit 1 will be described below with reference to FIG.

[0012] (1) Overview The driver circuit 1 is a driver circuit for a current-driven semiconductor switch element 2. The semiconductor switch element 2 has a gate 21 and a source 22 corresponding to the gate 21. The current-driven semiconductor switch element 2 is an element that is turned on by passing a current through the gate 21, and a current continues to flow through the gate 21 even after it is turned on. The current-driven semiconductor switch element 2 does not include, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).

[0013] The switch system 3 includes a driver circuit 1 and a semiconductor switch element 2. The semiconductor switch element 2 has a drain 23 in addition to the gate 21 and source 22 described above. The switch system 3 has a source terminal 32 and a drain terminal 33 connected to the source 22 and drain 23 of the semiconductor switch element 2, respectively.

[0014] (2) Components of the switch system (2.1) Semiconductor Switching Elements The semiconductor switch element 2 is, for example, a GaN-based semiconductor switch element. More specifically, the semiconductor switch element 2 is a GaN-based GIT (Gate Injection Transistor).

[0015] The semiconductor switch element 2 includes, for example, a substrate, a buffer layer, a first nitride semiconductor layer, a second nitride semiconductor layer, a source electrode, a gate electrode, a drain electrode, and a p-type layer. The buffer layer is formed on the substrate. The first nitride semiconductor layer is formed on the buffer layer. The second nitride semiconductor layer is formed on the first nitride semiconductor layer. The source electrode, the gate electrode, and the drain electrode are formed on the second nitride semiconductor layer. The p-type layer is interposed between the gate electrode and the second nitride semiconductor layer. In the semiconductor switch element 2, the second nitride semiconductor layer and the p-type layer form a diode structure. The gate 21 in the semiconductor switch element 2 includes a gate electrode and a p-type layer. The source 22 in the semiconductor switch element 2 includes a source electrode. The drain 23 in the semiconductor switch element 2 includes a drain electrode. The substrate is, for example, a silicon substrate. The buffer layer is, for example, an undoped GaN layer. The first nitride semiconductor layer is, for example, an undoped GaN layer. The second nitride semiconductor layer is, for example, an undoped AlGaN layer. The p-type layer is, for example, a p-type AlGaN layer. The buffer layer, the first nitride semiconductor layer, and the second nitride semiconductor layer may each contain impurities such as Mg, H, Si, C, and O that are inevitably mixed in during growth by MOVPE (Metal Organic Vapor Phase Epitaxy) or the like.

[0016] (2.2) Driver circuit (2.2.1) Driver circuit configuration As shown in FIG. 1, the driver circuit 1 according to the first embodiment includes a power supply terminal 11, a ground terminal 12, a signal input terminal 13, a speed-up circuit 14, and an impedance element 15.

[0017] The ground terminal 12 is connected to a source 22 of a current-driven semiconductor switch element 2 having a gate 21 , a source 22 and a drain 23 .

[0018] The speed-up circuit 14 is provided between the power supply terminal 11 and the gate 21 of the semiconductor switch element 2 .

[0019] The impedance element 15 is provided between the signal input terminal 13 and a node N1 between the speed-up circuit 14 and the gate 21 of the semiconductor switch element 2.

[0020] The speed-up circuit 14 includes a first field-effect transistor Q1 and a second field-effect transistor Q2.

[0021] The second field effect transistor Q2 is connected in series to the first field effect transistor Q1 and is connected to the gate 21 of the semiconductor switch element 2.

[0022] The impedance of the impedance element 15 is higher than the impedance of the speed-up circuit 14 when both the first field-effect transistor Q1 and the second field-effect transistor Q2 are in the on state.

[0023] The driver circuit 1 according to the first embodiment further includes a resistive voltage divider circuit 16. The resistive voltage divider circuit 16 is provided between the power supply terminal 11 and the ground terminal 12. In the driver circuit 1 according to the first embodiment, the gate GQ2 of the second field effect transistor Q2 is connected to the output terminal 161 of the resistive voltage divider circuit 16.

[0024] (2.2.2) Driver circuit details A DC power supply 4 having a high-potential output terminal and a low-potential output terminal is connected between a power supply terminal 11 and a ground terminal 12 of the driver circuit 1. The high-potential output terminal of the DC power supply 4 is connected to the power supply terminal 11 of the driver circuit 1. The low-potential output terminal of the DC power supply 4 is connected to the ground terminal 12 of the driver circuit 1. The output voltage of the DC power supply 4 is, for example, 12 V. The DC power supply 4 is an isolated power supply. Note that the DC power supply 4 is not a component of the driver circuit 1.

[0025] A series circuit of a driver IC (Integrated Circuit) 5 and a signal source 6 is connected between a signal input terminal 13 and a ground terminal 12 of the driver circuit 1. The driver IC 5 and the signal source 6 are not components of the driver circuit 1.

[0026] The signal source 6 outputs a drive signal (see FIG. 2). The drive signal is, for example, a signal whose potential level changes between a first potential level VL1 (for example, 0 V) ​​and a second potential level VL2 (for example, 12 V). The first potential level VL1 is, for example, the same potential level as the potential level of the low-potential output terminal of the DC power supply 4. The second potential level VL2 is, for example, the same potential level as the potential level of the high-potential output terminal of the DC power supply 4.

[0027] The driver IC5 is, for example, a CMOS (Complementary Metal-Oxide Semiconductor) inverter and includes an anti-series circuit of a p-channel MOSFET and an n-channel MOSFET. This anti-series circuit is connected between the high-potential output terminal and the low-potential output terminal of the DC power supply 4. In this anti-series circuit, the drains of the p-channel MOSFET and the n-channel MOSFET are connected to each other, the source of the p-channel MOSFET is connected to the high-potential output terminal of the DC power supply 4, and the source of the n-channel MOSFET is connected to the low-potential output terminal of the DC power supply 4. When the potential level of the drive signal input from the signal source 6 is the second potential level VL2, the p-channel MOSFET is in the OFF state and the n-channel MOSFET is in the ON state, and the potential level of the output signal from the driver IC5 is the first potential level VL1. When the potential level of the drive signal input from the signal source 6 is the first potential level VL1, the p-channel MOSFET is in the ON state and the n-channel MOSFET is in the OFF state, and the potential level of the output signal from the driver IC5 is the second potential level VL2. In the drive signal and the output signal of the driver IC5, the second potential level VL2 (for example, 12V) corresponds to logic 1, and the first potential level VL1 (for example, 0V) corresponds to logic 0.

[0028] The speed-up circuit 14 is a circuit for turning on the semiconductor switch element 2 at a higher speed.

[0029] In the speed-up circuit 14, a first field-effect transistor Q1 and a second field-effect transistor Q2 are connected in series. Like the semiconductor switch element 2, the first field-effect transistor Q1 and the second field-effect transistor Q2 are each a GaN-based GaN transistor. In the driver circuit 1 according to the first embodiment, the first field-effect transistor Q1 and the second field-effect transistor Q2 are each a normally-off field-effect transistor. The first field-effect transistor Q1 has a gate GQ1, a drain DQ1, and a source SQ1. The second field-effect transistor Q2 has a gate GQ2, a drain DQ2, and a source SQ2. In the speed-up circuit 14, the source SQ1 of the first field-effect transistor Q1 and the drain DQ2 of the second field-effect transistor Q2 are connected. In the speed-up circuit 14, the drain DQ1 of the first field-effect transistor Q1 is connected to the power supply terminal 11. In the speed-up circuit 14, the source SQ2 of the second field-effect transistor Q2 is connected to the gate 21 of the semiconductor switch element 2.

[0030] The current capacity of each of the first field effect transistor Q1 and the second field effect transistor Q2 is smaller than the current capacity of the semiconductor switch element 2. The gate width of each of the first field effect transistor Q1 and the second field effect transistor Q2 is smaller than the gate width of the semiconductor switch element 2. The gate width of the second field effect transistor Q2 is, for example, approximately the same as the gate width of the first field effect transistor Q1, but may be the same as or different from that of the first field effect transistor Q1.

[0031] The first field-effect transistor Q1 is an element that, when the semiconductor switch element 2 is turned on, passes a larger current (gate current) through the gate 21 of the semiconductor switch element 2 than in the steady-on state, thereby temporarily making the gate voltage of the semiconductor switch element 2 higher than a predetermined value Vg1 (see FIG. 2) that is higher than the threshold voltage.

[0032] In the driver circuit 1, the second field effect transistor Q2 is turned on to turn on the semiconductor switch element 2, and then the second field effect transistor Q2 is turned off.

[0033] The driver circuit 1 further includes a first gate resistor R1 and a second gate resistor R2. One end of the first gate resistor R1 is connected to a signal input terminal 13. The other end of the first gate resistor R1 is connected to a gate GQ1 of the first field-effect transistor Q1. One end of the second gate resistor R2 is connected to an output terminal 161 of a resistive voltage divider circuit 16. The other end of the second gate resistor R2 is connected to a gate GQ2 of the second field-effect transistor Q2. From the viewpoint of quickly turning on the first field-effect transistor Q1, the resistance value of the first gate resistor R1 is smaller than the resistance value of the second gate resistor R2.

[0034] The impedance element 15 is provided between a node N1 between the speed-up circuit 14 and the gate 21 of the semiconductor switch element 2 and the signal input terminal 13. One end of the impedance element 15 is connected to the node N1. The other end of the impedance element 15 is connected to the signal input terminal 13. The impedance element 15 is an element for determining the gate voltage (the above-mentioned predetermined value Vg1) applied between the gate 21 and source 22 of the semiconductor switch element 2 when the semiconductor switch element 2 is in a steady on-state. The impedance element 15 is, for example, a resistor R5. The resistance value of the resistor R5 is determined so that the gate current that turns on the semiconductor switch element 2 flows to the gate 21 of the semiconductor switch element 2. The magnitude relationship between the resistance values ​​of the gate resistor R2 and the resistor R5 is determined to be the opposite of the magnitude relationship between the gate width of the second field-effect transistor Q2 and the gate width of the semiconductor switch element 2.

[0035] The resistive voltage divider circuit 16 is a series circuit of resistors R3 and R4. The resistor R3 is connected to the power supply terminal 11, and the resistor R4 is connected to the ground terminal 12. The output terminal 161 of the resistive voltage divider circuit 16 is the connection point between the resistors R3 and R4. The ratio of the resistance values ​​of the resistors R3 and R4 in the resistive voltage divider circuit 16 is determined so that a voltage for turning on the second field-effect transistor Q2 can be output from the output terminal 161. When the DC power supply 4 is connected between the power supply terminal 11 and the ground terminal 12, a current always flows through the resistors R3 and R4 of the resistive voltage divider circuit 16. Therefore, if the resistance values ​​of the resistors R3 and R4 are small, the power loss of the DC power supply 4 increases. Therefore, from the perspective of reducing the power loss of the DC power supply 4, it is preferable that the resistance values ​​of the resistors R3 and R4 are large. However, from the viewpoint of increasing the gate voltage of the second field effect transistor Q2 and stabilizing the operation of the second field effect transistor Q2, it is necessary to prevent the resistance values ​​of the resistors R3 and R4 from being too large.

[0036] In the driver circuit 1, for example, by setting the resistance value of the second gate resistor R2 to be approximately the same as the resistance value of the resistor R3 of the resistive voltage divider circuit 16, the time until the second field-effect transistor Q2 turns off when the semiconductor switch element 2 is turned on is extended. This extends the time during which the gate voltage of the semiconductor switch element 2 can be temporarily higher than the predetermined value Vg1, thereby increasing the turn-on speed of the semiconductor switch element 2. Furthermore, while the gate voltage of the semiconductor switch element 2 is higher than the predetermined value Vg1, the driver circuit 1 can increase the drain current flowing through the semiconductor switch element 2 compared to the drain current when the gate voltage is the predetermined value Vg1. This allows the driver circuit 1 to gain the time necessary to completely flow the inrush current, depending on the application.

[0037] An example of the gate widths and circuit constants of the semiconductor switch element 2, first field effect transistor Q1, and second field effect transistor Q2 in the switch system 3 will be described below, assuming that the output voltage of the DC power supply 4 is, for example, 12 V.

[0038] The gate width of the semiconductor switch element 2 is, for example, 400 mm. The gate width of the first field effect transistor Q1 is, for example, 10 mm. The gate width of the second field effect transistor Q2 is, for example, 10 mm.

[0039] The resistance value of the first gate resistor R1 is, for example, 100Ω, and the resistance value of the second gate resistor R2 is, for example, 1 kΩ to 10 kΩ.

[0040] The resistance value of the resistor R3 is, for example, 5 kΩ, the resistance value of the resistor R4 is, for example, 2 kΩ, and the resistance value of the resistor R5 that constitutes the impedance element 15 is, for example, 500 Ω.

[0041] (3) Operation of the driver circuit and the switch system including the same As described above, the driver circuit 1 of embodiment 1 includes a power supply terminal 11, a ground terminal 12, a signal input terminal 13, a first field effect transistor Q1, a second field effect transistor Q2, and an impedance element 15 (resistor R5).

[0042] FIG. 2 is a timing chart showing a schematic relationship between the drive signal input to the signal source 6, the output signal of the driver IC 5, the gate voltage of the first field-effect transistor Q1, the gate voltage of the second field-effect transistor Q2, the gate voltage of the semiconductor switch element 2, and the voltage between the drain 23 and the source 22 of the semiconductor switch element 2.

[0043] In the driver circuit 1 of embodiment 1, when the second field-effect transistor Q2 is in the on state and the potential level of the signal input to the signal input terminal 13 (the output signal of the driver IC5) changes from the first potential level VL1 to the second potential level VL2 higher than the first potential level VL1, the first field-effect transistor Q1 turns on and causes a current (e.g., 1 [A]) larger than the current (e.g., 1 [mA]) passing through the impedance element 15 to flow to the gate 21 of the semiconductor switch element 2, thereby making the gate voltage of the semiconductor switch element 2 larger than a predetermined value Vg1 larger than the threshold voltage of the semiconductor switch element 2, and thereafter continues to cause a current to flow to the gate 21 of the semiconductor switch element 2 through the impedance element 15, thereby bringing the semiconductor switch element 2 into a steady on state.

[0044] (4) Advantages In the driver circuit 1 and the switch system 3 according to the first embodiment, the speed-up circuit 14 using the first field-effect transistor Q1 and the second field-effect transistor Q2 is provided, thereby shortening the turn-on time of the semiconductor switch element 2 without using a large-capacity capacitor.

[0045] Furthermore, when the driver circuit 1 according to the first embodiment is configured as a monolithic integrated circuit, it does not need to include a large-capacity capacitor, which allows for miniaturization. Furthermore, when the switch system 3 according to the first embodiment is configured as a monolithic integrated circuit, it does not need to include a large-capacity capacitor, which allows for miniaturization.

[0046] (Embodiment 2) A driver circuit 1a according to the second embodiment and a switch system 3a including the driver circuit 1a will be described below with reference to FIG.

[0047] The driver circuit 1a according to the second embodiment is substantially the same as the driver circuit 1 according to the first embodiment (see FIG. 1), but differs from the driver circuit 1 according to the first embodiment in that it includes a constant current circuit 17 instead of the resistor R4 of the driver circuit 1. Regarding the driver circuit 1a and the switch system 3a according to the second embodiment, components similar to those of the driver circuit 1 and the switch system 3 according to the first embodiment are denoted by the same reference numerals and descriptions thereof will be omitted.

[0048] The driver circuit 1a according to the second embodiment includes a series circuit of a resistor R3 and a constant current circuit 17, instead of the resistive voltage divider circuit 16 of the driver circuit 1 according to the first embodiment. The resistor R3 is connected to the power supply terminal 11. The constant current circuit 17 is provided between the resistor R3 and the ground terminal 12.

[0049] In the driver circuit 1a, the gate GQ2 of the second field effect transistor Q2 is connected to a node N2 between the resistor R3 and the constant current circuit 17.

[0050] The constant current circuit 17 includes, for example, a field effect transistor Q3 having a gate GQ3, a drain DQ3, and a source SQ3, and is configured by shorting the gate GQ3 and source SQ3 of this field effect transistor Q3. In the constant current circuit 17, the drain DQ3 of the field effect transistor Q3 is connected to a resistor R3, and the source SQ3 of the field effect transistor Q3 is connected to the ground terminal 12. The field effect transistor Q3 is, for example, a GaN-based GIT.

[0051] The driver circuit 1a and the switch system 3a according to the second embodiment, like the driver circuit 1 and the switch system 3 according to the first embodiment, are provided with a speed-up circuit 14, thereby enabling the turn-on time of the semiconductor switch element 2 to be shortened without using a large-capacity capacitor.

[0052] Furthermore, the driver circuit 1a according to the second embodiment can suppress the current flowing from the DC power supply 4 connected between the power supply terminal 11 and the ground terminal 12 to the second field effect transistor Q2 via the power supply terminal 11 and the first field effect transistor Q1 to the current of the constant current circuit 17, thereby making it possible to reduce power loss.

[0053] (Embodiment 3) A driver circuit 1b according to a third embodiment and a switch system 3b including the same will be described below with reference to FIG.

[0054] The driver circuit 1b according to the third embodiment is substantially the same as the driver circuit 1 according to the first embodiment (see FIG. 1), but differs from the driver circuit 1 according to the first embodiment in that it includes a constant voltage circuit 18 instead of the resistor R4. Regarding the driver circuit 1b and the switch system 3b according to the third embodiment, components similar to those of the driver circuit 1 and the switch system 3 according to the first embodiment are denoted by the same reference numerals and descriptions thereof will be omitted.

[0055] A driver circuit 1b according to the third embodiment includes a series circuit of a resistor R3 and a constant voltage circuit 18, instead of the resistive voltage divider circuit 16 of the driver circuit 1 according to the first embodiment. The resistor R3 is connected to a power supply terminal 11. The constant voltage circuit 18 is provided between the resistor R3 and a ground terminal 12. In the driver circuit 1b, a node N3 between the resistor R3 and the constant voltage circuit 18 is connected to a gate GQ2 of a second field effect transistor Q2.

[0056] The constant voltage circuit 18 is configured by connecting a plurality of diodes D1 in series. In the constant voltage circuit 18, the anode of the diode D1 that is closest to the resistor R3 in terms of the circuit is connected to the resistor R3, and the cathode of the diode D1 that is farthest from the resistor R3 in terms of the circuit is connected to the ground terminal 12. The number of diodes D1 connected in series in the constant voltage circuit 18 is determined so that the total value of the forward voltages (Vf) of the plurality of diodes D1 is greater than the threshold voltage of the second field effect transistor Q2 and so that the second field effect transistor Q2 is not broken.

[0057] The driver circuit 1b and the switch system 3b according to the third embodiment, like the driver circuit 1 and the switch system 3 according to the first embodiment, are provided with a speed-up circuit 14, thereby enabling the turn-on time of the semiconductor switch element 2 to be shortened without using a large-capacity capacitor.

[0058] Furthermore, the driver circuit 1b according to the third embodiment includes the constant voltage circuit 18, and therefore, it is possible to prevent an excessive gate voltage from being applied to the second field effect transistor Q2, regardless of the magnitude of the voltage applied between the power supply terminal 11 and the ground terminal 12.

[0059] (Embodiment 4) A driver circuit 1c according to a fourth embodiment and a switch system 3c including the same will be described below with reference to FIG.

[0060] The driver circuit 1c according to the fourth embodiment is substantially the same as the driver circuit 1 according to the first embodiment (see FIG. 1), but differs from the driver circuit 1 according to the first embodiment in that it includes a speed-up circuit 14c instead of the speed-up circuit 14. Regarding the driver circuit 1c and the switch system 3c according to the fourth embodiment, components similar to those of the driver circuit 1 and the switch system 3 according to the first embodiment are denoted by the same reference numerals and descriptions thereof will be omitted.

[0061] In the speed-up circuit 14c, the second field-effect transistor Q2 is configured by Darlington-connecting a third field-effect transistor Q21 and a fourth field-effect transistor Q22. Thus, the speed-up circuit 14c includes a first field-effect transistor Q1 and a second field-effect transistor Q2 configured by a Darlington circuit of the third field-effect transistor Q21 and the fourth field-effect transistor Q22. Each of the third field-effect transistor Q21 and the fourth field-effect transistor Q22 is, for example, a GaN-based GaN transistor.

[0062] The third field-effect transistor Q21 has a gate GQ21, a drain DQ21, and a source SQ21. The fourth field-effect transistor Q22 has a gate GQ22, a drain DQ22, and a source SQ22. The current capacity of the fourth field-effect transistor Q22 is larger than that of the third field-effect transistor Q21. The gate width of the fourth field-effect transistor Q22 is larger than that of the third field-effect transistor Q21. For example, if the gate width of the semiconductor switch element 2 is 400 mm, as in the switch system 3 of embodiment 1, in the driver circuit 1c and switch system 3c of embodiment 4, the gate width of the fourth field-effect transistor Q22 is the same as that of the first field-effect transistor Q1, e.g., 10 mm. In contrast, the gate width of the third field-effect transistor Q21 is, e.g., 1 mm.

[0063] In the speed-up circuit 14c, the gate GQ21 of the third field-effect transistor Q21 is connected to the output terminal 161 of the resistive voltage divider circuit 16. The source SQ22 of the fourth field-effect transistor Q22 is connected to the gate 21 of the semiconductor switch element 2.

[0064] The driver circuit 1c and the switch system 3c according to the fourth embodiment include the speed-up circuit 14c, thereby shortening the turn-on time of the semiconductor switch element 2 without using a large-capacity capacitor.

[0065] Furthermore, in the driver circuit 1c according to the fourth embodiment, the current amplification factor of the second field-effect transistor Q2 can be increased compared to the driver circuit 1 according to the first embodiment, and therefore the resistance values ​​of the resistors R3 and R4 of the resistive voltage divider circuit 16 can be increased. As a result, the driver circuit 1c according to the fourth embodiment can reduce power loss.

[0066] (Embodiment 5) A driver circuit 1d according to a fifth embodiment and a switch system 3d including the same will be described below with reference to FIG.

[0067] The driver circuit 1d according to the fifth embodiment is substantially the same as the driver circuit 1 according to the first embodiment (see FIG. 1), but differs from the driver circuit 1 according to the first embodiment in that it includes a speed-up circuit 14d instead of the speed-up circuit 14. Regarding the driver circuit 1d and the switch system 3d according to the fifth embodiment, components similar to those of the driver circuit 1 and the switch system 3 according to the first embodiment are denoted by the same reference numerals and descriptions thereof will be omitted.

[0068] The speed-up circuit 14d includes a normally-on second field-effect transistor Q2d instead of the normally-off second field-effect transistor Q2 in the speed-up circuit 14. The second field-effect transistor Q2d is a GaN-based GIT. The second field-effect transistor Q2d has a gate GQ2d, a drain DQ2d, and a source SQ2d. The gate GQ2 of the normally-off second field-effect transistor Q2 includes a p-type layer, similar to the gate 21 of the semiconductor switch element 2. In contrast, the gate GQ2d of the normally-on second field-effect transistor Q2d has a recess structure provided below the gate 21 on the surface of the second nitride semiconductor layer (e.g., an undoped AlGaN layer) so that the thickness of the second nitride semiconductor layer below the gate 21 is thinner than that below the source 22. The gate GQ2d of the normally-on second field effect transistor Q2d may be configured by a gate electrode that forms a Schottky junction with the second nitride semiconductor layer without including a p-type layer.

[0069] The driver circuit 1d and the switch system 3d according to the fifth embodiment include a speed-up circuit 14d, thereby shortening the turn-on time of the semiconductor switch element 2 without using a large-capacity capacitor.

[0070] Furthermore, in the driver circuit 1d according to the fifth embodiment, the second field effect transistor Q2d of the speed-up circuit 14d is a normally-on field effect transistor, and therefore the gate voltage of the first field effect transistor Q1 can be increased even when the output voltage of the DC power supply 4 is small (for example, 5 V).

[0071] In the switch system 3 according to the first embodiment, for example, if the threshold voltages of the second field-effect transistor Q2 and the semiconductor switch element 2 are each set to +2V and the predetermined value Vg1 is set to +3V, then when the output voltage of the DC power supply 4 is 5V, the turn-on speed of the semiconductor switch element 2 cannot be increased. If the gate voltage of the second field-effect transistor Q2 in its on state is set to 3V, when the semiconductor switch element 2 is turned on, current flows through the first field-effect transistor Q1 and the second field-effect transistor Q2, and the gate voltage of the semiconductor switch element 2 rises. However, because the second field-effect transistor Q2 turns off when the gate voltage of the semiconductor switch element 2 reaches 1V, the gate voltage of the semiconductor switch element 2 slowly rises to the predetermined value Vg1 (e.g., 3V).

[0072] In contrast, in a switch system 3d according to embodiment 5, for example, if the threshold voltages of the second field-effect transistor Q2d and the semiconductor switch element 2 are set to −3V and +2V, respectively, and the predetermined value Vg1 is set to +3V, the turn-on speed of the semiconductor switch element 2 can be increased even when the output voltage of the DC power supply 4 is 5V. If the gate voltage of the second field-effect transistor Q2d in its on state is set to 1V, when the semiconductor switch element 2 is turned on, current flows through the first field-effect transistor Q1 and the second field-effect transistor Q2d, and the gate voltage of the semiconductor switch element 2 increases. When the gate voltage of the semiconductor switch element 2 reaches 4V, the second field-effect transistor Q2d turns off, and the gate voltage of the semiconductor switch element 2 slowly decreases to the predetermined value Vg1 (3V). Therefore, in the driver circuit 1d and the switch system 3d according to the fifth embodiment, when the semiconductor switch element 2 is turned on, the gate voltage of the semiconductor switch element 2 can be temporarily increased to a value greater than the predetermined value Vg1, thereby shortening the turn-on time.

[0073] (Embodiment 6) A driver circuit 1e according to a sixth embodiment and a switch system 3e including the same will be described below with reference to FIG.

[0074] The driver circuit 1e according to the sixth embodiment is substantially the same as the driver circuit 1 (FIG. 1) according to the first embodiment, but differs from the driver circuit 1 according to the first embodiment in that it includes a constant current circuit 19 instead of the resistor R3. Regarding the driver circuit 1e and the switch system 3e according to the sixth embodiment, components similar to those of the driver circuit 1 and the switch system 3 according to the first embodiment are denoted by the same reference numerals and descriptions thereof will be omitted.

[0075] A driver circuit 1e according to the sixth embodiment includes a series circuit of a constant current circuit 19 and a resistor R4, instead of the resistive voltage divider circuit 16 of the driver circuit 1 according to the first embodiment. The constant current circuit 19 is connected to a power supply terminal 11. The resistor R4 is connected between the constant current circuit 19 and a ground terminal 12. In the driver circuit 1e, a gate GQ2 of a second field effect transistor Q2 is connected to a node N4 between the constant current circuit 19 and the resistor R4.

[0076] The constant current circuit 19 includes, for example, a field-effect transistor Q8 having a gate GQ8, a drain DQ8, and a source SQ8, and is configured by shorting the gate GQ8 and the source SQ8 of the field-effect transistor Q8. In the constant current circuit 19, the drain DQ8 of the field-effect transistor Q8 is connected to the power supply terminal 11, and the source SQ8 of the field-effect transistor Q8 is connected to a resistor R4. The field-effect transistor Q8 is, for example, a GaN-based GIT. Since the gate GQ8 and the source SQ8 of the field-effect transistor Q8 are shorted, the field-effect transistor Q8 has voltage-current characteristics as shown by the solid line in FIG. 8, where Vd is the drain voltage and Id is the drain current. In FIG. 8, "VCC" is the output voltage of the DC power supply 4. Furthermore, "VCC / R4" in FIG. 8 is the value obtained by dividing the output voltage of the DC power supply 4 by the resistance value of the resistor R4. In FIG. 8, the difference between the intersection of the line connecting VCC / R4 and VCC with the voltage-current characteristic and the horizontal axis (drain voltage), and the intersection of the horizontal axis with the perpendicular line, is the maximum value of the gate voltage of the second field effect transistor Q2.

[0077] The driver circuit 1e and the switch system 3e according to the sixth embodiment, like the driver circuit 1 and the switch system 3 according to the first embodiment, are provided with a speed-up circuit 14, thereby enabling the turn-on time of the semiconductor switch element 2 to be shortened without using a large-capacity capacitor.

[0078] Furthermore, since the driver circuit 1e according to the sixth embodiment includes the constant current circuit 19, the current flowing through the second field effect transistor Q2 can be limited even if the output voltage of the DC power supply 4 changes, thereby reducing the power loss of the driver circuit 1e and stabilizing the gate voltage of the second field effect transistor Q2.

[0079] (Embodiment 7) A driver circuit 1f according to a seventh embodiment and a switch system 3f including the same will be described below with reference to FIG.

[0080] The driver circuit 1f according to the seventh embodiment is substantially the same as the driver circuit 1 according to the first embodiment, but differs from the driver circuit 1 according to the first embodiment in that it further includes a DCFL (Direct Coupled FET Logic) circuit 10. Regarding the driver circuit 1f and the switch system 3f according to the seventh embodiment, components similar to those of the driver circuit 1 and the switch system 3 according to the first embodiment are denoted by the same reference numerals and descriptions thereof will be omitted.

[0081] The DCFL circuit 10 has an input terminal 101 and an output terminal 102 and is connected between a power supply terminal 11 and a ground terminal 12 .

[0082] In the driver circuit 1f, the input terminal 101 of the DCFL circuit 10 is connected to the signal input terminal 13. In the driver circuit 1f, the output terminal 102 of the DCFL circuit 10 is connected to the gate 21 of the semiconductor switch element 2 via the impedance element 15.

[0083] The DCFL circuit 10 is a logic circuit including a field effect transistor Q4 and a field effect transistor Q5. The field effect transistor Q4 has a gate GQ4, a drain DQ4, and a source SQ4. The field effect transistor Q5 has a gate GQ5, a drain DQ5, and a source SQ5. The field effect transistor Q4 is a normally-on GaN-based GIT. The field effect transistor Q5 is a normally-off GaN-based GIT.

[0084] In the DCFL circuit 10, the gate GQ4 and source SQ4 of the field effect transistor Q4 are shorted, and the field effect transistor Q4 operates as a constant current element.

[0085] In the field-effect transistor Q5, the gate GQ5 is connected to the signal input terminal 13. In the DCFL circuit 10, the gate GQ5 of the field-effect transistor Q5 forms the input terminal 101, and the connection point between the source SQ4 of the field-effect transistor Q4 and the drain DQ5 of the field-effect transistor Q5 forms the output terminal 102 of the DCFL circuit 10.

[0086] DCFL circuit 10 outputs an output logic 0 from output terminal 102 when the input logic of input terminal 101 is 1, and outputs an output logic 1 from output terminal 102 when the input logic of input terminal 101 is 0. In DCFL circuit 10, if a potential level equal to or greater than the threshold voltage of field-effect transistor Q5 is defined as input logic 1 and a potential level less than the threshold voltage of field-effect transistor Q5 is defined as input logic 0, when the input logic is 1, field-effect transistor Q5 is on and output terminal 102 has the same potential as ground terminal 12.

[0087] In the DCFL circuit 10, the impedance of the field-effect transistor Q5 in the on state is smaller than the impedance of the field-effect transistor Q4 in the on state so that the output logic is 0 when the input logic is 1. Here, the gate width of the field-effect transistor Q5 is larger than the gate width of the field-effect transistor Q4.

[0088] Furthermore, the driver circuit 1f further includes a resistor R6 provided between the DCFL circuit 10 and the power supply terminal 11, but this is not essential. Care must be taken when designing the circuit because if the resistance value of the resistor R6 is made larger than that of the resistor R5, the resistance value of the resistor R6 will determine the gate voltage of the semiconductor switch element 2 in the steady-on state.

[0089] The driver circuit 1f further includes a gate resistor R7 provided between the gate GQ5 of the field effect transistor Q5 and the signal input terminal 13. The gate resistor R7 is provided to prevent the gate GQ5 of the field effect transistor Q5 from being destroyed by an overvoltage when the gate GQ5 is directly connected to the driver IC5.

[0090] The driver circuit 1f further includes a field-effect transistor Q6 provided between the node N1 and the ground terminal 12. The field-effect transistor Q6 has a gate GQ6, a drain DQ6, and a source SQ6. The field-effect transistor Q6 is a normally-off GaN-based GIT. The field-effect transistor Q6 is an element provided to increase the turn-off speed of the semiconductor switch element 2, and has a drain DQ6 connected to the gate of the semiconductor switch element 2 and a source SQ6 connected to the source 22 of the semiconductor switch element 2. The field-effect transistor Q6 is provided to form a path that does not pass through the impedance element 15, as a path for extracting the gate charge of the semiconductor switch element 2 when the semiconductor switch element 2 is turned off.

[0091] The driver circuit 1f also includes a gate resistor R8 provided between the gate GQ6 of the field-effect transistor Q6 and the signal input terminal 13. The gate resistor R8 is provided to prevent the gate GQ6 of the field-effect transistor Q6 from being destroyed by an overvoltage when the gate GQ6 is directly connected to the driver IC5. From the viewpoint of increasing the turn-on speed of the field-effect transistor Q6 and thereby increasing the turn-off speed of the semiconductor switch element 2, it is preferable that the resistance value of the gate resistor R8 be small.

[0092] The driver circuit 1f further includes a field-effect transistor Q7 connected in parallel to the gate resistor R8. The field-effect transistor Q7 has a gate GQ7, a drain DQ7, and a source SQ7. The field-effect transistor Q7 is a normally-off GaN-based GIT. The source SQ7 of the field-effect transistor Q7 is connected to one end of the gate resistor R8 on the field-effect transistor Q6 side, and the drain DQ7 is connected to the other end of the gate resistor R8 on the signal input terminal 13 side. The gate GQ7 and source SQ7 of the field-effect transistor Q7 are short-circuited, and the field-effect transistor Q7 functions as a diode. The field-effect transistor Q7 is an element for increasing the turn-off speed of the field-effect transistor Q6.

[0093] An example of the gate widths of the semiconductor switch element 2, field effect transistors Q1, Q2, Q4 to Q7, and circuit constants of the resistors R2 to R8 in the switch system 3f will be described below, assuming that the output voltage of the DC power supply 4 is, for example, 12V.

[0094] The gate width of the semiconductor switch element 2 is, for example, 400 mm. The gate width of the first field effect transistor Q1 is, for example, 10 mm. The gate width of the second field effect transistor Q2 is, for example, 10 mm. The gate width of the field effect transistor Q4 is, for example, 0.1 mm. The gate width of the field effect transistor Q5 is, for example, 1 mm. The gate width of the field effect transistor Q6 is, for example, 10 mm. The gate width of the field effect transistor Q7 is, for example, 1 mm. The resistance value of the second gate resistor R2 is, for example, 1 kΩ. The resistance value of the resistor R3 is, for example, 5 kΩ. The resistance value of the resistor R4 is, for example, 2 kΩ. The resistance value of the resistor R5 constituting the impedance element 15 is, for example, 500 Ω. The resistance value of the resistor R6 is, for example, 100 Ω. The resistance value of the gate resistor R7 is, for example, 5 kΩ. The resistance value of the gate resistor R8 is, for example, 1 kΩ.

[0095] FIG. 10 is a timing chart schematically showing the relationship between the drive signal input to the signal source 6, the output signal of the driver IC5, the gate voltage of the first field effect transistor Q1 (first FET), the gate voltage of the second field effect transistor Q2 (second FET), the gate voltage of the semiconductor switch element 2, the drain-source voltage of the semiconductor switch element 2, the gate voltage of the field effect transistor Q5 (fifth FET), and the gate voltage of the field effect transistor Q6 (sixth FET).

[0096] In the driver circuit 1 according to the above-described first embodiment, when the second field-effect transistor Q2 is in the on state and the potential level of the signal input to the signal input terminal 13 (the output signal of the driver IC5) changes from the first potential level VL1 to the second potential level VL2 higher than the first potential level VL1, the first field-effect transistor Q1 turns on and causes a current larger than the current passing through the impedance element 15 to flow to the gate 21 of the semiconductor switch element 2, thereby making the gate voltage of the semiconductor switch element 2 larger than a predetermined value Vg1 larger than the threshold voltage of the semiconductor switch element 2, and thereafter continues to cause a current to flow to the gate 21 of the semiconductor switch element 2 through the impedance element 15, thereby bringing the semiconductor switch element 2 into a steady on state.

[0097] The driver circuit 1f and the switch system 3f according to the seventh embodiment, like the driver circuit 1 and the switch system 3 according to the first embodiment, are provided with a speed-up circuit 14, thereby enabling the turn-on time of the semiconductor switch element 2 to be shortened without using a large-capacity capacitor.

[0098] Furthermore, in the driver circuit 1f according to the seventh embodiment, the DCFL circuit 10 is provided, so that the turn-off speed of the semiconductor switch element 2 can be increased.

[0099] Furthermore, the driver circuit 1f according to the seventh embodiment includes the DCFL circuit 10, which allows it to be configured as a monolithic integrated circuit.

[0100] If the driver circuit 1f includes a field-effect transistor Q4, it may or may not include a resistor R6. Also, if the driver circuit 1f includes a resistor R6, it may or may not include a field-effect transistor Q4. By including the field-effect transistor Q4, a roughly constant current flows even when the output voltage of the DC power supply 4 changes, making it easy to handle. If the output voltage of the DC power supply 4 is fixed, it may be possible to include only the resistor R6 out of the field-effect transistor Q4 and the resistor R6. When only the resistor R6 is included, the resistance value of the resistor R6 is, for example, 10 kΩ.

[0101] (Embodiment 8) A driver circuit 1g according to the eighth embodiment and a switch system 3g including the same will be described below with reference to FIG.

[0102] A driver circuit 1g according to the eighth embodiment is a driver circuit for a current-driven semiconductor switch element 2A. Regarding the driver circuit 1g and the switch system 3g according to the eighth embodiment, the same components as those of the driver circuit 1 and the switch system 3 according to the first embodiment are denoted by the same reference numerals and description thereof will be omitted.

[0103] The semiconductor switch element 2A is a dual-gate bidirectional switch element having two gates 21 and two sources 22. The two gates 21 and the two sources 22 correspond one-to-one. For ease of explanation, one of the two gates 21 may be referred to as a first gate 21A, and the other as a second gate 21B below. Furthermore, of the two sources 22, the source 22 corresponding to the first gate 21A may be referred to as a first source 22A, and the source 22 corresponding to the second gate 21B may be referred to as a second source 22B.

[0104] Below, the semiconductor switch element 2A will be briefly described, followed by a description of the driver circuit 1g and the switch system 3g.

[0105] The semiconductor switch element 2A is a type of GaN-based GIT. The semiconductor switch element 2A includes, for example, a substrate, a buffer layer, a first nitride semiconductor layer, a second nitride semiconductor layer, a first source electrode, a first gate electrode, a second gate electrode, a second source electrode, a first p-type layer, and a second p-type layer. The buffer layer is formed on the substrate. The first nitride semiconductor layer is formed on the buffer layer. The second nitride semiconductor layer is formed on the first nitride semiconductor layer. The first source electrode, the first gate electrode, the second gate electrode, and the second source electrode are formed on the second nitride semiconductor layer. The first p-type layer is interposed between the first gate electrode and the second nitride semiconductor layer. The second p-type layer is interposed between the second gate electrode and the second nitride semiconductor layer. In the semiconductor switch element 2A, the first source 22A includes a first source electrode. The first gate 21A includes a first gate electrode and a first p-type layer. The second gate 21B includes a second gate electrode and a second p-type layer. The second source 22B includes a second source electrode. The substrate is, for example, a silicon substrate. The buffer layer is, for example, an undoped GaN layer. The first nitride semiconductor layer is, for example, an undoped GaN layer. The second nitride semiconductor layer is, for example, an undoped AlGaN layer. Each of the first p-type layer and the second p-type layer is, for example, a p-type AlGaN layer. The buffer layer, the first nitride semiconductor layer, and the second nitride semiconductor layer may each contain impurities such as Mg, H, Si, C, and O that are inevitably mixed in during growth by MOVPE (Metal Organic Vapor Phase Epitaxy) or the like.

[0106] In the semiconductor switch element 2A, the second nitride semiconductor layer and the first nitride semiconductor layer form a heterojunction. In the first nitride semiconductor layer, two-dimensional electron gas is generated in the vicinity of the heterojunction. The region containing the two-dimensional electron gas (hereinafter also referred to as the "two-dimensional electron gas layer") can function as an n-channel layer (electron conduction layer).

[0107] Hereinafter, for convenience of explanation, a state in which a voltage equal to or greater than the first threshold voltage (e.g., 1.3 V) is not applied between the first gate 21A and the first source 22A will also be referred to as an off state of the first gate 21A. A state in which a voltage equal to or greater than the first threshold voltage is applied between the first gate 21A and the first source 22A, with the first gate 21A acting as the high potential side, will also be referred to as an on state of the first gate 21A. A state in which a voltage equal to or greater than the second threshold voltage (e.g., 1.3 V) is not applied between the second gate 21B and the second source 22B will also be referred to as an off state of the second gate 21B. A state in which a voltage equal to or greater than the second threshold voltage is applied between the second gate 21B and the second source 22B, with the second gate 21B acting as the high potential side, will also be referred to as an on state of the second gate 21B.

[0108] The semiconductor switch element 2A includes the first p-type layer and the second p-type layer described above, thereby realizing a normally-off transistor.

[0109] The semiconductor switch element 2A can switch among a bidirectional on state, a bidirectional off state, a first diode state, and a second diode state according to a combination of a first gate voltage and a second gate voltage applied to the first gate 21A and the second gate 21B, respectively. The first gate voltage is a voltage applied between the first gate 21A and the first source 22A. The second gate voltage is a voltage applied between the second gate 21B and the second source 22B. The bidirectional on state is a state in which current passes in both directions (a first direction A1 and a second direction A2 opposite to the first direction A1). The bidirectional off state is a state in which current passes in both directions. The first diode state is a state in which current passes in the first direction A1. The second diode state is a state in which current passes in the second direction A2.

[0110] The semiconductor switch element 2A is in a bidirectional ON state when the first gate 21A is in the ON state and the second gate 21B is in the ON state. The semiconductor switch element 2A is in a bidirectional OFF state when the first gate 21A is in the OFF state and the second gate 21B is in the OFF state. The semiconductor switch element 2A is in a first diode state when the first gate 21A is in the OFF state and the second gate 21B is in the ON state. The semiconductor switch element 2A is in a second diode state when the first gate 21A is in the ON state and the second gate 21B is in the OFF state.

[0111] Next, the driver circuit 1g and the switch system 3g will be described.

[0112] The driver circuit 1g includes two speed-up circuits 14. In the following, of the two speed-up circuits 14, the speed-up circuit 14 connected to the first gate 21A of the semiconductor switch element 2A may be referred to as the first speed-up circuit 14A, and the speed-up circuit 14 connected to the second gate 21B may be referred to as the second speed-up circuit 14B.

[0113] The first speed-up circuit 14A and the second speed-up circuit 14B have the same circuit configuration.

[0114] The driver circuit 1g also has two sets of power supply terminals 11, ground terminals 12, and signal input terminals 13, and the two sets correspond one-to-one to the two speed-up circuits 14. Hereinafter, for ease of explanation, the power supply terminal 11, ground terminal 12, and signal input terminal 13 of one of the two sets will be referred to as a first power supply terminal 11A, a first ground terminal 12A, and a first signal input terminal 13A, and the power supply terminal 11, ground terminal 12, and signal input terminal 13 of the other set will be referred to as a second power supply terminal 11B, a second ground terminal 12B, and a second signal input terminal 13B. The first power supply terminal 11A, the first ground terminal 12A, and the first signal input terminal 13A correspond to the first gate 21A and the first source 22A of the semiconductor switch element 2A, and the second power supply terminal 11B, the second ground terminal 12B, and the second signal input terminal 13B correspond to the second gate 21B and the second source 22B of the semiconductor switch element 2A.

[0115] The driver circuit 1g also includes two resistive voltage divider circuits 16, which correspond one-to-one to the two sets described above. In Fig. 11, the resistive voltage divider circuit 16 corresponding to the first power supply terminal 11A, the first ground terminal 12A, and the first signal input terminal 13A is designated as the first resistive voltage divider circuit 16A, and the resistive voltage divider circuit 16 corresponding to the second power supply terminal 11B, the second ground terminal 12B, and the second signal input terminal 13B is designated as the second resistive voltage divider circuit 16B.

[0116] The driver circuit 1g also includes two impedance elements 15. In the driver circuit 1g, one of the two impedance elements 15 is provided between the first gate 21A and the first signal input terminal 13A, and the other impedance element 15 is provided between the second gate 21B and the second signal input terminal 13B.

[0117] Hereinafter, for convenience of explanation, the DC power supply 4 connected between the first power supply terminal 11A and the first ground terminal 12A of the driver circuit 1g will be referred to as the first DC power supply 4A, and the DC power supply 4 connected between the second power supply terminal 11B and the second ground terminal 12B will be referred to as the second DC power supply 4B. Also, with regard to the series circuit of the driver IC 5 and the signal source 6 connected between the first signal input terminal 13A and the first ground terminal 12A of the driver circuit 1g, the driver IC 5 will be referred to as the first driver IC 5A, and the signal source 6 will be referred to as the first signal source 6A. Also, with regard to the series circuit of the driver IC 5 and the signal source 6 connected between the second signal input terminal 13B and the second ground terminal 12B of the driver circuit 1g, the driver IC 5 will be referred to as the second driver IC 5B, and the signal source 6 will be referred to as the second signal source 6B.

[0118] The first DC power source 4A and the second DC power source 4B have the same output voltage, but may have different output voltages.

[0119] The first signal source 6A and the second signal source 6B have the same second potential level VL2, but may have different second potential levels VL2.

[0120] The driver circuit 1g and the switch system 3g according to the eighth embodiment include two speed-up circuits 14, thereby shortening the turn-on time of the semiconductor switch element 2A without using a large-capacity capacitor.

[0121] Furthermore, when the driver circuit 1g according to the eighth embodiment is configured as a monolithic integrated circuit, it is not necessary to include a large-capacity capacitor, which allows for miniaturization. Furthermore, when the switch system 3g according to the eighth embodiment is configured as a monolithic integrated circuit, it is not necessary to include a large-capacity capacitor, which allows for miniaturization.

[0122] The above-described first to eighth embodiments are merely examples of various embodiments of the present disclosure. The above-described first to eighth embodiments can be modified in various ways depending on the design and the like, as long as the object of the present disclosure can be achieved.

[0123] For example, the resistive voltage divider circuit 16 in the driver circuit 1 according to the first embodiment may include at least two resistors R3 and R4, and may also include three or more resistors connected in series.

[0124] In addition to the first field effect transistor Q1 and the second field effect transistor Q2, the speed-up circuit 14 may also include one or more field effect transistors connected in series or parallel to the second field effect transistor Q2.

[0125] Furthermore, the circuit configurations of the constant current circuit 17, the constant voltage circuit 18, and the constant current circuit 19 are merely examples and are not particularly limited, but by employing the above configurations, it becomes easier to form a monolithic integrated circuit.

[0126] Furthermore, the p-type layer in the semiconductor switch element 2 of the switch systems 3 to 3f is not limited to a p-type AlGaN layer, and may be, for example, a p-type GaN layer or a p-type metal oxide semiconductor layer. The p-type metal oxide semiconductor layer is, for example, a NiO layer. The NiO layer may contain, as an impurity, at least one alkali metal selected from the group consisting of lithium, sodium, potassium, rubidium, and cesium. The NiO layer may also contain, for example, a transition metal such as silver or copper that becomes monovalent when added as an impurity. The first p-type layer and the second p-type layer in the semiconductor switch element 2A of the switch system 3g are similar to the p-type layer in the semiconductor switch element 2.

[0127] Each of the semiconductor switch element 2 and the semiconductor switch element 2A may include one or more nitride semiconductor layers between the buffer layer and the first nitride semiconductor layer. The buffer layer is not limited to a single-layer structure and may have, for example, a superlattice structure.

[0128] Furthermore, the substrate in each of the semiconductor switch element 2 and the semiconductor switch element 2A is not limited to a silicon substrate, but may be, for example, a GaN substrate, a SiC substrate, a sapphire substrate, or the like.

[0129] The semiconductor switch element 2A can be applied to electrical devices such as a multilevel inverter, a dimmer, and a matrix converter that performs AC-AC power conversion.

[0130] (Aspect) Based on the above-described embodiments, the present specification discloses the following aspects.

[0131] A driver circuit (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) according to a first aspect is a driver circuit for a current-driven semiconductor switch element (2; 2A) having a gate (21) and a source (22) corresponding to the gate (21), and includes a power supply terminal (11), a ground terminal (12), a signal input terminal (13), a speed-up circuit (14; 14c; 14d), and an impedance element (15). The ground terminal (12) is connected to the source (22; 22A, 22B) of the semiconductor switch element (2; 2A). The speed-up circuit (14; 14c; 14d) is provided between the power supply terminal (11; 11A, 11B) and the gate (21) of the semiconductor switch element (2; 2A). The impedance element (15) is provided between a node (N1) between the speed-up circuit (14; 14c; 14d) and the gate (21) of the semiconductor switch element (2; 2A) and the signal input terminal (13; 13A, 13B). The speed-up circuit (14; 14c; 14d) includes a first field-effect transistor (Q1) and a second field-effect transistor (Q2; Q2d). The second field-effect transistor (Q2; Q2d) is connected in series with the first field-effect transistor (Q1) and to the gate (21) of the semiconductor switch element (2; 2A). The impedance of the impedance element (15) is higher than the impedance of the speed-up circuit (14; 14c; 14d) when both the first field-effect transistor (Q1) and the second field-effect transistor (Q2; Q2d) are in an on state.

[0132] The driver circuit (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) according to the first aspect can shorten the turn-on time of the semiconductor switch element (2; 2A) without using a large-capacity capacitor.

[0133] The driver circuit (1; 1c; 1d; 1f; 1g) according to the second aspect is the same as that of the first aspect, and further includes a resistive voltage divider circuit (16). The resistive voltage divider circuit (16) is provided between the power supply terminal (11) and the ground terminal (12). The gate (Q2G) of the second field effect transistor (Q2) is connected to the output terminal (161) of the resistive voltage divider circuit (16).

[0134] In the driver circuit (1; 1c; 1d; 1f; 1g) according to the second aspect, the gate voltage of the second field effect transistor (Q2) can be determined by the resistive voltage divider circuit (16).

[0135] The driver circuit (1a) according to the third aspect is the same as that according to the first aspect, but further includes a resistor (R3) and a constant current circuit (17). The resistor (R3) is connected to a power supply terminal (11). The constant current circuit (17) is provided between the resistor (R3) and a ground terminal (12). A gate (Q2G) of a second field effect transistor (Q2) is connected to a node (N2) between the resistor (R3) and the constant current circuit (17).

[0136] The driver circuit (1a) according to the third aspect can, for example, suppress the current flowing from the DC power supply (4) connected between the power supply terminal (11) and the ground terminal (12) through the power supply terminal (11) and the first field effect transistor (Q1) to the second field effect transistor (Q2) to the current of the constant current circuit (17), thereby making it possible to reduce power loss.

[0137] A driver circuit (1b) according to a fourth aspect is the same as that of the first aspect, but further includes a resistor (R3) and a constant voltage circuit (18). The resistor (R3) is connected to a power supply terminal (11). The constant voltage circuit (18) is provided between the resistor (R3) and a ground terminal (12). The constant voltage circuit (18) is configured by connecting a plurality of diodes (D1) in series. In the driver circuit (1b), a node (N3) between the resistor (R3) and the constant voltage circuit (18) is connected to a gate (GQ2) of a second field effect transistor (Q2).

[0138] The driver circuit (1b) according to the fourth aspect can prevent an excessive gate voltage from being applied to the second field effect transistor (Q2), regardless of the magnitude of the voltage applied between the power supply terminal (11) and the ground terminal (12).

[0139] In the driver circuit (1c) according to the fifth aspect, in the second aspect, the second field effect transistor (Q2) is configured by Darlington-connecting a third field effect transistor (Q21) and a fourth field effect transistor (Q22). The third field effect transistor (Q21) has a gate (GQ21) and a source (SQ21). The fourth field effect transistor (Q22) has a gate (GQ22) and a source (SQ22). The current capacity of the fourth field effect transistor (Q22) is larger than the current capacity of the third field effect transistor (Q21). The gate (GQ21) of the third field effect transistor (Q21) is connected to the output terminal (161) of the resistive voltage divider circuit (16). The source (SQ22) of the fourth field effect transistor (Q22) is connected to the gate (21) of the semiconductor switch element (2).

[0140] In the driver circuit (1c) according to the fifth aspect, the current amplification factor of the second field-effect transistor (Q2) can be increased, and therefore the resistance value of each resistor (R3, R4) of the resistive voltage divider circuit (16) can be increased, thereby reducing power loss in the driver circuit (1c) according to the fifth aspect.

[0141] In a driver circuit (1d) according to a sixth aspect, in any one of the first to fifth aspects, the second field effect transistor (Q2d) is a normally-on type field effect transistor.

[0142] In the driver circuit (1d) according to the sixth aspect, even when the voltage applied between the power supply terminal (11) and the ground terminal (12) is small (for example, 5 V), the gate voltage of the first field effect transistor (Q1) can be increased.

[0143] A driver circuit (1e) according to a seventh aspect is the same as that of the first aspect, but further includes a constant current circuit (19) and a resistor (R4). The constant current circuit (19) is connected to a power supply terminal (11). The resistor (R4) is provided between the constant current circuit (19) and a ground terminal (12). A gate (GQ2) of a second field effect transistor (Q2) is connected to a node (N4) between the constant current circuit (19) and the resistor (R4).

[0144] In the driver circuit (1e) according to the seventh aspect, even if the voltage applied between the power supply terminal (11) and the ground terminal (12) changes, the current flowing through the second field effect transistor (Q2) can be limited, thereby reducing power loss and stabilizing the gate voltage of the second field effect transistor (Q2).

[0145] A driver circuit (1f) according to an eighth aspect is any one of the first to seventh aspects, and further includes a DCFL circuit (10). The DCFL circuit (10) has an input terminal (101) and an output terminal (102) and is provided between a power supply terminal (11) and a ground terminal (12). The input terminal (101) of the DCFL circuit (10) is connected to a signal input terminal (13). The output terminal (102) of the DCFL circuit (10) is connected to a gate (21) of a semiconductor switch element (2) via an impedance element (15).

[0146] In the driver circuit (1f) according to the eighth aspect, the turn-off time of the semiconductor switch element (2) can be shortened.

[0147] In a driver circuit (1g) according to a ninth aspect, in any one of the first to eighth aspects, the semiconductor switch element (2A) is a dual-gate bidirectional switch element having two gates (21) and two sources (22). The driver circuit (1g) includes two speed-up circuits (14). One of the two speed-up circuits (14) is connected to a first gate (21A) that is one of the two gates 21, and the remaining speed-up circuit (14) is connected to a second gate (21B) that is the other of the two gates 21.

[0148] The driver circuit (1g) according to the ninth aspect can shorten the turn-on time of the semiconductor switch element (2A).

[0149] A driver circuit (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) according to a tenth aspect is configured in any one of the first to ninth aspects, wherein the semiconductor switch element (2; 2A) is a GaN-based semiconductor switch element.

[0150] In the driver circuit (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) according to the tenth aspect, the turn-on time of the semiconductor switch (2; 2A), which is a GaN-based semiconductor switch, can be shortened.

[0151] A driver circuit (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) according to an eleventh aspect is a driver circuit for a current-driven semiconductor switch element (2; 2A) having a gate (21) and a source (22) corresponding to the gate (21), and includes a power supply terminal (11), a ground terminal (12), a signal input terminal (13), a first field-effect transistor (Q1), a second field-effect transistor (Q2; Q2d), and an impedance element (15). The ground terminal (12) is connected to the source (22) of the semiconductor switch element (2; 2A). The first field-effect transistor (Q1) is connected to the power supply terminal (11). The second field-effect transistor (Q2; Q2d) is connected in series with the first field-effect transistor (Q1) and is connected to the gate (21) of the semiconductor switch element (2; 2A). The impedance element (15) is provided between a node (N1) between the second field effect transistor (Q2; Q2d) and the gate (21) of the semiconductor switch element (2; 2A) and the signal input terminal (13). When the voltage level of a signal input to a signal input terminal (13) changes from a first potential level (VL1) to a second potential level (VL2) higher than the first potential level (VL1) while the second field effect transistor (Q2; Q2d) is in an on state, the driver circuit (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) turns on the first field effect transistor (Q1) to pass a current larger than the current passing through the impedance element (15) to the gate (21) of the semiconductor switch element (2; 2A), thereby increasing the gate voltage of the semiconductor switch element (2; 2A) above a predetermined value (Vg1) larger than the threshold voltage, and thereafter continues to pass a current from the signal input terminal (13) through the impedance element (15) to the gate (21) of the semiconductor switch element (2; 2A), thereby bringing the semiconductor switch element (2; 2A) into a steady on state.

[0152] The driver circuit (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) according to the eleventh aspect can shorten the turn-on time of the semiconductor switch element (2; 2A) without using a capacitor with a large capacity.

[0153] In a driver circuit (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) according to a twelfth aspect, in any one of the first to eleventh aspects, the driver circuit (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) is a monolithic integrated circuit.

[0154] The driver circuit (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) according to the twelfth aspect can be made smaller.

[0155] A switch system (3; 3a; 3b; 3c; 3d; 3e; 3f; 3g) according to a thirteenth aspect includes a driver circuit (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) according to any one of the first to eleventh aspects, and a semiconductor switch element (2; 2A).

[0156] In the switch system (3; 3a; 3b; 3c; 3d; 3e; 3f; 3g) according to the thirteenth aspect, the turn-on time of the semiconductor switch element (2; 2A) can be shortened without using a capacitor with a large capacity.

[0157] In a switch system (3; 3a; 3b; 3c; 3d; 3e; 3f; 3g) according to a fourteenth aspect, in the thirteenth aspect, the driver circuit (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) is a monolithic integrated circuit.

[0158] In the switch system (3; 3a; 3b; 3c; 3d; 3e; 3f; 3g) according to the fourteenth aspect, the driver circuits (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) can be made smaller.

[0159] In the switch system (3; 3a; 3b; 3c; 3d; 3e; 3f; 3g) according to the fifteenth aspect, in the thirteenth aspect, the switch system (3; 3a; 3b; 3c; 3d; 3e; 3f; 3g) is a monolithic integrated circuit in which a driver circuit (1; 1a; 1b; 1c; 1d; 1e; 1f; 1g) and a semiconductor switch element (2; 2A) are integrated.

[0160] The switch system (3; 3a; 3b; 3c; 3d; 3e; 3f; 3g) according to the fifteenth aspect can be made smaller. [Explanation of symbols]

[0161] 1, 1a, 1b, 1c, 1d, 1e, 1f, 1g driver circuits 2, 2A semiconductor switch element Gate 21 21A Gate 1 21B Gate 2 22 sauces 22A First Source 22B Second Source 3, 3a, 3b, 3c, 3d, 3e, 3f, 3g switch systems 10 DCFL circuit 101 Input terminal 102 Output terminal 11 Power terminal 12 Ground terminal 13 Signal input terminal 14, 14c, 14d Speed-up circuit 15 Impedance element 16 Resistor voltage divider circuit 161 Output terminal 17 Constant current circuit 18 Constant voltage circuit 19 Constant current circuit D1 Diode N1 node N2 node Q1 First field effect transistor Q2, Q2d Second field effect transistor Q21 Third field-effect transistor Q22 Fourth field-effect transistor Vg1 specified value VL1 First potential level VL2 Second potential level

Claims

1. A driver circuit for a current-driven semiconductor switch element having a gate and a source corresponding to the gate, A power terminal and a ground terminal connected to the source of the semiconductor switch element; A signal input terminal; a speed-up circuit provided between the power supply terminal and the gate of the semiconductor switch element; an impedance element provided between the signal input terminal and a node between the speed-up circuit and the gate of the semiconductor switch element; a resistor connected to the power supply terminal; a constant current circuit provided between the resistor and the ground terminal, The speed-up circuit a first field effect transistor; a second field effect transistor connected in series to the first field effect transistor and connected to the gate of the semiconductor switch element; an impedance of the impedance element is higher than an impedance of the speed-up circuit when both the first field-effect transistor and the second field-effect transistor are in an on-state; the gate of the second field effect transistor is connected to a node between the resistor and the constant current circuit; Driver circuit.

2. A driver circuit for a current-driven semiconductor switch element having a gate and a source corresponding to the gate, A power terminal and a ground terminal connected to the source of the semiconductor switch element; A signal input terminal; a speed-up circuit provided between the power supply terminal and the gate of the semiconductor switch element; an impedance element provided between the signal input terminal and a node between the speed-up circuit and the gate of the semiconductor switch element; a resistor connected to the power supply terminal; a constant voltage circuit provided between the resistor and the ground terminal, The speed-up circuit a first field effect transistor; a second field effect transistor connected in series to the first field effect transistor and connected to the gate of the semiconductor switch element; an impedance of the impedance element is higher than an impedance of the speed-up circuit when both the first field-effect transistor and the second field-effect transistor are in an on-state; The constant voltage circuit is configured by connecting a plurality of diodes in series, a node between the resistor and the constant voltage circuit is connected to the gate of the second field effect transistor; Driver circuit.

3. the second field effect transistor is a normally-on field effect transistor.

3. A driver circuit according to claim 1 or 2.

4. A driver circuit for a current-driven semiconductor switch element having a gate and a source corresponding to the gate, A power terminal and a ground terminal connected to the source of the semiconductor switch element; A signal input terminal; a speed-up circuit provided between the power supply terminal and the gate of the semiconductor switch element; an impedance element provided between the signal input terminal and a node between the speed-up circuit and the gate of the semiconductor switch element; a constant current circuit connected to the power supply terminal; a resistor provided between the constant current circuit and the ground terminal, The speed-up circuit a first field effect transistor; a second field effect transistor connected in series to the first field effect transistor and connected to the gate of the semiconductor switch element; an impedance of the impedance element is higher than an impedance of the speed-up circuit when both the first field-effect transistor and the second field-effect transistor are in an on-state; the gate of the second field effect transistor is connected to a node between the constant current circuit and the resistor; Driver circuit.

5. a DCFL circuit having an input terminal and an output terminal and disposed between the power supply terminal and the ground terminal; an input end of the DCFL circuit is connected to the signal input terminal; an output terminal of the DCFL circuit is connected to the gate of the semiconductor switch element via the impedance element; A driver circuit according to any one of claims 1 to 4.

6. the semiconductor switch element is a dual-gate bidirectional switch element having two gates and two sources, two of the speed-up circuits; one of the two speed-up circuits is connected to a first gate which is one of the two gates, and the remaining speed-up circuit is connected to a second gate which is the other of the two gates; A driver circuit according to any one of claims 1 to 5.

7. The semiconductor switch element is a GaN-based semiconductor switch element. A driver circuit according to any one of claims 1 to 6.

8. the driver circuit is a monolithic integrated circuit; A driver circuit according to any one of claims 1 to 7.

9. A driver circuit according to any one of claims 1 to 7, and the semiconductor switch element. Switch system.

10. the driver circuit is a monolithic integrated circuit; The switch system of claim 9.

11. the switch system is a monolithic integrated circuit in which the driver circuit and the semiconductor switch element are integrated. The switch system of claim 9.

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