System and method for time management for a virtual machine having multiple virtual processing cores

Abstract

To provide a host computer, a method, and a memory for tracking virtual time in a virtual machine.SOLUTION: A host computer includes a host CPU and a host memory that stores a virtual time object and a VM. The host CPU runs multiple threads in parallel on corresponding virtual cores. The multiple threads include a first thread to be executed on a first virtual core and a second thread to be executed on a second virtual core. The VM assigns a designation to the first virtual core to increment the virtual time object by a first count of a first multiple directive instructions to be executed in the first thread over a first period. The VM moves the designation to the second virtual core in response to detecting an event defining the end of the first period. The second virtual core increments the virtual time object by a second count of directive instructions to be executed in the second thread over a second time period.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The field of this disclosure relates generally to virtualization of multi-core processors, and more particularly to tracking virtual time in a virtual machine having multiple virtual cores processing in parallel. [Background technology]

[0002] Computing systems are often virtualized, or emulated, to enable simulation, testing, and development of their computing environment on a host computer, such as a desktop personal computer. Virtualization refers to the mimicking of a given unit of hardware by a software program, such as a virtual machine (VM), that runs on the local or host computer via a hypervisor. In some cases, the VM runs without a hypervisor. Virtualization enables development, testing, and execution of target software without requiring a complete target computing system, which may have limited system availability.

[0003] At least some of these computing systems utilize multi-core processors and multi-threading, or parallel processing of target software. In some cases, multiprocessing hardware is used instead of or in combination with a multi-core processor to provide multiple processor cores for parallel execution. When the target software includes multiple threads, tasks, and / or processes intended to run in parallel on a multi-core processor or multiple processors, execution of the target software, and more specifically multiple threads, on multiple virtual cores requires that the threads be synchronized or coordinated in some way. One solution is to execute threads in a step-by-step order, for example, from interrupt to interrupt. However, this results in degradation of VM performance, especially as the number of threads and target processing cores increases. Another solution is to synchronize virtual time, i.e., timing in the VM, with "wall clock" time, i.e., actual time in the physical world; however, synchronization is often not possible if the virtualized system cannot execute software fast enough to match wall clock time. This may be the case when processor emulation is used in a virtual machine. In other scenarios, execution faster than wall clock time is desired. In this scenario, wall clock time cannot easily be used as a time source, and a synchronized virtual time source is required. Furthermore, these conventional solutions result in an inability to create VMs that meet the desired performance characteristics for multi-core applications that use VMs, such as test environments and trainers. Therefore, improved time management for VMs with virtual processing cores is desirable.

[0004] For purposes of this disclosure, the terms "virtualization" and "emulation" are used interchangeably to refer to a VM, in which any aspect of the target hardware is emulated, but the host computer may incorporate one or more other aspects of the target hardware.

[0005] This section is intended to introduce the reader to various aspects of technology that may be related to various aspects of the present disclosure, as described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art. Summary of the Invention

[0006] One aspect is directed to a host computer for virtualizing a target multicore processor. The host computer includes a host memory and a host CPU. The host memory includes a first section of memory that stores a virtual time object and a second section that stores a VM. The VM includes target code having multiple threads, where each thread includes a plurality of instruction instructions configured to execute on the target multicore processor. The host CPU is configured to execute the VM to virtualize the target multicore processor. The VM is configured to execute the multiple threads in parallel on corresponding virtual cores. The multiple threads include a first thread having a first plurality of instruction instructions that execute on the first virtual core and a second thread having a second plurality of instruction instructions that execute on the second virtual core. The VM is further configured to assign a designation to the first virtual core to increment the virtual time object by a first count of the first plurality of instruction instructions executed in the first thread over a first period of time. The VM is further configured to transfer the designation to the second virtual core in response to detecting an event that defines the end of the first period of time. The VM is further configured to increment the virtual time object by a second count of a second plurality of instruction instructions executed in the second thread over a second period of time by the second virtual core.

[0007] Another aspect is directed to a method for tracking virtual time in a VM having a virtual multi-core processor. The method includes executing a first thread on a first virtual core, where the first thread includes a first plurality of instruction instructions. The method includes executing a second thread in parallel with the first thread on a second virtual core, where the second thread includes a second plurality of instruction instructions. The method includes storing a virtual time object in a section of host memory. The method includes assigning a designation to the first virtual core for incrementing the virtual time object by a first count of the first plurality of instruction instructions executed in the first thread over a first period of time. The method includes transferring the designation to a second virtual core in response to detecting an event defining the end of the first period of time. The method includes incrementing the virtual time object by a second count of the second plurality of instruction instructions executed in the second thread over a second period of time, by the second virtual core.

[0008] Yet another aspect is directed to a computer-readable memory storing a VM having multiple virtual cores. The VM, when executed by a host CPU, is configured to execute a first thread including a first plurality of instruction instructions on a first virtual core of the multiple virtual cores and to execute a second thread including a second plurality of instruction instructions on a second virtual core of the multiple virtual cores in parallel with the first thread. The VM stores a virtual time object in a section of host memory and assigns a designation to the first virtual core to increment the virtual time object by a first count of the first plurality of instruction instructions executed in the first thread over a first period of time. In response to detecting an event defining the end of the first period of time, the VM transfers the designation to a second virtual core. The second virtual core increments the virtual time object by a second count of the second plurality of instruction instructions executed in the second thread over a second period of time.

[0009] Various refinements of the features described in connection with the above-described aspects exist. Additionally, additional features may be incorporated into the above-described aspects. Such refinements and additional features may exist individually or in any combination. For example, various features described below in connection with any of the illustrated embodiments may be incorporated into any of the above-described aspects, alone or in any combination. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a block diagram of an exemplary memory structure for a host computer running a VM. [Figure 2] FIG. 2 is an exemplary timing diagram of ordered processing of a multi-threaded target core. [Figure 3] FIG. 2 is an exemplary timing diagram of parallel processing of a multi-threaded target core. [Figure 4] FIG. 2 is a block diagram of an exemplary host computer. [Figure 5] FIG. 1 is a flow diagram of an example method for tracking virtual time in a VM having a virtual multi-core processor. DETAILED DESCRIPTION OF THE INVENTION

[0011] Corresponding reference characters indicate corresponding parts throughout the several views. While specific features of various embodiments may be shown in some drawings and not in others, this is for convenience only. Any feature of any drawing may be referenced and / or claimed in combination with any feature of any other drawing.

[0012] The host computer of the present disclosure provides a virtual time object stored in a memory section, whereby the virtual time object can be used within the virtualization layer by multiple virtualized cores of a VM. The virtual time object may include, for example, a variable, a data structure, or a class in which virtual time can be stored. When executing a target core with multiple threads running in parallel, the VM designates one virtual core as a timekeeper to increment the virtual time object by its count of executed instructions, and then the VM transfers that designation to another virtual core, which also increments the virtual time object by its count of executed instructions. The designation may include a variable, data structure, class, Boolean, flag, or other read / write software construct that can identify a given virtual core as a timekeeper. The timekeeper designation may be moved in response to detecting an event, such as an interruption or completion of execution of a transformation block of code.

[0013] Translation blocks are generated when processor emulation is used within a VM. Translation blocks improve the performance of processor emulation. In direct processor emulation (i.e., without translation blocks), all instructions in the target software are encountered logic in the processor emulation, and the VM translates the target software (e.g., assembly or machine code) into host code (e.g., host assembly or machine code). Translation blocks allow blocks of target software to be translated and cached for future use during execution. This caching is possible because the target software binary does not change and most software is cyclical in nature, executing only a small percentage of all common code within a binary. Translation blocks are variable in length and are designed to terminate at certain transitions in the code, such as branch statements or context switches. These transitions in the code result in the translation block being exited in the processor emulator and a new translation block being loaded into the processor emulator. Translation block transitions are conceptually similar to context switches.

[0014] FIG. 1 is a block diagram of an exemplary memory structure for a host computer having a host central processing unit (CPU) 100 with one or more cores. Referring to the embodiment shown in FIG. 1, host CPU 100 includes at least two cores, including core 0 102 and core 1 104. Host CPU 100 is configured or programmed to execute VM 105 using virtualization layer 107. VM 105 is configured to execute target code or software having multiple threads, tasks, and / or processes that may be processed in order or in parallel on the target multicore processor. VM 105 includes a virtual multicore processor 103 having N virtual cores 116. FIG. 2 is an exemplary timing diagram 200 of in-order processing of multithreaded target code. FIG. 3 is an exemplary timing diagram 300 of parallel processing of a multithreaded target core. FIG. 2 shows four threads executing in order on respective virtual cores 202, 204, 206, and 208. Sections of code 210, 212, 214, 216 within each thread are executed in order on virtual cores 202, 204, 206, 208 over virtual time, which is represented by virtual timeline 218. Notably, the time required to execute four threads in order is over four times longer than executing the same threads in parallel, as shown in Figure 3. However, time management can simply proceed in order with the threads in virtual time.

[0015] In FIG. 3, a timing diagram 300 shows identical virtual cores 202, 204, 206, and 208 processing identical target code 302, 304, 306, and 308 in parallel. Each target code 302, 304, 306, and 308 contains a unique set of executable instructions that vary in the time required for processing by its respective virtual core 202, 204, 206, and 208. The virtual cores 202, 204, 206, and 208 process in parallel and track virtual time with a virtual time object, without synchronizing the virtual time with wall clock time. Because each thread of target code 302, 304, 306, and 308 requires unequal time to execute instructions, time management is distributed among all virtual cores 202, 204, 206, and 208. In particular, threads executing in parallel are often interdependent and may need to stall, waiting for another thread to catch up or for a shared resource to become available. While Figure 3 shows four virtual cores, the time management methods of the present disclosure may be embodied in a virtualized multi-core processor having any number N of virtual cores, i.e., two or more.

[0016] 1, virtual time object 118 is stored in a section of memory accessible by virtualization layer 107 used by all virtual cores 116 in VM 105, from virtual core 0 116 through virtual core N 116. The memory space may include, for example, addresses in random access memory (RAM) 106. The target code itself, including its multiple threads, each consisting of multiple executable instructions, may be stored in RAM 106. Alternatively, the target code may be stored in another memory space, such as non-volatile RAM (NVRAM) or a mass storage device.

[0017] Alternatively, the memory space that stores the virtual time object 118 may include addresses in a shared cache, such as the layer 3 (L3) cache 108. Typically, each host core has one or more dedicated cache memory spaces. The dedicated caches may include, for example, one or more layer 1 (L1) caches 110 and one or more layer 2 (L2) caches 112. Each additional layer of cache memory is generally larger and slower than the next lower level. For example, the L1 cache 110 is typically the smallest capacity memory, but the fastest. The L2 cache 112 is typically larger than the L1 cache 110, but has slower read and write times. Similarly, the L3 cache 108 is even larger, but again has slower read and write times. In particular embodiments, one or more of the dedicated cache memories (L1 110 or L2 112) are associated with its corresponding host core, e.g., Core 0 102 or Core 1 104. In an alternative embodiment, the virtual time object 118 may be stored in a separate memory space coupled to the host core, for example across the memory bus 114 .

[0018] In each virtual core 116, e.g., virtual core 0116 and virtual core N116, the VM 105 tracks virtual time by counting the number of emulated instructions executed and then incrementing a virtual time object 118. However, only one virtual core increments or advances the virtual time object 118 at a given moment in time because that one core locks memory space, e.g., the L3 cache 108. Eventually, one or more other virtual cores may stop processing their threads to preserve cache coherency, resulting in degraded performance of the virtualized multi-core processor 103. As the number of virtual cores increases, cache coherency becomes a complex issue. Furthermore, one virtual core increments virtual time because virtual time advances too quickly (e.g., faster than the time on a wall clock) when all threads increment virtual time. For example, a virtual processor with N cores will run over N times faster than a virtual processor with a single core or a core that executes in sequence.

[0019] The VM 105 designates or assigns a designation to a first virtual core, e.g., virtual core N 116, to increment a virtual time object 118 by its count of instructions executed in that thread of target code over a first period of time. That designation is then transferred to another virtual core 116 in response to detecting an event that defines the end of the first period of time. That virtual core 116 then increments the virtual time object 118 by its count of instructions executed in that thread of target code over a second period of time. Otherwise, all virtual cores execute their respective threads in parallel, and only the designated virtual core increments the virtual time object 118.

[0020] The instructions, i.e., target code, executed within a given thread by a corresponding virtual core may include, for example, a block of assembly language instructions. Those instructions may also include instructions to read virtual time object 118 from time to time, e.g., periodically, which serve to synchronize the multiple threads with their corresponding virtual cores. Alternatively, VM 105 may periodically instruct each virtual core to read virtual time object 118.

[0021] The timekeeper designation is moved in response to events such as an interruption, completion of execution of a translation block of instructions, or the stopping of the virtual core holding the timekeeper designation. Moving the designation avoids locking up the shared memory space, which could cause one or more virtual cores 116 to stop executing. While the processing loads of the virtual cores 116 are often unequal or unbalanced at a given moment in time as each virtual core 116 contributes to the increment or progression of virtual time, the unequal processing loads across the virtual cores 116 are smoothed or tend to average out.

[0022] FIG. 4 is a block diagram of an exemplary host computer 400 for emulating a target multi-core processor. The target multi-core processor is a hardware multi-core processor being emulated. For example, the computing system, i.e., the target hardware, may utilize a dual-core or quad-core processor. Alternatively, the target multi-core processor may include eight or more processing cores. Generally, a target multi-core processor includes two or more processing cores. The host computer 400 includes a host CPU 402 coupled to a cache memory 403, which is further coupled to a RAM 404 and a host memory 406 via a memory bus 408. The cache memory 403 and RAM 404 are configured to operate with the host CPU 402 when the multi-core processor 100 operates with the RAM 106 and corresponding cache memory shown in FIG. 1. More specifically, a virtual time variable is stored in memory space allocated within the RAM 404 or the cache memory 403. Host memory 406 is computer-readable memory (e.g., volatile or non-volatile) that includes a memory section for storing VM 410, a section for storing OS 412, a section for storing virtualization layer 413, a section for storing target code 414, and a section for storing virtual-time objects 417, such as variables, data structures, or classes. In alternative embodiments, one or more sections of host memory 406 may be omitted and remotely stored data. For example, in certain embodiments, target code 414 may be stored remotely on a server or mass storage device and made available via a network to host CPU 402 and VM 410. VM 410 includes a virtualized multi-core processor 415.

[0023] The host computer 400 also includes a host I / O device 416, which may include, for example, a communication interface such as an Ethernet controller 418 or a peripheral interface for communicating with host peripheral devices 420 via a peripheral link 422. The host I / O device 416 may include, for example, a GPU for driving a peripheral display via a display link.

[0024] FIG. 5 is a flow diagram of an example method 500 for tracking virtual time in a VM having a virtual multi-core processor, such as VM 410 and virtualized multi-core processor 100 shown in FIGS. 4 and 1, respectively. A first virtual core, e.g., virtual core 0 102, executes a first thread including a first plurality of instruction instructions (502). A second virtual core, e.g., virtual core N 104, executes a second thread including a second plurality of instruction instructions (504). A virtual time object 417 is stored in a section of host memory shared between at least the first virtual core and the second virtual core (506). For example, as shown in FIG. 1, the virtual time object 417 may be stored in L3 cache 108. L3 cache 108 is shared by virtual core 0 102 and virtual core N 104.

[0025] The VM assigns (508) a designation to a first virtual core to increment a virtual time object 417 by a first count of a first plurality of instruction instructions executed in a first thread over a first period of time. The designation is then transferred (510) to a second virtual core in response to detecting an event that defines the end of the first period of time. For example, the event may include an interruption, completion of execution of a section of code, such as a translation block, or the first virtual core stopping. The second virtual core then increments (512) the virtual time object 417 by a second count of a second plurality of instruction instructions executed in a second thread over a second period of time. The virtual cores execute in parallel, and only one virtual core updates the virtual time.

[0026] In particular embodiments, method 500 includes mapping a shared cache, such as L3 cache 108, to a shared cache for the host multi-core processor. In particular embodiments, method 500 includes reading, by a second virtual core, the virtual time object 417 during the first time period. The reading may be by instruction in the second thread or alternatively by instruction from the VM.

[0027] Example technical effects of the methods, systems, and apparatus described herein include at least one of the following: (a) tracking virtual time in a virtualized multi-core processor executing multiple multi-target threads of code in parallel, (b) eliminating virtual time wall clock synchronization, (c) storing virtual time objects in a shared memory space without disturbing cache coherency, and (d) distributing timekeeping among multiple virtual cores by moving timekeeping designations on an event-driven basis.

[0028] Some embodiments involve the use of one or more electronic processing or computing devices. As used herein, the terms “processor” and “computer,” as well as related terms such as “processing device,” “computing device,” and “controller,” are not limited to those integrated circuits commonly referred to in the art as computers, but rather refer broadly to processors, processing devices, controllers, general-purpose central processing units (CPUs), graphics processing units (GPUs), microcontrollers, microcomputers, programmable logic controllers (PLCs), reduced instruction set computer (RISC) processors, field programmable gate arrays (FPGAs), digital signal processing (DSP) devices, application-specific integrated circuits (ASICs), and other programmable circuits or processing devices capable of performing the functions described herein, and these terms are used interchangeably herein. These processing devices are generally “configured” to perform functions according to a set of instructions that are programmed or that are programmed or executed. The above examples are not intended to limit in any way the definition or meaning of the terms processor, processing device, and related terms.

[0029] In embodiments described herein, memory may include non-transitory computer-readable media such as, but not limited to, flash memory, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and non-volatile RAM (NVRAM). As used herein, the term "non-transitory computer-readable media" is intended to refer to any tangible computer-readable medium, including non-transitory computer storage devices, including, but not limited to, removable and non-removable media, such as firmware, physical and virtual storage, CD-ROMs, DVDs, and any digital source, such as a network or the Internet, and any digital means yet to be developed, excluding ephemeral propagated signals. Alternatively, a floppy disk, compact disk-read-only memory (CD-ROM), magnetic optical disk (MOD), digital versatile disk (DVD), or any other computer-based device implemented in any method or technology for short-term or long-term storage of information, such as computer-readable instructions, data structures, program modules and sub-modules, or data, may also be used. Accordingly, the methods described herein may be encoded as executable instructions, e.g., "software" and "firmware," embodied in a non-transitory computer-readable medium. Furthermore, as used herein, the terms "software" and "firmware" are used interchangeably and include any computer program stored in memory for execution by personal computers, workstations, clients, and servers. Such instructions, when executed by a processor, cause the processor to perform at least a portion of the methods described herein.

[0030] Also, in the embodiments described herein, additional input channels may be computer peripherals associated with an operator interface, such as, but not limited to, a mouse or keyboard. Alternatively, other computer peripherals may be used, which may include, for example, but not limited to, a scanner. Furthermore, in some embodiments, additional output channels may include, but are not limited to, an operator interface monitor.

[0031] The systems and methods described herein are not limited to the specific embodiments described herein; rather, the system components and / or method steps may be utilized independently and separately from the other components and / or steps described herein.

[0032] Although specific features of various embodiments of the present disclosure may be shown in some drawings and not in others, this is for convenience only, and in accordance with the principles of the present disclosure, any feature of a drawing may be referenced and / or claimed in combination with any feature of any other drawing.

[0033] As used herein, an element or step described in the singular and preceded by the word "a" or "an" should be understood to not exclude a plural of that element or step, unless such exclusion is expressly stated. Furthermore, references to "one embodiment or example embodiment" of the invention are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the described features.

[0034] Furthermore, the present disclosure includes embodiments according to the following clauses: Article 1. A host computer (400) for virtualizing a target multi-core processor, comprising: a host memory (406) including a first section of memory storing a virtual time object (118, 417) and a second section storing a virtual machine (VM) (105, 410), the VM including target code (414) including multiple threads, each thread including multiple instructions configured to execute on the target multi-core processor; a host central processing unit (CPU) (100, 402) configured to execute the VM to virtualize the target multi-core processor, the VM comprising: executing a plurality of threads in parallel on corresponding virtual cores (116, 415), the plurality of threads including a first thread having a first plurality of instructions executed on a first virtual core and a second thread having a second plurality of instructions executed on a second virtual core; assigning a designation to the first virtual core to increment the virtual time object by a first count of the first plurality of instructions executed in the first thread over a first period of time; transferring the assignment to the second virtual core in response to detecting an event defining an end of the first period; and A host computer (400) configured to execute, by the second virtual core, incrementing the virtual time object by a second count of the second plurality of instruction instructions executed in the second thread over a second period of time. Article 2. The host computer (400) according to clause 1, wherein the event is an interrupt. Article 3. 2. The host computer (400) of claim 1, wherein the event is completion of execution of a transformation block within the first plurality of instructions. Article 4. A host computer (400) described in any one of clauses 1 to 3, wherein the second plurality of instructions executed on the second virtual core (116, 415) include reading the virtual time object (118, 417) during the first period. Article 5. The host computer (400) of any one of clauses 1 to 4, wherein the VM (105, 410) is further configured to periodically read the virtual time object (118, 417) to update at least one of an emulated counter or an emulated hardware timer within the VM. Article 6. 6. The host computer (400) of any one of clauses 1 to 5, wherein the plurality of instructions for each thread include assembly instructions. Article 7. 2. The host computer (400) of claim 1, wherein the event is a shutdown of the first virtual core (116, 415). Article 8. A host computer (400) as described in any one of clauses 1 to 7, wherein the first section of the host memory is mapped to a shared cache level (108) for storing the virtual time object (118, 417). Article 9. A method (500) for tracking virtual time in a virtual machine (VM) (105, 410) having a virtual multi-core processor (103), comprising: Executing (502) a first thread including a first plurality of instructions on a first virtual core (116, 415); executing (504) a second thread including a second plurality of instructions in parallel with the first thread on a second virtual core (116, 415); storing (506) the virtual time object (118, 417) in a section of the host memory (406); assigning a designation to the first virtual core to increment the virtual time object by a first count of the first plurality of instructions executed in the first thread over a first period of time (508); transferring the assignment to the second virtual core in response to detecting an event defining the end of the first period (510); and A method (500) comprising incrementing (512) the virtual time object by a second count of the second plurality of instructions executed in the second thread over a second period of time by the second virtual core. Article 10. 10. The method (500) of clause 9, further comprising detecting the event, the event comprising a cessation of execution by the first virtual core. Article 11. 11. The method (500) of clause 9 or 10, wherein storing (506) the virtual time object (118, 417) includes storing the virtual time object in a section of random access memory (RAM) (404). Article 12. 12. The method (500) of any one of clauses 9 to 11, further comprising reading the virtual time object (118, 417) during the first period by the second virtual core (116, 415). Article 13. 13. The method (500) of any one of clauses 9 to 12, further comprising reading the virtual time object (118, 417) by the VM (105, 410) to update at least one of an emulated counter or an emulated hardware timer within the VM. Article 14. 10. The method (500) of clause 9, further comprising detecting the event, wherein the event comprises an interrupt. Article 15. 14. The method (500) of any one of clauses 9 to 13, further comprising detecting the event, the event comprising completing execution of a conversion block of instructions of the first plurality of instructions. Article 16. A computer-readable memory (406) storing a virtual machine (VM) (105, 410) having a plurality of virtual cores (116, 415), the VM, when executed by a host central processing unit (CPU) (100, 402), executing a first thread including a first plurality of instructions on a first virtual core of the plurality of virtual cores (116, 415); executing a second thread including a second plurality of instructions in parallel with the first thread on a second virtual core of the plurality of virtual cores; storing a virtual time object (118, 417) within a section of host memory (403, 404, 406); assigning a designation to the first virtual core to increment the virtual time object by a first count of the first plurality of instructions executed in the first thread over a first period of time; transferring the assignment to the second virtual core in response to detecting an event defining an end of the first period; and and a computer-readable memory (406) configured to execute, by the second virtual core, incrementing the virtual time object by a second count of the second plurality of instruction instructions executed in the second thread for a second period of time. Article 17. 17. The computer-readable memory (406) of clause 16, wherein the VM (105, 410), when executed by the host CPU (100, 402), is further configured to detect the event, the event comprising an interrupt. Article 18. The computer-readable memory (406) of clause 17, wherein the VM (105, 410), when executed by the host CPU (100, 402), is further configured to detect the event, the event including completion of execution of a translation block of target code. Article 19. The computer-readable memory (406) of any one of clauses 16 to 18, wherein the VM (105, 410), when executed by the host CPU (100, 402), is further configured to read the virtual time object (118, 417) during the first period by the second virtual core (116, 415). Article 20. The computer-readable memory (406) of any one of clauses 16 to 19, wherein the VM (105, 410) is further configured to detect the event when executed by the host CPU (100, 402), the event including a cessation of execution by the first virtual core (116, 415).

[0035] This specification uses examples to disclose various embodiments, including the best mode, so that one skilled in the art can practice those embodiments, including making and using any device or system and practicing any methods incorporating them. The scope of patentability is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements that differ only insignificantly from the literal language of the claims.

Claims

1. A host computer (400) for virtualizing a target multi-core processor, comprising: a host memory (406) including a first section of memory storing a virtual time object (118, 417) and a second section storing a virtual machine (VM) (105, 410), the VM including target code (414) including multiple threads, each thread including multiple instructions configured to execute on the target multi-core processor; a host central processing unit (CPU) (100, 402) configured to execute the VM to virtualize the target multi-core processor, the VM comprising: executing a plurality of threads in parallel on corresponding virtual cores (116, 415), the plurality of threads including a first thread having a first plurality of instructions executed on a first virtual core and a second thread having a second plurality of instructions executed on a second virtual core; assigning a designation to the first virtual core to increment the virtual time object by a first count of the first plurality of instruction instructions executed in the first thread over a first period of time; transferring the assignment to the second virtual core in response to detecting an event defining an end of the first period; and The host computer (400) is configured to execute, by the second virtual core, incrementing the virtual time object by a second count of the second plurality of instruction instructions executed in the second thread over a second period of time.

2. The host computer (400) of claim 1, wherein the event is an interrupt.

3. 2. The host computer (400) of claim 1, wherein the event is completion of execution of a transformation block within the first plurality of instructions.

4. 4. The host computer (400) of claim 1, wherein the second plurality of instructions executed on the second virtual core (116, 415) include reading the virtual time object (118, 417) during the first period.

5. 5. The host computer (400) of claim 1, wherein the VM (105, 410) is further configured to periodically read the virtual time object (118, 417) to update at least one of an emulated counter or an emulated hardware timer within the VM.

6. The host computer (400) of claim 1 , wherein the plurality of instructions for each thread include assembly instructions.

7. The host computer (400) of claim 1, wherein the event is a shutdown of the first virtual core (116, 415).

8. 8. The host computer (400) of claim 1, wherein the first section of the host memory is mapped to a shared cache level (108) for storing the virtual time object (118, 417).

9. A method (500) for tracking virtual time in a virtual machine (VM) (105, 410) having a virtual multi-core processor (103), comprising: Executing (502) a first thread including a first plurality of instructions on a first virtual core (116, 415); executing (504) a second thread including a second plurality of instructions in parallel with the first thread on a second virtual core (116, 415); Storing (506) the virtual time object (118, 417) in a section of host memory (406); assigning a designation to the first virtual core to increment the virtual time object by a first count of the first plurality of instruction instructions executed in the first thread over a first time period (508); responsive to detecting an event defining the end of the first period, transferring the assignment to the second virtual core (510); and and incrementing (512) the virtual time object by a second count of the second plurality of instructions executed in the second thread over a second period of time by the second virtual core.

10. 10. The method (500) of claim 9, further comprising detecting the event, wherein the event comprises a cessation of execution by the first virtual core.

11. 11. The method (500) of claim 9 or 10, wherein storing (506) the virtual time object (118, 417) comprises storing the virtual time object in a section of random access memory (RAM) (404).

12. 12. The method (500) of any one of claims 9 to 11, further comprising reading, by the second virtual core (116, 415), the virtual time object (118, 417) during the first period of time.

13. 13. The method (500) of any one of claims 9 to 12, further comprising reading the virtual time object (118, 417) by the VM (105, 410) to update at least one of an emulated counter or an emulated hardware timer within the VM.

14. 14. The method (500) of any one of claims 9 to 13, further comprising detecting the event, wherein the event comprises an interrupt.

15. 14. The method (500) of any one of claims 9 to 13, further comprising detecting the event, the event comprising completing execution of a transformation block of instructions of the first plurality of instructions.

16. A computer-readable memory (406) storing a virtual machine (VM) (105, 410) having a plurality of virtual cores (116, 415), the VM, when executed by a host central processing unit (CPU) (100, 402), executing a first thread including a first plurality of instructions on a first virtual core of the plurality of virtual cores; executing a second thread including a second plurality of instructions in parallel with the first thread on a second virtual core of the plurality of virtual cores; storing the virtual time object (118, 417) in a section of the host memory (403, 404, 406); assigning a designation to the first virtual core to increment the virtual time object by a first count of the first plurality of instruction instructions executed in the first thread over a first period of time; transferring the assignment to the second virtual core in response to detecting an event defining an end of the first period; and and a computer-readable memory (406) configured to execute, by the second virtual core, incrementing the virtual time object by a second count of the second plurality of instruction instructions executed in the second thread for a second period of time.

17. 17. The computer-readable memory of claim 16, wherein the VM is further configured to detect the event when executed by the host CPU, the event comprising an interrupt.

18. 20. The computer-readable memory of claim 17, wherein the VM is further configured to detect the event when executed by the host CPU, the event comprising completion of execution of a translation block of target code.

19. The computer-readable memory (406) of any one of claims 16 to 18, wherein the VM (105, 410), when executed by the host CPU (100, 402), is further configured to read the virtual time object (118, 417) by the second virtual core (116, 415) during the first period.

20. The computer-readable memory (406) of any one of claims 16 to 19, wherein the VM (105, 410) is further configured to detect the event when executed by the host CPU (100, 402), the event comprising a cessation of execution by the first virtual core (116, 415).

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