Solid-state imaging element, imaging device, and electronic device

Abstract

The present disclosure relates to a solid-state imaging element, an imaging apparatus and an electronic device wherein the influence caused by forming a PAD electrode can be reduced. When a logic board that is smaller than an image sensor is laminated, a via hole is formed in the image sensor in such a manner that a PAD electrode is formed in an embedded member that is embedded around the logic board. The present disclosure can be applied to imaging apparatuses.

Description

[Technical Field]

[0001] The present disclosure relates to a solid-state imaging element, an imaging device, and an electronic device, and more particularly to a solid-state imaging element, an imaging device, and an electronic device that are capable of reducing the influence when forming a pad electrode. [Background technology]

[0002] When stacking multiple semiconductor elements to form a single semiconductor device, a technology has been proposed that achieves miniaturization and improved efficiency by collecting, arranging, and stacking only good chips (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 087764 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in a semiconductor device configured by the technique described in Patent Document 1, when pad electrodes are arranged in the wiring layer of a miniaturized semiconductor device, the layout area of ​​the circuit is reduced due to the layout area of ​​the pad electrodes.

[0005] Furthermore, when a pad electrode is formed on a large semiconductor element, the wiring distance from the small semiconductor element to the pad electrode becomes long, increasing the parasitic capacitance generated in the wiring.

[0006] The present disclosure has been made in view of such circumstances, and particularly aims to reduce the influence when forming a pad electrode. [Means for solving the problem]

[0007] A solid-state imaging element, an imaging device, and an electronic device according to one aspect of the present disclosure include a first semiconductor element having an imaging element that photoelectrically converts incident light, and a second semiconductor element that is smaller than the first semiconductor element and has a signal processing circuit that processes pixel signals of the imaging element, the second semiconductor element being surrounded by an embedding material, and a PAD electrode being formed in the embedding material.

[0008] In one aspect of the present disclosure, a first semiconductor element having an imaging element that photoelectrically converts incident light, and a second semiconductor element smaller than the first semiconductor element having a signal processing circuit that processes pixel signals of the imaging element are provided, and the periphery of the second semiconductor element is embedded with an embedding material, and a PAD electrode is formed in the embedding material. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a top view of a configuration example of a solid-state imaging device according to a first embodiment of the present disclosure. [Figure 2] 2 is a cross-sectional view of FIG. 1 taken along line AB. [Figure 3] 3 is a diagram illustrating a first step of a method for manufacturing the solid-state imaging device of FIG. 1 and FIG. 2. [Figure 4] 3 is a diagram illustrating a second step in the method for manufacturing the solid-state imaging device of FIGS. 1 and 2. FIG. [Figure 5] 1 and 2. FIG. 4 is a diagram illustrating a third step in the method for manufacturing the solid-state imaging device of FIG. [Figure 6] 1 and 2. FIG. 4 is a diagram illustrating a fourth step in the method for manufacturing the solid-state imaging device of FIG. [Figure 7] 1 and 2. FIG. 4 is a diagram illustrating a fifth step in the method for manufacturing the solid-state imaging device of FIG. [Figure 8] 1 and 2. FIG. 4 is a diagram illustrating a sixth step in the method for manufacturing the solid-state imaging device of FIG. [Figure 9] 1 and 2. FIG. 4 is a diagram illustrating a seventh step in the method for manufacturing the solid-state imaging device of FIG. [Figure 10]1 and 2. FIG. 4 is a diagram illustrating an eighth step of the method for manufacturing the solid-state imaging device of FIG. [Figure 11] FIG. 10 is a cross-sectional view of a configuration example of a solid-state imaging device according to a second embodiment of the present disclosure. [Figure 12] 12 is a diagram illustrating a first step of the method for manufacturing the solid-state imaging device of FIG. [Figure 13] 12A to 12C are diagrams illustrating a second step in the method for manufacturing the solid-state imaging device of FIG. [Figure 14] 12A to 12C are diagrams illustrating a third step in the method for manufacturing the solid-state imaging device of FIG. [Figure 15] 12A to 12C are diagrams illustrating a fourth step of the method for manufacturing the solid-state imaging device of FIG. [Figure 16] 12 is a diagram illustrating a fifth step of the method for manufacturing the solid-state imaging device of FIG. [Figure 17] 12 is a diagram illustrating a sixth step of the method for manufacturing the solid-state imaging device of FIG. [Figure 18] FIG. 10 is a cross-sectional view of a first application example of the second embodiment of the solid-state imaging device of the present disclosure. [Figure 19] FIG. 10 is a cross-sectional view of a second application example of the second embodiment of the solid-state imaging device of the present disclosure. [Figure 20] FIG. 10 is a cross-sectional view of a third application example of the second embodiment of the solid-state imaging device of the present disclosure. [Figure 21] FIG. 10 is a top view of a configuration example of a solid-state imaging device according to a third embodiment of the present disclosure. [Figure 22] 22 is a cross-sectional view taken along line AB in FIG. 21. [Figure 23] 23 is a diagram illustrating a first step of a method for manufacturing the solid-state imaging device of FIGS. 21 and 22. FIG. [Figure 24] 23 is a diagram illustrating a second step in the method for manufacturing the solid-state imaging device of FIGS. 21 and 22. FIG. [Figure 25] 23 is a diagram illustrating a third step of the method for manufacturing the solid-state imaging device of FIGS. 21 and 22. FIG. [Figure 26] 23 is a diagram illustrating a fourth step of the method for manufacturing the solid-state imaging device of FIGS. 21 and 22. FIG. [Figure 27]23 is a diagram illustrating a fifth step of the method for manufacturing the solid-state imaging device of FIGS. 21 and 22. FIG. [Figure 28] 23 is a diagram illustrating a sixth step of the method for manufacturing the solid-state imaging device of FIGS. 21 and 22. FIG. [Figure 29] 23 is a diagram illustrating a seventh step of the method for manufacturing the solid-state imaging device of FIGS. 21 and 22. FIG. [Figure 30] 23 is a diagram illustrating an eighth step of the method for manufacturing the solid-state imaging device of FIGS. 21 and 22. FIG. [Figure 31] 23 is a diagram illustrating a ninth step of the method for manufacturing the solid-state imaging device of FIGS. 21 and 22. FIG. [Figure 32] 10A and 10B are diagrams illustrating examples of application to electronic devices. [Figure 33] 1A and 1B are diagrams illustrating an example of use of a solid-state imaging device. [Figure 34] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 35] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. DETAILED DESCRIPTION OF THE INVENTION

[0010] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0011] Hereinafter, embodiments of the present technology will be described in the following order. 1. First embodiment 2. Second embodiment 3. First Application Example of the Second Embodiment 4. Second Application Example of Second Embodiment 5. Third Application Example of the Second Embodiment 6. Third Embodiment 7. Application examples to electronic devices 8. Examples of using solid-state imaging devices 9. Mobile Application Examples

[0012] <<1. First Embodiment>> 1 and 2 show a configuration example of a first embodiment of a solid-state imaging device according to the present disclosure.

[0013] FIG. 1 shows a top view of the solid-state imaging device 11 when viewed from the incident direction of incident light, and FIG. 2 is an AB cross-sectional view of the solid-state imaging device 11 of FIG.

[0014] As shown in FIG. 2, the solid-state imaging device 11 is formed by stacking a layer made of a support substrate 55, a layer made of a logic substrate 34, a layer made of an oxide film 53, and a layer made of an image sensor 31 in this order from the bottom.

[0015] The image sensor 31 comprises a photoelectric conversion layer 31a and a wiring layer 31b, and the wiring layer 31b has terminals 31c-1 to 31c-4 electrically connected by CuCu bonding formed at positions opposite to the terminals 53a-1 to 53a-4 formed on the oxide film 53.

[0016] In addition, on the upper surface of the image sensor (sensor substrate) 31, an on-chip filter 51 that transmits incident light corresponding to the RGB wavelengths from below, and an on-chip lens 52 that condenses the incident light in the photoelectric conversion layer 31a are formed.

[0017] The logic board 34 is made up of circuits that perform various signal processing operations on pixel signals that constitute an image captured by the image sensor 31, and is manufactured on a wafer, and from the individual pieces that are separated, those that are confirmed to be non-defective by electrical testing are selected and stacked on the support substrate 55. In addition, the logic board 43 has a silicon layer 34a formed in the lower part in the figure and a wiring layer 34b formed in the upper part.

[0018] 1, the logic substrate 34 has a rectangular configuration that is smaller than the image sensor 31 when viewed from above, and therefore, when the image sensor 31 is stacked on the logic substrate 34, a gap is formed between the image sensor 31 and the support substrate 55 so as to surround the logic substrate 34. An embedding member 54 is embedded in this gap.

[0019] Furthermore, as shown in Figures 1 and 2, rectangular, concave recessed portions 54a are formed at predetermined intervals in the embedded member 54 so as to surround the logic substrate 34, and rectangular PAD electrodes 33 are formed in each of the recessed portions 54a.

[0020] As shown in FIG. 1, the image sensor 31 has a rectangular through-hole 32 formed therein, which is located above the pad electrode 33 and is smaller than the pad electrode 33 and passes through the image sensor 31 .

[0021] Therefore, a wire (metal wiring) (not shown) connected to an external signal processing unit is bonded (connected) to the PAD electrode 33 by passing through the through hole 32 .

[0022] With this configuration, in the solid-state imaging element 11 of Figures 1 and 2, wires (not shown) are electrically connected to the Logic board 34 via the PAD electrode 33, terminals 53a-4 and 31c-4, wiring 31b-1, terminals 31c-3 and 53a-3, and the image sensor 31.

[0023] This allows the PAD electrodes 33 to be formed and laid out outside the wiring layer of the Logic substrate 34, which is a small semiconductor element, and therefore makes it possible to improve the area efficiency related to the arrangement of the PAD electrodes 33.

[0024] Furthermore, in wire bonding, soldering is performed with heating, so if there is wiring or the like directly below the PAD electrode 33, there is a risk that it will be damaged by the heat.

[0025] However, as shown in FIG. 2, in the solid-state imaging element 11 of the present disclosure, the PAD electrode 33 is formed in the recessed portion 54a of the embedded member 54, and therefore there is no wiring directly below the PAD electrode 33, making it possible to suppress damage to the wiring associated with solder connections that involve heating.

[0026] Furthermore, since the metal parts such as aluminum that make up the PAD electrode 33 are configured in the recessed portion 54a within the embedded member 54, a HDP (High Density Plasma) film is not required, and the influence of hydrogen caused by HDP can be reduced.

[0027] In addition, since the PAD electrode 33 is configured to be embedded in the embedding member 54, it is possible to reduce the parasitic capacitance compared to when the PAD electrode 33 is formed in a semiconductor element such as the logic substrate 34. Furthermore, by using a material with a lower dielectric constant for the embedding member 54, it is possible to further reduce the parasitic capacitance that occurs when the PAD electrode 33 is formed.

[0028] That is, in the solid-state imaging device 11 of the present disclosure, the configuration shown in FIGS. 1 and 2 makes it possible to reduce various influences that occur when the PAD electrodes 33 are formed.

[0029] <Manufacturing method of the solid-state imaging device shown in Figures 1 and 2> Next, a method for manufacturing the solid-state imaging device 11 shown in FIGS. 1 and 2 will be described with reference to FIGS.

[0030] 3, in the first step, a plurality of logic substrates 34 are formed on a wafer (not shown), which is then thinned and separated into individual pieces by a cutter 101. In FIG. 3, logic substrates 34-1 and 34-2 are shown to be manufactured by being separated into individual pieces by the cutter 101.

[0031] 4, non-defective products are selected from the individualized Logic substrates 34 by electrical inspection and temporarily bonded onto the rearrangement substrate 71. At this time, the temporary bonding is performed so that the wiring layer 34b of the Logic substrate 34 and the rearrangement substrate 71 face each other.

[0032] In the third step, as shown in FIG. 5, the logic substrate 34 temporarily bonded onto the rearrangement substrate 71 is bonded to the support substrate 55 with the silicon layer 34a facing the support substrate 55.

[0033] In a fourth step, as shown in FIG. 6, as described with reference to FIG. 1, an embedding material 54 is embedded in the outer periphery surrounding the logic substrate 34 to the same thickness as the logic substrate 34.

[0034] In the fifth step, as shown in FIG. 7, as described with reference to FIG. 1, recessed portions 54a that are rectangular when viewed from above and concave from the side are formed at predetermined intervals so as to surround the logic substrate 34, and further, PAD electrodes 33 are formed in the recessed portions 54a.

[0035] In the sixth step, as shown in FIG. 8, the terminals 53a-1 to 53a-4 are connected to the PAD electrode 33 and the wiring layer 34b of the logic substrate 34, respectively, and an oxide film 53 is formed on the recessed portion 54a, the embedded member 54 including the PAD electrode 33, and the logic substrate 34.

[0036] In a seventh step, as shown in FIG. 9, the terminals 31c-1 to 31c-4 of the wiring layer 31b of the image sensor 31 and the terminals 53a-1 to 53a-4 of the oxide film 53 are CuCu bonded in a state where they face each other.

[0037] In the eighth step, as shown in FIG. 10, the photoelectric conversion layer 31a of the image sensor 31 is thinned, and an on-chip filter 51 and an on-chip lens 52 are laminated on the image sensor 31. Thereafter, a rectangular through-hole 32, which is located at a position corresponding to the PAD electrode 33 and is smaller than the PAD electrode 33 when viewed from above, is formed so as to penetrate the image sensor 31, thereby completing the solid-state imaging element 11.

[0038] <<2. Second Embodiment>> In the above, an example has been described in which one Logic board 34 is stacked on the support board 55, and then the image sensor 31 is stacked on top of it; however, it is also possible to stack two Logic boards 34 on the support board 55, and then stack the image sensor 31 on top of it.

[0039] FIG. 11 shows an example of the configuration of a solid-state imaging device 11A in which two logic boards 34 are stacked on a support substrate 55.

[0040] In the solid-state imaging device 11A of FIG. 11, components having functions corresponding to those in the solid-state imaging device 11 of FIGS. 1 and 2 are marked with "A" and their description will be omitted as appropriate.

[0041] The solid-state imaging device 11A in FIG. 11 differs from the solid-state imaging device 11 in FIGS. 1 and 2 in that two logic boards 34A-1 and 34A-2 are stacked.

[0042] The logic substrates 34A-1 and 34A-2 each have silicon layers 34Aa-1 and 34Aa-2 formed at the bottom in the drawing, and wiring layers 34Ab-1 and 34Ab-2 formed thereon.

[0043] Between the logic substrates 34A-1 and 34A-2, three terminals 53Aa are formed at positions facing the terminals 34Ac-2 of the logic substrate 34A-2, and are electrically connected.

[0044] Furthermore, in the solid-state imaging device 11A, the terminals 34Ac-2-1 to 34Ac-2-3 of the three sets of logic substrates 34A-2 in FIG. 11 are CuCu bonded to the terminals 53Aa-1 to 53Aa-3 at positions opposite to them.

[0045] The logic substrate 34A-1 has through electrodes 61A-1 and 61A-2 formed therein that penetrate the silicon layer 34Aa-1. The through electrodes 61A-1 and 61A-2 are connected to the terminals 53Aa-1 and 53Aa-2, respectively, thereby electrically connecting the logic substrates 34A-1 and 34A-2 to each other.

[0046] Furthermore, a terminal 34Ac-2-3 of the logic substrate 34A-2 is Cu-Cu bonded to a terminal 53Aa-3 of the oxide film 53A provided at an opposing position, and the terminal 53Aa-3 is further connected to the PAD electrode 33A via a wiring 53Ab in the oxide film 53A, thereby electrically connecting the logic substrate 34A-2 to the PAD electrode 33A.

[0047] Furthermore, the pad electrode 33A is formed in a recessed portion 54Aa recessed upward in the drawing, which is formed in an embedded member 54A-1 of the logic substrate 34A-1.

[0048] Moreover, directly above the PAD electrode 33A in the drawing, a through-hole 32A is formed which penetrates the image sensor 31A and the logic substrate 34A-1.

[0049] With this configuration, the solid-state imaging device 11A in FIG. 11 can also reduce various influences that occur when the pad electrodes 33 are formed, similar to the solid-state imaging device 11 in FIGS.

[0050] <Method for manufacturing the solid-state imaging device shown in FIG. 11> Next, a method for manufacturing the solid-state imaging device 11A of FIG. 11 will be described with reference to FIGS.

[0051] In the first step, the singulated logic substrate 34A-1 and the image sensor 31A are bonded together, as shown in Fig. 12. At this time, the terminals 34Ac-1-1 to 34Ac-1-3 of the wiring layer 34Ab-1 of the logic substrate 34A-1 are Cu-Cu bonded to the terminals 31Ac-1 to 31Ac-3 of the wiring layer 31Ab of the image sensor 31, which are provided at opposing positions.

[0052] In the second step, as shown in FIG. 13, an embedding material 54A-1 is embedded in the outer periphery surrounding the logic substrate 34A-1 to the same thickness as the logic substrate 34A-1, and further, rectangular recessed portions 54Aa-1 are formed at predetermined intervals in the embedding material 54A-1 so as to surround the logic substrate 34A-1.

[0053] In a third step, as shown in FIG. 14, a pad electrode 33A is formed in the recessed portion 54Aa-1, and a through electrode 61A is also formed.

[0054] 15, an oxide film 53 is formed, and then terminals 53Aa-1 to 53Aa-3 are formed. Then, the terminals 53Aa-1 to 53Aa-3 and the terminals 34Ac-2-1 to 34Ac-2-3 are Cu-Cu bonded to each other while facing each other, thereby joining the oxide film 53 to the logic substrate 34-2.

[0055] In the fifth step, as shown in FIG. 16, an embedding material 54A-2 is embedded to surround the logic substrate 34-2 and to the same thickness, and then a support substrate 55A is stacked and bonded on top of the logic substrate 34-2 and the embedding material 54A-2.

[0056] In the sixth step, as shown in FIG. 17, the configuration shown in FIG. 16 is inverted, the photoelectric conversion layer 31Aa of the image sensor 31A is thinned, and an on-chip filter 51A and an on-chip lens 52A are stacked on the image sensor 31A.

[0057] Then, a rectangular through-hole 32A, which is smaller than the PAD electrode 33 when viewed from above and is located at a position corresponding to the PAD electrode 33A, is formed so as to penetrate the on-chip filter 51A, the image sensor 31A, and the embedded member 54A-2, thereby completing the solid-state imaging element 11A.

[0058] <<3. First Application Example of Second Embodiment>> The above has described an example of a solid-state imaging element 11A in which two logic substrates 34A-1 and 34A-2 are stacked in the same direction so that the silicon layers 34Aa-1 and 34Aa-2 are on the image sensor 31A side and the wiring layers 34Ab-1 and 34Ab-2 are on the support substrate 55A side.

[0059] However, the silicon layers and wiring layers of the two logic substrates do not have to be stacked in the same direction.

[0060] FIG. 18 shows an example of the configuration of a solid-state imaging device in which the silicon layers and wiring layers of two logic substrates are stacked upside down.

[0061] In the solid-state imaging device 11B of FIG. 18, components having functions corresponding to those in the solid-state imaging device 11A of FIG. 11 are marked with "B" and their description will be omitted as appropriate.

[0062] In the solid-state imaging element 11B of FIG. 18, the silicon layer 34Ba-1 of the Logic substrate 34B-1 is at the top in the figure, and the wiring layer 34Bb-1 is at the bottom, which is upside down compared to the silicon layer 34Aa-1 and wiring layer 34Ab-1 of the corresponding Logic substrate 34A-1 of FIG. 11.

[0063] Furthermore, the oxide film 53A in FIG. 11, which corresponds to the oxide film 53B, is formed between the logic substrates 34A-1 and 34A-2, but the oxide film 53B is formed between the image sensor 31B and the logic substrate 34B-1.

[0064] Furthermore, in FIG. 18, terminals 34Ac-2-1 and 34Ac-2-2 of the logic substrate 34B-2 are formed between the logic substrates 34B-1 and 34B-2 at positions opposite to the terminals 34Bc-1-1 and 34Bc-1-2 of the logic substrate 34B-1, and are connected to each other by Cu-Cu bonding.

[0065] In the solid-state imaging device 11B, the terminals 53Ba-1 to 53Ba-4 of the oxide film 53B and the terminals 31Bc-1 to 31Bc-4 of the image sensor 31B, which are provided at positions opposite to the terminals 53Ba-1 to 53Ba-4, are connected to each other by CuCu bonding.

[0066] Furthermore, terminals 53Ba-2 to 53Ba-4 and terminals 31Bc-2 to 31Bc-4, which are mutually CuCu-bonded, are connected to through electrodes 61B-1 to 61B-3 that penetrate the silicon layer 34Ba-1 of the logic substrate 34B-1, thereby electrically connecting the logic substrates 34B-1 and 34B-2.

[0067] Terminals 31Bc-3 and 31Bc-4 of image sensor 31B are connected via wiring 31Bd within image sensor 31B. Terminal 31Bc-4 is Cu-Cu bonded to terminal 53Ba-4 of oxide film 53B, and terminal 53Ba-4 is connected to pad electrode 33B. As a result, logic substrate 34B-1 is electrically connected to pad electrode 33B via image sensor 31B.

[0068] Furthermore, the pad electrode 33B is formed in a recessed portion 54Ba-1 recessed downward in the drawing, which is formed in an embedded member 54B-1 of the logic substrate 34B-1.

[0069] Also, an image sensor 31B corresponding to the PAD electrode 33B and a through-hole 32B penetrating the oxide film 53B are formed.

[0070] With this configuration, in the solid-state imaging device 11B of FIG. 18 as well, it is possible to reduce various influences that occur when the PAD electrodes 33 are formed, similarly to the solid-state imaging device 11 of FIGS.

[0071] The method for manufacturing the solid-state imaging device 11B is basically the same as that for the solid-state imaging device 11A, and therefore a description thereof will be omitted.

[0072] <<4. Second Application Example of Second Embodiment>> In the above, an example of the solid-state imaging device 11B in which two logic boards 34B-1 and 34B-2 are stacked and sandwiched between the image sensor 31B and the support substrate 55B has been described.

[0073] However, the logic board that is not in contact with the image sensor 31 may be configured to have the same size as the image sensor 31 and function as a support board, thereby omitting the support board.

[0074] FIG. 19 shows an example of the configuration of a solid-state imaging device in which two logic substrates and an image sensor are stacked, and the support substrate is omitted.

[0075] In the solid-state imaging device 11C of FIG. 19, components having functions corresponding to those in the solid-state imaging device 11B of FIG. 18 are marked with the letter "C," and the description thereof will be omitted as appropriate.

[0076] The solid-state imaging element 11C in Figure 19 differs from the solid-state imaging element 11B in Figure 18 in that the Logic board 34C-2 corresponding to the Logic board 34B-2 is the same size as the image sensor 31C, and the configuration corresponding to the support board 55B is omitted.

[0077] In other words, with the configuration shown in the solid-state imaging element 11C in Figure 19, the logic substrate 34C-2 can be made the same size as the image sensor 31, allowing it to function as a support substrate, and it is possible to have a configuration consisting of three layers: a layer consisting of the image sensor 31C, a layer consisting of the logic substrate 34C-1 and the embedded member 54C, and a layer consisting of the logic substrate 34C-2.

[0078] The method for manufacturing the solid-state imaging device 11C is basically the same as that for the solid-state imaging device 11A, except that the step of stacking the support substrate is omitted, and therefore the explanation thereof will be omitted.

[0079] With this configuration, in the solid-state imaging device 11C of FIG. 19 as well, it is possible to reduce various influences that occur when the PAD electrodes 33 are formed, similarly to the solid-state imaging device 11 of FIGS.

[0080] Furthermore, since the process of stacking the support substrate is not required, the manufacturing process can be simplified, thereby reducing costs, and the device can be made thinner by the amount that the support substrate is omitted.

[0081] <<5. Third Application Example of Second Embodiment>> The above has described an example of the configuration of a solid-state imaging element in which two logic substrates and an image sensor are stacked, a through hole is formed from the imaging surface side of the image sensor, and direct wire bonding is possible to the PAD electrode provided inside the embedded member.

[0082] However, a through hole may be provided on the back side of the image sensor with respect to the imaging surface, and a back electrode may be provided therein.

[0083] FIG. 20 shows an example of the configuration of a solid-state imaging element in which two logic boards and an image sensor are stacked, and a through hole is provided on the back side of the imaging surface of the image sensor, and a back electrode is provided.

[0084] In the solid-state imaging device 11D of FIG. 20, components having functions corresponding to those in the solid-state imaging device 11A of FIG. 11 are marked with "D" and their description will be omitted as appropriate.

[0085] The solid-state imaging element 11D of Figure 20 differs from the solid-state imaging element 11A of Figure 11 in that a through-hole 81 that penetrates the support substrate 55D and the embedded member 54D-2 is formed at a position corresponding to the PAD electrode 33D when viewed from the back side of the imaging surface of the image sensor 31D.

[0086] Furthermore, on the inner surface of the through hole 81, a wiring 82 connected to the wiring 53Db in the oxide film 53D connected to the PAD electrode 33 is formed.

[0087] Furthermore, a back electrode 83 is formed on the back surface side of the solid-state imaging device 11D, connected to the wiring .

[0088] Furthermore, an insulating material is filled in the through-hole 32D on the image sensor 31 side, so that wire bonding cannot be performed from the imaging surface side.

[0089] This configuration makes it possible to connect a wiring board to the back side. In this case, since wiring is not formed inside the logic board 34-2 or the image sensor 31, unnecessary parasitic capacitance can be suppressed.

[0090] <<6. Third Embodiment>> In the above, an example has been described in which each layer is configured with one image sensor, one logic board, one support board, etc. However, for example, a configuration in which multiple logic boards are arranged on the same layer is also possible.

[0091] 21 and 22 show a configuration example of a solid-state imaging device according to a third embodiment, in which a plurality of logic boards are arranged on the same layer.

[0092] FIG. 21 shows a top view of the solid-state imaging device 111 as seen from the incident direction of incident light, and FIG. 22 is an AB cross-sectional view of the solid-state imaging device 111 of FIG.

[0093] As shown in Figure 21, the solid-state imaging element 111 is stacked in the following order from the bottom: a layer consisting of a support substrate 155, a layer consisting of logic substrates 134-2-1, 134-2-2 and embedded member 154-2, a layer consisting of oxide film 153-2, a layer consisting of logic substrate 134-1 and embedded member 154-1, a layer consisting of oxide film 153-1, and a layer consisting of image sensor 131.

[0094] The image sensor 131 comprises a photoelectric conversion layer 131a and a wiring layer 131b, and three terminals 131c-1 to 131c-3 electrically connected by CuCu bonding are formed on the wiring layer 131b at positions opposite to the three terminals 153a-1-1 to 153a-1-3 formed on the oxide film 153-1.

[0095] Also, on the upper surface of the image sensor 131, an on-chip filter 151 that transmits incident light corresponding to the RGB wavelengths from below, and an on-chip lens 152 that condenses the incident light in the photoelectric conversion layer 131a are formed.

[0096] The logic substrates 134-2-1 and 134-2-2 are selected from those that have been confirmed to be electrically good and are stacked on a support substrate 155, with the silicon layers 134a-2-1 and 134a-2-2 at the bottom in the figure and the wiring layers 134b-2-1 and 134b-2-2 at the top.

[0097] As shown in FIG. 21, when viewed from above, the logic substrates 134-2-1 and 134-2-2 each have a rectangular shape that is smaller than both the image sensor 131 and the logic substrate 134-1, and therefore the embedding material 154-2 is embedded in the area surrounding both the logic substrates 134-2-1 and 134-2-2, including the space between them.

[0098] The logic substrate 134-1 is selected from those that have been confirmed to be electrically good, and is stacked so as to straddle the logic substrates 134-2-1 and 134-2-2, with the silicon layer 134a-1 at the bottom in the figure and the wiring layer 134b-1 at the top.

[0099] As shown in FIG. 21, the logic substrate 134-1 has a rectangular shape smaller than the image sensor 131 when viewed from above, and therefore the embedding member 154-1 is embedded in an area surrounding the logic substrate 134-1.

[0100] Furthermore, as shown in Figures 21 and 22, rectangular recessed portions 154a are formed at predetermined intervals in the embedded member 154-1 so as to surround the logic substrate 134-1, and rectangular PAD electrodes 133 are formed in each of the recessed portions 154a.

[0101] Furthermore, the oxide film 153-1 is provided with terminals 153a-1-1 to 153a-1-3 which are connected to the terminals 131c-1 to 131c-3 of the image sensor 131 by Cu-Cu bonding, and in FIG. 21, the terminals 131c-1 to 131c-3 and the terminals 153a-1-1 to 153a-1-3 are provided, which are positioned opposite each other and are Cu-Cu bonded to each other.

[0102] Of these, the two terminals 131c-2 and 131c-3 on the left side in FIG. 22 are connected by a wire 131d in the wiring layer 131b of the image sensor 131.

[0103] Furthermore, the terminal 131c-3 and terminal 153a-1-3 on the left side in FIG. 22 are electrically connected to the logic substrate 134-2-1 via a through electrode 161-2 formed in the embedded member 154-1 and via a wiring 153a-2-2 in the oxide film 153-2.

[0104] Furthermore, a through electrode 161-1 electrically connected to the PAD electrode 133 is provided within the embedded member 154-1, unlike the through electrode 161-2, and is electrically connected to the logic substrate 134-2-1 via wiring 153a-2-3 within the oxide film 153-2.

[0105] Furthermore, the logic substrates 134-2-1 and 134-2-2 are electrically connected to each other via wiring 153a-2-1 in the oxide film 153.

[0106] As shown in FIG. 21, the image sensor 131 and the oxide film 153 have a rectangular through-hole 132 formed above the pad electrode 133 and smaller than the pad electrode 133 .

[0107] Therefore, a wire (not shown) connected to an external signal processing unit is bonded to the PAD electrode 133 by passing through the through hole 132 .

[0108] With this configuration, in the solid-state imaging device 111 of FIGS. 21 and 22, wires (not shown) are connected to the logic board 134-2-1 via the pad electrodes 133, the through electrodes 161-1, and the wiring 153a-2-3 of the oxide film 153-2.

[0109] Furthermore, the logic substrate 134-2-1 is connected to the image sensor 131 via the through electrode 161-2 and the terminals 153a-1-3 and 131c-3. Therefore, the pad electrode 133 is also connected to the image sensor 131 via the logic substrate 134-2-1.

[0110] Furthermore, since the logic substrate 134-1 is also connected to the image sensor 131, the pad electrode 133 is also connected to the logic substrate 134-1 via the through electrode 161-1, the logic substrate 134-2-1, the through electrode 161-2, and the image sensor 131.

[0111] This allows the PAD electrodes 133 to be formed and laid out outside the wiring layer of the Logic substrate 134-1, which is a small semiconductor element, and therefore the area efficiency related to the arrangement of the PAD electrodes 133 can be improved.

[0112] Furthermore, in wire bonding, soldering is performed with heating, so if there is wiring or the like directly below the PAD electrode 133, there is a risk that it will be damaged by the heat.

[0113] However, as shown in FIG. 22, the PAD electrode 133 is formed in the recessed portion 154a of the embedded member 154-1, and therefore there is no wiring directly below the PAD electrode 133, making it possible to suppress damage to the wiring.

[0114] Furthermore, since the metal parts such as aluminum that make up the PAD electrode 133 are configured in the recessed portion 154a within the embedded material 154-1, a HDP (High Density Plasma) film is not required, and the influence of hydrogen caused by HDP can be reduced.

[0115] In addition, since the PAD electrode 133 is configured to be embedded in the embedding material 154-1, it is possible to reduce the parasitic capacitance compared to when the PAD electrode 133 is formed in a semiconductor element such as the logic substrate 134. Furthermore, by using a material with a lower dielectric constant for the embedding material 154-1, it is possible to further reduce the parasitic capacitance that occurs when the PAD electrode 133 is formed.

[0116] That is, in the solid-state imaging device 111 of the present disclosure, the configuration shown in FIGS. 21 and 22 makes it possible to reduce various influences that occur when the PAD electrode 133 is formed.

[0117] <Method of manufacturing the solid-state imaging device shown in Figs. 21 and 22> Next, a method for manufacturing the solid-state imaging device 111 shown in FIGS. 21 and 22 will be described with reference to FIGS.

[0118] In the first step, a plurality of logic substrates 134-1 and 134-2 are formed on a wafer, thinned, and diced. Then, as shown in Fig. 23, good products are selected from the diced logic substrates 134-1 and 134-2 by electrical inspection, and they are temporarily bonded onto rearrangement substrates 201-1 and 201-2, respectively.

[0119] More specifically, as shown in FIG. 23, the wiring layer 134b-1 of the Logic board 134-1 and the rearrangement board 201-1 are temporarily bonded to face each other, and the wiring layers 134b-2-1 and 134b-2-2 of the Logic boards 134-2-1 and 134-2-2 and the rearrangement board 201-2 are temporarily bonded to face each other.

[0120] In a second step, as shown in FIG. 24, the logic substrates 134-2-1 and 134-2-2 that have been temporarily bonded onto the rearrangement substrate 201-2 are bonded to the support substrate 155 with the silicon layers 134a-2-1 and 134a-2-2 facing each other.

[0121] In a third step, as shown in FIG. 25, an embedding material 154-2 is embedded in the outer periphery surrounding and including the space between the logic substrates 134-2-1 and 134-2-2, and to the same thickness as the logic substrates 134-2-1 and 134-2-2.

[0122] In a fourth step, as shown in FIG. 26, an oxide film 153-2 including wiring 153a-2 is formed on the logic substrates 134-2-1 and 134-2-2 and the embedded member 154-2.

[0123] In a fifth step, as shown in FIG. 27, the logic substrate 134-1 temporarily bonded onto the rearrangement substrate 201-1 is pasted and bonded with the silicon layer 134a-1 facing the oxide film 153-2.

[0124] In the sixth step, as shown in FIG. 28, embedded members 154-1 are formed to surround the logic substrate 134-1, and recessed portions 154a are formed at predetermined intervals, each having a rectangular shape when viewed from above and a concave shape extending downward from the side.

[0125] In a seventh step, as shown in Fig. 29, through electrodes 161-1 and 161-2 are formed in the embedded member 154-1 and connected to the wirings 153a-2-3 and 153a-2-2 of the oxide film 153-2, respectively. At this time, in Fig. 28, the through electrode 161-1 is formed in a part of the recessed portion 154a and connected to the wiring 153a-2-3 of the oxide film 153-2.

[0126] 30, after the PAD electrode 33 is formed in the recessed portion 54a, an oxide film 153-1 having terminals 153a-1-1 to 153a-1-3 is formed. Furthermore, the terminals 131c-1 to 131c-3 of the wiring layer 131b of the image sensor 131 and the terminals 153a-1-1 to 153a-1-3 of the oxide film 153-1 are joined in an opposing state.

[0127] In the ninth step, as shown in FIG. 31 , the photoelectric conversion layer 131 a of the image sensor 131 is thinned, and an on-chip filter 151 and an on-chip lens 152 are laminated on the image sensor 131. Thereafter, a rectangular through-hole 132, which is located at a position corresponding to the PAD electrode 133 and is smaller than the PAD electrode 133 when viewed from above, is formed so as to penetrate the image sensor 131 and the oxide film 153-1, thereby completing the solid-state imaging element 111.

[0128] <<7. Application Examples to Electronic Devices>> The above-described solid-state imaging device can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, and other devices with imaging functions.

[0129] FIG. 32 is a block diagram showing an example of the configuration of an imaging device as an electronic device to which the present technology is applied.

[0130] The imaging device 501 shown in Figure 32 is configured with an optical system 502, a shutter device 503, a solid-state imaging element 504, a drive circuit 505, a signal processing circuit 506, a monitor 507, and a memory 508, and is capable of capturing still images and moving images.

[0131] The optical system 502 is configured to have one or more lenses, and guides light from a subject (incident light) to the solid-state image sensor 504 to form an image on the light-receiving surface of the solid-state image sensor 504 .

[0132] The shutter device 503 is disposed between the optical system 502 and the solid-state image sensor 504 , and controls the light irradiation period and light blocking period for the solid-state image sensor 504 under the control of the drive circuit 505 .

[0133] The solid-state imaging element 504 is configured by a package including the above-mentioned solid-state imaging element. The solid-state imaging element 504 accumulates signal charges for a certain period of time in response to light that is focused on the light-receiving surface via the optical system 502 and the shutter device 503. The signal charges accumulated in the solid-state imaging element 504 are transferred in accordance with a drive signal (timing signal) supplied from a drive circuit 505.

[0134] The drive circuit 505 outputs drive signals that control the transfer operation of the solid-state image sensor 504 and the shutter operation of the shutter device 503 , thereby driving the solid-state image sensor 504 and the shutter device 503 .

[0135] The signal processing circuit 506 performs various signal processing on the signal charges output from the solid-state imaging device 504. The image (image data) obtained by the signal processing performed by the signal processing circuit 506 is supplied to a monitor 507 to be displayed, or supplied to a memory 508 to be stored (recorded).

[0136] Even in the imaging device 501 configured in this manner, by applying the above-described solid-state imaging elements 11, 11A to 11D, and 111, it is possible to improve the area efficiency related to the arrangement of PAD electrodes. Also, it is possible to suppress damage to wiring during wire bonding. Furthermore, by configuring the PAD electrodes within the embedded material, a HDP (High Density Plasma) film is not required, making it possible to reduce the influence of hydrogen caused by HDP. Also, it is possible to reduce the parasitic capacitance occurring in the wiring connected to the PAD electrodes.

[0137] <<8. Examples of using solid-state imaging devices>> 33 is a diagram showing an example of using the above-described solid-state imaging elements 11, 11A to 11D, and 111. The above-described solid-state imaging elements can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows. ·Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes - Devices used for traffic purposes, such as in-vehicle sensors that take pictures of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping, and for recognizing the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. A device used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and operate the appliances according to those gestures. -Medical and healthcare equipment, such as endoscopes and devices that take blood vessel images using infrared light - Security devices such as surveillance cameras for crime prevention and cameras for person authentication Cosmetic devices such as skin measuring devices that take pictures of the skin and microscopes that take pictures of the scalp Sports equipment such as action cameras and wearable cameras for sports purposes

[0138] <<9. Mobile Application Examples>> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0139] FIG. 34 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0140] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 34, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0141] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0142] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0143] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0144] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0145] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0146] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0147] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0148] Furthermore, the microcomputer 12051 can output a control command to the vehicle exterior information detection unit 12030 based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0149] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 34, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0150] FIG. 35 is a diagram showing an example of the installation position of the imaging unit 12031.

[0151] In FIG. 35, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0152] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0153] 35 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0154] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0155] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0156] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0157] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0158] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 in the configuration described above. Specifically, the solid-state imaging elements 11, 11A to 11D, and 111 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to improve the area efficiency related to the arrangement of PAD electrodes, suppress damage to wiring, reduce the influence of hydrogen caused by HDP, and reduce parasitic capacitance.

[0159] The present disclosure can also be configured as follows.

[0160] <1> a first semiconductor element having an image pickup element that photoelectrically converts incident light; a second semiconductor element smaller than the first semiconductor element, the second semiconductor element having a signal processing circuit that processes pixel signals of the image sensor; The second semiconductor element is surrounded by a filling material, and a pad electrode is formed in the filling material. Solid-state imaging element. <2> A recessed portion is formed in the embedded member, and the pad electrode is formed in the recessed portion. <1> The solid-state imaging device according to claim 1. <3> The filling member is made of a material with a low dielectric constant. <1> or <2> The solid-state imaging device according to claim 1. <4> A through hole is formed directly above the PAD electrode in the direction opposite to the incident direction of the incident light, passing through the first semiconductor element and reaching the PAD electrode. <1> ~ <3> 10. The solid-state imaging device according to claim 9, wherein <5> The through-hole is formed to penetrate the first semiconductor element and the embedded member to reach the pad electrode. <4> The solid-state imaging device according to claim 1. <6> Wires connected to an external signal processing device are inserted through the through holes and bonded to the pad electrodes. <4> The solid-state imaging device according to claim 1. <7> a third semiconductor element different from the second semiconductor element, the third semiconductor element having a signal processing circuit that processes pixel signals of the image sensor; Layers including the first semiconductor element, the second semiconductor element, and the third semiconductor element are stacked in this order from the incident direction of the incident light. <1> The solid-state imaging device according to claim 1. <8> The third semiconductor element is the same size as the first semiconductor element. <7> The solid-state imaging device according to claim 1. <9> the third semiconductor element is smaller than the first semiconductor element; In the layer including the third semiconductor element, the periphery of the third semiconductor element is filled with another filling material different from the filling material. <7> The solid-state imaging device according to claim 1. <10> Further comprising a support substrate having the same size as the first semiconductor element; The layers including the first semiconductor element, the second semiconductor element, the third semiconductor element, and the support substrate are stacked in this order from the incident direction of the incident light: the first semiconductor element, the second semiconductor element, the third semiconductor element, and the support substrate. <9> The solid-state imaging device according to claim 1. <11> a through hole penetrating the support substrate and the third semiconductor element from a direction opposite to the incident direction of the incident light; an inner wall wiring electrically connected to the PAD electrode on an inner wall of the through hole; a back surface electrode is formed near the through hole on a back surface side of the support substrate when the incident direction of the incident light is the front surface; The back surface electrode is electrically connected to the pad electrode via the inner wall wiring. <10> The solid-state imaging device according to claim 1. <12> The second semiconductor element and the third semiconductor element each include a silicon layer and a wiring layer, and the silicon layer and the wiring layer are stacked in the same order with respect to the incident direction of the incident light. <9> The solid-state imaging device according to claim 1. <13> The second semiconductor element and the third semiconductor element each include a silicon layer and a wiring layer, and the silicon layer and the wiring layer are stacked in different orders with respect to the incident direction of the incident light. <9> The solid-state imaging device according to claim 1. <14> The second semiconductor element includes a silicon layer and a wiring layer, and includes a through electrode formed through the silicon layer. <9> The solid-state imaging device according to claim 1. <15> A plurality of the third semiconductor elements are arranged on the same layer. <9> The solid-state imaging device according to claim 1. <16> A through electrode is formed through the embedded member. <9> The solid-state imaging device according to claim 1. <17> The through electrode electrically connects the first semiconductor element and the third semiconductor element. <16> The solid-state imaging device according to claim 1. <18> The through electrode electrically connects the pad electrode and the third semiconductor element. <16> The solid-state imaging device according to claim 1. <19> a first semiconductor element having an image pickup element that photoelectrically converts incident light; a second semiconductor element smaller than the first semiconductor element, the second semiconductor element having a signal processing circuit that processes pixel signals of the image sensor; a solid-state imaging device in which the periphery of the second semiconductor element is embedded in an embedding material, and a pad electrode is formed in the embedding material; An imaging device comprising: <20> a first semiconductor element having an image pickup element that photoelectrically converts incident light; a second semiconductor element smaller than the first semiconductor element, the second semiconductor element having a signal processing circuit that processes pixel signals of the image sensor; a solid-state imaging device in which the periphery of the second semiconductor element is embedded in an embedding material, and a pad electrode is formed in the embedding material; Electronic equipment equipped with [Explanation of symbols]

[0161] 11, 11A to 11D solid-state imaging device, 31, 31A to 31D image sensor, 32, 32A to 32D through hole, 33, 33A to 33D pad electrode, 34, 34A-1 to 34D-1, 34A-2 to 34D-2 logic substrate, 51, 51A to 51D on-chip filter, 52, 52A to 52D on-chip lens, 53, 53A to 53D oxide film, 54, 54A to 54D embedding member, 55, 55A to 55D support substrate, 111 solid-state imaging device, 131 image sensor, 132 through hole, 133 pad electrode, 134-1, 134-2 logic substrate, 151 on-chip filter, 152 on-chip lens 153-1, 153-2 oxide film, 154-1, 154-2 embedded member, 155 support substrate

Claims

1. a first semiconductor element having an image pickup element that photoelectrically converts incident light; a second semiconductor element smaller than the first semiconductor element, the second semiconductor element having a signal processing circuit for processing pixel signals of the imaging element; The periphery of the second semiconductor element is filled with a filling material, and a pad electrode is formed in the filling material. Solid-state imaging element.

2. A recessed portion is formed in the embedded member, and the pad electrode is formed in the recessed portion. The solid-state imaging device according to claim 1 .

3. The filling member is made of a material with a low dielectric constant. The solid-state imaging device according to claim 1 .

4. A through hole is formed directly above the PAD electrode in the direction opposite to the incident direction of the incident light, passing through the first semiconductor element and reaching the PAD electrode. The solid-state imaging device according to claim 1 .

5. The through-hole is formed to penetrate the first semiconductor element and the embedded member to reach the pad electrode.

5. The solid-state imaging device according to claim 4.

6. Wires connected to an external signal processing device are inserted through the through holes and bonded to the pad electrodes.

5. The solid-state imaging device according to claim 4.

7. a third semiconductor element different from the second semiconductor element, the third semiconductor element having a signal processing circuit that processes pixel signals of the image sensor; Layers including the first semiconductor element, the second semiconductor element, and the third semiconductor element are stacked in this order from the incident direction of the incident light. The solid-state imaging device according to claim 1 .

8. The third semiconductor element has the same size as the first semiconductor element. The solid-state imaging device according to claim 7 .

9. the third semiconductor element is smaller than the first semiconductor element; In the layer including the third semiconductor element, the periphery of the third semiconductor element is filled with another filling material different from the filling material. The solid-state imaging device according to claim 7 .

10. further comprising a support substrate having the same size as the first semiconductor element; The layers including the first semiconductor element, the second semiconductor element, the third semiconductor element, and the support substrate are stacked in this order from the incident direction of the incident light: the first semiconductor element, the second semiconductor element, the third semiconductor element, and the support substrate. The solid-state imaging device according to claim 9 .

11. a through hole penetrating the support substrate and the third semiconductor element from a direction opposite to the incident direction of the incident light; an inner wall wiring electrically connected to the PAD electrode on an inner wall of the through hole; a back surface electrode is formed near the through hole on a back surface side of the support substrate when the incident direction of the incident light is the front surface; The back surface electrode is electrically connected to the pad electrode via the inner wall wiring. The solid-state imaging device according to claim 10.

12. The second semiconductor element and the third semiconductor element each include a silicon layer and a wiring layer, and the silicon layer and the wiring layer are stacked in the same order with respect to the incident direction of the incident light. The solid-state imaging device according to claim 9 .

13. The second semiconductor element and the third semiconductor element each include a silicon layer and a wiring layer, and the silicon layer and the wiring layer are stacked in different orders with respect to the incident direction of the incident light. The solid-state imaging device according to claim 9 .

14. The second semiconductor element includes a silicon layer and a wiring layer, and includes a through electrode formed through the silicon layer. The solid-state imaging device according to claim 9 .

15. A plurality of the third semiconductor elements are arranged on the same layer. The solid-state imaging device according to claim 9 .

16. A through electrode is formed through the embedded member. The solid-state imaging device according to claim 9 .

17. The through electrode electrically connects the first semiconductor element and the third semiconductor element. The solid-state imaging device according to claim 16.

18. The through electrode electrically connects the pad electrode and the third semiconductor element. The solid-state imaging device according to claim 16.

19. a first semiconductor element having an image pickup element that photoelectrically converts incident light; a second semiconductor element smaller than the first semiconductor element, the second semiconductor element having a signal processing circuit for processing pixel signals of the imaging element; a solid-state imaging device in which the periphery of the second semiconductor element is embedded in an embedding material, and a pad electrode is formed in the embedding material; An imaging device comprising:

20. a first semiconductor element having an image pickup element that photoelectrically converts incident light; a second semiconductor element smaller than the first semiconductor element, the second semiconductor element having a signal processing circuit for processing pixel signals of the imaging element; a solid-state imaging device in which the periphery of the second semiconductor element is embedded in an embedding material, and a pad electrode is formed in the embedding material; Electronic equipment equipped with

Images