Neutral point potential control device and neutral point potential control method for three-level inverter

Abstract

To maintain balance of a neutral point potential of a three-level inverter.SOLUTION: A voltage command of an inverter is produced based on a deviation (output of subtractors 8, 9) between a current command value obtained by adding a reverse phase fifth-order higher harmonic current command value and a normal phase basic wave current command value, and a detection current obtained by detecting an output current of the inverter (dq inverse converter 13); a zero-phase voltage of DC is obtained based on a deviation between a voltage of an upper side capacitor at a DC part of the inverter and a voltage of a lower side capacitor, and the reverse phase fifth-order higher harmonic current command value (multiplier 19); a sixth-order higher harmonic zero-phase voltage is obtained based on the deviation between the voltage of the upper side capacitor and the voltage of the lower side capacitor, a produced sixth-sinusoidal signal and the reverse phase fifth-order higher harmonic current command value (multiplier 22); the zero-phase voltage of the DC and the sixth-order higher harmonic zero-phase voltage are superposed on the voltage command of the inverter (adders 23, 24); and a switching element of the inverter is subjected to PWM control with a gate signal produced based on the superposed voltage.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to balance control of neutral point potential in a three-level neutral point clamped multilevel inverter. [Background technology]

[0002] The configuration of a neutral-point clamped three-level inverter is shown in Figure 1, and the configuration of a T-type three-level inverter is shown in Figure 2. In Figure 1, P and N are the positive and negative terminals of a DC power supply (not shown). Between the positive terminal P and the negative terminal N, the upper capacitor C1 and the lower capacitor C2 of the DC section are connected in series.

[0003] Between the positive terminal P and the negative terminal N, a series circuit of switching elements S1 to S4, a series circuit of switching elements S5 to S8, and a series circuit of switching elements S9 to S12 are connected in parallel.

[0004] Diodes D1 and D2 are connected in series between the common connection point of switching elements S1 and S2 and the common connection point of switching elements S3 and S4, diodes D3 and D4 are connected in series between the common connection point of switching elements S5 and S6 and the common connection point of switching elements S7 and S8, and diodes D5 and D6 are connected in series between the common connection point of switching elements S9 and S10 and the common connection point of switching elements S11 and S12.

[0005] The common connection point (neutral point O) of the upper capacitor C1 and the lower capacitor C2 is connected to the common connection point of the diodes D1 and D2, the common connection point of the diodes D3 and D4, and the common connection point of the diodes D5 and D6, respectively.

[0006] The common connection point of switching elements S2 and S3 is connected to U-phase terminal U, the common connection point of switching elements S6 and S7 is connected to V-phase terminal V, and the common connection point of switching elements S10 and S11 is connected to W-phase terminal W.

[0007] 2, P and N are the positive and negative terminals of a DC power supply (not shown). An upper capacitor C1 and a lower capacitor C2 of the DC section are connected in series between the positive terminal P and the negative terminal N.

[0008] Between the positive terminal P and the negative terminal N, a series circuit of switching elements S1 and S4, a series circuit of switching elements S5 and S8, and a series circuit of switching elements S9 and S12 are connected in parallel.

[0009] Switching elements S2 and S3 are connected in series between the common connection point (neutral point O) of the upper capacitor C1 and the lower capacitor C2 and the common connection point of the switching elements S1 and S4, switching elements S6 and S7 are connected in series between the neutral point O and the common connection point of the switching elements S5 and S8, and switching elements S10 and S11 are connected in series between the neutral point O and the common connection point of the switching elements S9 and S12.

[0010] The common connection point of switching elements S1 and S4 is connected to U-phase terminal U, the common connection point of switching elements S5 and S8 is connected to V-phase terminal V, and the common connection point of switching elements S9 and S12 is connected to W-phase terminal W.

[0011] The switching elements S1 to S12 are configured by semiconductor switching elements such as IGBTs.

[0012] In Figures 1 and 2, V DCP is the upper capacitor voltage, V DCN is the lower capacitor voltage, i NP is the neutral current, i NPU is the neutral point current of the U phase, i U represents the U-phase output current.

[0013] In such inverters, imbalances in neutral point potential can occur due to conditions such as load, variations in the characteristics of switching elements and DC capacitors, etc. This imbalance can cause problems such as distortion in the voltage and current waveforms output from the inverter, adversely affecting the load and the system, or excessive voltage being applied to switching elements, causing them to be destroyed.

[0014] Conventional technologies allow the neutral point potential to be controlled by superimposing a zero-sequence voltage on the inverter output voltage during input and output of active power and reactive power. However, in applications that barely handle active or reactive power, it is difficult to control the neutral point potential even with these technologies, and neutral point clamping or T-type three-level inverters cannot be applied. Examples of such applications include active filters connected to a grid and negative-sequence current compensators.

[0015] Furthermore, Non-Patent Document 1 reports an example in which the inverter in question is connected in parallel to an inverter with a lower switching frequency to absorb harmonic currents, thereby reducing the impact on the outside and improving the efficiency of the entire device.

[0016] Non-Patent Document 2 proposes a method for controlling the neutral point potential by superimposing a DC zero-phase sequence voltage on the inverter output voltage when a neutral point clamped three-level inverter or a T-type three-level inverter is outputting active power.

[0017] Patent Documents 1 and 2 propose a method of controlling the neutral point potential by superimposing a sixth-order sine wave zero-phase voltage on the inverter output voltage when reactive power is being output.

[0018] Patent Document 3 uses Non-Patent Document 2 and Patent Documents 1 and 2 in combination to enable control of the neutral point potential when the inverter is operating at an arbitrary power factor.

[0019] Patent Document 4 proposes a method of controlling the neutral point potential using a negative-phase sequence second harmonic current without using a zero-phase sequence voltage. [Prior art documents] [Non-patent literature]

[0020] [Non-Patent Document 1] "Three-phase grid-connected inverter with parallel connection of instantaneous reactive power compensator", IEEJ Transactions on Power Systems, Vol. 138, No. 6, pp. 530-537 (2018) [Non-patent document 2] "Analysis of Neutral Point Potential Fluctuations in Neutral Point Clamped Voltage-Type PWM Inverters," IEEJ Transactions on Power Systems, Vol. 113, No. 1, pp. 41-48 (1993) [Patent documents]

[0021] [Patent Document 1] Japanese Patent Application Publication No. 07-079574 [Patent Document 2] Japanese Patent Application Publication No. 07-135782 [Patent Document 3] Japanese Patent Application Laid-Open No. 2013-255317 [Patent Document 4] Japanese Patent Application Laid-Open No. 2017-60272 Summary of the Invention [Problem to be solved by the invention]

[0022] Non-Patent Document 2 and Patent Documents 1 to 3 are methods that are effective only when a positive-phase fundamental wave current is output. Even if the output current is a fundamental wave, it cannot control the neutral point potential if it is in the opposite phase or is mainly composed of harmonics.

[0023] Patent Document 4 makes it possible to control the neutral point potential even in such cases. In particular, under light load conditions where the output current is close to zero, disturbances to the neutral point potential are small, but Non-Patent Document 2 and Patent Documents 1 to 3 make it difficult to control the neutral point potential. If Patent Document 4 is applied, the stability of the neutral point potential can be significantly improved under light load conditions simply by blocking unnecessary negative-phase second harmonic current, and further, the neutral point potential can be controlled without any problems by outputting a very small amount of negative-phase second harmonic current with the appropriate phase.

[0024] However, if the output current increases, the disturbance to the neutral point potential will become greater, and the negative-phase second harmonic current required to maintain the neutral point potential will increase, increasing the risk of adverse effects on the system and load.

[0025] The present invention solves the above-mentioned problems, and its purpose is to provide a neutral point potential control device for a three-level inverter that can maintain the balance of the neutral point potential even when the majority of the output current is harmonics or negative phase and almost no positive phase fundamental wave current is output. [Means for solving the problem]

[0026] The neutral point potential control device for a three-level inverter according to claim 1 for solving the above problem comprises: A neutral point potential control device for a three-level inverter that outputs harmonic currents, which controls the neutral point potential of the inverter by superimposing a zero-phase sequence voltage on the output voltage of the inverter, a current control unit that generates a voltage command for the inverter based on a deviation between a command value of at least one harmonic current of negative phase fifth order, positive phase seventh order, negative phase eleventh order, and positive phase thirteenth order and a detected current obtained by detecting an output current of the inverter; a neutral point potential balance controller that calculates a DC zero-phase sequence voltage or a sixth harmonic zero-phase sequence voltage based on a deviation between a voltage of an upper capacitor and a voltage of a lower capacitor that divide a DC voltage of a DC section of an inverter and a command value of the harmonic current, and that superimposes the calculated DC zero-phase sequence voltage or the sixth harmonic zero-phase sequence voltage on a voltage command of the inverter generated by the current control unit, The neutral point potential balance controller generates a gate signal based on the superimposed voltage, and PWM controls the switching elements of the inverter.

[0027] The neutral point potential control device for a three-level inverter according to claim 2 is the same as claim 1, the current control unit generates a voltage command for the inverter based on a deviation between a current command value obtained by adding a negative-phase fifth-order harmonic current command value and a positive-phase fundamental current command value and a detected current obtained by detecting an output current of the inverter; The neutral point potential balance controller calculates a DC zero-phase sequence voltage based on the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor which divide the DC voltage of the DC part of the inverter and the negative-phase fifth-order harmonic current command value, calculates a sixth-order harmonic zero-phase sequence voltage based on the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor which divide the DC voltage of the DC part of the inverter, the generated sixth-order sine wave signal, and the negative-phase fifth-order harmonic current command value, and superimposes the calculated DC zero-phase sequence voltage and sixth-order harmonic zero-phase sequence voltage on the inverter voltage command generated by the current control unit.

[0028] The neutral point potential control device for a three-level inverter according to claim 3 is the same as claim 2, The current control unit Negative-phase fifth harmonic d-axis current command value I d-5 * and the q-axis current command value I q-5 * The voltage phase ωt of the grid voltage is multiplied by 6 to obtain a dq transform of ωt, which is the value on the rotating coordinate system synchronized with ωt, and the positive-phase d-axis current command value I d1 * and the positive-phase q-axis current command value I q1 * a current command value adder that adds a subtractor for calculating a deviation between a value on a rotating coordinate system synchronized with ωt, which is obtained by performing a dq transformation on an output current detection signal of the inverter using a voltage phase ωt of the system voltage, and an output of the current command value adder; a PI amplifier that amplifies the output of the subtractor and outputs a voltage command on a rotating coordinate system that is synchronized with the voltage phase ωt; The voltage command obtained by adding the reference voltage to the output of the PI amplifier is subjected to dq inverse transformation to obtain the inverter voltage command value vu on the fixed coordinate system. * , vv * , vw * a dq inverse transformer that outputs The neutral point potential balance controller includes: The d-axis current command value I d-5 * and a d-axis side sign detector that detects the value of The q-axis current command value I q-5 * and a q-axis side sign detector that detects the value of a d-axis side multiplier that multiplies the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter by the sign output from the d-axis side sign detector to obtain a DC zero-phase voltage α; and a q-axis side multiplier that multiplies sin6ωt, which is obtained by multiplying the voltage phase ωt of the system voltage by six to obtain a sine wave of the corresponding phase, by the code output from the q-axis side code detector and the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter, to obtain the zero-phase voltage γ of the sixth harmonic.

[0029] The neutral point potential control device for a three-level inverter according to claim 4 is the device according to claim 1, The current control unit converts the d-axis current command value and the q-axis current command value of the 1±6n-th harmonic (n is an integer) into a value on a rotating coordinate system synchronized with the voltage phase ωt of the system voltage, which is obtained by dq-transforming the d-axis current command value and the q-axis current command value of the 1±6n-th harmonic (n is an integer), and converts the value into a positive-phase d-axis current command value I d1 * and the positive-phase q-axis current command value I q1 * a current command value adder that adds a subtractor for calculating a deviation between a value on a rotating coordinate system synchronized with ωt, which is obtained by performing a dq transformation on an output current detection signal of the inverter using a voltage phase ωt of the system voltage, and an output of the current command value adder; a PI amplifier that amplifies the output of the subtractor and outputs a voltage command on a rotating coordinate system that is synchronized with the voltage phase ωt; The voltage command obtained by adding the reference voltage to the output of the PI amplifier is subjected to dq inverse transformation to obtain the inverter voltage command value vu on the fixed coordinate system. * , vv * , vw * a dq inverse transformer that outputs The neutral point potential balance controller includes: a d-axis side sign detector that multiplies the d-axis current command values ​​of the 1±6n-th harmonic by respective coefficients, detects the sum of the multiplication outputs, and outputs a sign corresponding to the detected value; a q-axis side sign detector that multiplies the q-axis current command values ​​of the 1±6n-th harmonic by respective coefficients, detects the sum of the multiplication outputs, and outputs a sign corresponding to the detected value; a d-axis side multiplier that multiplies the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter by the sign output from the d-axis side sign detector to obtain a DC zero-phase voltage α; and a q-axis side multiplier that multiplies the voltage phase ωt of the system voltage by the order of the harmonic, and multiplies the sine wave of the corresponding phase by the sign output from the q-axis side sign detector and the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter, to obtain the zero-phase voltage of the 1±6n-th harmonic.

[0030] The neutral point potential control device for a three-level inverter according to claim 5 is the same as claim 4, the d-axis current command value and the q-axis current command value of the harmonics added by the current command value adder of the current control unit include at least one of a negative-phase fifth harmonic, a positive-phase seventh harmonic, a negative-phase eleventh harmonic, and a positive-phase thirteenth harmonic; The d-axis side multiplier of the neutral point potential balance controller is characterized in that, instead of the DC zero-phase sequence voltage α, it multiplies the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter, the sign output from the d-axis side sign detector, and the voltage phase ωt of the system voltage by the order of the harmonic, and multiplies it by a cosine wave of a corresponding phase, thereby obtaining a harmonic zero-phase sequence voltage that is 90° out of phase with the zero-phase sequence voltage obtained by the q-axis side multiplier.

[0031] The neutral point potential control device for a three-level inverter according to claim 6 is the same as claim 3, The current command value adder of the current control unit calculates the negative-phase fundamental wave d-axis current command value I d-1 * and the negative-phase fundamental wave q-axis current command value I q-1 * Adding more, The neutral point potential balance controller includes: The negative-phase fundamental wave d-axis current command value I d-1 * and a negative-phase fundamental wave d-axis side sign detector that detects the value of The negative-phase fundamental wave q-axis current command value I q-1 * and a negative-phase fundamental wave q-axis side sign detector that detects the value of a negative-phase-sequence fundamental wave d-axis side multiplier that calculates a zero-phase-sequence voltage ε of a second harmonic by multiplying the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter, the sign output from the negative-phase-sequence fundamental wave d-axis side sign detector, and cos2ωt, which is obtained by doubling the voltage phase ωt of the system voltage and calculating a cosine wave of the corresponding phase; a negative-phase-sequence fundamental wave q-axis side multiplier that multiplies a deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC section of the inverter by the sign output from the negative-phase-sequence fundamental wave q-axis side sign detector, and sin2ωt obtained by doubling the voltage phase ωt of the system voltage and determining a sine wave of a corresponding phase, thereby determining a zero-phase-sequence voltage ζ of a second harmonic that is 90° out of phase with the zero-phase-sequence voltage ε; The d-axis side multiplier of the neutral point potential balance controller is characterized in that, instead of the DC zero-phase sequence voltage α, it multiplies the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter, the detection code output from the d-axis side code detector, and cos6ωt, which is obtained by multiplying the voltage phase ωt of the system voltage by six and determining a cosine wave of the corresponding phase, to determine a sixth-order harmonic zero-phase sequence voltage δ which is 90° out of phase with the zero-phase sequence voltage γ.

[0032] The neutral point potential control device for a three-level inverter according to claim 7 comprises: The neutral point potential control device according to claim 4; The neutral point potential control device according to claim 5; The present invention is characterized in that it includes a switching unit that switches to either the neutral point potential control device described in claim 4 or the neutral point potential control device described in claim 5 when a set switching condition is met.

[0033] The method for controlling a neutral point potential of a three-level inverter according to claim 8 comprises: A method for controlling a neutral point potential of a three-level inverter that outputs harmonic currents by superimposing a zero-phase sequence voltage on an output voltage of the inverter, comprising: a current control step in which the current control unit generates a voltage command for the inverter based on a deviation between a command value of at least one harmonic current of negative phase 5th, positive phase 7th, negative phase 11th, and positive phase 13th and a detected current obtained by detecting the output current of the inverter; a neutral point potential balance control step in which a neutral point potential balance controller calculates a DC zero-phase-sequence voltage or a sixth-order harmonic zero-phase-sequence voltage based on a deviation between a voltage of an upper capacitor and a voltage of a lower capacitor which divide a DC voltage of a DC section of an inverter and a command value of the harmonic current, and superimposes the calculated DC zero-phase-sequence voltage or the sixth-order harmonic zero-phase-sequence voltage on a voltage command of the inverter generated by the current control section; The method is characterized in that the switching elements of the inverter are PWM controlled by a gate signal generated based on the voltage superimposed in the neutral point potential balance control step. [Effects of the Invention]

[0034] (1) According to the inventions described in claims 1 to 8, the neutral point potential balance can be maintained even when the majority of the output current of a three-level inverter is harmonics or negative phase and there is almost no output of positive-phase fundamental current. This makes it possible to suppress distortion of the output voltage and current caused by imbalance in the neutral point potential and to equalize the voltage applied to the switching elements. (2) According to the inventions set forth in claims 2 and 3, even when the majority of the output current of the three-level inverter is a negative-phase fifth harmonic current, the balance of the neutral point potential can be maintained. (3) According to the inventions set forth in claims 4 and 5, the balance of the neutral point potential can be maintained even when the output current of the three-level inverter contains a mixture of positive-phase fundamental current, negative-phase fifth harmonic current, and positive-phase seventh harmonic current. Similarly, by extending the scope of the invention, it is also possible to handle negative-phase 11th and positive-phase 13th harmonic currents. (4) According to the invention described in claim 4, a high effect of maintaining the balance of the neutral point potential can be obtained, particularly when applied to applications where a certain degree of input and output of effective power is expected. (5) According to the invention described in claim 5, a high neutral point potential balance can be maintained effectively, especially when applied to applications where the input and output of effective power is very small. (6) According to the invention as set forth in claim 6, even when the majority of the output current of the three-level inverter is a negative-phase fundamental current, the balance of the neutral point potential can be maintained. [Brief explanation of the drawings]

[0035] [Figure 1] Main circuit configuration diagram of a neutral point clamped three-level inverter. [Figure 2] Main circuit configuration diagram of a T-type three-level inverter. [Figure 3] FIG. 1 is a control block diagram of a first embodiment of the present invention. [Figure 4] FIG. 10 is a control block diagram of a second embodiment of the present invention. [Figure 5] FIG. 10 is a control block diagram of a third embodiment of the present invention. [Figure 6]FIG. 10 is a control block diagram of a fourth embodiment of the present invention. [Figure 7] FIG. 10 is an explanatory diagram showing simulation conditions when the effects of the present invention are confirmed by simulation. [Figure 8] FIG. 4 is a waveform diagram showing a simulation result of the first embodiment of the present invention. [Figure 9] FIG. 10 is a waveform diagram showing a simulation result of Example 3 of the present invention. [Figure 10] FIG. 10 is a waveform diagram showing a simulation result of Example 4 of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0036] Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments. In the following Examples 1 to 4, it is assumed that current control is applied to an inverter. [Example]

[0037] Fig. 3 shows a control block diagram of the first embodiment. Fig. 3 includes a current control block (current control unit) and a neutral point potential balance controller. First, the configuration of the current control block will be described.

[0038] Reference numeral 1 denotes a PLL (Phase Locked Loop) circuit that receives the detection signal Vs of the system voltage (the voltage of the system to which the three-level inverter is connected) as input and outputs the voltage phase ωt, and reference numeral 2 denotes a low-pass filter (LPF) that receives the three-phase inverter output current detection signal I as input and removes noise, switching ripple, etc. from the detected current I.

[0039] A dq converter 3 receives the output of the low-pass filter 2 and converts the inverter output current detection signal into a value on a rotating coordinate system synchronized with the voltage phase ωt. The d-axis component of the output of the dq converter 3 is Id, and the q-axis component is Iq.

[0040] I d-5 * is the negative-phase fifth-order d-axis current command value, I q-5 *is the negative-phase fifth-order q-axis current command value, I d1 * is the positive-phase d-axis current command value, I q1 * is the positive-phase q-axis current command value.

[0041] 4 is a multiplier that multiplies the voltage phase ωt by 6 and outputs 6ωt, and 5 is a current command value I, which is a DC value on a rotating coordinate system synchronized with -5 times the voltage phase ωt. d-5 * , I q-5 * is a dq converter that converts the value on the rotating coordinate system synchronized with the voltage phase ωt using 6ωt.

[0042] 6 is the negative-phase fifth-order d-axis current command value I d-5 * and the positive-phase d-axis current command value I d1 * , and 7 is the negative-phase fifth-order q-axis current command value I q-5 * and the positive-phase q-axis current command value I q1 * is an adder that adds

[0043] 8 is the output of adder 6 and the d-axis component I d 9 is the subtractor that calculates the deviation between the output of adder 7 and the q-axis component I q It is a subtractor that calculates the deviation from

[0044] Reference numeral 10 denotes a PI amplifier that amplifies the d-axis deviation (output of subtractor 8) and outputs a voltage command value on a rotating coordinate system synchronized with the voltage phase ωt, and reference numeral 11 denotes a PI amplifier that amplifies the q-axis deviation (output of subtractor 9) and outputs a voltage command value on a rotating coordinate system synchronized with the voltage phase ωt.

[0045] An adder 12 adds a reference voltage to the output of the PI amplifier 10 on the d-axis side. This reference voltage may be a fixed value representing the rated amplitude of the grid voltage, or it may be the amplitude detected from the grid voltage detection signal Vs and added. Vs may also be dq-transformed and added to both the d-axis and q-axis.

[0046] 13 is a dq inverse converter that receives a voltage command value on the rotating coordinate system and converts it into a value on the fixed coordinate system using the voltage phase ωt. The output of the dq inverse converter 13 is the voltage command value vu * , vv * , vw * This becomes:

[0047] Next, the configuration of the neutral point potential balance controller will be described. 14 is the negative-phase fifth-order d-axis current command value I d-5 * This is a sign detector (d-axis side sign detector) that detects the value of and outputs 1 if it is positive, -1 if it is negative, and 0 if it is zero.

[0048] 15 is the negative-phase fifth-order q-axis current command value I q-5 * This is a sign detector (q-axis side sign detector) that detects the value of and outputs 1 if it is positive, -1 if it is negative, and 0 if it is zero.

[0049] 16 is the upper capacitor voltage V of the DC part of the inverter DCP The detection signal and the lower capacitor voltage V DCN It is a subtractor that calculates the deviation of the detection signal.

[0050] Reference numeral 17 denotes a low-pass filter (LPF) that removes noise, switching ripple, and third-order harmonic ripple that is superimposed in principle from the deviation obtained by subtractor 16, and reference numeral 18 denotes a multiplier that multiplies the output of low-pass filter 17 by a gain G.

[0051] 19 is the negative-phase fifth-order d-axis current command value I d-5 * and the sign of the upper capacitor voltage V DCP and the lower capacitor voltage V DCN The output of multiplier 19 is a DC zero-phase sequence voltage α (described later) that is superimposed on the inverter voltage command (output of dq inverter 13).

[0052] Reference numeral 20 denotes a multiplier that multiplies the voltage phase ωt by six and outputs 6ωt, and 21 denotes a sine wave generator that inputs 6ωt and outputs a sine wave (sin6ωt) of the corresponding phase.

[0053] 22 is the negative-phase fifth-order q-axis current command value I q-5 * The sign of the sine wave generator 21, the output sin6ωt, and the upper capacitor voltage V DCP and the lower capacitor voltage V DCN The output of multiplier 22 is a zero-phase voltage γsin6ωt of the sixth harmonic, which will be described later, and is superimposed on the voltage command of the inverter (the output of dq inverter 13).

[0054] An adder 23 calculates the sum of the output of the multiplier 19 and the output of the multiplier 22, and the output of this adder 23 becomes the output of the neutral point potential balance controller. The output of the adder 23 is converted into the voltage command value vu * , vv * , vw * It adds up to everything.

[0055] Reference numeral 25 denotes a PWM modulator that PWM-modulates the output of the adder 24, adds a dead time, converts it into a gate signal for the switching element of the inverter, and outputs it.

[0056] Next, the operation of the first embodiment will be explained. First, the relationship between the inverter output voltage and current and the current flowing out from the neutral point will be clarified. The U-phase output voltage command value is set to v U * , U-phase output current is i Un and is defined as in the following equation (1).

[0057]

number

[0058] V is the amplitude of the voltage command value, and assumes -1≦V≦1. ω is the angular frequency of the fundamental wave. α is the DC zero-phase voltage, and γ and δ are the amplitudes of the sixth-order harmonic zero-phase voltages that are 90° out of phase with each other. β is the amplitude of the third-order harmonic zero-phase voltage that is superimposed to improve the voltage utilization rate. n represents the harmonic order of the current and is an integer that can contain negative values. n=1 represents the positive-phase fundamental current, and n=-5 represents the negative-phase fifth-order harmonic current. φ n is the phase difference of the current relative to the voltage.

[0059] Calculate the average value of the neutral point current of the U phase per cycle. * If = 0, the middle arm (switching elements S2, S3, S6, S7, S10, and S11 in the circuits of Figures 1 and 2) is turned on, and the U-phase output current i U All of the current flows out from the neutral point (O).

[0060] v U * =±1, i U passes through the upper and lower arm switching elements (S1, S5, S9, S4, S8, S12) and no current flows to the neutral point O.

[0061] vu * = 0.3, then i U Of this, 70% passes through the neutral point O, and the remaining 30% passes through the upper arm switching element. The proportion of this output current passing through the neutral point can be expressed by the following equation (2).

[0062]

number

[0063] U-phase neutral current i due to n-th harmonic NPUn is the rate at which the output current passes through the neutral point, and i U This can be calculated using the following equation (3):

[0064]

number

[0065] Average value of neutral point current of U phase per one period I NPUn is i NPUn However, the absolute value must be evaluated by dividing the integration interval. Here, the cases are divided into phase angles ±π / 2 and ±3π / 2, but this only works as an approximate solution when α, β, γ, and δ are close to 0. The average value I of the U-phase neutral point current when n=1 NPU1 is expressed as the following equation (4).

[0066]

number

[0067] The neutral point current can be calculated in the same way for the V and W phases, and the average value I of the neutral point current per cycle for the total of the three phases can be calculated. NPn Furthermore, I dn ,I qn is defined as the following equation (5).

[0068]

number

[0069] Enter the order of harmonics that are likely to appear in n and get I NPn Find φ n By substituting equation (5), we obtain the following equation (6).

[0070]

number

[0071] As shown in Non-Patent Document 2, it is true that when a positive-phase fundamental wave d-axis current, i.e., active power, is input or output, superimposing a DC zero-phase sequence voltage can generate a neutral point current, which can be used to control the neutral point potential.

[0072] Furthermore, as shown in Patent Documents 1 and 2, when a positive-phase fundamental wave q-axis current, i.e., reactive power, is input or output, a neutral point current can be generated by superimposing a sixth-order zero-phase sequence voltage. Although it is possible to generate a neutral point current by superimposing a sixth-order zero-phase sequence voltage during input or output of active power, it is clear that the neutral point current obtained is only 1 / 35 of that obtained with a DC zero-phase sequence voltage, and the effect of controlling the neutral point potential is extremely low.

[0073] The control methods of Non-Patent Document 2 and Patent Documents 1 and 2 do not interfere with each other, and it is also shown that both can be used in combination, as in Patent Document 3. As Patent Document 4 shows, a negative-phase second harmonic current directly affects the neutral point current (or the neutral point current can be manipulated) without superimposing a zero-phase sequence voltage, and while there is an effect when a third harmonic is superimposed on a zero-phase sequence voltage, there is no effect when a DC or sixth harmonic zero-phase sequence voltage is used. Therefore, Patent Document 4 and Non-Patent Document 2, and Patent Documents 1 to 3 can be used in combination without interfering with each other.

[0074] On the other hand, equation (6) shows that when a DC zero-phase sequence voltage is superimposed, a neutral point current can be generated if the d-axis current is even a negative-phase fifth or positive-phase seventh harmonic.

[0075] Furthermore, a neutral point current can also be generated by combining a sixth-order zero-phase sequence voltage with a negative fifth-order or positive seventh-order harmonic. In particular, when superimposing a sixth-order harmonic zero-phase sequence voltage, the coefficient of equation (6) becomes larger when combined with a negative fifth-order or positive seventh-order harmonic current rather than the fundamental wave. This indicates that a larger neutral point current can be obtained, making it easier to control the neutral point potential.

[0076] Based on the above results, Example 1 controls the neutral point potential by combining the d-axis negative-phase fifth harmonic and DC zero-phase voltage (α), and the q-axis negative-phase fifth harmonic and sixth harmonic zero-phase voltage (γ).

[0077] That is, the current control section uses subtractors 8 and 9 to calculate the deviation between the current command value (output of adders 6 and 7) obtained by adding the negative-phase fifth-order harmonic current command value and the positive-phase fundamental current command value and the detected current (output of dq converter 3) obtained by detecting the inverter output current, and generates a voltage command for the inverter based on this deviation (dq inverse converter 13).The neutral point potential balance controller calculates the DC zero-phase voltage α using d-axis side multiplier 19 and the sixth-order harmonic zero-phase voltage γ using q-axis side multiplier 22, and superimposes the sum of the zero-phase voltages α and γ on the inverter voltage command (output of dq inverse converter 13).

[0078] Negative-phase fifth-order d-axis current command value I d-5 * But, I d-5 * >0 and V DCP >V DCN In this case, the voltage command value vu * , vv * , vw * A positive DC zero-phase voltage (α: output of multiplier 19) is superimposed on I. That is, in equation (1), α>0. At this time, from equation (6), I NP-5 <0, a negative neutral current is generated, and when the inverter is connected to the grid, it flows from the grid to the inverter. This neutral current discharges the upper capacitor (C1) and charges the lower capacitor (C2), resulting in V DCP and V DCN The difference becomes smaller.

[0079] Also V DCP >V DC But I d-5 * <0, the output of the sign detector 14 becomes negative, and α<0 in equation (1). NP-5 <0 remains unchanged V DCP and V DCN It operates to reduce the difference between

[0080] I q-5 * >0 and V DCP >V DCNIn this case, a sixth-order sine wave is superimposed as a zero-phase voltage (γ: output of multiplier 22) and γ>0. From equation (6), a negative neutral point current is generated, and V DCP and V DCN The difference becomes smaller.

[0081] This allows the neutral point potential to be balanced, suppresses distortion in the output voltage and current caused by an imbalance in the neutral point potential, and equalizes the voltage applied to the switching elements.

[0082] In general harmonic loads, the current tends to be smaller as the harmonic order increases. Example 1 is a method for controlling the neutral point potential, assuming a device that outputs mainly negative-phase fifth harmonic, such as an active filter connected to the same system as such a load. [Example]

[0083] In Example 1, for example, while outputting a negative-phase fifth-order d-axis current of 0.5 pu (I d-5 =0.5) and superimpose a DC zero-phase voltage (α) to obtain I NP-5 Consider the case where the neutral point potential is controlled by generating

[0084] At this time, the positive-phase fundamental wave d-axis current I d1 If you also output I NP1 also occurs, but I d1 >-0.1 pu then I NP-5 and I NP1 The orientation of is the same, or I NP-5 The absolute value of I NP1 Since this is larger than the absolute value of , the neutral point potential can be controlled without any problems.

[0085] However, I d1 <-0.1 pu is I NP-5 and I NP1 The direction of is reversed and I NP-5 The absolute value of I NP1 Since the absolute value of the neutral point current is smaller than the intended value, the neutral point current flows in the opposite direction to the intended direction, making it impossible to control the neutral point potential, and in fact promoting a deterioration of the balance.

[0086] In this case, the voltage command value vu * , vv * , vw * The direction of the DC voltage added as a zero-phase voltage to I d1 Ga-I d-5 You have to judge whether it is greater or less than / 5.

[0087] In the second embodiment, a countermeasure against the above problem is applied to the first embodiment. FIG. 4 shows a control block of the second embodiment. In FIG. 4, the same parts as in FIG. 3 are designated by the same reference numerals. The current control block in FIG. 4 differs from the configuration in FIG. 3 in that the detected current (I d、 I q ) and a positive-phase seventh-order current command value is added as a current command value for taking the deviation from the

[0088] That is, a multiplier 31 multiplies the voltage phase ωt by -6 and outputs -6ωt, and a positive-phase seventh-order d-axis current command value I d7 * and the q-axis current command value I q7 * The output of the dq converter 32 is converted into a value on the rotation coordinate system synchronized with ωt using -6ωt, and the output of the dq converter 32 is converted into an inverse-phase fifth-order d-axis current command value I d-5 * , q-axis current command value I q-5 * and adders 33 and 34 are added to add the values ​​after dq transformation of the input signal and the output signal, respectively.

[0089] The neutral point potential balance controller in FIG. 4 differs from the configuration in FIG. 3 in that each current command value is multiplied by a coefficient, and the sum of these coefficients determines the signs of the DC zero-phase sequence voltage α and the sixth-order harmonic zero-phase sequence voltage γ.

[0090] That is, the positive-phase seventh-order d-axis current command value I d7 * by a coefficient -1 / 7, and the negative-phase fifth-order d-axis current command value I d-5 *a multiplier 36 that multiplies the output value of the multipliers 35 and 36 and the positive-phase d-axis current command value I d1 The output of the adder 37 is input to the sign detector 14 to obtain the positive phase seventh order q-axis current command value I q7 * by a coefficient -1 / 13, and the negative-phase fifth-order q-axis current command value I q-5 * by a coefficient 1 / 11, and a positive-phase q-axis current command value I q1 * A multiplier 40 is provided to multiply the value by a coefficient -1 / 35, and an adder 41 is provided to sum the output values ​​of the multipliers 38, 39, and 40, and the output of the adder 41 is input to the sign detector 15. Other parts are configured in the same way as in FIG.

[0091] In the second embodiment, the output of the adder 37 input to the sign detector 14 on the d-axis side, that is, I d1 +I d-5 / 5-I d7 The sign of the DC zero-phase voltage α (output of the d-axis multiplier 19) is determined depending on whether / 7 is greater than or less than zero. d-5 =0.5, I d7 At =0, I d1 When is less than -0.1, the sign of α is reversed, and an appropriate zero-phase sequence voltage can be superimposed. In the second embodiment, this measure is also applied to the q axis.

[0092] That is, the sign of the zero-phase sequence voltage γ of the sixth harmonic (the output of the q-axis side multiplier 22) is determined depending on whether the output of the adder 41 input to the sign detector 15 is greater than or less than zero.

[0093] Therefore, the neutral point potential control can be performed by applying the second embodiment to a device that also outputs a positive-phase fundamental current or that mainly outputs a positive-phase seventh harmonic current instead of a negative-phase fifth harmonic current.Similarly, the invention can be extended to harmonics of the tenth order and above.

[0094] That is, an adder is added to the current control block in Figure 4 to add the d-axis and q-axis current command values ​​of the 1±6n-th order (n is an integer) harmonics, and the neutral point potential balance controller is provided with a multiplier that multiplies by a coefficient, an adder that calculates the total value, a sign detector, and a q-axis multiplier, similar to those described above, corresponding to the 1±6n-th order harmonics, to calculate the zero-phase sequence voltage of the 1±6n-th order harmonics and superimpose it on the inverter voltage command (output of the dq inverse converter 13).

[0095] Therefore, according to the second embodiment, even when the output current of the three-level inverter contains a mixture of a positive-phase fundamental current, a negative-phase fifth-order harmonic current, a positive-phase seventh-order harmonic current, and 1±6n-order harmonics, for example, a negative-phase eleventh-order harmonic current and a positive-phase thirteenth-order harmonic current, the neutral point potential can be balanced. [Example]

[0096] In the first and second embodiments, the neutral point potential is controlled by a combination of the d-axis current and the DC zero-phase sequence voltage (α). In contrast, in the third embodiment, the neutral point potential is controlled by a combination of the d-axis current and the sixth-order zero-phase sequence voltage (δ). I in the above equation (6) d1 and I d-5 When comparing the α and δ terms in d1 The next largest coefficient is I d-5 Therefore, for example, in the case of an application in which the input and output of effective power is expected to a certain extent even if the harmonic current is larger, such as when an active filter function is added to a power storage converter, the neutral point potential control using the DC zero-phase sequence voltage (α) according to the second embodiment is effective.

[0097] However, for applications where the input and output of active power is very small, such as converters with only an active filter function, neutral point potential control using the sixth harmonic zero-phase voltage (δ) is more effective. Example 3 is a neutral point potential control method suitable for such applications.

[0098] FIG. 5 shows a control block diagram of the third embodiment. In FIG. 5, the same parts as in FIG. 4 are designated by the same reference numerals. The neutral point potential balance controller in FIG. 5 differs from the configuration in FIG. 4 in that the multipliers 35 and 36 that multiply the coefficients and the adder 37 that calculates the sum are replaced by a positive-phase seventh-order d-axis current command value I d7 * by a coefficient 7 / 13, and the negative-phase fifth-order d-axis current command value I d-5 * by a coefficient 5 / 11, and a positive-phase d-axis current command value I d1 * The system is further provided with a multiplier 53 that multiplies the voltage phase ωt by a coefficient 1 / 35, an adder 54 that sums the output values ​​of each multiplier, a multiplier 55 that multiplies the voltage phase ωt by six and outputs 6ωt, and a cosine wave generator 56 that inputs 6ωt and outputs a cosine wave (cos6ωt) of the corresponding phase, and the output (cos6ωt) of the cosine wave generator 56 is multiplied by the multiplier 19 (d-axis side multiplier) to obtain a sixth-order harmonic zero-phase voltage δcos6ωt that is 90° out of phase with the zero-phase voltage γsin6ωt. Other parts are configured in the same way as in Figure 4.

[0099] The configuration of FIG. 5 (third embodiment) can also be extended to harmonics of the 10th order and higher (1±6n-th order harmonics) in the same manner as in FIG. 4 (second embodiment).

[0100] Therefore, according to the third embodiment, similar to the second embodiment, even when a positive-phase fundamental current and harmonic currents of multiple orders are mixed, it is possible to maintain the balance of the neutral point potential, and further, when applied to applications in which the input and output of active power is very small, a high effect of maintaining the balance of the neutral point potential can be obtained.

[0101] In the second and third embodiments, the switching may be performed by a switching unit depending on the output of the active power. The switching condition may be, for example, simply comparing the command value of the fundamental wave d-axis current with a fixed threshold value |I d1 * If |>0.1 holds, then the method of using Example 2 can be used. Alternatively, the coefficients of the above equation (6) can be compared to d1 * |>5|Id-5 * If | / 11 is established, it may be switched to Example 2. More precisely, by comparing the magnitude of the sum of the neutral point currents due to the respective harmonics at α=δ, the following equation (7) is obtained.

[0102]

number

[0103] If the above is true, the system may switch to the second embodiment, and if the above is false, the system may switch to the third embodiment. [Example]

[0104] In the first to third embodiments, when only the negative-phase fundamental current is output, the neutral point potential cannot be controlled. This is because I NP-1 As shown in the figure, when n = -1, the neutral point potential cannot be controlled even if DC or third- or sixth-order harmonic voltages are superimposed as zero-phase sequence voltages. Here, we consider superimposing a second-order zero-phase sequence voltage as shown in the following equation (8).

[0105]

number

[0106] εcos2ωt and ζsin2ωt are second-order harmonic zero-sequence voltages that are 90° out of phase with each other.

[0107] Then, if we calculate the neutral current at n=-1 again, we get the following equation (9):

[0108]

number

[0109] From this result, it can be seen that the neutral point potential can be controlled by superimposing a second harmonic on the zero-phase sequence voltage when a negative-phase sequence fundamental current is being output. Based on the above results, Example 4 is designed to enable control of the neutral point potential even when a negative-phase sequence fundamental current is being output. A function is added to Example 1 to superimpose a second-order cosine wave when a negative-phase sequence fundamental d-axis current flows and to superimpose a second-order sine wave on the q-axis current. Furthermore, unlike the DC zero-phase sequence voltage α of Example 1, a combination of a d-axis negative-phase sequence fifth harmonic and a sixth-order zero-phase sequence voltage (δ) is applied. As a result, when a negative-phase sequence fifth harmonic or a negative-phase sequence fundamental current is output, a neutral point current can be generated and the neutral point potential can be controlled.

[0110] FIG. 6 shows a control block diagram of the fourth embodiment. In FIG. 6, the same parts as in FIG. 3 are designated by the same reference numerals. The current control block in FIG. 6 differs from the configuration in FIG. 3 in that it includes a multiplier 61 that doubles the voltage phase ωt and outputs 2ωt, and a d-axis current command value I of the negative-phase fundamental wave, which is a DC value, on a rotating coordinate system synchronized with −1 times ωt. d-1 * and the q-axis current command value I q-1 * The output of the dq converter 62 is converted into a negative-phase fifth-order d-axis current command value I d-5 * , q-axis current command value I q-5 * The difference is that adders 63 and 64 are added to add the values ​​after dq transformation of the input signal and the output signal, respectively.

[0111] The neutral point potential balance controller in FIG. 6 has the following additional components compared to the neutral point potential balance controller in FIG. 3. 65 is a negative-phase fundamental wave d-axis current command value I d-1 * This is a sign detector (negative-phase fundamental wave d-axis side sign detector) that detects the value of and outputs a sign corresponding to the detected value (1 if positive, -1 if negative, 0 if zero).

[0112] 66 is the negative phase fundamental wave q-axis current command value I q-1 *This is a sign detector (negative-phase fundamental wave q-axis side sign detector) that detects the value of and outputs a sign corresponding to the detected value (1 if positive, -1 if negative, 0 if zero).

[0113] Reference numeral 67 denotes a multiplier that doubles the voltage phase ωt and outputs 2ωt, and 68 denotes a cosine wave generator that receives 2ωt as input and outputs a cosine wave (cos2ωt) of the corresponding phase.

[0114] 69 is the negative-phase fundamental wave d-axis current command value I d-1 * The sign of the cosine wave generator 68, the output cos2ωt, and the upper capacitor voltage V DCP and the lower capacitor voltage V DCN The output of multiplier 69 is the zero-phase sequence voltage ε of the second harmonic.

[0115] Reference numeral 70 denotes a multiplier that doubles the voltage phase ωt and outputs 2ωt, and 71 denotes a sine wave generator that inputs 2ωt and outputs a sine wave (sin2ωt) of the corresponding phase.

[0116] 72 is the negative-phase fundamental wave q-axis current command value I q-1 * The sign of the sine wave generator 71, the output sin2ωt, and the upper capacitor voltage V DCP and the lower capacitor voltage V DCN The output of multiplier 72 is the zero-phase sequence voltage ζ of the second harmonic that is 90° out of phase with the ε.

[0117] Reference numeral 73 denotes an adder that adds the output of adder 23 and the output of multiplier 69, and 74 denotes an adder that adds the output of adder 73 and the output of multiplier 72, and the output of adder 74 and the output of the dq inverse transformer 13 are configured to be added in adder 24.

[0118] Furthermore, the multiplier 19 (d-axis side multiplier) in FIG. 6 is a negative-phase fifth-order d-axis current command value I d-5 * The sign of the cosine wave generator 56, the output cos6ωt, and the upper capacitor voltage V DCP and the lower capacitor voltage V DCN The zero-phase voltage δ of the sixth harmonic is calculated by multiplying the deviation of the signal δ by a gain G (the output of the multiplier 18).

[0119] The fourth embodiment can be combined with the second or third embodiment to perform neutral point potential control even when a positive-phase seventh harmonic current or a positive-phase fundamental current is output.

[0120] Furthermore, Example 4 can be used in combination with Examples 1 to 3 since it does not interfere with them, and can maintain the balance of the neutral point potential even when negative-phase fundamental current and harmonic current are mixed.

[0121] In the first to third embodiments, as shown in equation (6), there is no interference with the negative-phase second harmonic current. Also in the third embodiment, even if the neutral point current at n=-2 is calculated using the voltage command value defined in equation (8), the following equation (10) is obtained.

[0122]

number

[0123] Therefore, the present invention can be used in combination with Patent Document 4, and the neutral point potential balance can be maintained even when the output current is close to zero.

[0124] Next, the results of verifying the effects of the present invention through simulation will be described. The main circuit conditions used for the simulation verification are shown in FIG.

[0125] In Fig. 7, the output side of a three-level inverter 70 is connected to a system power supply 100 via a filter circuit 80 consisting of a reactor and a capacitor. This is a model assuming a 415V, 500kVA neutral-point clamped three-level inverter (e.g., Fig. 1).

[0126] Reference numeral 71 denotes a DC power supply for the three-level inverter 70, and a 32Ω resistor 73 is connected between the positive terminal and the neutral point O via a switch 72.

[0127] In this simulation, the control of Examples 1, 3, and 4 was enabled to output current, and at time 0.05 seconds, a 32Ω resistor 73 was connected as a voltage balance disturbance by switch 72. Furthermore, at time 0.15 seconds, the balance control was disabled.

[0128] Figure 8 shows the simulation results for Example 1 (Figure 3). The output current (a) is a 1 p.u. fifth harmonic inverse-phase on the d-axis, and (b) is a fifth harmonic inverse-phase on the q-axis. Note that a 300 Hz resonant amplifier is also used in conjunction with the current-controlled PI amplifiers (10, 11). The superimposed zero-phase voltage (a) is DC (α), and (b) is a sixth harmonic (γ).

[0129] When resistor 73 is turned on, a deviation occurs in the neutral point balance, but it remains constant and stable operation continues. When balance control is disabled, the deviation continues to increase and the system becomes unstable. Comparing (a) and (b), the deviation when resistor 73 is turned on is larger in (a).

[0130] Since there is no difference in the control parameters and the amplitude of the superimposed zero-phase sequence voltage is proportional to the deviation, the amplitude of the zero-phase sequence voltage required to generate the same magnitude of neutral point current is smaller in (b), which means that it is easier to control the neutral point potential. NP-5 In the above, the coefficient of γ is larger than the coefficient of α, and the same tendency is observed.

[0131] In Example 3 (Fig. 5), we proposed superimposing a sixth-harmonic (δ) zero-phase voltage instead of DC on the d-axis negative-phase fifth-harmonic output. The effectiveness of this method was also confirmed by simulation. Fig. 9 shows the results of neutral point potential control using a sixth-harmonic zero-phase voltage on the d-axis negative-phase fifth-harmonic output of 1 p.u.

[0132] Compared to Fig. 8(a), the deviation when the resistor is turned on is small, and I NP-5 As shown in the difference between the coefficients of α and δ in the graph, it is easier to control the neutral point potential in Example 3 with respect to the negative-phase fifth harmonic of the d axis.

[0133] Figure 10 shows the simulation results for Example 4 (Figure 6). The output current is a 1 p.u. fundamental wave of the d-axis or q-axis inverse phase. However, the frequency of the current-controlled resonant amplifier was changed to 100 Hz. The results are the same as those in Figure 8, and if the control is enabled, the neutral point potential balance can be maintained even if resistor 73 is inserted. If the control is disabled, divergence occurs. [Explanation of symbols]

[0134] 1...PLL circuit 2,17...Low-pass filter 3,5,32,62...dq converter 4,18,19,20,22,31,35,36,38,39,40,51,52,53,55,67,69,70,72... multiplier 6,7,12,23,24,33,37,34,41,54,63,64,73,74...adder 8,9,16...Subtractor 10,11...PI amplifier 13...dq inverter 14,15,65,66...Code detector 21,71…sine wave generator 56,68…cosine wave generator

Claims

1. A neutral point potential control device for a three-level inverter that outputs harmonic currents, which controls the neutral point potential of the inverter by superimposing a zero-phase sequence voltage on the output voltage of the inverter, a current control unit that generates a voltage command for the inverter based on a deviation between a command value of at least one harmonic current of negative phase fifth order, positive phase seventh order, negative phase eleventh order, and positive phase thirteenth order and a detected current obtained by detecting an output current of the inverter; a neutral point potential balance controller that calculates a DC zero-phase-sequence voltage or a sixth-order harmonic zero-phase-sequence voltage based on a deviation between a voltage of an upper capacitor and a voltage of a lower capacitor that divide a DC voltage of a DC section of an inverter and a command value of the harmonic current, and superimposes the calculated DC zero-phase-sequence voltage or the sixth-order harmonic zero-phase-sequence voltage on a voltage command of the inverter generated by the current control unit, A neutral point potential control device for a three-level inverter, characterized in that a switching element of the inverter is PWM-controlled by a gate signal generated based on the voltage superimposed by the neutral point potential balance controller.

2. the current control unit generates a voltage command for the inverter based on a deviation between a current command value obtained by adding a negative-phase fifth-order harmonic current command value and a positive-phase fundamental current command value and a detected current obtained by detecting an output current of the inverter; 2. The neutral point potential control device for a three-level inverter according to claim 1, wherein the neutral point potential balance controller calculates a DC zero-phase sequence voltage based on a deviation between a voltage of an upper capacitor and a voltage of a lower capacitor which divide the DC voltage of a DC part of the inverter and the negative-phase-sequence fifth-order harmonic current command value, calculates a sixth-order harmonic zero-phase sequence voltage based on a deviation between a voltage of an upper capacitor and a voltage of a lower capacitor which divide the DC voltage of the DC part of the inverter, the generated sixth-order sine wave signal, and the negative-phase-sequence fifth-order harmonic current command value, and superimposes the calculated DC zero-phase sequence voltage and sixth-order harmonic zero-phase sequence voltage on the inverter voltage command generated by the current control unit.

3. The current control unit Negative-phase fifth harmonic d-axis current command value I ｄ-５ ＊ and the q-axis current command value I ｑ-５ ＊ The voltage phase ωt of the system voltage is multiplied by six to obtain a dq transform of 6ωt, which is a value on the rotating coordinate system synchronized with ωt, and the positive-phase d-axis current command value I ｄ１ ＊ and the positive phase q-axis current command value I ｑ１ ＊ a current command value adder that adds a subtractor for calculating a deviation between a value on a rotating coordinate system synchronized with ωt, the value being obtained by performing dq transformation on an output current detection signal of the inverter using a voltage phase ωt of the system voltage, and the output of the current command value adder; a PI amplifier that amplifies the output of the subtractor and outputs a voltage command on a rotating coordinate system that is synchronized with the voltage phase ωt; The voltage command obtained by adding the reference voltage to the output of the PI amplifier is subjected to dq inverse transformation to obtain the inverter voltage command value vu on the fixed coordinate system. ＊ , vv * , vw * and a dq inverse transformer that outputs The neutral point potential balance controller includes: The negative-phase fifth harmonic d-axis current command value I ｄ-５ ＊ a d-axis side sign detector that detects the value of and outputs a sign corresponding to the detected value; The q-axis current command value I ｑ-５ ＊ a q-axis side sign detector that detects the value of a d-axis side multiplier that multiplies the difference between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter by the sign output from the d-axis side sign detector to obtain a DC zero-phase voltage α; 3. The neutral point potential control device for a three-level inverter according to claim 2, further comprising: a q-axis side multiplier that multiplies sin6ωt, which is obtained by multiplying the voltage phase ωt of the system voltage by six to obtain a sine wave of a corresponding phase, by the sign output from the q-axis side sign detector and the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter, to obtain a zero-phase voltage γ of a sixth harmonic.

4. The current control unit converts the d-axis current command value and the q-axis current command value of the 1±6n-th harmonic (n is an integer) into a value on a rotating coordinate system synchronized with the voltage phase ωt of the system voltage, which is obtained by dq transformation, and a positive-phase d-axis current command value I ｄ１ ＊ and the positive phase q-axis current command value I ｑ１ ＊ a current command value adder that adds a subtractor for calculating a deviation between a value on a rotating coordinate system synchronized with ωt, the value being obtained by performing dq transformation on an output current detection signal of the inverter using a voltage phase ωt of the system voltage, and the output of the current command value adder; a PI amplifier that amplifies the output of the subtractor and outputs a voltage command on a rotating coordinate system that is synchronized with the voltage phase ωt; The voltage command obtained by adding the reference voltage to the output of the PI amplifier is subjected to dq inverse transformation to obtain the inverter voltage command value vu on the fixed coordinate system. ＊ , vv * , vw * and a dq inverse transformer that outputs The neutral point potential balance controller includes: a d-axis side sign detector that multiplies the d-axis current command values ​​of the 1±6n-th harmonic by respective coefficients, detects the sum of the multiplication outputs, and outputs a sign corresponding to the detected value; a q-axis side sign detector that multiplies the q-axis current command values ​​of the 1±6n-th harmonic by respective coefficients, detects the sum of the multiplication outputs, and outputs a sign corresponding to the detected value; a d-axis side multiplier that multiplies the difference between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter by the sign output from the d-axis side sign detector to obtain a DC zero-phase voltage α; 2. The neutral point potential control device for a three-level inverter according to claim 1, further comprising: a q-axis side multiplier that multiplies a voltage phase ωt of a system voltage by the order of the harmonic, and multiplies a sine wave of a corresponding phase by the voltage, the sign output from the q-axis side sign detector, and the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter, thereby determining the zero-phase voltage of the 1±6n-th harmonic.

5. the d-axis current command value and the q-axis current command value of harmonics added by the current command value adder of the current control unit include at least one of a negative-phase fifth harmonic, a positive-phase seventh harmonic, a negative-phase eleventh harmonic, and a positive-phase thirteenth harmonic; 5. The neutral point potential control device for a three-level inverter according to claim 4, wherein the d-axis side multiplier of the neutral point potential balance controller multiplies, instead of the DC zero-phase sequence voltage α, a deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC section of the inverter, the sign output from the d-axis side sign detector, and a voltage phase ωt of the system voltage multiplied by the order of the harmonic and a cosine wave of a phase corresponding to the multiplied voltage, thereby obtaining a harmonic zero-phase sequence voltage that is 90° out of phase with the zero-phase sequence voltage obtained by the q-axis side multiplier.

6. The current command value adder of the current control unit calculates the negative-phase fundamental wave d-axis current command value I ｄ-１ ＊ and the negative-phase fundamental wave q-axis current command value I ｑ-１ ＊ Adding more, The neutral point potential balance controller includes: The negative-phase fundamental wave d-axis current command value I ｄ-１ ＊ and a negative-phase fundamental wave d-axis side sign detector that detects the value of The negative-phase fundamental wave q-axis current command value I ｑ-１ ＊ and a negative-phase fundamental wave q-axis side sign detector that detects the value of a negative-phase-sequence fundamental wave d-axis side multiplier that calculates a zero-phase-sequence voltage ε of a second harmonic by multiplying the deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC part of the inverter, the sign output from the negative-phase-sequence fundamental wave d-axis side sign detector, and cos2ωt, which is obtained by doubling the voltage phase ωt of the system voltage and calculating a cosine wave of a corresponding phase; a negative-phase-sequence fundamental wave q-axis side multiplier that multiplies a deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC section of the inverter by the sign output from the negative-phase-sequence fundamental wave q-axis side sign detector, and sin2ωt obtained by doubling the voltage phase ωt of the system voltage and determining a sine wave of a corresponding phase, to determine a zero-phase-sequence voltage ζ of a second harmonic that is 90° out of phase with the zero-phase-sequence voltage ε, 4. The neutral point potential control device for a three-level inverter according to claim 3, wherein the d-axis side multiplier of the neutral point potential balance controller multiplies, instead of the DC zero-phase sequence voltage α, a deviation between the voltage of the upper capacitor and the voltage of the lower capacitor of the DC section of the inverter, the detection code output from the d-axis side code detector, and cos6ωt, which is obtained by multiplying the voltage phase ωt of the system voltage by six and determining a cosine wave of a corresponding phase, to determine a zero-phase sequence voltage δ of a sixth harmonic which is 90° out of phase with the zero-phase sequence voltage γ.

7. The neutral point potential control device according to claim 4; The neutral point potential control device according to claim 5 ; a switching unit that switches to either the neutral point potential control device according to claim 4 or the neutral point potential control device according to claim 5 when a set switching condition is met.

8. A method for controlling a neutral point potential of a three-level inverter that outputs harmonic currents by superimposing a zero-phase sequence voltage on an output voltage of the inverter, comprising: a current control step in which the current control unit generates a voltage command for the inverter based on a deviation between a command value of at least one harmonic current of negative phase fifth order, positive phase seventh order, negative phase eleventh order, and positive phase thirteenth order and a detected current obtained by detecting an output current of the inverter; a neutral point potential balance control step in which a neutral point potential balance controller determines a DC zero-phase sequence voltage or a sixth-order harmonic zero-phase sequence voltage based on a deviation between a voltage of an upper capacitor and a voltage of a lower capacitor which divide a DC voltage of a DC section of the inverter and a command value of the harmonic current, and superimposes the determined DC zero-phase sequence voltage or the sixth-order harmonic zero-phase sequence voltage on a voltage command of the inverter generated by the current control unit, A method for controlling a neutral point potential of a three-level inverter, comprising PWM-controlling a switching element of the inverter by a gate signal generated based on the voltage superimposed in the neutral point potential balance control step.

Images