MEMORY ARRAY WITH BONDED SHARED LOGIC CIRCUITRY - Patent application

Abstract

To decrease the complexity, power consumption and / or cost of logic circuitry, and avoid adverse effects of thermal cycles of memory array processing on the logic circuitry.SOLUTION: A memory structure 100 includes logic circuitry bonded to a memory array. The logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers and sense amplifiers for the memory array. Instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. The logic circuitry is between the two memory arrays. Due to the bonding process, a bonding interface layer is formed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] [Background technology] Flash memory, such as NAND flash memory, is a non-volatile storage medium. Typically, a flash memory array is coupled to logic circuitry that facilitates operation of the memory array. The logic circuitry includes components such as word line drivers, bit line drivers, and sense amplifiers for the memory array. Logic circuitry includes, for example, complementary metal-oxide semiconductor (CMOS) logic. Often, thermal cycling of the memory array fabrication process adversely affects the logic circuitry. As will be appreciated in light of this disclosure and as will be described below, there are significant challenges associated with reducing logic circuit complexity, power consumption, and / or cost (e.g., cost per bit of memory) as well as avoiding adverse effects of thermal cycling of memory array processing on the logic circuitry. [Brief explanation of the drawings]

[0002] [Figure 1] 1 illustrates a cross-sectional view of an integrated memory structure including a first memory array, a second memory array, and a logic circuit, according to some embodiments, where a first bonding interface layer is between the first memory array and the logic circuit, and a second bonding interface layer is between the second memory array and the logic circuit.

[0003] [Figure 2A] 1 illustrates an exemplary process for bonding a memory array and a logic circuit using a fusion bonding process to form a bonding interface layer between the memory array and the logic circuit, according to some embodiments. [Figure 2B] 1 illustrates an exemplary process for bonding a memory array and a logic circuit using a fusion bonding process to form a bonding interface layer between the memory array and the logic circuit, according to some embodiments. [Figure 2C]1 illustrates an exemplary process for bonding a memory array and a logic circuit using a fusion bonding process to form a bonding interface layer between the memory array and the logic circuit, according to some embodiments.

[0004] [Figure 3A] 1 illustrates an exemplary process for bonding a memory array and a logic circuit using a hybrid bonding process to form a bonding interface layer between the memory array and the logic circuit, according to some embodiments. [Figure 3B] 1 illustrates an exemplary process for bonding a memory array and a logic circuit using a hybrid bonding process to form a bonding interface layer between the memory array and the logic circuit, according to some embodiments.

[0005] [Figure 3C] 1 illustrates an exemplary process for bonding a memory array and logic circuitry to form a bonding interface layer using a hybrid bonding process, where the hybrid bonding includes via-to-line bonding, according to some embodiments.

[0006] [Figure 4] 1 illustrates a cross-sectional view of an integrated memory structure comprising a first memory array, a second memory array, and logic circuitry between the first memory array and the second memory array, wherein the logic circuitry is separated from the first memory array and the second memory array through a first bonding interface layer and a second bonding interface layer, respectively, according to some embodiments.

[0007] [Figure 5A]A method is illustrated for forming a memory structure according to some embodiments, comprising a first memory array, a second memory array, and logic circuitry interposed between the first memory array and the second memory array, wherein a first bonding interface layer is between the first memory array and the logic circuitry and a second bonding interface layer is between the second memory array and the logic circuitry. [Figure 5B] A method is illustrated for forming a memory structure according to some embodiments, comprising a first memory array, a second memory array, and logic circuitry interposed between the first memory array and the second memory array, wherein a first bonding interface layer is between the first memory array and the logic circuitry and a second bonding interface layer is between the second memory array and the logic circuitry. [Figure 5C] A method is illustrated for forming a memory structure according to some embodiments, comprising a first memory array, a second memory array, and logic circuitry interposed between the first memory array and the second memory array, wherein a first bonding interface layer is between the first memory array and the logic circuitry and a second bonding interface layer is between the second memory array and the logic circuitry. [Figure 5D] A method is illustrated for forming a memory structure according to some embodiments, comprising a first memory array, a second memory array, and logic circuitry interposed between the first memory array and the second memory array, wherein a first bonding interface layer is between the first memory array and the logic circuitry and a second bonding interface layer is between the second memory array and the logic circuitry. [Figure 5E] A method is illustrated for forming a memory structure according to some embodiments, comprising a first memory array, a second memory array, and logic circuitry interposed between the first memory array and the second memory array, wherein a first bonding interface layer is between the first memory array and the logic circuitry and a second bonding interface layer is between the second memory array and the logic circuitry. [Figure 5F]A method is illustrated for forming a memory structure according to some embodiments, comprising a first memory array, a second memory array, and logic circuitry interposed between the first memory array and the second memory array, wherein a first bonding interface layer is between the first memory array and the logic circuitry and a second bonding interface layer is between the second memory array and the logic circuitry.

[0008] [Figure 6] 1 illustrates a cross-sectional view of a memory structure comprising a memory array and logic circuitry, with a bonding interface layer interposed between the memory array and the logic circuitry, according to some embodiments.

[0009] [Figure 7A] 1 illustrates a method of forming a memory structure comprising a memory array and logic circuitry, with a bonding interface layer between the memory array and the logic circuitry, according to some embodiments. [Figure 7B] 1 illustrates a method of forming a memory structure comprising a memory array and logic circuitry, with a bonding interface layer between the memory array and the logic circuitry, according to some embodiments. [Figure 7C] 1 illustrates a method of forming a memory structure comprising a memory array and logic circuitry, with a bonding interface layer between the memory array and the logic circuitry, according to some embodiments.

[0010] [Figure 8] 1 illustrates a cross-sectional view of a memory structure comprising a first memory array, a second memory array, and logic circuitry, according to some embodiments, where a bonding interface layer is interposed between the second memory array and the logic circuitry, and no such bonding interface layer is present between the first memory array and the logic circuitry.

[0011] [Figure 9A]According to some embodiments, a method of forming a memory structure comprising a first memory array, a second memory array, and a logic circuit is illustrated, wherein a bonding interface layer is interposed between the second memory array and the logic circuit, and no such bonding interface layer is present between the first memory array and the logic circuit. [Figure 9B] According to some embodiments, a method of forming a memory structure comprising a first memory array, a second memory array, and a logic circuit is illustrated, wherein a bonding interface layer is interposed between the second memory array and the logic circuit, and no such bonding interface layer is present between the first memory array and the logic circuit. [Figure 9C] According to some embodiments, a method of forming a memory structure comprising a first memory array, a second memory array, and a logic circuit is illustrated, wherein a bonding interface layer is interposed between the second memory array and the logic circuit, and no such bonding interface layer is present between the first memory array and the logic circuit. [Figure 9D] According to some embodiments, a method of forming a memory structure comprising a first memory array, a second memory array, and a logic circuit is illustrated, wherein a bonding interface layer is interposed between the second memory array and the logic circuit, and no such bonding interface layer is present between the first memory array and the logic circuit.

[0012] [Figure 10] 1 illustrates an exemplary computing system implemented with one or more unified memory structures of the present disclosure, in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] Disclosed herein is an integrated memory structure. The integrated memory structure includes multiple memory arrays, such as flash memory arrays, that share a common logic circuit. In some embodiments, a shared logic circuit is interposed between a first memory array and a second memory array. In one example, the first memory array and the second memory array are processed and formed separately from the logic circuit. After forming the memory arrays and the logic circuit, the logic circuit is bonded to the first memory array and the second memory array. Thus, in one example, the integrated memory structure includes a first die including the first memory array, a second die including the second memory array, and a third die including the logic circuit, the third die being between the first die and the second die and bonded to each of the first die and the second die.

[0014] In one example, a first layer is deposited on a surface of a logic circuit to be bonded to a memory array, and a second layer is deposited on a surface of the memory array to be bonded to the logic circuit. Each of the first and second layers comprises, for example, an oxide material (such as silicon dioxide), a nitride material (such as silicon nitride), an oxynitride material (such as silicon oxynitride), and / or the like. The first and second layers are cleaned and polished, pre-bonded to each other, and annealed at an elevated temperature to bond the first and second layers and form a bonding interface layer. Thus, the logic circuit and the memory array in the integrated memory structure are separated by the bonding interface layer. As described above, the bonding interface layer comprises silicon dioxide, silicon nitride, silicon oxynitride, or other suitable electrically insulating bonding material. The thickness of the bonding interface layer can vary, but in some embodiments, the thickness ranges from 3000 Angstroms (300 nanometers) to 10 microns (10 micrometers). Thus, in an integrated memory structure including logic circuitry between and bonded to two memory arrays, a first bonding interface layer will be between the logic circuitry and the first memory array, and a second bonding interface layer will be between the logic circuitry and the second memory array.

[0015] In some examples, bonds between the logic circuit and the memory array may be formed using fusion bonding or hybrid bonding. As described in more detail below, in fusion bonding, the bonding process occurs between a first layer and a second layer (and not between conductive materials such as metals). For example, in fusion bonding (also referred to as direct bonding), conductive structures (e.g., vias containing metal) do not extend through the first and second layers when the first and second layers are bonded together to form a bonding interface layer. After bonding is complete, via holes extending through the bonding interface layer are formed and filled with metal to form interconnect structures between the logic circuit and the memory array that penetrate the bonding interface layer. Because vias are formed through the bonding interface layer after the first and second layers are bonded, as described in more detail below, sections of the interconnect structures that extend through the bonding interface layer do not have misalignment or offset (no unlanded portions).

[0016] In contrast to fusion bonding, as will be described in more detail below, in hybrid bonding, the bonding process is performed between a first layer and a second layer, and also between a conductive structure in the first layer and a conductive structure in the second layer. For example, in hybrid bonding, before the first layer and the second layer are bonded to form a bonding interface layer, a conductive structure (e.g., a via including a metal) extends through each of the first layer and the second layer. For example, a first interconnect structure extends through the first layer and is exposed from and coplanar with the surface of the first layer, and a second interconnect structure extends through the second layer and is exposed from and coplanar with the surface of the second layer (e.g., before the bonding process). During the bonding process, the surfaces of the first layer and the second layer are bonded together with the bonding or contact of the first interconnect structure and the second interconnect structure to form a bonding interface layer. In one example, due to unintended implementation considerations of the bonding process, the memory array and logic circuitry may not be perfectly aligned during the bonding process, and therefore the first interconnect structure and the second interconnect structure may not be perfectly aligned during bonding. Thus, some sections of the coupled interconnect structure that extend through the bonding interface layer formed through bonding or contacting of the first interconnect structure and the second interconnect structure may have some misalignment or offset, as will be described in more detail below.

[0017] Bonding logic circuits to two memory arrays or sharing logic circuits between two memory arrays has several advantages. For example, sharing logic circuits between memory arrays reduces the complexity and / or power consumption of the logic circuits. For example, a single shared voltage divider block in the logic circuit can be used for both memory arrays. Sharing logic circuits between memory arrays also reduces the logic circuit cost per bit of memory. Therefore, the cost of the logic circuit is amortized between the two memory arrays, resulting in cost savings. In addition, using a bonding process between the logic circuit and the memory array allows the logic circuit process to be separated from the memory array process, so that the logic circuit is not affected by the thermal cycle of the memory array formation process. In addition, forming the memory array and logic circuit independently and separately reduces the overall cycle time for manufacturing the integrated memory structure.

[0018] According to some embodiments, instead of bonding the logic circuitry to each of the two memory arrays, in another exemplary embodiment, the logic circuitry may be bonded to a single memory array. For example, the memory array and the logic circuitry may be formed separately and then bonded together (e.g., using fusion bonding or hybrid bonding). Thus, as a result of the formation of the logic circuitry being separate from the formation of the memory arrays, the logic circuitry is not affected by the thermal cycles of the memory array formation process.

[0019] In an exemplary embodiment, instead of bonding the logic circuitry to each of the two memory arrays, the logic circuitry is formed to be integrated with the first memory array (e.g., instead of bonding separately formed logic circuitry to the first memory array, a combined structure is formed that includes both the logic circuitry and the first memory array). After the combined first memory array and logic circuitry is formed, the combined structure is bonded to the second memory array. In the final memory structure, the logic circuitry is interposed between the first memory array and the second memory array. A bonding interface layer exists between the logic circuitry and the second memory array (in other words, the combined first memory array and logic circuitry is bonded to the second memory array). However, such a bonding interface layer does not exist between the logic circuitry and the first memory array. This alternative fabrication process still allows logic circuitry to be shared between the first memory array and the second memory array, thereby reducing logic circuit complexity, power consumption, and / or cost per bit, as described herein above.

[0020] Terms referring to directions such as up, down, vertical, horizontal, left, right, front, back, etc. in the description herein are used for convenience to describe embodiments of integrated circuits having a base or substrate that extends in a horizontal plane. Embodiments of the present disclosure are not limited by these directional references, and it is intended that integrated circuits and device structures according to the present disclosure may be used in any orientation.

[0021] As used herein, "compositionally different" or "compositionally distinct" materials refer to two materials that have different chemical compositions. This compositional difference may be due, for example, to elements present in one material but not the other (e.g., SiGe is compositionally distinct from silicon), or it may be due to one material having all the same elements as a second material, but at least one of those elements being intentionally provided in a different concentration in one material compared to the other (e.g., SiGe with 70 atomic percent germanium is compositionally distinct from SiGe with 25 atomic percent germanium). In addition to such variations in chemical composition, the materials may also have distinct dopants (e.g., gallium and magnesium) or may have different concentrations of the same dopant. In yet other embodiments, compositionally distinct materials may also refer to two materials with different crystal orientations. For example, (110) silicon is compositionally distinct or distinct from (100) silicon. For example, blanket wafer layer transfer can be used to form stacks with different orientations.

[0022] It should be noted that the phrase "X comprises at least one of A or B," as used herein, refers to X that may include, for example, only A, only B, or both A and B. For this purpose, X that includes at least one of A or B should not be understood as X requiring each of A and B, unless expressly stated otherwise. For example, the phrase "X comprises A and B" refers to X that explicitly includes both A and B. Furthermore, this also applies to any number of items greater than two, where "at least one" of those items is included in X. For example, the phrase "X comprises at least one of A, B, or C," as used herein, refers to X that may include only A, only B, only C, only A and B (but not C), only A and C (but not B), only B and C (but not A), or each of A, B, and C. This is true even if any of A, B, or C happens to include multiple types or variations. For this purpose, X that includes at least one of A, B, or C should not be understood as X requiring each of A, B, and C, unless expressly stated otherwise. For example, the phrase "X includes A, B, and C" refers to X that explicitly includes each of A, B, and C. Similarly, the phrase "X that is included in at least one of A or B" refers to X that may be included in A only, B only, or both A and B, for example. As will be understood, the above discussion regarding "X includes at least one of A or B" applies equally here.

[0023] Elements referred to herein by a common reference number followed by a particular number or letter may be referred to generically by the reference number alone. For example, memory arrays 104a, 104b in FIG. 1 and described later herein may be referred to generically and generally as memory arrays 104 in the plural and memory array 104 in the singular. [architecture]

[0024] 1 illustrates a cross-sectional view of an integrated memory structure 100 (also referred to as structure 100) comprising a first memory array (also referred to as “array”) 104a, a second memory array 104b, and logic circuitry 108, according to some embodiments. A first bonding interface layer 110a exists between the first array 104a and the logic circuitry 108, and a second bonding interface layer 110b exists between the second array 104b and the logic circuitry 108.

[0025] In one example, each of the arrays 104a, 104b comprises any suitable three-dimensional (3D) memory array, such as a floating gate flash memory array, a charge trap (e.g., exchange gate) flash memory array, a phase change memory array, a resistive memory array, an ovonic memory array, a ferroelectric random access memory (FeTRAM) array, a nanowire memory array, or any other 3D memory array. In one example, each of the memory arrays 104a, 104b is a stacked NAND flash memory array, which stacks multiple floating gate flash memory cells or charge trap flash memory cells in a vertical stack wired in a NAND (not AND) manner. In another example, the 3D memory arrays 104a, 104b include NOR (not OR) storage cells.

[0026] Array 104a includes word lines (WL) 114a, and array 104b includes WL 114b. Although three WLs are shown in each of arrays 104, the arrays may have any suitable number of WLs.

[0027] Three exemplary logic components 118 of logic circuit 108 are symbolically illustrated in FIG. 1 . Examples of logic components 118 include, but are not limited to, address decoders, state machines, buffers, word line drivers, bit line drivers, sense amplifiers, voltage dividers, charge pumps, digital logic blocks, logic gates, switches, inverters, adders, multipliers, etc. In one example, one or more of logic components 118 include complementary metal-oxide semiconductor (CMOS) logic. In one example, logic circuit 108 may be referred to as “CMOS logic,” “CMOS circuitry,” and / or the like due to the presence of CMOS circuitry within logic circuit 108. In one example, logic circuit 108 includes high-voltage logic components (e.g., components and / or transistors operating at relatively high voltages, such as in the range of 5V to 30V) and / or low-voltage logic components (e.g., components and / or transistors operating at relatively low voltages, such as in the range of 0.9V to 5V).

[0028] 1, structure 100 is shown broadly and symbolically without showing the various internal components within arrays 104a, 104b and logic circuitry 108. Further details of arrays 104a, 104b and logic circuitry 108 are provided below.

[0029] As described in more detail below, array 104a, array 104b, and logic circuit 108 are formed and processed separately. Array 104a and logic circuit 108 are then bonded (e.g., using wafer-to-wafer bonding, die-to-die bonding, wafer-to-die bonding, or die-to-wafer bonding) to form bonding interface layer 110a. Thus, in one example, bonding between array 104a and logic circuit 108 is achieved by bonding wafers containing these components together and then dicing the wafers (e.g., wafer-to-wafer bonding). In another example, bonding between array 104a and logic circuit 108 is achieved by bonding a die containing array 104a to a die containing logic circuit 108 (e.g., die-to-die bonding). In yet another example, bonding of array 104a to logic circuit 108 is achieved by bonding a wafer including array 104a to a die including logic circuit 108 and then dicing the wafer (e.g., wafer-to-die bonding). In yet another example, bonding of array 104a to logic circuit 108 is achieved by bonding a wafer including logic circuit 108 to a die including array 104a and then dicing the wafer (e.g., wafer-to-die bonding). Similarly, bonding of array 104b to logic circuit 108 (e.g., using wafer-to-wafer bonding, die-to-die bonding, wafer-to-die bonding, or die-to-wafer bonding) forms bonding interface layer 110b. Thus, each of bonding interface layers 110a, 110b is a remnant of the bonding process between logic circuit 108 and the corresponding array 104.

[0030] In an exemplary embodiment, bonding between logic circuitry 108 and array 104 occurs relatively late in the process used to form structure 100. For example, as described in more detail below, logic circuitry 108 is processed and formed independently and separately from the processing and formation of array 104. That is, logic circuitry 108 and array 104 are processed and formed prior to bonding between logic circuitry 108 and array 104. Logic circuitry 108 and array 104 are then bonded (e.g., thereby forming bonding interface layer 110).

[0031] In some embodiments, the interconnect structure electrically coupling the logic circuitry 108 and the array 104 is formed after the bonding process (e.g., when fusion bonding is used, as described in more detail below), while in other embodiments, at least a portion of the interconnect structure is formed before the bonding process (e.g., when hybrid bonding is used, as described in more detail below).

[0032] In one example, logic circuitry 108 is shared between arrays 104a, 104b, for example, at least a portion of logic component 118 is shared and used by the two arrays 104a, 104b.

[0033] Bonding the logic circuit 408 to the two arrays 104a, 104b and sharing the logic circuit 108 between the two arrays 104a, 104b has several advantages. For example, as described above, sharing the logic circuit 108 between the arrays 104a, 104b reduces the complexity and / or power consumption of the logic circuit 108. For example, a single shared voltage divider block may be used for the two arrays 104a, 104b. Sharing the logic circuit 108 between the arrays 104a, 104b also reduces the cost of the logic circuit 108 (e.g., the cost per bit of memory in the logic circuit). Thus, the cost of the logic circuit 108 is amortized across the two memory arrays, thereby resulting in cost savings. Additionally, using a bonding process between the logic circuit 108 and the array 104 allows the logic circuit process to be separated from the array process, so that the logic circuit 108 is not subject to the thermal cycles of the memory array fabrication process. Additionally, forming memory array 104 and logic circuitry 108 independently and separately reduces the overall cycle time for manufacturing structure 100 .

[0034] 2A-2C illustrate an exemplary process for bonding a memory array 204 and a logic circuit 208 using a fusion bonding process to form a bonding interface layer 210, according to some embodiments. In one example, the memory array 204 of FIGS. 2A-2C can be any of the memory arrays 104a, 104b of FIG. 1 (or any other memory array described herein), the logic circuit 208 of FIGS. 2A-2C can be the logic circuit 108 of FIG. 1 (or any other logic circuit described herein), and the bonding interface layer 210 of FIGS. 2A-2C can be any of the bonding interface layers 110a, 110b of FIG. 1 (or any other bonding interface layer described herein).

[0035] 1, the array 204 in Figures 2A-2C includes an exemplary WL 214. In Figures 2A-2C, three exemplary logic components 218 of the logic circuit 208 are also shown symbolically.

[0036] 2A , array 204 and logic circuitry 208 are formed separately. In some embodiments, one or both of array 204 and logic circuitry 208 may be at the wafer level during bonding, i.e., may be on corresponding wafers. In some other embodiments, one or both of array 204 and logic circuitry 208 may be at the die level (i.e., singulated and separated into individual dies) during bonding.

[0037] Array 204 has layer 211a on its bottom surface to be bonded to logic circuit 208, and logic circuit 208 has layer 211b on its top surface to be bonded to array 204. That is, layers 211a and 211b are to be bonded. Layers 211a and 211b are described in more detail below. Arrow 203 in Figure 2A symbolically indicates that array 204 and logic circuit 208 are bonded together.

[0038] As shown in FIG. 2A , there are no interconnect structures including conductive material (e.g., metal, etc.) extending through layers 211 a, 211 b. For example, FIG. 2A shows an exemplary interconnect structure 219 extending from logic component 218 to layer 211 b, but interconnect structure 219 does not extend through layer 211 b. Thus, surface 201 b of layer 211 b (e.g., opposite logic circuitry 208) does not have any metal or other conductive material protruding through layer 211 b. Similarly, surface 201 a of layer 211 a (e.g., opposite array 204) does not have any metal or other conductive material protruding through layer 211 a.

[0039] 2B illustrates a bonded structure in which the array 204 and the logic circuit 208 are bonded to form a bonding interface layer 210. The bonding between the array 204 and the logic circuit 208 is performed using fusion bonding (also referred to as direct bonding). In fusion bonding, the smooth surfaces 201a and 201b of the layers 211a and 211b, respectively, are first polished, smoothed, and / or cleaned (e.g., to remove impurities). The layers 211a and 211b are then pre-bonded, for example, at room temperature. The layers 211a and 211b are then annealed, for example, at an elevated temperature, thereby bonding the layers 211a and 211b to form the bonding interface layer 210. Alternatively, any other suitable type of process flow may be employed for the fusion bonding process.

[0040] In one example, layers 211a, 211b, and 210 each include silicon and oxygen. For example, bonding interface layer 210 is silicon dioxide (SiO2). In one example, layers 211a, 211b, and 210 each include silicon and nitrogen. For example, bonding interface layer 210 is silicon nitride (Si3N4). In another example, any other suitable material used in fusion bonding or direct bonding may be used for bonding interface layer 210.

[0041] In one example, the thickness of bonding interface layer 210 is in the range of approximately 3000 Angstroms (300 nanometers) to 10 microns (10 micrometers). The thickness of bonding interface layer 210 may be based on the material used for bonding interface layer 210, the size of surface 201 of layer 211, the cleanliness or level of purity of surface 201 before bonding, the desired degree of electrical isolation between logic circuitry 208 and memory array 204, and / or the desired degree of structural integrity.

[0042] In one example, during the bonding process, layers 211 a, 211 b are bonded to form a single bonding interface layer 210, and the individual layers 211 a, 211 b are not separately discernible in the bonding interface layer 210. In another example, the individual layers 211 a, 211 b are separately discernible in the bonding interface layer 210. For example, there may be a visible seam between layers 211 a, 211 b.

[0043] In one example, in a fusion bonding process, prior to bonding, no metal or other conductive material extends through layer 211a to surface 201a, and no metal or other conductive material extends through layer 211b to surface 201b. That is, the fusion bonding of Figures 2A-2B occurs between layers 211a and 211b, and no bonding or attachment occurs between the two conductive materials (in contrast, a hybrid bonding process, as described in more detail below, involves bonding between conductive materials).

[0044] 2C, multiple interconnect structures are formed through bonding interface layer 210, with a single exemplary interconnect structure 220 shown in FIG. 2C. Interconnect structure 220 is formed using a deep via etch, resulting in a through-hole via through array 204 and bonding interface layer 210, which is filled with a conductive material such as a metal. Interconnect structure 220 may be coupled to interconnect structure 219 of FIG. 2B to form a continuous interconnect structure between array 204 and logic circuit 208, for example.

[0045] FIG. 2C further illustrates an enlarged view of section 205, including sections of bonding interface layer 210 and interconnect structure 220. For example, in the enlarged view, phantom line AA′ passes through bonding interface layer 210, dividing bonding interface layer 210 into layers 211a and 211b. Interconnect structure 220 passes through line AA′. Also shown is side 221 of interconnect structure 220. Because interconnect structure 220 is formed after the bonding process, there is no discontinuity, offset, or misalignment in side 221 of interconnect structure 220 in the section of interconnect structure 220 passing through line AA′. As described later herein, if hybrid bonding, for example, is employed instead of fusion bonding, the side of the interconnect layer may have a discontinuity or misalignment.

[0046] 3A-3B illustrate an exemplary process for bonding a memory array 304 and a logic circuit 308 using a hybrid bonding process to form a bonding interface layer 310, according to some embodiments. In one example, the memory array 304 of FIGS. 3A-3B can be any of the memory arrays 104a, 104b of FIG. 1 (or any other memory array described herein), the logic circuit 308 of FIGS. 3A-3B can be the logic circuit 108 of FIG. 1 (or any other logic circuit described herein), and the bonding interface layer 310 of FIGS. 3A-3B can be any of the bonding interface layers 110a, 110b of FIG. 1 (or any other bonding interface layer described herein).

[0047] 1, in Figures 3A-3B, array 304 includes an exemplary WL 314. Three exemplary logic components 318 of logic circuit 308 are symbolically shown in Figures 3A-3B.

[0048] 3A, array 304 and logic circuitry 308 are formed separately. In some embodiments, one or both of array 304 and logic circuitry 308 may be at the wafer level, i.e., may be part of a corresponding wafer, while in some other embodiments, one or both of array 304 and logic circuitry 308 may be at the die level (i.e., singulated and separated into individual dies).

[0049] Array 304 has layer 311a on its bottom surface to be bonded to logic circuit 308, and logic circuit 308 has layer 311b on its top surface to be bonded to array 304a. That is, layers 311a and 311b are to be bonded. Layers 311a and 311b may be similar to layers 211a and 211b described with reference to Figures 2A to 2C. Arrow 303 in Figure 3A symbolically indicates that array 304 and logic circuit 308 are bonded together.

[0050] In one example, a plurality of interconnect structures comprising a conductive material (e.g., metal, etc.) extend through layers 311a and 311b. For example, FIG. 3A shows exemplary interconnect structure 319a comprising a conductive material (e.g., metal, etc.) extending through layer 311a, and interconnect structure 319b comprising a conductive material (e.g., metal, etc.) extending through layer 311b. Thus, surface 301a of layer 311a (e.g., opposite array 304) has a plurality of metals or other conductive materials exposed from layer 311a (e.g., tips of interconnect structures 319a exposed from surface 301a). As shown, the tips of interconnect structures 319a are flush or coplanar with surface 301a of layer 311a. In one example, layer 311a is polished or cleaned to make the tips of interconnect structures 319a flush or coplanar with surface 301a of layer 311a.

[0051] Similarly, surface 301b of layer 311b (e.g., opposite logic circuitry 208) has a plurality of metals or other conductive materials exposed from layer 311b (such as tips of interconnect structures 319b protruding or exposed from surface 301b).

[0052] FIG. 3B illustrates a bonded structure in which the array 304 and logic circuitry 308 are bonded together to form a bonding interface layer 310. The bonding between the array 304 and logic circuitry 308 is achieved using hybrid bonding. As described above with reference to FIGS. 2A-2C, in fusion bonding, bonding occurs between the two layers 211a, 211b, without bonding between the metal or other conductive material exposed at the bonding surfaces of the two layers. In contrast, in hybrid bonding, the layers 311a, 311b are bonded together with attachment or contact between the corresponding conductive material exposed at the bonding surfaces of the two layers. For example, in the hybrid bonding of FIG. 3B, the layers 311a, 311b are bonded together with attachment, bonding, or contact between the conductive material at the tips of the respective interconnect structures 319a, 319b exposed at the bonding surfaces of the layers 311a, 311b. Thus, in FIG. 3B, interconnect structures 319a, 319b are brought into contact to form bonded interconnect structure 320.

[0053] Similar to fusion bonding, in hybrid bonding, the smooth surfaces 301 a and 301 b of layers 311 a and 311 b, respectively, and the exposed tips of interconnect structures 319 a and 319 b are polished, smoothed, and / or cleaned (e.g., free of impurities). The layers 311 a and 311 b are then pre-bonded, e.g., at room temperature. The layers 311 a and 311 b are subsequently annealed, e.g., at an elevated temperature, resulting in bonding of the layers 311 a and 311 b to form the bonding interface layer 310. Alternatively, any other suitable process flow may be employed for the hybrid bonding process.

[0054] In one example, layers 311a, 311b, and 310 may be similar to those described with reference to Figures 2A-2C. For example, layers 311a, 311b, and 310 each include silicon and oxygen, such as silicon dioxide (SiO2). In one example, layers 311a, 311b, and 310 each include silicon and nitrogen, such as silicon nitride (Si3N4). In another example, any other suitable material commonly used in hybrid bonding may be used for bonding interface layer 310. In one example, the thickness of bonding interface layer 310 is in the range of approximately 3000 angstroms (300 nanometers) to 1 micron (1 micrometer).

[0055] In one example, during the bonding process, the layers 311 a, 311 b are bonded to form a single bonding interface layer 310, and the individual layers 311 a, 311 b are not separately discernible in the bonding interface layer 310. In another example, the individual layers 311 a, 311 b are separately discernible in the bonding interface layer 310.

[0056] FIG. 3B further illustrates an enlarged view of section 305, including sections of bonding interface layer 310 and interconnect structure 320. For example, in the enlarged view, imaginary line AA′ passes through bonding interface layer 310, dividing bonding interface layer 310 into layers 311 a and 311 b. Interconnect structure 320 passes through line AA′. A side 321 of interconnect structure 320 is also shown. Interconnect structure 320 includes interconnect structures 319 a, 319 b. Ideally, when array 304 and logic circuitry 308 are perfectly aligned during the bonding process, interconnect structures 319 a, 319 b would also be perfectly aligned. However, due to unintended implementation considerations of the bonding process, array 304 and logic circuitry 308 may not be perfectly aligned during the bonding process, and therefore interconnect structures 319 a, 319 b may also not be perfectly aligned in interconnect structure 320. For example, as shown in Figure 3B, a close-up of section 305 shows a misalignment or offset between two sections of interconnect structure 320 that runs through bonding interface layer 310. The misalignment or offset may be an unintended consequence of the hybrid bonding process itself. If fusion bonding is employed instead, as described with reference to Figure 2C, such misalignment or offset is not present.

[0057] 3B , the sections of interconnect structure 320 passing through bonding interface layer 310 are misaligned, such that the misaligned sections of interconnect structure 320 are exposed (e.g., a section of the bottom surface of interconnect structure 319a is not bonded to the top surface of interconnect structure 319b). Thus, in one example, bonding interface layer 310 includes a diffusion barrier for the exposed sections of interconnect structure 320. In such an example, bonding interface layer 310 includes, for example, silicon (Si), carbon (C), nitrogen (N), and / or oxygen (O) (e.g., a Si-C-N-O system) in addition to or in place of the exemplary materials for bonding interface layer 310 previously described herein. That is, the bonding interface layer 210 comprises an insulator having a compositional mixture of silicon, carbon, nitrogen, and / or oxygen, which is used to enable good bonding and also to form a diffusion barrier to the misaligned (and therefore exposed) metal (e.g., copper) of the interconnect structure 320.

[0058] In Figures 3A-3B, the metal-metal bonding is via-to-via bonding. However, hybrid bonding may also include via-to-line bonding. Figure 3C illustrates an exemplary process for bonding the memory array 304 and the logic circuit 308 to form the bonding interface layer 310 using a hybrid bonding process, according to some embodiments, where the hybrid bonding involves via-to-line bonding. For example, interconnect structure 319a includes a via that includes a conductive material through layer 311a, and interconnect structure 319b includes a conductive line (e.g., a metal line) through layer 311b, where the conductive material of the via and the line are bonded during the hybrid bonding process.

[0059] 4 illustrates a cross-sectional view of an integrated memory structure (also referred to as structure 400) comprising a first memory array 404a, a second memory array 404b, and logic circuitry 408 between the first and second memory arrays, with the logic circuitry 408 separated from the first and second memory arrays by first and second bonding interface layers 410a and 410b, respectively. In one example, arrays 404a, 404b and logic circuitry 408 in FIG. 4 correspond to arrays 104a, 104b and logic circuitry 108, respectively, in FIG. 1. Similarly, bonding interface layers 410a, 410b correspond to bonding interface layers 110a, 110b, respectively, in FIG. 1.

[0060] In one example, bonding interface layer 410a is formed via fusion bonding of array 404a and logic circuitry 408 (e.g., as described with reference to FIGS. 2A-2C), and bonding interface layer 410b is formed via fusion bonding of array 404b and logic circuitry 408. In one example, bonding interface layers 410a, 410b are similar to bonding interface layer 210 of FIGS. 2A-2C. For example, bonding interface layers 410a, 410b may include an oxide material such as silicon dioxide (SiO), a nitride material such as silicon nitride (SiN), or the like, although any other suitable material used in bonding two wafer-level components may also be used. In one example, the thickness of each of bonding interface layers 410 is in the range of approximately 3000 angstroms (300 nanometers) to 1 micron (1 micrometer).

[0061] Details of the memory arrays 404a, 404b will now be described, however, such details are merely exemplary and any suitable modifications of the internal structure of the arrays 404a, 404b will occur to those skilled in the art.

[0062] Memory array 404b is formed on substrate 479. In one example, substrate 479 is a wafer on which a plurality of such arrays are formed. In one example, the bonding process occurs while array 404b is still on the wafer, i.e., before dicing the wafer. In another example, the bonding process occurs after dicing the wafer.

[0063] In one example, array 404a includes memory cells, such as NAND flash memory cells, formed at memory pillars 456a. Array 404a also includes conductive access lines that provide access to the memory cells, such as bit lines 464a, word lines (WL) 420a, select gate sources (SGS) 452a, and select gate drains (SGD) 460a that extend out of the plane of FIG. 4 (e.g., perpendicular to the plane of the page). Word lines 420a are arranged in a staggered or stepped pattern. Array 404a also includes current source and ground circuits (SRCs, also referred to as source plates) 455a disposed below memory pillars 456a.

[0064] Array 404a further includes WL connection terminals 457a, with each WL connection terminal 457a coupled to a corresponding WL 420a, for example, via interconnect structure 459a. Array 404a also includes SDG connection terminals 461a, with each SGD connection terminal 459a coupled to a corresponding SGD 460a, for example, via interconnect structure 459a. Array 404a includes multiple metallization levels 407a, including metal, that electrically couple the various components within array 404a.

[0065] In the exemplary embodiment, structure 400 is accessed from a top surface 403a of array 404a. For example, array 404a includes a plurality of interconnect structures 407a including one or more metallization levels. Interconnect terminals 402 (only one shown in FIG. 4) for connecting structure 400 to external components are coupled to the surface of array 404a.

[0066] In one example, one or more interconnect structures 411 penetrate array 404a and bonding interface layer 410a, for example, for electrically coupling to logic circuit 408 and / or array 404b. Interconnect structures 411 may be used to transmit signals to and / or from logic circuit 408 and / or array 404b.

[0067] In one example, array 404b has a structure at least partially similar to that of array 404a. For example, array 404b includes memory cells, such as NAND flash memory cells, formed at memory pillars 456b. Array 404b further includes conductive access lines that enable access to the memory cells, such as bit lines 464b, WL 420b, SG 452b, and SGD 460b. Array 404b also includes SRC 455b disposed below memory pillars 456b.

[0068] Array 404b further includes WL connection terminals 457b, each WL connection terminal 457b coupled to a corresponding WL 420b, for example, via interconnect structure 459b. Array 404b further includes SDG connection terminals 461b coupled to a corresponding SGD 460b, for example, via interconnect structure 459b.

[0069] In the exemplary embodiment, various interconnect structures 413 penetrate array 404a and bonding interface layer 410b, and these interconnect structures 413 transmit access line signals to and / or from logic circuit 408 and / or array 404b. For example, interconnect structure 413a transmits SGD signals to and / or from SGD 460b of array 404b (even though only two such interconnect structures 413a are shown in FIG. 4). Similarly, interconnect structure 413b transmits word line signals to and / or from WL 420b of array 404b. Similarly, interconnect structure 413c transmits SGS signals to and / or from SG 452b of array 404b. Interconnect structure 413d transmits SRC signals to and / or from SRC 455b of array 404b. Interconnect structure 413e transmits bit line signals to and / or from bit lines 464b of array 404b. Thus, at least interconnect structures 411, 413 extend through bonding interface layer 410a.

[0070] In an exemplary embodiment, logic circuitry 408 includes various logic circuits generally denoted as logic components 418a, 418b, and 418c. As described with reference to FIG. 1 , exemplary logic components 418 include, but are not limited to, address decoders, state machines, buffers, word line drivers, bit line drivers, sense amplifiers, voltage dividers, charge pumps, digital logic blocks, and the like. In one example, one or more of logic components 418 include CMOS logic. In one example, logic circuitry 408 includes high-voltage logic components (e.g., components and / or transistors operating at relatively high voltages, such as in the range of 5V to 30V) and / or low-voltage logic components (e.g., components and / or transistors operating at relatively low voltages, such as in the range of 0.9V to 5V). For example, logic circuitry 408 includes n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), p-channel MOSFETs, or both.

[0071] Various interconnect structures 415 couple logic circuitry 408 to array 404b. For example, interconnect structures 415 may extend through bonding interface layer 410b to couple logic circuitry 408 and array 404b.

[0072] 4 also shows an expanded view of section 425, which includes a section of bonding interface layer 410a and interconnect structures 413 extending through bonding interface layer 410a. As described with reference to FIGS. 2A-2C, in one example, for example, array 404a and logic circuitry 408 are bonded using fusion bonding so that interconnect structures 413 extending through bonding interface layer 410a do not have discontinuities, offsets, or misalignments.

[0073] 4 also shows an expanded view of section 427, which includes a section of bonding interface layer 410b and interconnect structures 415 extending through bonding interface layer 410b. As described with reference to FIGS. 2A-2C, in one example, for example, array 404b and logic circuitry 408 are bonded using fusion bonding so that interconnect structures 415 extending through bonding interface layer 410b do not have discontinuities, offsets, or misalignments.

[0074] In the exemplary embodiment, as described previously herein, the bonding interface layer 410a separates the array 404a and the logic circuitry 408. For example, the structure 400 has a left side wall 403m and an opposing right side wall 403n ("left" and "right" are for ease of identification only, and are not limiting), and the bonding interface layer 410a extends from the left side wall 403m to the right side wall 403n. Similarly, the structure 400 has a front wall and an opposing rear wall (e.g., these are not visible or labeled in FIG. 4 and are perpendicular to the left and right sides), and the bonding interface layer 410a extends from the front wall to the rear wall. That is, the structure 400 has a top and a bottom surface and multiple walls or surfaces extending between the top and bottom surfaces, and the bonding interface layer 410a generally divides the structure, such that the bonding interface layer 410a extends to each of the multiple walls or surfaces. Similarly, bonding interface layer 410b also generally divides structure 400, such that bonding interface layer 410b extends to each of multiple walls or surfaces. In one example, a first die includes array 404a, a second die includes logic circuitry 408, and a third die includes array 404b, where the three dies are bonded together using bonding interface layers 410a, 410b as described herein.

[0075] 5A, 5B, 5C, 5D, 5E, and 5F together illustrate a method of forming a memory structure (such as memory structure 400 of FIG. 4) according to some embodiments, the memory structure comprising a first memory array (e.g., memory array 404a), a second memory array (e.g., memory array 404b), and logic circuitry (e.g., logic circuitry 408) interposed between the first memory array and the second memory array, with a first bonding interface layer (e.g., bonding interface layer 410a) present between the first memory array and the logic circuitry and a second bonding interface layer (e.g., bonding interface layer 410b) present between the second memory array and the logic circuitry.

[0076] 5A, there is shown memory array 404b formed on substrate 479. In one example, substrate 479 is a wafer and array 404b is formed thereon. Array 404 also includes layer 501a on the surface to be bonded to logic circuitry 408, which may be similar to layer 211a in FIG. 2A.

[0077] 5A also shows logic circuitry 408 formed on support substrate 502. In one example, substrate 502 is a wafer and logic circuitry 408 is formed on a wafer, for example, if logic circuitry 408 is still on the wafer during bonding with array 404b. In another example, substrate 502 is the substrate of the die including logic circuitry 408, for example, if the die including logic circuitry 408 is to be bonded with array 404b. Logic circuitry 408 also includes layer 501b on the surface to be bonded with array 404b, which layer 501b may be similar to layer 211b in FIG. 2A.

[0078] 5B, logic circuit 408 is bonded to array 404b, for example, as described with reference to FIG. 2B. For example, layers 501a and 501b are bonded to form bonding interface layer 410b. As shown, logic circuit 408 has a height H1. Support substrate 502 is then peeled from logic circuit 408.

[0079] 5C, various conductive structures or interconnect structures 513, 415, etc. are formed within logic circuitry 408. Some of the conductive structures include a conductive material (such as a metal) deposited within vias, such as conductive structure 415, that extend through bonding interface layer 410b. For example, because interconnect structure 415 is formed after the formation of bonding interface layer 410b, there is no offset or misalignment in interconnect structure 415, as shown in the expanded view of section 427.

[0080] Logic circuit 408 includes a surface 515 (e.g., in FIG. 5A , surface 515 was attached to support substrate 502) that faces the surface of logic circuit 408 to which array 404 b is bonded. Some of the interconnect structures have ends that are adjacent to or exposed from surface 515 of logic circuit 408. In an exemplary embodiment, interconnect structures 415, 513 are formed by accessing logic circuit 408 from surface 515. In an exemplary embodiment, various metallization levels, vias, and interconnect structures are formed within logic circuit 408, resulting in an increase in the height of logic circuit 408. For example, in FIGS. 5A-5B , the height of logic circuit 408 is H1, while in FIG. 5C after the formation of the interconnect structures, the height has been increased to H2.

[0081] 5D, layer 501c is formed on surface 515 of logic circuitry 408, where layer 501c is similar to layer 211 of FIG. 2A. Also shown in FIG. 5D is array 404a with layer 501d formed on its surface to be bonded to logic circuitry 408. Array 404a may be supported by support substrate 552, which may be, for example, a wafer (e.g., if the wafer supporting array 404a has not yet been diced).

[0082] Layer 501d is similar to layer 211 of Figure 2A. The height of array 404a is H3, as shown in Figure 5D. Note that for clarity, some of the components of array 404a that are labeled in Figure 4 are not labeled in Figure 5D (or in some of the subsequent figures).

[0083] 5E, logic circuitry 408 is bonded to array 404a, for example, as described with reference to FIG. 2B, and support substrate 552 is peeled from array 404a. For example, layers 501c and 501d are bonded to form bonding interface layer 410a.

[0084] 5F, interconnect structures 411, 413 are formed in array 404a using, for example, deep via etching. For example, deep through-hole vias extending through array 404a and bonding interface layer 410a are formed and filled with a conductive material, such as a metal, to form interconnect structures 411, 413. In one example, such through-hole vias are formed above corresponding interconnect structures 513 in logic circuitry 408 (e.g., where interconnect structure 513 is to be formed in FIG. 5C), such that the conductive material in the vias and interconnect structure 513 combine to form interconnect structure 413.

[0085] Additionally, various metallization levels, various terminals (e.g., WL connection terminal 457a, SDG connection terminal 461a, etc.), etc. are formed near the top surface of array 404a and extend the height of array 404a. For example, array 404a in FIG. 5F has a height H4 that is higher than height H3 of array 404a in FIG. 5E. That is, at least a portion of array 404a is formed after array 404a is bonded to logic circuit 408. The resulting structure 400 in FIG. 5F is similar to structure 400 in FIG. 4.

[0086] 4 and 5A-5E, array 404b and logic circuitry 408 of structure 400 are bonded together using fusion bonding, and logic circuitry 408 and array 404a are also bonded together using fusion bonding. Thus, the interconnect structures extending through bonding interface layer 410 are formed after the corresponding components are bonded. However, in another exemplary embodiment, one or both bonds in structure 400 may be hybrid bonding (e.g., as described with reference to FIGS. 3A-3C). In such an embodiment, the interconnect structures through layers 501a, 501b and / or layers 501c, 501d are pre-formed, and hybrid bonding bonds the corresponding interconnect structures.

[0087] FIG. 6 shows a cross-sectional view of a memory structure 600 (also referred to as structure 600) according to some embodiments, comprising a memory array 604 and logic circuitry 608, with a bonding interface layer 610 interposed between the memory array 604 and the logic circuitry 608.

[0088] In one example, memory array 604 of Figure 6 is at least partially similar to memory array 404a of Figure 4, and therefore, like components in the two memory arrays are referenced with like labels, and individual components in memory array 604 of Figure 6 will not be described in detail. In one example, logic circuit 608 of Figure 6 is at least partially similar to logic circuit 408 of Figure 4, and therefore, like components in the two logic circuits are referenced with like labels, and individual components in logic circuit 608 of Figure 6 will not be described in detail.

[0089] In Figure 4, logic circuitry 408 was interposed between two arrays 404a, 404b. In contrast, logic circuitry 608 in Figure 6 is bonded to a single array 604. In one example, bonding between logic circuitry 608 and array 604 is performed using fusion bonding to form bonding interface 610 (e.g., similar to bonding interface 410 in Figure 4). Logic circuitry 408 is formed on a substrate 679.

[0090] 7A, 7B, and 7C together illustrate a method of forming a memory structure (such as memory structure 600 of FIG. 6) comprising a memory array (e.g., memory array 604) and a logic circuit (e.g., logic circuit 608 of FIG. 6), according to some embodiments, wherein a bonding interface layer (e.g., bonding interface layer 610) is present between the memory array and the logic circuit.

[0091] Referring to Figure 7A, logic circuitry 608 is shown on substrate 679. Layer 501b, similar to layer 211 of Figure 2A, is deposited on logic circuitry 608. Also shown is array 604, which may be similar to array 404a of Figure 5D. In Figure 7A, logic circuitry 408 and array 604 have not yet been bonded together.

[0092] 7B, array 604 is bonded to logic circuitry 608 using fusion bonding as described with reference to FIG. 5E. Thus, bonding interface layer 610 is formed by bonding layers 501a, 501b.

[0093] 7C, interconnect structures 411, 413 are formed in array 604 using, for example, deep via etching as described with reference to FIG. 5E. Additionally, various metallization levels, various terminals (e.g., WL connection terminal 457a, SDG connection terminal 461a, etc.), etc. are formed near the top surface of array 604, e.g., they extend the height of array 604. For example, as described with reference to FIG. 5E, array 604 in FIG. 7C has a height H4 that is higher than height H3 of array 604 in FIG. 7B. The resulting structure of FIG. 7C is structure 600 of FIG. 6.

[0094] FIG. 8 illustrates a cross-sectional view of a memory structure 800 (also referred to as structure 800) according to some embodiments, comprising a first memory array 804a, a second memory array 804b, and logic circuitry 808, with a bonding interface layer 810 interposed between the second memory array 804b and the logic circuitry 808, and no such bonding interface layer being present between the first memory array 804a and the logic circuitry 808.

[0095] In one example, memory arrays 804a, 804b of Figure 8 are at least partially similar to memory arrays 404a, 404b of Figure 4, respectively, and accordingly, like components in the memory arrays in the two figures are referenced with like labels, and individual components in memory arrays 804a, 804b of Figure 8 will not be described in detail. In one example, logic circuitry 808 of Figure 8 is at least partially similar to logic circuitry 408 of Figure 4, and accordingly, like components in the two logic circuits are referenced with like labels, and individual components in logic circuitry 808 of Figure 8 will not be described in detail.

[0096] 8 is at least partially formed along with the formation of memory array 804a. That is, logic circuitry 808 is not bonded to memory array 804a; rather, logic circuitry 808 is formed in situ with memory array 804a, as will be described in more detail herein. Thus, array 804a and logic circuitry 808 reside within a single die, while array 804b resides on a different die.

[0097] In the exemplary embodiment, the combination of memory array 804a and logic circuitry 808 is bonded to memory array 804b via bonding interface layer 810. Bonding interface layer 810 is at least partially similar to bonding interface layer 410 of FIG.

[0098] As described in more detail herein, layer 815 resides between bonding interface layer 810 and logic circuitry 808. In one example, bonding interface layer 810 extends substantially from sidewall 403 n to sidewall 403 m, and layer 815 also extends substantially from sidewall 403 n to sidewall 403 m. For example, layer 815 substantially covers a bottom surface (e.g., greater than 90%, or greater than 95%, or greater than 99%) of logic circuitry 808, and bonding interface layer 810 substantially covers a bottom surface of layer 815. In one example, layer 815 comprises silicon, e.g., crystalline silicon. In one example, layer 815 is a remnant of a wafer or substrate on which the combination of array 804 a and logic circuitry 808 is formed, as described in more detail below.

[0099] 9A, 9B, 9C, and 9D together illustrate, according to some embodiments, a method of forming a memory structure (such as memory structure 800 of FIG. 8) comprising a first memory array (e.g., array 804a), a second memory array (e.g., array 804b), and a logic circuit (e.g., logic circuit 808), wherein a bonding interface layer (e.g., bonding interface layer 810) is interposed between the second memory array and the logic circuit, and no such bonding interface layer is present between the first memory array and the logic circuit.

[0100] Referring to FIG. 9A, there is shown a combination of an array 804a and logic circuitry 808 formed on a wafer 915, such as a silicon wafer.

[0101] 9B, a temporary carrier wafer 919 is attached to the top surface of the combination array 804a and logic circuit 808 (e.g., the opposing bottom surface of the combination array 804a and logic circuit 808 has wafer 915 attached thereto). Subsequently, wafer 915 is polished, or thinned, to reduce the height of wafer 915 and form layer 815. For example, in FIG. 9A, the original height of wafer 915 is Hw1, and wafer 915 is thinned so that the height of layer 815 in FIG. 9B is Hw2, where Hw2 is less than Hw1. In one example, height Hw2 of layer 815 is in the range of 7 microns (7 micrometers) to 10 microns (10 micrometers).

[0102] Referring now to Figure 9C, layer 901a is deposited on the bottom surface of layer 815. Also shown in Figure 9C is array 804b with layer 901b deposited on the top surface of array 804b. Layers 901a and 901b are similar to layer 501 in Figure 5A.

[0103] After deposition of layer 901a (and before the bonding process), vias are formed through layer 901a, 815 and filled with a conductive material, such as metal, to form interconnect structures 915a through layers 901a, 815. The union of array 804a and logic circuitry 808 is accessed from the bottom (e.g., from the exposed surface of layer 901a) when forming the vias of interconnect structures 915a.

[0104] Similarly, after deposition of layer 901b, vias are formed through layer 901b and filled with a conductive material, such as a metal, to form interconnect structures 915b through layer 901b. Array 804b is accessed from the top (e.g., from the exposed surface of layer 901a) when forming the vias for interconnect structures 915b.

[0105] Thus, each of layers 901a and 901b has openings (e.g., similar to those described with reference to FIGS. 3A-3B) through which the tips of corresponding interconnect structures 915a, 915b are exposed. For example, the conductive material at the tips of interconnect structures 915a exposed from layer 901a is flush with, or coplanar to, the bottom surface of layer 901a. For example, the bottom surface of layer 901a is polished until the tips of interconnect structures 915a exposed from layer 901a are flush with, or coplanar to, the bottom surface of layer 901a. Similarly, the conductive material at the tips of interconnect structures 915b exposed from layer 901a is flush with, or coplanar to, the bottom surface of layer 901a.

[0106] Referring now to FIG. 9D , layers 901 a and 901 b are bonded together to form bonding interface layer 810. During the bonding process, two corresponding interconnect structures 915 a, 915 b are also bonded together, or brought into contact, to form common interconnect structure 415. Thus, bonding is not only between layers 901 a, 901 b but also between corresponding interconnect structures 915 a, 915 b; thus, the bonding in FIG. 9D is a hybrid bond, as described with reference to FIGS. 3A-3B . Also, as described with reference to FIGS. 3A-3B , there is a misalignment or offset between the two sections of interconnect structure 415 in FIG. 9D , as shown in the enlarged view of section 427. While FIG. 9D shows multiple via-to-via bonds passing through layer 810 (e.g., as described with reference to FIGS. 3A-3B ), there may also be via-to-line bonds passing through layer 810 (e.g., as described with reference to FIG. 3C ). The resulting structure in FIG. 9D is structure 800 in FIG.

[0107] 10 illustrates an exemplary computing system implementing the unified memory structure disclosed herein, in accordance with one or more embodiments of the present disclosure. As can be seen, computing system 2000 houses a motherboard 2002. Motherboard 2002 may include multiple components, including, but not limited to, a processor 2004 and at least one communications chip 2006, each of which may be physically and electrically coupled to or integrated into motherboard 2002. As will be appreciated, motherboard 2002 may be any printed circuit board, such as a main board, a daughter board mounted on a main board, or the only board in system 2000.

[0108] Depending on its application, computing system 2000 may include one or more other components that may or may not be physically and electrically coupled to motherboard 2002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM, flash memory such as 3D NAND flash memory), graphics processors, digital signal processors, cryptoprocessors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.). In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that communications chip 2006 may be part of or integrated into processor 2004).

[0109] Any memory, such as any flash memory (e.g., 3D NAND flash memory), included in computing system 2000 may include one or more memory arrays bonded to logic circuitry as described herein. In one example, logic circuitry may be interposed between and shared between two memory arrays as described herein.

[0110] Communications chip 2006 enables wireless communication for the transfer of data to and from computing system 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may communicate data using modulated electromagnetic waves through a non-solid medium. The term does not imply that the associated devices are wire-free, although in some embodiments the devices may be wire-free. The communications chip 2006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G, and beyond. The computing system 2000 may include multiple communications chips 2006. For example, the first communications chip 2006 may be dedicated to shorter-range wireless communications such as Wi-Fi (registered trademark) and Bluetooth (registered trademark), and the second communications chip 2006 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX (registered trademark), LTE, Ev-DO, and others.

[0111] The processor 2004 of the computing system 2000 includes an integrated circuit die packaged within the processor 2004. The term "processor" may refer to any device or part of a device that processes electronic data, for example from registers and / or memory, and transforms the electronic data into other electronic data that can be stored in the registers and / or memory.

[0112] The communications chip 2006 may also include an integrated circuit die packaged within the communications chip 2006. As will be understood in light of this disclosure, it should be noted that multi-standard wireless functionality may be integrated directly into the processor 2004 (e.g., in which case, rather than having a separate communications chip, functionality of any chip 2006 is integrated into the processor 2004). It should also be noted that the processor 2004 may be a chipset that has such wireless functionality. In short, any number of processors 2004 and / or communications chips 2006 may be used. Similarly, any one chip or chipset may have multiple functions integrated therein.

[0113] In various implementations, computing system 2000 may be a laptop, netbook, notebook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device that processes data or uses one or more integrated circuit structures or devices, as variously described herein. Further Exemplary Embodiments

[0114] Many variations and configurations will be apparent in light of this disclosure and the following examples.

[0115] Example 1 a memory array including a plurality of memory cells; A logic circuit; a layer comprising silicon and having a thickness of at least 3000 angstroms (300 nanometers), said layer being between said memory array and said logic circuitry.

[0116] Example 2 the memory array having a first sidewall and an opposing second sidewall; 2. The integrated circuit memory of Example 1, wherein the layer extends from the first sidewall to the second sidewall.

[0117] Example 3 3. The integrated circuit memory of any of Examples 1 to 2, wherein the layer further comprises at least one of oxygen or nitrogen.

[0118] Example 4 4. The integrated circuit memory of any of Examples 1 to 3, wherein the logic circuitry includes one or more of an address decoder, a buffer, a word line driver, a bit line driver, a sense amplifier, a voltage divider, a charge pump, and / or a digital logic block.

[0119] Example 5 The logic circuit is a first transistor or transistors operating at a first voltage in the range of 5 volts (V) to 30 V; and a second transistor or transistors operating at a second voltage in the range of 0.9V to 5V.

[0120] Example 6 6. The integrated circuit memory of any of Examples 1 to 5, wherein the logic circuitry comprises complementary metal oxide semiconductor (CMOS) logic.

[0121] Example 7 7. The integrated circuit memory of any one of Examples 1 to 6, wherein the memory array is included in a first die to be bonded to a second die including the logic circuitry.

[0122] Example 8 8. The integrated circuit memory of Example 7, wherein the layer is a bonding interface layer between the first die and the second die.

[0123] Example 9 The memory array is a first memory array, the layer is a first layer, and the integrated circuit memory is a second memory array, the logic circuitry being between the first memory array and the second memory array; 9. The integrated circuit memory of any of Examples 1 to 8, further comprising: a second layer comprising silicon and having a thickness of at least 3000 angstroms (300 nanometers), the second layer being between the second memory array and the logic circuitry.

[0124] Example 10 the first memory array is included in a first die to be bonded to a second die including the logic circuit; the second memory array is included in a third die to be bonded to the second die; the first layer is a first bonding interface layer between the first die and the second die; the second layer is a second bonding interface layer between the third die and the second die; Example 10. The integrated circuit memory of Example 9, wherein one or more logic components of the logic circuit are shared between the first memory array and the second memory array.

[0125] Example 11 the memory array is a first memory array, and the integrated circuit memory further comprises a second memory array; the first memory array and the logic circuit are included in a first die; the second memory array is included in a second die to be bonded to the first die; the layer is a bonding interface layer between the first die and the second die; 11. The integrated circuit memory of any of Examples 1 to 10, wherein the logic circuit is between the first memory array and the second memory array, and one or more logic components of the logic circuit are shared between the first memory array and the second memory array.

[0126] Example 12 The layer is a first layer, and the integrated circuit memory comprises: 9. The integrated circuit memory of any of Examples 1 to 8, further comprising a second layer in direct contact with the first layer, the second layer comprising silicon, the second layer being compositionally different from the first layer.

[0127] Example 13 further comprising an interconnect structure extending through the first layer and the second layer; the interconnect structure has a first portion extending through the second layer and a first section of the first layer, and a second portion extending through a second section of the first layer; Example 13. The integrated circuit memory of Example 12, wherein the first portion of the interconnect structure is offset relative to the second portion of the interconnect structure.

[0128] Example 14 14. The integrated circuit memory of any of Examples 12-13, wherein the length and width of the first layer are substantially similar to the length and width, respectively, of the second layer.

[0129] Example 15 14. The integrated circuit memory of any of Examples 12-13, wherein the memory array has a first sidewall and an opposing second sidewall, and each of the first layer and the second layer extends from the first sidewall to the second sidewall.

[0130] Example 16 14. The integrated circuit memory of any of Examples 12-13, wherein the second layer has a thickness in the range of seven microns (seven micrometers) to ten microns (ten micrometers).

[0131] Example 17 17. The integrated circuit memory of any of Examples 1 to 16, wherein the memory array is a flash memory array.

[0132] Example 18 18. The integrated circuit memory of any of Examples 1 to 17, wherein the memory array is a three-dimensional (3D) NAND flash memory array.

[0133] Example 19 A motherboard having the integrated circuit memory of any of Examples 1 to 18 mounted thereon.

[0134] Example 20 A computing system comprising the integrated circuit memory of any of Examples 1 to 19.

[0135] Example 21 a first die including a first memory array; a second die including a second memory array; a third die including a logic circuit including a plurality of logic components, the third die being between the first die and the second die; a first bonding interface bonding the first die to the third die; a second bonding interface bonding the second die to the third die.

[0136] Example 22 22. The integrated circuit memory of Example 21, wherein at least one of the first bonding interface and the second bonding interface comprises silicon and oxygen and has a thickness of at least 3000 angstroms (300 nanometers).

[0137] Example 23 23. The integrated circuit memory of any of Examples 21-22, wherein at least one of the first bonding interface and the second bonding interface comprises silicon and nitrogen and has a thickness of at least 3000 angstroms (300 nanometers).

[0138] Example 24 the first die has a first surface facing a second surface of the third die; 24. The integrated circuit memory of any one of Examples 21 to 23, wherein the first bonding interface is on substantially the entire first surface of the first die.

[0139] Example 25 25. The integrated circuit memory of any of Examples 21 to 24, wherein the first bonding interface is on substantially the entire second surface of the third die.

[0140] Example 26 26. The integrated circuit memory of any of Examples 21 to 25, wherein the plurality of logic components include one or more of an address decoder, a buffer, a word line driver, a bit line driver, a sense amplifier, a voltage divider, a charge pump, and / or a digital logic block.

[0141] Example 27 Multiple logic components on a first transistor or transistors operating at a first voltage in the range of 5 volts (V) to 30 V; and a second one or more transistors operating at a second voltage in the range of 0.9V to 5V.

[0142] Example 28 28. The integrated circuit memory of any of Examples 21 to 27, wherein the first memory array and the second memory array are three-dimensional (3D) flash memory arrays and the logic components include complementary metal-oxide semiconductor (CMOS) logic components.

[0143] Example 29 29. The integrated circuit memory of any of Examples 21 to 28, wherein the first memory array and the second memory array are three-dimensional (3D) NAND flash memory arrays.

[0144] Example 30 30. A motherboard having the integrated circuit memory of any one of examples 21 to 29 attached thereto.

[0145] Example 31 A computing system comprising the integrated circuit memory of any of Examples 21 to 30.

[0146] Example 32 1. An integrated circuit memory comprising: a first die including a first memory array and a logic circuit; a second die including a second memory array; and a bonding interface bonding the first die to the second die, wherein the logic circuit resides between the first memory array and the second memory array, and one or more logic components of the logic circuit are shared between the first memory array and the second memory array.

[0147] Example 33 33. The integrated circuit memory of Example 32, wherein the first memory array and the second memory array are three-dimensional (3D) NAND flash memory arrays.

[0148] Example 34 A motherboard having the integrated circuit memory of example 32 or 33 installed thereon.

[0149] Example 35 A computing system comprising the integrated circuit memory of any of Examples 32 to 34.

[0150] Example 36 1. A method for forming an integrated flash memory structure, comprising: forming a memory array having a first layer on a surface of the memory array; forming a logic circuit having a second layer on a surface of the logic circuit; bonding the memory array and the logic circuitry using the first layer and the second layer.

[0151] Example 37 forming a via through a bonding interface formed between the memory array and the logic circuit after bonding the memory array and the logic circuit; 37. The method of Example 36, further comprising depositing a metal material in the via.

[0152] Example 38 forming a first conductive structure extending through the first layer and a second conductive structure extending through the second layer prior to bonding the memory array and the logic circuit; Example 37. The method of Example 36, wherein after bonding the memory array and the logic circuitry, the first conductive structure and the second conductive structure are bonded to form an integrated conductive structure.

[0153] Example 39 39. The method of example 38, wherein within the integrated conductive structure, the first conductive structure is offset relative to the second conductive structure.

[0154] Example 40 Example 39. The method of Example 39, wherein the first conductive structure is one of a first via comprising a conductive material or a first conductive line, and the second conductive structure is one of a second via comprising a conductive material or a second conductive line.

[0155] Example 41 41. The method of any one of Examples 38 to 40, wherein, prior to bonding the memory array and the logic circuit, the first conductive structure is exposed from a first surface of the first layer to be bonded to the second layer, with an end of the first conductive structure being flush with the first surface; and prior to bonding the memory array and the logic circuit, the second conductive structure is exposed from a second surface of the second layer to be bonded to the first layer, with an end of the second conductive structure being flush with the second surface.

[0156] Example 42 42. The method of any of Examples 36 to 41, wherein the memory array is a first memory array, and the method further comprises forming a second memory array having a third layer on a surface of the second memory array, forming a fourth layer on another surface of the logic circuit, and bonding the second memory array to the logic circuit using the third layer and the fourth layer.

[0157] Example 43 43. The method of Example 42, wherein the logic circuitry resides between the first memory array and the second memory array.

[0158] Example 44 Example 37. The method of Example 36, wherein the memory array is a first memory array, bonding the first memory array and the logic circuit comprises bonding the first layer and the second layer to form a bonding interface layer, forming the logic circuit comprises forming the logic circuit in conjunction with forming a second memory array such that there is no bonding interface layer between the logic circuit and the second memory array, and bonding the first memory array and the logic circuit comprises bonding the first memory array to a combination of the logic circuit and the second memory array.

[0159] The above detailed description has been provided for illustrative purposes. It is not intended to be exhaustive or to limit the disclosure to the precise form described. Many modifications and variations are possible in light of this disclosure. Accordingly, it is intended that the scope of this application be limited not by this detailed description, but by the claims that follow. Future applications filed claiming priority to this application may claim the disclosed subject matter differently and may generally include any set of one or more of the limitations variously disclosed or set forth herein. Other possible claims Item 1 a memory array including a plurality of memory cells; A logic circuit; a layer comprising silicon and having a thickness of at least 3000 angstroms (300 nanometers), said layer being between said memory array and said logic circuitry. Item 2 the memory array having a first sidewall and an opposing second sidewall; Item 2. The integrated circuit memory of item 1, wherein the layer extends from the first sidewall to the second sidewall. Item 3 Item 1 , wherein the layer further comprises at least one of oxygen or nitrogen. Item 4 2. The integrated circuit memory of claim 1, wherein the logic circuitry includes one or more of an address decoder, a buffer, a word line driver, a bit line driver, a sense amplifier, a voltage divider, a charge pump, and / or a digital logic block. Item 5 The logic circuit is a first transistor or transistors operating at a first voltage in the range of 5 volts (V) to 30 V; and a second transistor or transistors operating at a second voltage in the range of 0.9V to 5V. Item 6 Item 1. The integrated circuit memory of item 1, wherein the logic circuitry comprises complementary metal oxide semiconductor (CMOS) logic. Item 7 the memory array is included in a first die to be bonded to a second die including the logic circuitry; 2. The integrated circuit memory of claim 1, wherein the layer is a bonding interface layer between the first die and the second die. Item 8 The memory array is a first memory array, the layer is a first layer, and the integrated circuit memory is a second memory array, the logic circuitry being between the first memory array and the second memory array; 10. The integrated circuit memory of claim 1, further comprising: a second layer comprising silicon and having a thickness of at least 3000 angstroms (300 nanometers), the second layer being between the second memory array and the logic circuitry. Item 9 the first memory array is included in a first die to be bonded to a second die including the logic circuit; the second memory array is included in a third die to be coupled to the second die; the first layer is a first bonding interface layer between the first die and the second die; the second layer is a second bonding interface layer between the third die and the second die; 9. The integrated circuit memory of claim 8, wherein one or more logic components of the logic circuit are shared between the first memory array and the second memory array. Item 10 the memory array is a first memory array, and the integrated circuit memory further comprises a second memory array; the first memory array and the logic circuit are included in a first die; the second memory array is included in a second die to be bonded to the first die; the layer is a bonding interface layer between the first die and the second die; 2. The integrated circuit memory of claim 1, wherein the logic circuit is between the first memory array and the second memory array, and one or more logic components of the logic circuit are shared between the first memory array and the second memory array. Item 11 The layer is a first layer, and the integrated circuit memory comprises: Item 14. The integrated circuit memory of item 1, further comprising a second layer in direct contact with the first layer, the second layer comprising silicon, the second layer being compositionally different from the first layer. Item 12 further comprising an interconnect structure extending through the first layer and the second layer; the interconnect structure has a first portion extending through the second layer and a first section of the first layer, and a second portion extending through a second section of the first layer; Item 12. The integrated circuit memory of item 11, wherein the first portion of the interconnect structure is offset relative to the second portion of the interconnect structure. Item 13 Item 1, wherein the memory array is a three-dimensional (3D) NAND flash memory array. Item 14 Item 1. A motherboard having the integrated circuit memory of item 1 installed thereon. Item 15 a first die including a first memory array; a second die including a second memory array; a third die including a logic circuit including a plurality of logic components, the third die being between the first die and the second die; a first bonding interface bonding the first die to the third die; a second bonding interface bonding the second die to the third die. Item 16 Item 16. The integrated circuit memory of item 15, wherein at least one of the first bonding interface and the second bonding interface comprises silicon and oxygen and has a thickness of at least 3000 angstroms (300 nanometers). Item 17 the first die has a first surface facing a second surface of the third die; Item 16. The integrated circuit memory of item 15, wherein the first bonding interface is on substantially the entire first surface of the first die. Item 18 1. A method for forming an integrated flash memory structure, comprising: forming a memory array having a first layer on a surface of the memory array; forming a logic circuit having a second layer on a surface of the logic circuit; bonding the memory array and the logic circuitry using the first layer and the second layer. Item 19 forming a via through a bonding interface formed between the memory array and the logic circuit after bonding the memory array and the logic circuit; Item 19. The method of item 18, further comprising depositing a metal material in the via. Item 20 Item 19. The method of item 18, further comprising forming a first conductive structure extending through the first layer and a second conductive structure extending through the second layer before bonding the memory array and the logic circuit, and after bonding the memory array and the logic circuit, the first conductive structure and the second conductive structure are bonded to form an integrated conductive structure.

Claims

1. a memory array including a plurality of memory cells; A logic circuit; a layer that is an insulator comprising silicon, said layer being between said memory array and said logic circuitry, the layer is a first layer, The integrated circuit memory comprises: a second layer in direct contact with the first layer, the second layer comprising silicon, the second layer being compositionally different from the first layer; a thickness of the first layer, a bonding interface layer, between the memory array and the logic circuit, of 3000 angstroms (300 nanometers) to 10 microns (10 micrometers); the integrated circuit memory further comprising an interconnect structure extending through the first layer and the second layer; the interconnect structure has a first portion extending through the second layer and a first section of the first layer, and a second portion extending through a second section of the first layer; The integrated circuit memory, wherein the first portion of the interconnect structure is offset relative to the second portion of the interconnect structure.

2. 10. The integrated circuit memory of claim 1, wherein said memory array is a first memory array and said integrated circuit memory further comprises a second memory array.

3. the memory array having a first sidewall and an opposing second sidewall; 3. The integrated circuit memory of claim 1, wherein said layer extends from said first sidewall to said second sidewall.

4. 3. The integrated circuit memory of claim 1, wherein the layer further comprises at least one of oxygen or nitrogen.

5. 3. The integrated circuit memory of claim 1, wherein the logic circuitry includes one or more of an address decoder, a buffer, a word line driver, a bit line driver, a sense amplifier, a voltage divider, a charge pump, and / or a digital logic block.

6. The logic circuit a first transistor or transistors operating at a first voltage in the range of 5 volts (V) to 30 V; and a second transistor or transistors operating at a second voltage in the range of 0.9V to 5V.

7. 3. The integrated circuit memory of claim 1, wherein the logic circuitry comprises complementary metal oxide semiconductor (CMOS) logic.

8. the first memory array is included in a first die to be bonded to a second die including the logic circuit; 3. The integrated circuit memory of claim 2, wherein the layer resides between the first die and the second die.

9. The integrated circuit memory of claim 1 , wherein the memory array is a three-dimensional (3D) NAND flash memory array.

10. A motherboard having an integrated circuit memory according to any one of claims 1 to 8 mounted on a printed circuit board.

11. 1. A method for manufacturing an integrated circuit memory, comprising: forming a memory array having a first layer on a surface of the memory array, the first layer being an insulator comprising silicon; forming a logic circuit on a surface thereof, the logic circuit having a second layer of an insulator comprising silicon, the second layer being compositionally different from the first layer, and a third layer comprising silicon, the third layer being compositionally different from the first layer and the second layer; bonding the memory array and the logic circuit using the first layer and the second layer; a bonding interface layer including the first layer and the second layer between the bonded memory array and the logic circuit has a thickness of at least 3000 angstroms (300 nanometers) and at most 10 microns (10 micrometers); forming a first portion extending through the first layer and a second portion extending through the second layer and the third layer before bonding the memory array and the logic circuit together; after bonding the memory array and the logic circuitry, the first portion and the second portion are bonded together to form an interconnect structure extending through the first layer, the second layer, and the third layer; The method of claim 1, wherein the first portion of the interconnect structure is offset relative to the second portion of the interconnect structure.

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