Semiconductor device and manufacturing method thereof

Abstract

To efficiently form a structure in which a recess is provided on a first electrode layer and a surface of the first electrode layer is covered by a second electrode layer.SOLUTION: A semiconductor device comprises: a semiconductor substrate including an element region and an outer peripheral region; a plurality of interlayer insulation layers arranged at intervals on a surface of the semiconductor substrate in the outer peripheral region; a first electrode layer made of an Al alloy and covering the surface of the semiconductor substrate and the plurality of interlayer insulation layers within a range straddling the element region and the outer peripheral region; and a second electrode layer made of a metal containing Ni and covering s surface of the first electrode layer within the range straddling the element region and the outer peripheral region. The surface of the first electrode layer in the outer peripheral region is provided with a recess in which an upper portion of the intervals is dented for an upper portion of the interlayer insulation layer. The second electrode layer is in contact with the first electrode layer in the recess.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

[0002] Patent Document 1 discloses a technique for forming a Ni metal layer on the surface of an Al-Si metal layer after forming recesses in the surface of the Al-Si metal layer. This technique provides an anchor effect with the Ni metal layer filled in the recesses, thereby preventing the Ni metal layer from peeling off from the Al-Si metal layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-219828 Summary of the Invention [Problem to be solved by the invention]

[0004] In the technology of Patent Document 1, Si particles are formed on the outermost surface of an Al-Si metal layer by baking the Al-Si metal layer. Then, the Si particles are removed by etching to form micropores on the surface of the Al-Si metal layer. Then, zincate treatment is performed to enlarge the micropores, forming recesses. Thus, the technology of Patent Document 1 requires multiple steps to form recesses on the surface of the Al-Si metal layer. This specification proposes a semiconductor device structure and a manufacturing method thereof that can efficiently form a structure in which recesses are provided on the surface of a first electrode layer made of an Al alloy, and the surface of the first electrode layer is covered with a second electrode layer made of a metal containing Ni. [Means for solving the problem]

[0005] The semiconductor device disclosed in this specification includes a semiconductor substrate having an element region where switching elements are provided and a peripheral region arranged around the element region, multiple interlayer insulating layers arranged at intervals on the surface of the semiconductor substrate in the peripheral region, a first electrode layer made of an Al alloy and covering the surface of the semiconductor substrate and the multiple interlayer insulating layers in an area spanning the element region and the peripheral region, and a second electrode layer made of a metal containing Ni and covering the surface of the first electrode layer in an area spanning the element region and the peripheral region.The surface of the first electrode layer in the peripheral region is provided with a recess, with an upper portion of the gap recessed relative to an upper portion of the interlayer insulating layer.The second electrode layer is in contact with the first electrode layer within the recess.

[0006] The plurality of interlayer insulating layers arranged at intervals may be divided into a plurality of parts at specific positions, and may be connected to each other at other positions.

[0007] In this semiconductor device, multiple interlayer insulating layers are provided at intervals on the surface of the semiconductor substrate within a peripheral region surrounding the element region. Therefore, a concave shape is formed by the interlayer insulating layers and the intervals. The first electrode layer covers the multiple interlayer insulating layers, and therefore a recess is formed on the surface of the first electrode layer following the concave shape formed by the interlayer insulating layers and the intervals. That is, the surface of the first electrode layer has a recess, where the upper portion of the interval is recessed relative to the upper portion of the interlayer insulating layer. The second electrode layer covers the first electrode layer and contacts the first electrode layer within the recess. Therefore, an anchor effect suppresses peeling of the second electrode layer from the first electrode layer. Furthermore, in the manufacturing process of this semiconductor device, multiple interlayer insulating layers are formed at intervals, and the first electrode layer is formed to cover the multiple interlayer insulating layers, thereby forming a recess on the surface of the first electrode layer. Therefore, the anchor effect can be obtained by forming the second electrode layer to cover the recess. In this way, the recess structure of the first electrode layer of this semiconductor device can be formed with almost no increase in the number of steps compared to a typical manufacturing process. Therefore, this semiconductor device can be manufactured efficiently.

[0008] This specification also proposes a method for manufacturing a semiconductor device. The method includes the steps of: forming a plurality of interlayer insulating layers at intervals on a surface within a peripheral region of a semiconductor substrate having an element region in which switching elements are provided and a peripheral region surrounding the element region; forming a first electrode layer composed of an Al alloy in an area spanning the element region and the peripheral region, the first electrode layer covering the surface of the semiconductor substrate and the plurality of interlayer insulating layers; and forming a second electrode layer composed of a metal containing Ni in an area spanning the element region and the peripheral region, the second electrode layer covering the surface of the first electrode layer. In the step of forming the first electrode layer, a recess is formed in the surface of the first electrode layer within the peripheral region, following the recess formed by the interlayer insulating layer and the gap, such that an upper portion of the gap is recessed relative to an upper portion of the interlayer insulating layer. In the step of forming the second electrode layer, the second electrode layer is formed so that the second electrode layer contacts the first electrode layer within the recess.

[0009] According to this manufacturing method, it is possible to efficiently manufacture a semiconductor device in which the second electrode layer is unlikely to peel off from the first electrode layer. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view of the semiconductor device taken along line II-II in FIG. [Figure 3] 3A to 3C are explanatory diagrams of a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] 3A to 3C are explanatory diagrams of a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] 3A to 3C are explanatory diagrams of a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 3A to 3C are explanatory diagrams of a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 3A to 3C are explanatory diagrams of a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 3A to 3C are explanatory diagrams of a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] FIG. 10 is a plan view of a semiconductor device according to a first modified example. [Figure 10] FIG. 10 is a plan view of a semiconductor device according to a second modification. [Figure 11] FIG. 11 is a plan view of a semiconductor device according to a third modified example. [Figure 12] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth modification. DETAILED DESCRIPTION OF THE INVENTION

[0011] The semiconductor device described above may further include a protective insulating layer covering the surface of the first electrode layer in the peripheral region. The protective insulating layer may have an opening distributed over a range spanning the element region and the peripheral region. The recess may be disposed within the opening and extend along the edge of the opening. The second electrode layer may be disposed within the opening.

[0012] This configuration can prevent peeling in the vicinity of the end portion of the second electrode layer, where peeling is likely to occur.

[0013] The semiconductor device described above may include a plurality of trenches provided on the surface of the semiconductor substrate within the element region. When viewed along the thickness direction of the semiconductor substrate, the plurality of trenches may extend parallel to one another along a specific direction. A gate electrode may be disposed within each of the trenches. The recess may have a linear portion extending in a direction intersecting the specific direction when viewed along the thickness direction of the semiconductor substrate.

[0014] A recess is formed in the surface of the first electrode layer above the trench, and the anchor effect of this recess can sometimes suppress peeling of the second electrode layer from the first electrode layer. With the above configuration, the recess at the top of the trench and the recess at the top of the gap extend in a direction that intersects with each other, so peeling of the second electrode layer from the first electrode layer can be more effectively suppressed.

[0015] The above-described manufacturing method may further include a step of forming a protective insulating layer covering the surface of the first electrode layer in the peripheral region before the step of forming the second electrode layer. The protective insulating layer may have an opening distributed over a range spanning the element region and the peripheral region. In the step of forming the protective insulating layer, the protective insulating layer may be formed so that the recess is disposed within the opening and extends along the edge of the opening. In the step of forming the second electrode layer, the second electrode layer may be formed within the opening.

[0016] This configuration can prevent peeling in the vicinity of the end portion of the second electrode layer, where peeling is likely to occur.

[0017] In the above-described manufacturing method, a plurality of trenches may be provided in the surface of the semiconductor substrate within the element region. When viewed along the thickness direction of the semiconductor substrate, the plurality of trenches may extend parallel to one another along a specific direction. A gate electrode may be disposed in each of the trenches. In the step of forming the plurality of interlayer insulating layers, the plurality of interlayer insulating layers may be formed so that the spacing has linear portions extending in a direction intersecting the specific direction when viewed along the thickness direction of the semiconductor substrate.

[0018] According to this configuration, the recessed portion at the top of the trench and the recessed portion at the top of the gap are formed to extend and intersect with each other, so that peeling of the second electrode layer from the first electrode layer can be more effectively suppressed.

[0019] The semiconductor device 10 of the embodiment shown in FIGS. 1 and 2 has a semiconductor substrate 12 made of SiC (i.e., silicon carbide). The semiconductor substrate 12 may be made of other semiconductor materials (e.g., Si, GaN, etc.). As shown in FIG. 1, two source electrodes 20 and four electrode pads 28 are provided on the top surface of the semiconductor device 10. The areas of the top surface of the semiconductor device 10 outside the source electrodes 20 and the electrode pads 28 are covered with a protective insulating layer 30. The semiconductor substrate 12 incorporates a MOSFET (metal-oxide-semiconductor field effect transistor). The source electrode 20 is an electrode that functions as the source of the MOSFET. The electrode pads 28 are, for example, electrode pads that control the gate voltage of the MOSFET or electrode pads that detect the temperature of the MOSFET.

[0020] As shown in FIG. 2, a plurality of trenches 40 are provided on the upper surface 12a of the semiconductor substrate 12. As shown in FIGS. 1 and 2, the plurality of trenches 40 are provided on the upper surface 12a below the source electrode 20. When the semiconductor substrate 12 is viewed in the thickness direction as shown in FIG. 1, the trenches 40 extend parallel to one another. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, and a direction parallel to the upper surface 12a and perpendicular to the x-direction is referred to as the y-direction. Each trench 40 extends linearly along the x-direction on the upper surface 12a. As shown in FIG. 2, a gate insulating film 42 and a gate electrode 44 are disposed in each trench 40. The inner surface of each trench 40 is covered with the gate insulating film 42. Each gate electrode 44 is insulated from the semiconductor substrate 12 by the gate insulating film 42. The semiconductor substrate 12 has an n-type source layer 50, a p-type body layer 52, an n-type drift layer 54, and an n-type drain layer 56. The source layer 50 is in contact with the source electrode 20 and the gate insulating film 42. The body layer 52 is disposed around the source layer 50. The body layer 52 is in contact with the source electrode 20 at a position adjacent to the source layer 50. The body layer 52 is in contact with the gate insulating film 42 below the source layer 50. The drift layer 54 is disposed below the body layer 52. The drift layer 54 is in contact with the gate insulating film 42 below the body layer 52. The drift layer 54 is separated from the source layer 50 by the body layer 52. The drain layer 56 is an n-layer having a higher n-type impurity concentration than the drift layer 54. The drain layer 56 is disposed below the drift layer 54. A drain electrode 38 is disposed on the lower surface 12b of the semiconductor substrate 12. The drift layer 54 is in contact with the drain electrode 38. The gate electrode 44, the gate insulating film 42, the source layer 50, the body layer 52, the drift layer 54, and the drain layer 56 constitute the above-mentioned MOSFET. In this manner, the MOSFET is provided below the source electrode 20. Hereinafter, the region of the semiconductor substrate 12 where the MOSFET is provided will be referred to as an element region 14. Furthermore, the region of the semiconductor substrate 12 surrounding the element region 14 will be referred to as an outer periphery region 16. As shown in FIG. 1 , the element region 14 is disposed below the center of the source electrode 20.

[0021] 2, the upper surface of the gate electrode 44 is covered with a cap insulating film 43. The cap insulating film 43 is disposed in the trench 40. The gate electrode 44 is insulated from the source electrode 20 by the cap insulating film 43. The upper surface of the cap insulating film 43 is located below the upper surface 12a of the semiconductor substrate 12. Therefore, the upper surface of the cap insulating film 43 and the upper surface 12a of the semiconductor substrate 12 form a recessed shape 43a.

[0022] As shown in FIG. 2, a plurality of interlayer insulating layers 32 are disposed on the upper surface 12a of the semiconductor substrate 12 in the peripheral region 16. The interlayer insulating layers 32 are made of silicon oxide. The interlayer insulating layers 32 are disposed at intervals. That is, the plurality of interlayer insulating layers 32 are provided on the upper surface 12a so that the interlayer insulating layers 32 and the intervals 33 alternate. In FIG. 1, the intervals 33 are indicated by hatching. When viewed along the thickness direction of the semiconductor substrate 12 as shown in FIG. 1, each interval 33 extends around the periphery of the element region 14. The upper surface 12a of the semiconductor substrate 12 within the intervals 33 is located below the upper surfaces of the interlayer insulating layers 32. Therefore, a recessed shape 33a is formed by the upper surface 12a of the semiconductor substrate 12 and the upper surfaces of the interlayer insulating layers 32 within the intervals 33. The recessed depth of the recessed shape 33a is greater than the recessed depth of the recessed shape 43a.

[0023] The source electrode 20 has a first electrode layer 21 and a second electrode layer 22. The first electrode layer 21 is made of an AlSi alloy. However, the first electrode layer 21 may be made of other Al alloys (e.g., AlCu alloy, AlSiCu alloy, AlMg alloy, AlSiMg alloy, etc.). The second electrode layer 22 is made of simple Ni. However, the second electrode layer 22 may be made of other metals containing Ni (e.g., Ni alloy).

[0024] The first electrode layer 21 is distributed across the element region 14 and the periphery region 16. The first electrode layer 21 contacts the upper surface 12a of the semiconductor substrate 12 and the upper surface of the cap insulating film 43 within the element region 14. As described above, the upper surface of the cap insulating film 43 and the upper surface 12a of the semiconductor substrate 12 form a recessed shape 43a. A recess 21a extending along the recessed shape 43a is formed on the surface of the first electrode layer 21 within the element region 14. That is, in the recess 21a, the upper portion of the trench 40 is recessed relative to the upper portion of the upper surface 12a of the semiconductor substrate 12. The recess 21a extends in the x-direction, similar to the trench 40 extending in the x-direction in FIG. 1 . The first electrode layer 21 covers the interlayer insulating layer 32 and the upper surface 12a of the semiconductor substrate 12 within the periphery region 16. The first electrode layer 21 contacts the upper surface of the interlayer insulating layer 32 and fills the gap 33. The first electrode layer 21 contacts the upper surface 12a of the semiconductor substrate 12 and the side surface of the interlayer insulating layer 32 within the gap 33. As described above, the upper surface 12a of the semiconductor substrate 12 and the upper surface of the interlayer insulating layer 32 within the gap 33 form a recessed shape 33a. A recess 21b extending along the recessed shape 33a is formed on the surface of the first electrode layer 21 within the peripheral region 16. That is, in the recessed shape 21b, the upper portion of the gap 33 is recessed more than the upper portion of the interlayer insulating layer 32. The recessed shape 21b extends in an annular shape similar to the gap 33 extending in an annular shape in FIG. 1. Because the recessed amount of the recessed shape 33a is greater than the recessed amount of the recessed shape 43a, the recessed amount of the recessed shape 21b is greater than the recessed amount of the recessed shape 21a.

[0025] The protective insulating layer 30 is made of polyimide. As shown in FIG. 2, the protective insulating layer 30 covers the top surfaces of the first electrode layer 21 and the interlayer insulating layer 32 on the outer periphery side of the recess 21b. In other words, the protective insulating layer 30 has an opening 30a, and the source electrode 20 is disposed within the opening 30a. As shown in FIG. 1, the opening 30a is rectangular, with two sides extending along the x direction and the remaining two sides extending along the y direction. When the semiconductor substrate 12 is viewed along the thickness direction as shown in FIG. 1, the trench 40 and the gap 33 are disposed within the opening 30a. Therefore, the recesses 21a and 21b provided on the surface of the first electrode layer 21 are disposed within the opening 30a. The gap 33 extends annularly along the edge of the opening 30a. Therefore, the recess 21b disposed above the gap 33 also extends annularly along the edge of the opening 30a. Therefore, the recess 21b has a portion 21bx extending along the x direction and a portion 21by extending along the y direction. The portion 21by is a linear portion that extends in a direction intersecting the x direction in which each trench 40 extends (that is, the x direction in which each recess 21a extends).

[0026] The second electrode layer 22 is disposed in the opening 30a of the protective insulating layer 30. The second electrode layer 22 covers the upper surface of the first electrode layer 21 in an area spanning the element region 14 and the peripheral region 16. The second electrode layer 22 is in contact with the upper surface of the first electrode layer 21 and also fills the recesses 21b and 22b. That is, the second electrode layer 22 is in contact with the first electrode layer 21 on the inner surface of the recess 21a and the inner surface of the recess 21b. Because the second electrode layer 22 is filled in the recesses 21a and 21b, the second electrode layer 22 is less likely to peel off from the first electrode layer 21 due to an anchor effect. In particular, the recess 21b has a larger recess amount than the recess 21a, so a stronger anchor effect can be obtained in the recess 21b.

[0027] During use of the semiconductor device 10, the semiconductor substrate 12 repeatedly generates heat. This causes repeated thermal stress to be applied to the interface between the second electrode layer 22 and the first electrode layer 21. Repeated thermal stress applied to the interface may cause the second electrode layer 22 to peel off from the first electrode layer 21. The outer periphery of the second electrode layer 22 is particularly prone to peeling off from the first electrode layer 21. In contrast, in this embodiment, the recess 21b, which provides a strong anchor effect, extends along the edge of the opening 30a (i.e., the outer periphery of the second electrode layer 22). This prevents the outer periphery of the second electrode layer 22 from peeling off from the first electrode layer 21. Furthermore, the upper surface of the first electrode layer 21 is provided with a recess 21a extending along the trench 40. The anchor effect provided by the recess 21a prevents the second electrode layer 22 from peeling off from the first electrode layer 21 within the element region 14. Furthermore, the recess 22a has a portion 21by extending in a direction intersecting the recess 21a. In this way, when the recess 21a and the portion 21by extend in different directions, it is possible to more suitably suppress peeling of the second electrode layer 22 from the first electrode layer 21. For example, there are cases where peeling of the second electrode layer 22 tends to progress along a specific direction. When the recess 21a and the portion 21by extend in different directions, if peeling progresses along a specific direction, it is possible to stop the progress of the peeling in at least one of the recess 21a and the portion 21by.

[0028] Next, a method for manufacturing the semiconductor device 10 will be described. First, as shown in Fig. 3, a MOSFET is formed inside the semiconductor substrate 12. That is, a source layer 50, a body layer 52, a drift layer 54, a drain layer 56, a trench 40, a gate insulating film 42, a gate electrode 44, and a cap insulating film 43 are formed in the semiconductor substrate 12. At this stage, a recessed shape 43a is formed by the upper surface 12a of the semiconductor substrate 12 and the upper surface of the cap insulating film 43.

[0029] Next, as shown in FIG. 4, an interlayer insulating layer 32 is formed over the entire upper region of the semiconductor substrate 12. Next, a resist layer 90 is patterned and formed on the interlayer insulating layer 32. Next, as shown in FIG. 5, the interlayer insulating layer 32 is etched through the resist layer 90. As a result, the interlayer insulating layer 32 in the element region 14 is removed, and a gap 33 is formed in the interlayer insulating layer 32 in the peripheral region 16. In the gap 33, the upper surface 12a of the semiconductor substrate 12 is exposed. When the gap 33 is formed, a recessed shape 33a is formed by the interlayer insulating layer 32 and the upper surface 12a of the semiconductor substrate 12 in the gap 33. After etching the interlayer insulating layer 32, the resist layer 90 is removed.

[0030] Next, as shown in FIG. 6, a first electrode layer 21 is formed over the entire upper surface of the semiconductor substrate 12 by sputtering or the like. At this time, the recessed shapes 33a and 43a are filled with the first electrode layer 21. As a result, a recess 21a is formed on the surface of the first electrode layer 21 in the element region 14, following the recessed shape 43a. Furthermore, a recess 21b is formed on the surface of the first electrode layer 21 in the peripheral region 16, following the recessed shape 33a. Next, a mask layer 92 is formed on the first electrode layer 21 so that the peripheral edge of the upper surface of the first electrode layer 21 is exposed, and the first electrode layer 21 is etched through the mask layer 92. This removes the peripheral edge of the first electrode layer 21, as shown in FIG. 7. After etching the first electrode layer 21, the mask layer 92 is removed.

[0031] 8, a protective insulating layer 30 is formed on the interlayer insulating layer 32 and the first electrode layer 21, and an opening 30a is formed in the protective insulating layer 30. Here, the opening 30a is formed so as to be distributed across the element region 14 and the peripheral region 16. The opening 30a is also formed so that the recesses 21a and 21b are arranged within the opening 30a and the edge of the opening 30a extends along the recess 21b.

[0032] Next, as shown in FIG. 2, the second electrode layer 22 is formed by plating on the upper surface of the first electrode layer 21 in the opening 30a. The second electrode layer 22 fills the recesses 21a and 21b. Therefore, the second electrode layer 22 contacts the first electrode layer 21 in the recesses 21a and 21b. This makes the second electrode layer 22 less likely to peel off from the first electrode layer 21 due to an anchor effect. In addition, a drain electrode 38 is formed on the lower surface 12b of the semiconductor substrate 12. Through the above steps, the semiconductor device 10 is completed.

[0033] As described above, in this manufacturing method, the gap 33 is formed in the interlayer insulating layer 32, and the first electrode layer 21 is formed to cover the gap 33, thereby forming the recess 21b on the surface of the first electrode layer 21. Therefore, by forming the second electrode layer 22 to cover the recess 21b, the second electrode layer 22 can be made less likely to peel off from the first electrode layer 21. Furthermore, the interlayer insulating layer 32 is an insulating layer required in general semiconductor devices, and the gap 33 can be formed simultaneously in the etching process for removing the interlayer insulating layer 32 in the element region 14. Therefore, in this manufacturing method, the recess 21b can be formed without increasing the number of steps from the manufacturing process of a general semiconductor device. Therefore, this manufacturing method can efficiently manufacture a semiconductor device 10 in which the second electrode layer 22 is less likely to peel off from the first electrode layer 21.

[0034] In the above-described embodiment, the intervals 33 (i.e., the recesses 21b) extend to surround the periphery of the element region 14. However, as shown in FIG. 9, the intervals 33 extending along the y direction may be provided at positions adjacent to the element region 14 in the x direction (i.e., positions adjacent to the longitudinal ends of the trenches 40), and the intervals 33 may not be provided at positions adjacent to the element region 14 in the y direction. Also, as shown in FIG. 10, each trench 40 may extend along the y direction. In this case, the intervals 33 extending along the x direction may be provided at positions adjacent to the element region 14 in the y direction, and the intervals 33 may not be provided at positions adjacent to the element region 14 in the x direction. Even in the configurations of FIGS. 9 and 10, the extension direction of the trenches 40 (i.e., the recesses 21a) and the extension direction of the intervals 33 (i.e., the recesses 21b) intersect, so peeling of the second electrode layer 22 can be effectively suppressed. Also, as shown in FIG. 11, the trenches 40 and the intervals 33 may be parallel to each other. This configuration also makes it possible to suppress peeling of the second electrode layer 22 due to the anchor effect.

[0035] Furthermore, in the above-described embodiment, the interlayer insulating layer 32 is not provided on the upper part of the trench 40, but the interlayer insulating layer 32 may be provided on the upper part of the trench 40 as shown in Fig. 12. In this case, a recessed shape is formed in the element region 14 by the upper surface of the interlayer insulating layer 32 and the upper surface 12a of the semiconductor substrate 12 (i.e., exposed portions of the source layer 50 and the body layer 52), and a recess 21c is formed in the surface of the first electrode layer 21 above the recessed shape. In this case, the second electrode layer 22 is filled in the recess 21c, and therefore an anchor effect due to the recess 21c is obtained in the element region 14.

[0036] In the above-described embodiment, a trench gate type MOSFET is formed in the element region 14. However, other switching elements (for example, planar gate type switching elements) may be formed in the element region 14.

[0037] The x direction is an example of the specific direction. The portion 21by of the recess 21b is an example of a linear portion that extends in a direction intersecting the specific direction.

[0038] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0039] 10: semiconductor device, 12: semiconductor substrate, 14: element region, 16: peripheral region, 21: first electrode layer, 21b: recess, 22: second electrode layer, 32: interlayer insulating layer, 33: gap

Claims

1. A semiconductor device, a semiconductor substrate having an element region in which a switching element is provided and a peripheral region disposed around the element region; a plurality of interlayer insulating layers arranged at intervals on the surface of the semiconductor substrate in the peripheral region; a first electrode layer made of an Al alloy and covering the surface of the semiconductor substrate and the plurality of interlayer insulating layers in a range spanning the element region and the peripheral region; a second electrode layer made of a metal containing Ni and covering a surface of the first electrode layer in an area spanning the element region and the peripheral region; and a recess is provided on the surface of the first electrode layer in the outer circumferential region, in which an upper portion of the gap is recessed relative to an upper portion of the interlayer insulating layer; the second electrode layer is in contact with the first electrode layer within the recess; Semiconductor device.

2. a protective insulating layer covering the surface of the first electrode layer within the outer periphery; the protective insulating layer has openings distributed over a range spanning the element region and the peripheral region, the recess is disposed within the opening and extends along an edge of the opening; the second electrode layer is disposed in the opening; The semiconductor device according to claim 1 .

3. a plurality of trenches are provided in the surface of the semiconductor substrate within the element region; When viewed along a thickness direction of the semiconductor substrate, the plurality of trenches extend parallel to each other along a specific direction, a gate electrode is disposed within each of the trenches; the recess has a linear portion extending in a direction intersecting the specific direction when viewed along the thickness direction of the semiconductor substrate.

3. The semiconductor device according to claim 1.

4. A method for manufacturing a semiconductor device, comprising: forming a plurality of interlayer insulating layers at intervals on a surface of a semiconductor substrate in an element region in which a switching element is provided and an outer periphery region arranged around the element region; forming a first electrode layer made of an Al alloy in an area spanning the element region and the peripheral region, the first electrode layer covering the surface of the semiconductor substrate and the plurality of interlayer insulating layers; forming a second electrode layer made of a metal containing Ni in an area spanning the element region and the peripheral region, the second electrode layer covering a surface of the first electrode layer; and In the step of forming the first electrode layer, a recess is formed on the surface of the first electrode layer in the outer circumferential region, in such a way that an upper portion of the interval is recessed relative to an upper portion of the interlayer insulating layer, following a recessed shape formed by the interlayer insulating layer and the interval; In the step of forming the second electrode layer, the second electrode layer is formed so as to be in contact with the first electrode layer within the recess. Manufacturing method.

5. The method further includes a step of forming a protective insulating layer covering the surface of the first electrode layer in the outer circumferential region before the step of forming the second electrode layer, the protective insulating layer has openings distributed over a range spanning the element region and the peripheral region, In the step of forming the protective insulating layer, the protective insulating layer is formed so that the recess is disposed within the opening and extends along the edge of the opening; In the step of forming the second electrode layer, the second electrode layer is formed in the opening. The method of claim 4.

6. a plurality of trenches are provided in the surface of the semiconductor substrate within the element region; When viewed along a thickness direction of the semiconductor substrate, the plurality of trenches extend parallel to each other along a specific direction, a gate electrode is disposed within each of the trenches; In the step of forming the plurality of interlayer insulating layers, the plurality of interlayer insulating layers are formed so that the intervals have linear portions extending in a direction intersecting the specific direction when viewed along the thickness direction of the semiconductor substrate. The method according to claim 4 or 5.

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