Semiconductor packaging structure and method for manufacturing the same

Abstract

To provide a semiconductor package structure that enables finer pitch electrodes, further space saving on the surface of connecting members, and suppresses warpage of the substrate. [Solution] The semiconductor package structure (1) includes a semiconductor package (12) including a semiconductor chip (2) and a first rewiring layer (4) having an area larger than that of the semiconductor chip (2) in a plan view in the thickness direction, a cured resin layer (5) made of a cured product of an anisotropic conductive film (14) in which conductors (10) are arranged at predetermined intervals on an insulating resin layer, and another substrate (6). The first rewiring layer (4) has the semiconductor chip (2) mounted on one surface (4A) and has a first electrode (7) on the other surface (4B) that connects to the other substrate (6). The other substrate (6) has a second electrode (11) on one surface (6A) that connects to the first electrode (7). In the semiconductor package structure (1), the first electrode (7) and the second electrode (11) are connected by the conductors (10) in the cured resin layer (5).

Description

[Technical Field]

[0001] The present technology relates to a semiconductor packaging structure and a method for manufacturing the semiconductor packaging structure. [Background technology]

[0002] FOWLP is a technology that forms electrodes for connecting to a substrate outside the semiconductor chip by forming a redistribution layer (RDL) on the electrode surface of the semiconductor chip (die) through wafer processing. FOWLP makes it possible to minimize the wiring inside the semiconductor chip, enabling the miniaturization and high performance of semiconductor chips.

[0003] Fig. 1 is a cross-sectional view showing an example of a fan-out wafer level package (FOWLP). Fig. 2 is a cross-sectional view showing an example of a semiconductor packaging structure 100 in which the FOWLP and a substrate are connected.

[0004] 1 and 2, in a conventional semiconductor package structure 100, electrodes 102 drawn out by a FOWLP 101 are connected (joined) to electrodes 105 on a substrate 104 by solder joints 103A consisting of solder balls (solder bumps) 103 (see, for example, Patent Document 1). The FOWLP 101 includes, for example, a semiconductor chip 106, a redistribution layer 107 having an area larger than that of the semiconductor chip 106 in a plan view in the thickness direction, and a sealing material 108.

[0005] As the performance of semiconductor chips improves, for example, if the line spacing (L / S) of the redistribution layer 107 in the FOWLP 101 is reduced, the risk of short circuits is thought to increase. Therefore, if the line spacing of the redistribution layer 107 is reduced, it is desirable to also reduce the solder balls 103. Furthermore, as the performance of semiconductor chips 106 improves, if the pitch of the electrodes 105 is reduced, it is thought to be desirable to also reduce the solder balls 103. However, due to the characteristics of the solder balls 103, the pitch of the electrodes 105 for connections using solder joints 103A is thought to be industrially limited to several tens of micrometers.

[0006] Furthermore, when connecting the FOWLP 101 and the substrate 104 with the solder balls 103, pads for the solder balls 103 are required. Therefore, it is considered difficult to reduce the space on the surface of the electrode side of the rewiring layer 107 of the FOWLP 101, for example.

[0007] Furthermore, when connecting the FOWLP 101 and the substrate 104 with the solder balls 103, the bonding temperature must be high, and this high temperature may cause, for example, warping of the substrate 104. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 6443893 Summary of the Invention [Problem to be solved by the invention]

[0009] This technology was proposed in consideration of the current situation, and provides a semiconductor package structure that enables finer electrode pitch and further space-saving on the surface of connecting components, while suppressing warping of the substrate. [Means for solving the problem]

[0010] The semiconductor package structure according to the present technology includes a semiconductor package having a semiconductor chip and a first redistribution layer having an area larger than that of the semiconductor chip when viewed in a planar view in the thickness direction; a cured resin layer made of a cured product of an anisotropic conductive film in which conductors are aligned at predetermined intervals on an insulating resin layer; and another substrate, wherein the first redistribution layer has the semiconductor chip mounted on one side and a first electrode connected to the other substrate on the other side, and the other substrate has a second electrode connected to the first electrode on one side, and the first electrode and the second electrode are connected by the conductor in the cured resin layer.

[0011] A method for manufacturing a semiconductor package structure according to the present technology includes a step of arranging a semiconductor package, which includes a semiconductor chip and a first redistribution layer having an area larger than that of the semiconductor chip in a planar view in the thickness direction, the semiconductor chip being mounted on one side, and a first electrode for connecting to another substrate on the other side, on the other substrate having a second electrode connecting to the first electrode, and connecting the first electrode and the second electrode via an anisotropic conductive film in which conductors are aligned at predetermined intervals on an insulating resin layer. [Effects of the Invention]

[0012] According to this technology, the first electrode and the second electrode are connected by a conductor in the cured resin layer, which makes it possible to achieve a finer pitch for the first electrode and the second electrode compared to when solder bumps are used.

[0013] Furthermore, according to the present technology, the first electrode and the second electrode are connected by a conductor in the cured resin layer, which makes it possible to further reduce the space required on the surface of the first rewiring layer on the first electrode side, for example.

[0014] Furthermore, according to the present technology, the semiconductor chip can be connected to another substrate at a lower temperature than when solder bumps are used, and warping of the other substrate can be suppressed. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a FOWLP. [Figure 2] FIG. 2 is a cross-sectional view showing an example of a semiconductor package structure in which a FOWLP and a substrate are connected. [Figure 3] FIG. 3 is a cross-sectional view showing an example of a semiconductor packaging structure according to the present technology. [Figure 4] FIG. 4 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor packaging structure according to the present technology. [Figure 5] FIG. 5 is an exploded cross-sectional view for explaining an example of a method for manufacturing a semiconductor packaging structure according to the present technology. [Figure 6] FIG. 6 is an exploded cross-sectional view for explaining an example of a method for manufacturing a semiconductor packaging structure according to the present technology. [Figure 7] FIG. 7 is an exploded cross-sectional view for explaining an example of a method for manufacturing a semiconductor packaging structure according to the present technology. [Figure 8] FIG. 8 is an exploded cross-sectional view for explaining an example of a method for manufacturing a semiconductor packaging structure according to the present technology. [Figure 9] FIG. 9 is an exploded cross-sectional view for explaining an example of a method for manufacturing a semiconductor packaging structure according to the present technology. DETAILED DESCRIPTION OF THE INVENTION

[0016] A semiconductor package structure and a method for manufacturing a semiconductor package structure to which the present technology is applied will be described in detail below with reference to the drawings. Note that the present technology is not limited to the following embodiments, and various modifications are possible within the scope of the gist of the present technology. Also, the drawings are schematic, and the ratios of each dimension may differ from the actual dimensions. Specific dimensions should be determined with reference to the following explanation. Of course, the drawings also include parts in which the dimensional relationships and ratios differ from one another.

[0017] <Semiconductor package structure> [First embodiment] 3 is a cross-sectional view showing an example of a semiconductor packaging structure 1 according to the present technology. The semiconductor packaging structure 1 includes a semiconductor chip 2, an encapsulant 3, a first redistribution layer 4, a cured resin layer 5, and another substrate 6. In the semiconductor packaging structure 1, a first electrode 7 and a second electrode 11 are connected by a conductor 10 in the cured resin layer 5. In the semiconductor packaging structure 1, a FOWLP (semiconductor package 12) composed of the semiconductor chip 2, the encapsulant 3, and the first redistribution layer 4 is connected to the other substrate 6 by the conductor 10 in the cured resin layer 5.

[0018] The semiconductor chip 2 is made of a semiconductor such as silicon, and has a circuit formed therein. The semiconductor chip 2 has, for example, a cubic shape having one surface 2A, another surface 2B opposite to the one surface 2A, and a side surface 2C between the one surface 2A and the other surface 2B. The one surface 2A of the semiconductor chip 2 contacts the first rewiring layer 4, and at least the side surface 2C contacts the encapsulant 3.

[0019] The encapsulant 3 is in contact with, for example, both the semiconductor chip 2 and the first redistribution layer 4. The encapsulant 3 can be made of an insulating resin, such as an epoxy resin. The encapsulant 3 may be a single layer or a multilayer. When the encapsulant 3 is a multilayer, the configuration of each layer may be the same or different.

[0020] The first redistribution layer 4 has the semiconductor chip 2 mounted on one surface 4A. The first redistribution layer 4 has first electrodes 7 on the other surface 4B that connect to another substrate 6. The first redistribution layer 4 is a wiring layer for drawing the circuit of the semiconductor chip 2 to the first electrodes 7. The first redistribution layer 4 has a larger area than the semiconductor chip 2 in a plan view in the thickness direction D of the semiconductor package structure 1.

[0021] The first redistribution layer 4 includes, for example, first wirings 8 connected to the semiconductor chip 2 and an insulating layer 9 in contact with the first wirings 8. The first redistribution layer 4 can be configured as a laminate of the first wirings 8 and the insulating layer 9. The first redistribution layer 4 may be a single layer or may be two or more layers. The first wirings 8 can be configured of a highly conductive material (metal), for example, copper. The insulating layer 9 is intended to prevent unintended conduction between the first wirings 8. The insulating layer 9 is in contact with, for example, the semiconductor chip 2 and the encapsulant 3. The thickness of the first redistribution layer 4 is not particularly limited and can be, for example, 10 to 100 μm.

[0022] The first electrode 7 can be made of, for example, a metal. Examples of metals that can be used include gold, silver, and copper. The first electrode 7 may be made of two or more metals. For example, the first electrode 7 may be made of a first metal, and the surface may be made of a second metal different from the first metal.

[0023] The first electrode 7 is, for example, a planar electrode. The outer shape and size of the first electrode 7 are not particularly limited, and may be, for example, a rectangular shape with a length of 3 to 20 μm, a width of 3 to 20 μm, and a height of 0.1 to 10 μm. From the viewpoint of enabling a finer pitch and further space-saving on the surface of the connecting member, the length and width of the first electrode 7 are, for example, preferably 20 μm or less, and may be 15 μm or less, 10 μm or less, or 5 μm or less. The space between the first electrodes 7 (the distance between adjacent first electrodes 7) is, for example, preferably 20 μm or less, and may be 15 μm or less, 10 μm or less, or 5 μm or less, from the viewpoint of realizing a finer pitch.

[0024] The other substrate 6 has, on one surface 6A, a second electrode 11 connected to the first electrode 7. The second electrode 11 is, for example, a planar electrode. The material of the second electrode 11, the outer shape and size of the second electrode 11, the space between the second electrodes 11 (the distance between adjacent second electrodes 11), etc. are not particularly limited and can be, for example, the same as that of the first electrode 7. The other substrate 6 may or may not have an electrode (not shown) on the other surface 6B.

[0025] The other substrate 6 is not particularly limited and may be, for example, a package substrate or an interposer. The interposer may have a base material made of, for example, silicon, resin, glass, or a combination of two or more of these materials, and specific examples include a silicon interposer, an organic interposer, and a glass interposer. For example, when the other substrate 6 is an organic interposer, it may be an organic substrate having a silicon bridge embedded therein. The other substrate 6 may be, for example, a combination of an interposer and a package substrate. For example, the other substrate 6 may have an embedded passive element array called an IPD (Integrated Passive Device) embedded therein in order to further improve signal quality.

[0026] The thickness of the other substrate 6 is not particularly limited, and can be, for example, 50 to 200 μm.

[0027] The cured resin layer 5 has conductors 10 aligned at predetermined intervals in a cured insulating resin. The cured resin layer 5 is made of, for example, a cured anisotropically conductive film 14 in which conductors 10 are aligned at predetermined intervals in an insulating resin layer 13. This makes it easier to stabilize the capture of conductors 10 between the first electrode 7 and the second electrode 11, further improving conductivity and insulation. The anisotropically conductive film 14 will be described in detail later.

[0028] The conductors 10 in the cured resin layer 5 are aligned at a predetermined interval. For example, the arrangement of the conductors 10 may be regular and repeatable, or the conductors 10 may be aligned but not uniformly within the cured resin layer 5. For example, the cured resin layer 5 may have unevenly distributed regions where the conductors 10 are aligned at a predetermined interval at positions corresponding to the first electrode 7 and the second electrode 11 (between the first electrode 7 and the second electrode 11), and other regions of the cured resin layer 5 other than these unevenly distributed regions where the conductors 10 are substantially absent. The shape of the arrangement of the conductors 10 is not particularly limited, and examples thereof include lattice arrangements such as a square lattice, a hexagonal lattice, an orthorhombic lattice, and a rectangular lattice in a plan view.

[0029] The shape of the conductor 10 is not particularly limited, and examples thereof include spherical and columnar shapes. The following description will be given taking an example where conductive particles are used as the conductor 10. The particle diameter of the conductor 10 is not particularly limited, and from the viewpoint of achieving finer pitches for the first electrodes 7 and the second electrodes 11 in the semiconductor packaging structure 1 and the capture efficiency of the conductor 10, it is preferably 20 μm or less, and may be 15 μm or less, 10 μm or less, or 5 μm or less. The particle diameter of the conductor 10 may be, for example, 1 μm or more, 3 μm or more, or 5 μm or more. The particle diameter of the conductor 10 may be a value measured, for example, using an imaging particle size distribution analyzer (e.g., FPIA-3000, manufactured by Malvern Instruments). In this case, the number of conductors 10 measured may be, for example, 1,000 or more.

[0030] Conductor 10 can be appropriately selected from conductive particles used in known anisotropic conductive films. Conductor 10 can be made of a material that allows electrical connection with another substrate 6 even when the semiconductor chip 2 does not have solder bumps as connection sites. For example, metal particles such as nickel, cobalt, silver, copper, gold, or palladium, alloy particles such as solder, or metal-coated resin particles in which the surface of resin particles such as polyamide or polybenzoguanamine is coated with a metal such as nickel can be used. Conductor 10 can be made of a single material or a combination of two or more materials. Metal-coated resin particles are preferred for conductor 10, for example, because repulsion of resin particles after connection facilitates maintaining contact between the first electrode 7 and the second electrode 11, resulting in more stable electrical conductivity. Furthermore, the surface of conductor 10 may be insulated using known techniques to the extent that it does not impair electrical conductivity.

[0031] The thickness of the cured resin layer 5 is not particularly limited, and can be, for example, 60% or more of the particle diameter of the conductor 10. The thickness of the cured resin layer 5 may be, for example, 1.3 times or more the particle diameter of the conductor 10, or may be 3 μm or more. The upper limit of the thickness of the cured resin layer 5 may be, for example, 3 times or less the particle diameter of the conductor 10, or may be 20 μm or less.

[0032] From the viewpoint of further improving the thermal conductivity of the cured resin layer 5, the cured resin layer 5 may further contain a thermally conductive filler, for example, in a region other than the conductive paths in the cured resin layer 5. Examples of the shape of the thermally conductive filler include spherical, fibrous, scaly, powdery, and granular shapes. Examples of the material of the thermally conductive filler include aluminum oxide (alumina, sapphire), aluminum nitride, aluminum, aluminum hydroxide, and boron nitride. One type of thermally conductive filler may be used alone, or two or more types may be used in combination.

[0033] As described above, in the semiconductor packaging structure 1, the first electrodes 7 and the second electrodes 11 are connected by the conductors 10 in the cured resin layer 5, so there is no need to introduce solder bumps on the semiconductor chip 2 side, for example. This allows for even finer pitches of the first electrodes 7 and the second electrodes 11. For example, in the semiconductor packaging structure 1, the width of the first electrodes 7 and the second electrodes 11 can be 20 μm or less, the space between multiple first electrodes 7 and the space between multiple second electrodes 11 can be 20 μm or less, and the average particle size of the conductors 10 can be 5 μm or less.

[0034] Furthermore, the semiconductor packaging structure 1 does not require the use of, for example, solder bumps, and therefore does not require the use of pads for solder bumps. This, for example, enables further space saving on the surface of the first redistribution layer 4 on the side of the first electrodes 7. Furthermore, since the semiconductor packaging structure 1 does not require the use of pads for solder bumps, for example, mounting with an even lower height is possible. Therefore, the semiconductor packaging structure 1 can achieve higher performance at the package level (for example, the semiconductor package 12).

[0035] <Method of manufacturing semiconductor package structure> 4 is an exploded cross-sectional view illustrating an example of a method for manufacturing a semiconductor package structure according to the present technology. The method for manufacturing the semiconductor package structure 1 (hereinafter also referred to as a first manufacturing method) includes, for example, the following steps A, B, and C, and may further include other steps.

[0036] In step A, an anisotropic conductive film 14 is attached to the surface of the semiconductor package 12 on the stage on the side of the first electrode 7, using, for example, a bonding device. The semiconductor package 12 includes a semiconductor chip 2 and a first redistribution layer 4 that is larger in area than the semiconductor chip 2 in a plan view in the thickness direction D, has the semiconductor chip 2 mounted on one surface 4A, and has first electrodes 7 on the other surface 4B. The anisotropic conductive film 14 has conductors 10 aligned at predetermined intervals on an insulating resin layer 13. In step A, instead of attaching the anisotropic conductive film 14 to the surface of the semiconductor package 12 on the side of the first electrode 7, the anisotropic conductive film 14 may be attached to the surface of the other substrate 6 on the side of the second electrode 11.

[0037] In step B, for example, the second electrodes 11 of the other substrate 6 and the first electrodes 7 of the semiconductor package 12 are aligned, and the semiconductor package 12 is mounted on the other substrate 6.

[0038] In step C, the first electrode 7 of the semiconductor package 12 is connected to the second electrode 11 of the other substrate 6 via the anisotropic conductive film 14. In step C, for example, the semiconductor package 12 is pressed with a pressure bonding tool via a buffer material. In step C, the anisotropic conductive film 14 is cured by heating, light irradiation, or the like, depending on the curing type of the anisotropic conductive film 14. As a result, the conductor 10 is sandwiched between the first electrode 7 and the second electrode 11, and the first electrode 7 and the second electrode 11 are connected. For example, the thermocompression bonding conditions can be a temperature of 150 to 260°C, a pressure of 1 to 60 MPa, and a time of 5 to 300 seconds.

[0039] Thus, the first manufacturing method includes a step of connecting the first electrode 7 and the second electrode 11 via an anisotropic conductive film 14 while a semiconductor package 12 having a semiconductor chip 2 and a first redistribution layer 4 is arranged on another substrate 6, thereby obtaining a semiconductor package structure 1 shown in, for example, Figure 3.

[0040] Next, a configuration example of the anisotropic conductive film 14 will be described. The anisotropic conductive film 14 is, for example, provided on a release-treated film and separated into individual anisotropic conductive films 14 by, for example, adhering to an object to be connected. The anisotropic conductive film 14 is, for example, a particle-aligned film in which conductors 10 are arranged in the planar direction. The conductors 10 may be arranged, for example, with a repeating regularity. The shape of the arrangement of the conductors 10 is not particularly limited, and examples include lattice arrangements such as a square lattice, a hexagonal lattice, an oblique lattice, and a rectangular lattice. By arranging the conductors 10 in the planar direction of the anisotropic conductive film 14, it becomes easier to stabilize the capture of the conductors 10 by the first electrode 7 and the second electrode 11, thereby further improving the conductivity and insulation properties.

[0041] The anisotropic conductive film 14 may also be configured to have unevenly distributed regions where the conductors 10 are unevenly distributed at positions corresponding to the first electrode 7 and the second electrode 11, and to have no conductors 10 in regions other than these unevenly distributed regions. From the viewpoint of capturing the conductors 10, the unevenly distributed regions may be, for example, 0.8 times or more the size of the first electrode 7 and the second electrode 11. From the viewpoint of reducing the amount of conductors 10, the unevenly distributed regions may be, for example, 1.2 times or less the size of the first electrode 7 and the second electrode 11.

[0042] The anisotropic conductive film 14 is formed in the form of a film with the arrangement direction of the first electrode 7 and the second electrode 11 as the longitudinal direction, and the conductors 10 may be arranged sparsely in the longitudinal direction and densely in the width direction, or the conductors 10 may be arranged densely in the longitudinal direction and sparsely in the width direction.

[0043] The particle surface density of the conductor 10 in the anisotropic conductive film 14 can be appropriately designed depending on, for example, the sizes of the first electrode 7 and the second electrode 11. The lower limit of the particle surface density of the anisotropic conductive film 14 is, for example, 500 particles / mm from the viewpoint of obtaining excellent conductivity and insulation properties even when the electrode size is small. 2 Can be more than 20000 pieces / mm 2 It may be 40,000 pieces / mm or more. 2It may be 50,000 pieces / mm or more. 2 The upper limit of the particle surface density is, for example, 1,500,000 particles / mm from the viewpoint of obtaining excellent conductivity and insulation properties even when the electrode size is small. 2 Can be less than 1,000,000 pieces / mm 2 It may be 500,000 pieces / mm or less. 2 It may be less than 100,000 pieces / mm 2 It may be the following:

[0044] The thickness of the anisotropic conductive film 14 may be, for example, the same as the particle diameter of the conductor 10, or may be 1.3 times or more the particle diameter of the conductor 10, or may be 2 μm or more, or may be 10 μm or more. The thickness of the anisotropic conductive film 14 may be, for example, 200 μm or less, 50 μm or less, or may be 2 times or less the particle diameter of the conductor 10.

[0045] The anisotropic conductive film 14 may be laminated with an adhesive layer or pressure-sensitive adhesive layer that does not contain the conductor 10, and the number of layers and lamination surface can be selected appropriately according to the object and purpose.

[0046] The conductor 10 has the same meaning as the conductor 10 in the cured resin layer 5 described above, and the preferred range is also the same.

[0047] A known insulating resin (insulating binder) can be used for the insulating resin layer 13. Examples of the curing type include a heat-curing type, a photo-curing type, and a combined photo- and heat-curing type. Examples include a photo-radical polymerization type resin composition containing a (meth)acrylate compound and a photo-radical polymerization initiator, a thermal radical polymerization type resin composition containing a (meth)acrylate compound and a thermal radical polymerization initiator, a thermal cationic polymerization type resin composition containing an epoxy compound and a thermal cationic polymerization initiator, and a thermal anionic polymerization type resin composition containing an epoxy compound and a thermal anionic polymerization initiator.

[0048] Hereinafter, a specific example will be described, taking as an example a thermal radical polymerization insulating binder containing a film-forming resin, an elastomer, a (meth)acrylic monomer, a polymerization initiator, and a silane coupling agent. Note that the term "(meth)acrylic monomer" means both an acrylic monomer and a methacrylic monomer.

[0049] The film-forming resin is not particularly limited, and examples thereof include phenoxy resin, unsaturated polyester resin, saturated polyester resin, urethane resin, butadiene resin, polyimide resin, polyamide resin, and polyolefin resin. The film-forming resin may be used alone or in combination of two or more. Among these, phenoxy resin is preferred in terms of film-forming properties, processability, and connection reliability. Phenoxy resin is a resin synthesized from bisphenol A and epichlorohydrin, and an appropriately synthesized product or a commercially available product may be used. The content of the film-forming resin may be, for example, 10 to 60% by mass.

[0050] The elastomer is not particularly limited, and examples thereof include polyurethane resin (polyurethane-based elastomer), acrylic rubber, silicone rubber, and butadiene rubber.

[0051] The (meth)acrylic monomer is not particularly limited, and may be, for example, a monofunctional (meth)acrylic monomer or a polyfunctional (meth)acrylic monomer having two or more functional groups. From the viewpoint of stress relaxation of the polymer, it is preferable that 80 mass % or more of the (meth)acrylic monomers in the insulating binder are monofunctional (meth)acrylic monomers. Furthermore, from the viewpoint of adhesiveness, it is preferable that the monofunctional (meth)acrylic monomer has a carboxylic acid. Furthermore, the molecular weight of the monofunctional (meth)acrylic monomer having a carboxylic acid can be, for example, 100 to 500. Furthermore, the content of the monofunctional (meth)acrylic monomer having a carboxylic acid in the insulating binder can be, for example, 3 to 20 mass %.

[0052] The polymerization initiator is not particularly limited as long as it can cure the (meth)acrylic monomer at a predetermined temperature during thermocompression bonding, and examples thereof include organic peroxides. Examples of organic peroxides include lauroyl peroxide, butyl peroxide, benzyl peroxide, dilauroyl peroxide, dibutyl peroxide, peroxydicarbonate, and benzoyl peroxide. These may be used alone or in combination of two or more. The content of the polymerization initiator in the insulating binder is not particularly limited, and can be, for example, 0.5 to 15 mass%.

[0053] The silane coupling agent is not particularly limited, and examples thereof include epoxy-based silane coupling agents, acrylic-based silane coupling agents, thiol-based silane coupling agents, amine-based silane coupling agents, etc. The content of the silane coupling agent in the insulating binder is not particularly limited, and can be, for example, 0.1 to 5.0 mass%.

[0054] As described above, in the first manufacturing method of the semiconductor package structure, the first electrode 7 and the second electrode 11 are connected via the anisotropic conductive film 14, so that solder bumps do not need to be used to connect the semiconductor package 12 and the other substrate 6, and the semiconductor chip 2 can be connected to the other substrate 6 at a lower temperature, thereby suppressing warpage of the other substrate 6. This makes it possible to suppress, for example, adverse effects (misalignment of assembly) caused by warpage of the other substrate 6. In particular, when the interface between the semiconductor package 12 and the other substrate 6 is made of an organic material, for example, when the other substrate 6 is an organic interposer, warpage of the sealant of the semiconductor package 12 and the other substrate 6 can be effectively suppressed.

[0055] Furthermore, in the first manufacturing method of the semiconductor package structure, since solder bumps are not required to connect the semiconductor package 12 to the other substrate 6, underfill material is also not required, which further reduces the manufacturing process and prevents the risk of underfill material not being filled.

[0056] <Other embodiments> The semiconductor packaging structure according to the present technology is not limited to the above-described semiconductor packaging structure 1, and may have other forms. For example, the semiconductor packaging structure may further include a plurality of semiconductor chips including a semiconductor package 12 (FOWLP) constituting the semiconductor packaging structure 1 mounted on another substrate 6.

[0057] [Second embodiment] 5 is an exploded cross-sectional view illustrating an example of a manufacturing method for a semiconductor package structure 20 according to the present technology. The semiconductor package structure 20 includes, for example, a semiconductor package 12, which is a FOWLP, a semiconductor chip group 21, which is a combination of semiconductor chip pieces (chiplets) 21a and 21b fabricated for each function, and an HBM (High Bandwidth Memory) 22, which are mounted on a silicon interposer 23 serving as another substrate 6 along direction A, which is the arrangement direction of these. The semiconductor chip group 21 has a third electrode 24 on one surface 21A. The HBM 22 has a fourth electrode 25 on one surface 22A. The semiconductor chip group 21 and the HBM 22 may also have a redistribution layer similar to the first redistribution layer 4 of the semiconductor package 12.

[0058] The silicon interposer 23 has, for example, a wiring layer and through-silicon vias (TSVs) 26. The through-silicon vias 26 are for connecting the wiring layer to the other surface 23B. An electrode (not shown) (hereinafter also referred to as a fifth electrode) for connecting the first electrode 7, the third electrode 24, and the fourth electrode 25 is formed on one surface 23A of the silicon interposer 23. This fifth electrode corresponds to the second electrode 11 described above and can have a configuration similar to that of the second electrode 11. In the semiconductor package structure 20, the first electrode 7, the third electrode 24, and the fourth electrode 25 are connected to the fifth electrode (corresponding to the second electrode 11 described above) of the silicon interposer 23 by the conductor 10 in the cured resin layer 5 made of the cured product of the anisotropic conductive film 14 described above.

[0059] Such a semiconductor package structure 20 does not require the introduction of solder bumps on the semiconductor package 12, semiconductor chip group 21, and HBM 22 sides, for example. This allows for even finer pitches of the first electrodes 7, third electrodes 24, and fourth electrodes 25. For example, in the semiconductor package structure 20, the widths of the first electrodes 7, third electrodes 24, and fourth electrodes 25 can be 20 μm or less, the spaces between multiple first electrodes 7, the spaces between multiple third electrodes 24, and the spaces between multiple fourth electrodes 25 can be 20 μm or less, and the average particle diameter of the conductors 10 can be 5 μm or less.

[0060] Furthermore, the semiconductor package structure 20 does not require solder bumps, and therefore does not require pads for solder bumps, which makes it possible to further reduce the space required on the surfaces of the first electrode 7, the third electrode 24, and the fourth electrode 25, for example.

[0061] Electrodes 27 are formed on the other surface 23B of the silicon interposer 23 for connection to, for example, another package substrate 28. The semiconductor package structure 20 can be mounted on the package substrate 28 via the electrodes 27. For example, solder bumps are used as the electrodes 27. For example, a printed wiring board can be used as the package substrate 28.

[0062] The manufacturing method of the semiconductor packaging structure 20 (hereinafter also referred to as the second manufacturing method) includes, for example, the following steps A1, B1, and C1, and may further include other steps.

[0063] In step A1, an anisotropic conductive film 14 is attached to the surfaces of the stage on the side of the first electrode 7, the third electrode 24, and the fourth electrode 25, for example, using a bonding device. The anisotropic conductive film 14 has conductors 10 aligned at predetermined intervals on an insulating resin layer 13. In step A1, instead of attaching the anisotropic conductive film 14 to the surfaces of the stage on the side of the first electrode 7, the third electrode 24, and the fourth electrode 25, the anisotropic conductive film 14 may be attached to the surface of the silicon interposer 23 on the side of the fifth electrode (corresponding to the second electrode 11 described above).

[0064] In step B1, for example, the fifth electrode (corresponding to the second electrode 11 described above) of the silicon interposer 23 is aligned with the first electrode 7, the third electrode 24, and the fourth electrode 25, and the semiconductor package 12, the semiconductor chip group 21, and the HBM 22 are mounted on the silicon interposer 23.

[0065] In step C1, the first electrode 7, the third electrode 24, and the fourth electrode 25 are connected to the fifth electrode of the silicon interposer 23 via the anisotropic conductive film 14. As a result, the conductor 10 is sandwiched between the first electrode 7, the third electrode 24, and the fourth electrode 25 and the fifth electrode of the silicon interposer 23, and the first electrode 7, the third electrode 24, and the fourth electrode 25 are connected to the fifth electrode of the silicon interposer 23. In step C1, as in the above-described step C, the anisotropic conductive film 14 can be cured depending on the curing type of the anisotropic conductive film 14.

[0066] In the second manufacturing method, solder bumps do not need to be used to connect the first electrode 7, the third electrode 24, and the fourth electrode 25 to the fifth electrode of the silicon interposer 23 (corresponding to the second electrode 11 described above), so the semiconductor package 12, the semiconductor chip group 21, and the HBM 22 can be connected to the silicon interposer 23 at a lower temperature, and warping of the silicon interposer 23 can be suppressed.

[0067] Furthermore, in the second manufacturing method, since solder bumps do not need to be used to connect the first electrode 7, the third electrode 24, and the fourth electrode 25 to the fifth electrode, underfill material does not need to be used either, which further reduces the manufacturing process and prevents the risk of underfill material not being filled.

[0068] [Third embodiment] 6 is an exploded cross-sectional view illustrating an example of a manufacturing method for a semiconductor packaging structure 30 according to the present technology. The semiconductor packaging structure 30 has the same configuration as the semiconductor packaging structure 20, except that the silicon interposer 23 in the semiconductor packaging structure 20 is changed to an interposer 32 (corresponding to the other substrate 6 described above) having a silicon bridge 31.

[0069] The interposer 32 has, for example, a silicon bridge 31 and a silicon through electrode 33. The interposer 32 has, for example, the silicon bridge 31 embedded in an organic substrate. The semiconductor package structure 20 has, as the silicon bridge 31, for example, a silicon bridge 31A for connecting the first electrode 7 and the third electrode 24, and a silicon bridge 31B for connecting the third electrode 24 and the fourth electrode 25.

[0070] Electrodes (not shown) (corresponding to the second electrode 11 described above) are formed on one surface 32A of the interposer 32 for connection to the first electrode 7, the third electrode 24, and the fourth electrode 25. The electrodes on the one surface 32A of the interposer 32 can have the same configuration as the second electrode 11 described above. In the semiconductor package structure 30, the first electrode 7, the third electrode 24, and the fourth electrode 25 are connected to the electrodes on the one surface 32A of the interposer 32 (corresponding to the second electrode 11 described above) by conductors 10 in the cured resin layer 5 made of the cured product of the anisotropic conductive film 14. Electrodes 27 for connection to another package substrate 28 are formed on the other surface 32B of the interposer 32.

[0071] Such a semiconductor packaging structure 30 can achieve the same effects as the above-described semiconductor packaging structure 20. Moreover, the semiconductor packaging structure 30 can be manufactured in the same manner as the second manufacturing method. Therefore, the manufacturing method of the semiconductor packaging structure 30 can also achieve the same effects as the above-described second manufacturing method.

[0072] [Fourth embodiment] 7 is an exploded cross-sectional view illustrating an example of a manufacturing method for a semiconductor packaging structure 40 according to the present technology. The semiconductor packaging structure 40 has the same configuration as the semiconductor packaging structure 20, except that the silicon interposer 23 in the semiconductor packaging structure 20 is changed to an organic interposer 41 (corresponding to the other substrate 6 described above). As the organic interposer 41, for example, a build-up substrate having a thin-film wiring layer formed on the surface thereof can be used.

[0073] Electrodes (not shown) (corresponding to the second electrode 11 described above) for connecting the first electrode 7, the third electrode 24, and the fourth electrode 25 are formed on one surface 41A of the organic interposer 41. The electrodes on the one surface 41A of the organic interposer 41 can have the same configuration as the second electrode 11 described above. In the semiconductor package structure 40, the first electrode 7, the third electrode 24, and the fourth electrode 25 are connected to the electrodes on the one surface 41A of the organic interposer 41 (corresponding to the second electrode 11 described above) by conductors 10 in the cured resin layer 5 made of the cured product of the anisotropic conductive film 14. An electrode 27 for connecting to another package substrate 28 is formed on the other surface 41B of the organic interposer 41.

[0074] Such a semiconductor packaging structure 40 can achieve the same effects as the above-described semiconductor packaging structure 20. Moreover, the semiconductor packaging structure 40 can be manufactured in the same manner as the second manufacturing method. Therefore, the manufacturing method of the semiconductor packaging structure 40 can also achieve the same effects as the above-described second manufacturing method.

[0075] [Fifth embodiment] 8 is an exploded cross-sectional view for explaining an example of a manufacturing method of a semiconductor packaging structure 50 according to the present technology. The semiconductor packaging structure 50 has the same configuration as the semiconductor packaging structure 20, except that the silicon interposer 23 in the semiconductor packaging structure 20 is changed to a glass interposer 51 (corresponding to the other substrate 6 described above). As the glass interposer 51, for example, one in which a thin film wiring layer is formed on the surface of a glass base material, fine through holes are formed inside the glass base material, and through electrodes 52 called TGVs (Through Glass vias) in which a conductive material is filled are disposed in the through holes can be used.

[0076] Electrodes (not shown) (corresponding to the second electrode 11 described above) are formed on one surface 51A of the glass interposer 51 for connection to the first electrode 7, the third electrode 24, and the fourth electrode 25. The electrodes on the one surface 51A of the glass interposer 51 can have the same configuration as the second electrode 11 described above. In the semiconductor package structure 50, the first electrode 7, the third electrode 24, and the fourth electrode 25 are connected to the electrodes on the one surface 51A of the glass interposer 51 by conductors 10 in the cured resin layer 5 made of a cured product of the anisotropic conductive film 14. Electrodes 27 for connection to another package substrate 28 are formed on the other surface 51B of the glass interposer 51.

[0077] Such a semiconductor packaging structure 50 can achieve the same effects as the above-described semiconductor packaging structure 20. Moreover, the semiconductor packaging structure 50 can be manufactured in the same manner as the second manufacturing method. Therefore, the manufacturing method of the semiconductor packaging structure 50 can also achieve the same effects as the above-described second manufacturing method.

[0078] [Sixth embodiment] 9 is an exploded cross-sectional view illustrating an example of a manufacturing method for a semiconductor packaging structure 60 according to the present technology. The semiconductor packaging structure 60 has the same configuration as the semiconductor packaging structure 20, except that the silicon interposer 23 in the semiconductor packaging structure 20 is changed to an interposer 64 (corresponding to the other substrate 6 described above) in which an organic resin wiring layer 63 is formed on a silicon substrate 62 having Si through electrodes 61 (TSV: Through Silicon via).

[0079] Electrodes (not shown) (corresponding to the second electrode 11 described above) are formed on one surface 64A of the interposer 64 for connection to the first electrode 7, the third electrode 24, and the fourth electrode 25. The electrodes on the one surface 64A of the interposer 64 can have the same configuration as the second electrode 11 described above. In the semiconductor package structure 60, the first electrode 7, the third electrode 24, and the fourth electrode 25 are connected to the electrodes on the one surface 64A of the interposer 64 by conductors 10 in the cured resin layer 5 made of the cured product of the anisotropic conductive film 14. Electrodes 27 for connection to another package substrate 28 are formed on the other surface 64B of the interposer 64.

[0080] Such a semiconductor packaging structure 60 can achieve the same effects as the above-described semiconductor packaging structure 20. Moreover, the semiconductor packaging structure 60 can be manufactured in the same manner as the second manufacturing method. Therefore, the manufacturing method of the semiconductor packaging structure 60 can also achieve the same effects as the above-described second manufacturing method. [Explanation of symbols]

[0081] 1 semiconductor package structure, 2 semiconductor chips, 2A One side, 2B The other side, 2C side, 3 sealant, 4 first redistribution layer; 4A One side, 4B The other side, 5 Cured resin layer, 6 other boards, 6A One side, 6B The other side, 7 first electrode, 8 first wiring, 9 first insulating layer, 10 conductors, 11 second electrode, 12 semiconductor packages, 13 insulating resin layer, 14 Anisotropic conductive film, 20 semiconductor package structure, 21 semiconductor chips, 21A One side, 21a Small pieces of semiconductor chips; 21b Small pieces of semiconductor chips; 22 HBM, 22A One side, 23 silicon interposer, 23A One side, 23B On the other side, 24 third electrode, 25 fourth electrode, 26 through silicon vias, 27 electrodes, 28 package substrate, 30 semiconductor package structure, 31 Silicon Bridge, 32 interposers, 32A One side, 32B On the other side, 33 through silicon vias, 40 semiconductor package structure, 41 Organic interposer, 41A One side, 41B On the other side, 50 semiconductor package structure, 51 Glass interposer, 51A One side, 51B the other side, 52 Through electrode, 60 semiconductor package structure, 61 Si through electrode, 62 silicon substrate, 63 Organic resin rewiring layer, 64 interposers, 64A One side, 64B On the other side, 100 semiconductor package structure, 101 FOWLP, 102 electrodes, 103 solder balls, 103A solder joint, 104 boards, 105 electrodes, 106 semiconductor chips, 107 redistribution layer, 108 Sealant

Claims

1. a semiconductor package including a semiconductor chip and a first rewiring layer having an area larger than that of the semiconductor chip in a plan view in the thickness direction; a cured resin layer made of a cured product of an anisotropic conductive film in which conductors are arranged at predetermined intervals on an insulating resin layer; Other boards Equipped with the first rewiring layer has the semiconductor chip mounted on one surface and a first electrode for connection to the other substrate on the other surface; the other substrate has, on one surface thereof, a second electrode connected to the first electrode; the cured resin layer has an unevenly distributed region in which the conductors are aligned at a predetermined interval between the first electrode of the first redistribution layer and the second electrode of the other substrate, and another region other than the unevenly distributed region in which the conductors are substantially not present; The semiconductor package structure, wherein the first electrode and the second electrode are connected by the conductor in the cured resin layer.

2. a semiconductor package including a semiconductor chip and a first rewiring layer having an area larger than that of the semiconductor chip in a plan view in the thickness direction; A group of semiconductor chips made by combining small pieces of semiconductor chips; High bandwidth wide memory and a cured resin layer made of a cured product of an anisotropic conductive film in which conductors are arranged at predetermined intervals on an insulating resin layer; Other boards Equipped with the first rewiring layer has the semiconductor chip mounted on one surface and a first electrode for connection to the other substrate on the other surface; the semiconductor chip group has a third electrode on the surface on the other surface side for connection to the other substrate, the high bandwidth wide memory has a fourth electrode on the surface on the other surface side for connection to the other substrate, the other substrate has, on one surface thereof, a second electrode connected to the first electrode, the third electrode, and the fourth electrode; the cured resin layer has unevenly distributed regions in which the conductors are aligned at predetermined intervals between the first electrode of the first redistribution layer and the second electrode of the other substrate, between the third electrode and the second electrode, and between the fourth electrode and the second electrode, and other regions other than the unevenly distributed regions in which the conductors are substantially absent; a semiconductor package structure in which the first electrode and the second electrode, the third electrode and the second electrode, and the fourth electrode and the second electrode are connected by the conductor in the cured resin layer.

3. a semiconductor package including a semiconductor chip and a first rewiring layer having an area larger than that of the semiconductor chip in a plan view in the thickness direction; a cured resin layer made of a cured product of a single anisotropic conductive film in which conductors are aligned at predetermined intervals on an insulating resin layer; Other boards Equipped with the first rewiring layer has the semiconductor chip mounted on one surface and a first electrode for connection to the other substrate on the other surface; the other substrate has, on one surface thereof, a second electrode connected to the first electrode; the cured resin layer has an unevenly distributed region in which the conductors are aligned at a predetermined interval between the first electrode of the first redistribution layer and the second electrode of the other substrate, and another region other than the unevenly distributed region in which the conductors are substantially not present; the first electrode and the second electrode are connected by the conductor in the cured resin layer, The width of the first electrode and the second electrode is 20 μm or less, a space between the plurality of first electrodes and a space between the plurality of second electrodes are 20 μm or less; A semiconductor package structure, wherein the average particle size of the conductor is 5 μm or less.

4. a semiconductor package including a semiconductor chip and a first rewiring layer having an area larger than that of the semiconductor chip in a plan view in the thickness direction; A group of semiconductor chips made by combining small pieces of semiconductor chips; High bandwidth wide memory and a cured resin layer made of a cured product of a single anisotropic conductive film in which conductors are aligned at predetermined intervals on an insulating resin layer; Other boards Equipped with the first rewiring layer has the semiconductor chip mounted on one surface and a first electrode for connection to the other substrate on the other surface; the semiconductor chip group has a third electrode on the surface on the other surface side for connection to the other substrate, the high bandwidth wide memory has a fourth electrode on the surface on the other surface side for connection to the other substrate, the other substrate has, on one surface thereof, a second electrode connected to the first electrode, the third electrode, and the fourth electrode; the cured resin layer has unevenly distributed regions in which the conductors are aligned at predetermined intervals between the first electrode of the first redistribution layer and the second electrode of the other substrate, between the third electrode and the second electrode, and between the fourth electrode and the second electrode, and other regions other than the unevenly distributed regions in which the conductors are substantially absent; the conductor in the cured resin layer connects the first electrode to the second electrode, the third electrode to the second electrode, and the fourth electrode to the second electrode; The width of the first electrode and the second electrode is 20 μm or less, a space between the plurality of first electrodes and a space between the plurality of second electrodes are 20 μm or less; A semiconductor package structure, wherein the average particle size of the conductor is 5 μm or less.

5. The semiconductor packaging structure of claim 1 or 2, wherein the first electrode is a planar electrode.

6. The semiconductor package structure according to claim 1 or 2, wherein the other substrate is an interposer or a package substrate.

7. 3. The semiconductor package structure according to claim 1, wherein the other substrate is an interposer, and the base material is silicon, resin, glass, or a combination of two or more of these.

8. The semiconductor packaging structure according to claim 1 or 2, wherein the cured resin layer further comprises a thermally conductive filler.

9. a step of connecting the first electrode and the second electrode via an anisotropic conductive film in which conductors are arranged at predetermined intervals on an insulating resin layer, the step comprising: a semiconductor package including a semiconductor chip; and a first rewiring layer having an area larger than that of the semiconductor chip in a plan view in the thickness direction, the semiconductor chip being mounted on one surface thereof, and a first electrode for connecting to another substrate on the other surface thereof; the first electrode and the second electrode being arranged on the other substrate, the first electrode and the second electrode being connected to each other via an anisotropic conductive film in which conductors are arranged at predetermined intervals on an insulating resin layer; A method for manufacturing a semiconductor package structure, wherein the anisotropic conductive film has an uneven distribution region in which the conductors are aligned at a predetermined interval between a first electrode of the first redistribution layer and a second electrode of the other substrate, and other regions other than the uneven distribution region in which the conductors are substantially absent.

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