Chip, ultrasonic fingerprint module, and electronic device

Abstract

The present application relates to the technical field of chips. Particularly disclosed are a chip, an ultrasonic fingerprint module, and an electronic device. The chip comprises a substrate, the substrate comprising an electrode located on the substrate and an internal conductive layer located inside the substrate; the internal conductive layer inside the substrate comprises a first conductive layer located on the top layer and a second conductive layer located below the first conductive layer, the electrode being electrically connected to the first conductive layer, and the electrode being further electrically connected to a circuit board by means of an anisotropic conductive film (ACF) bonding process. In a first direction of the substrate, the minimum distance between the edge of the substrate provided with the electrode and the wiring of the second conductive layer is a first preset distance, and in a second direction of the substrate, the arrangement position area of the electrode is partially or totally free of the wiring of the second conductive layer, the first direction being perpendicular to the second direction.

Description

Chips, ultrasonic fingerprint modules and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202520269857.7, filed on February 19, 2025, entitled “Chip, Ultrasonic Fingerprint Module and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip technology, and more particularly to a chip, an ultrasonic fingerprint module, and an electronic device. Background Technology

[0003] Currently, chips are generally connected to the gold fingers of the circuit board by anisotropic conductive film (ACF) bonding technology. For example, the connection between the ultrasonic fingerprint chip and the module circuit board in an ultrasonic fingerprint module for fingerprint recognition.

[0004] ACF bonding process requires appropriate temperature and pressure to ensure electrical connection between the chip's electrodes and the circuit board. There are metal traces under the electrodes inside the chip. If there are foreign objects such as silicon debris on the chip's electrodes, short circuits may occur between the chip's electrodes and the traces under the electrodes due to electrode damage, causing the chip to malfunction. Summary of the Invention

[0005] This application provides a chip, an ultrasonic fingerprint module, and an electronic device to solve the technical problem that the chip's function fails due to short circuits caused by damage to the bonding pad and the traces under the pad.

[0006] Based on the above technical issues, the following solutions are provided:

[0007] In a first aspect, a chip is provided, the chip including a substrate, the substrate including electrodes located on the substrate and an internal conductive layer located inside the substrate;

[0008] The internal conductive layer inside the substrate includes a first conductive layer at the top and a second conductive layer below the first conductive layer. The electrode is electrically connected to the first conductive layer. The electrode is also used to be electrically connected to the circuit board via anisotropic conductive film (ACF) bonding process. The minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer in the first direction of the substrate is a first preset distance, so that the area where the electrode is disposed is wholly or partially free of traces of the second conductive layer along the second direction of the substrate. The first direction is perpendicular to the second direction.

[0009] Furthermore, the first preset distance includes a first distance, where the minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer in the first direction of the substrate is the first distance, so that the part of the electrode's arrangement area has no trace of the second conductive layer along the second direction of the substrate.

[0010] Furthermore, the ratio of the partial arrangement area of ​​the electrode to the total arrangement area of ​​the electrode is greater than 50%.

[0011] Furthermore, the first preset distance includes a second distance, where the minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer in the first direction of the substrate is the second distance, such that there are no traces of the second conductive layer in the entire arrangement area of ​​the electrode along the second direction of the substrate.

[0012] Furthermore, the minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the first conductive layer is a second preset distance, which is less than the first preset distance.

[0013] Furthermore, the circuit board includes a flexible circuit board.

[0014] Furthermore, the chip includes an ultrasonic fingerprint chip.

[0015] Secondly, an ultrasonic fingerprint module is provided, the ultrasonic fingerprint module including an ultrasonic fingerprint chip and a circuit board;

[0016] The ultrasonic fingerprint chip includes a substrate, on which electrodes are located and an internal conductive layer is located. The internal conductive layer includes a first conductive layer at the top and a second conductive layer below the first conductive layer. The electrodes are electrically connected to the first conductive layer. The electrodes are also used to be electrically connected to the circuit board via anisotropic conductive film (ACF) bonding process. The minimum distance between the edge of the substrate where the electrodes are located and the trace of the second conductive layer in a first direction of the substrate is a first preset distance, so that the area where the electrodes are located is entirely or partially free of traces of the second conductive layer along a second direction of the substrate.

[0017] Furthermore, the first preset distance includes a first distance, where the minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer in the first direction of the substrate is the first distance, so that the part of the electrode's arrangement area has no trace of the second conductive layer along the second direction of the substrate.

[0018] Furthermore, the ratio of the partial arrangement area of ​​the electrode to the total arrangement area of ​​the electrode is greater than 50%.

[0019] Furthermore, the first preset distance includes a second distance, where the minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer in the first direction of the substrate is the second distance, such that there are no traces of the second conductive layer in the entire arrangement area of ​​the electrode along the second direction of the substrate.

[0020] Furthermore, the minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the first conductive layer is a second preset distance, which is less than the first preset distance.

[0021] Furthermore, the circuit board includes a flexible circuit board.

[0022] Thirdly, an electronic device is provided, including a chip as described in any of the preceding claims, or an ultrasonic fingerprint module as described in any of the preceding claims.

[0023] In one of the above-described solutions, the chip includes a substrate, on which electrodes are located and an internal conductive layer is located. The internal conductive layer includes a first conductive layer at the top and a second conductive layer below the first conductive layer. The electrodes are electrically connected to the first conductive layer and are also used for electrical connection to a circuit board via anisotropic conductive film (ACF) bonding. The minimum distance between the edge of the substrate where the electrodes are located and the trace of the second conductive layer in the first direction of the substrate is a first preset distance, so that the electrode placement area has no trace of the second conductive layer in the second direction of the substrate. The first direction is perpendicular to the second direction. Therefore, the electrode placement area of ​​the chip has no trace of the second conductive layer in all or part of the second direction of the substrate. Thus, there is a clearance space between the electrodes and the trace below in the second direction. Therefore, even if the electrodes of the chip are damaged, it will not cause a short circuit and will not affect the subsequent chip function. This improves production yield and reduces the reliability risk of chip use, thus having significant application value. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 is a cross-sectional view of the connection between the chip and the circuit board and the conductive traces inside the chip substrate.

[0026] Figure 2 is a top view schematic diagram showing the relationship between the conductive traces inside the chip substrate and the arrangement of the chip electrodes.

[0027] Figure 3 is a cross-sectional schematic diagram of the connection relationship between the chip and the circuit board and the conductive traces inside the chip substrate in the partial avoidance method.

[0028] Figure 4 is a top view schematic diagram of the relationship between the conductive traces inside the chip substrate and the arrangement of the chip electrodes in the local avoidance method.

[0029] Figure 5 is a cross-sectional schematic diagram of the connection relationship between the chip and the circuit board and the conductive traces inside the chip substrate in all avoidance methods.

[0030] Figure 6 is a top view schematic diagram showing the relationship between the conductive traces inside the chip substrate and the arrangement of the chip electrodes in all avoidance methods. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] To fully understand this application, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0033] In one embodiment, a chip is provided. The chip type includes, but is not limited to, an ultrasonic fingerprint chip or other chip 1 that is electrically connected to the gold fingers 21 of the circuit board 2 using a substrate and an ACF bonding process. No specific limitation is made. An anisotropic conductive adhesive film 3 is provided between the gold fingers 21 of the circuit board 2 and the electrodes of the chip 1. The ACF bonding process uses conductive particles 31 to connect the electrodes between the chip 1 and the substrate 11 to achieve conductivity.

[0034] In this embodiment, the chip 1 includes a substrate 11, on which electrodes 12 are located and an internal conductive layer is located. The substrate 11 includes, but is not limited to, a silicon-based substrate, a silicon carbide substrate, or a gallium nitride substrate, etc., and is not specifically limited thereto. The electrodes 12 on the substrate 11 are the bonding pads on the chip, and the internal conductive layer inside the substrate 11 is the metal layer inside the substrate. The internal conductive layer includes the circuit layers required to implement the chip's functions. For example, the internal conductive layer includes conductive layers for signal transmission and power distribution within the chip. The circuit functions of the chip are realized through wiring in the internal conductive layer. Exemplarily, the internal conductive layer can be made of aluminum, copper, or other conductive materials, and is not specifically limited thereto.

[0035] The internal conductive layer inside the substrate 11 includes a first conductive layer 131 (Top Metal) at the top and a second conductive layer 132 below the first conductive layer 131. That is, the internal conductive layer of the substrate 11 includes multiple circuit layers. The uppermost conductive layer inside the substrate is designated as the first conductive layer 131, and the conductive layer below the first conductive layer 131 is designated as the second conductive layer 132. The electrode 12 is electrically connected to the first conductive layer 131. The electrode 12 is also used for electrical connection to a circuit board via ACF bonding. The circuit board refers to a module used to connect to the electrodes of the chip 1 to realize the corresponding functions of the chip. The minimum distance between the edge of the substrate 11 where the electrode 12 is located and the trace of the second conductive layer 132 in the first direction of the substrate 11 is a first preset distance, so that the area where the electrode 12 is located has no trace of the second conductive layer 132 along the second direction of the substrate 11, where the first direction and the second direction are perpendicular to each other. In other words, there is no trace of the second conductive layer 132 below the area where the electrode 12 is located.

[0036] It should be understood that, as shown in Figures 1 and 2, these figures illustrate the structural diagrams of the area where electrode 12 is located and the second conductive layer 132 is below it. Figure 2 is a top view, where the small squares on the bottom edge of the chip represent the electrodes of chip 1, and the large squares represent the traces of the second conductive layer 132. It can be seen that the electrodes 12 of chip 1 and the traces of the second conductive layer 132 overlap in the second direction, with no clearance. As shown in Figure 1, the ACF bonding process requires appropriate temperature and pressure to ensure electrical connection, allowing the gold fingers 21 of circuit board 2 to connect with the electrodes 12 of externally connected chip 1. When foreign objects (including silicon debris) are present on electrode 12, the circuitry of electrode 12 and the traces of the second conductive layer 132 below electrode 12 may short-circuit due to pressure damage to electrode 12, causing chip malfunction. It is worth noting that in some cases, the electrode 12 of chip 1 may be fine during the pressure failure test, but problems may arise when chip 1 is subjected to stress or aging, thus affecting the reliability of the chip.

[0037] Therefore, in this embodiment of the application, the arrangement area of ​​the electrode 12 is partially or completely free of the traces of the second conductive layer 132 along the second direction of the substrate 11. Therefore, there is a clearance space between the electrode 12 and the traces below in the second direction. Thus, even if the electrode 12 of the chip 1 is damaged by pressure, it will not cause a short circuit, and will not affect the subsequent chip function. This can improve the production yield and reduce the reliability risk of the chip 1, which has great application value.

[0038] It should be noted that, in this application, the minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the trace of the second conductive layer 132 in the first direction of the substrate 11 is a first preset distance, so that the arrangement area of ​​the electrode 12 is completely or partially free of the trace of the second conductive layer 132 along the second direction of the substrate 11, can be implemented in various ways, which will be described below.

[0039] In the first method, as shown in Figures 3 and 4, as an example, the first preset distance includes a first distance. The first distance is the minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the trace of the second conductive layer 132 in the first direction of the substrate 11, so that the part of the arrangement area of ​​the electrode 12 has no trace of the second conductive layer 132 along the second direction of the substrate 11.

[0040] This embodiment is a implementation method for partial avoidance of traces. The first preset distance includes a first distance. The minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the trace of the second conductive layer 132 in the first direction of the substrate 11 is the first distance. This ensures that a portion of the arrangement area of ​​the electrode 12 has no trace of the second conductive layer 132 along the second direction of the substrate 11. That is, the trace of the second conductive layer 132 below the electrode 12 avoids the arrangement area of ​​the electrode 12. Figures 3 and 4 show schematic diagrams of the structure in which the arrangement area of ​​the electrode 12 and the trace of the second conductive layer 132 below it are partially avoided. Figure 4 is a top view. The small square on the bottom edge of the chip 1 in Figure 4 represents the electrode 12 of the chip 1, and the large square represents the trace of the second conductive layer 132. It can be seen that the trace of the electrode 12 and the trace of the second conductive layer 132 of the chip 1 partially overlap in the second direction, and there is a partial avoidance space.

[0041] The inventors discovered that when the electrode 12 of chip 1 is connected to the circuit board via ACF bonding, foreign objects (such as silicon debris) are often found on the electrode 12 of chip 1 near the edge of the bonding position. Therefore, as shown in Figure 3, in this embodiment, the minimum distance between the edge of the substrate 11 where the electrode 12 is located and the trace of the second conductive layer 132 in the first direction of the substrate 11 is the first distance, so that there are no traces of the second conductive layer 132 in the second direction of the substrate 11 for part of the electrode 12. In other words, the trace of the second conductive layer 132 near the edge of the chip 1 where the electrode 12 is located partially avoids the electrode 12 above it. Since there are no traces below the position where foreign objects are easily dropped, even if the electrode 12 of chip 1 is damaged, it will not affect the subsequent function. Moreover, since it is a partial avoidance method, part of the traces of the second conductive layer 132 are still located below the electrode 12, so that the traces of the second conductive layer 132 in the chip 1 will not occupy much chip space, ensuring that the chip size will not be too large.

[0042] In one embodiment, the proportion of a portion of the electrode 12's arrangement area to the entire arrangement area of ​​the electrode 12 is greater than 50%. In this embodiment, more than half of the electrode 12's arrangement area is separated from the traces of the underlying second conductive layer 132. Therefore, it can be effectively ensured that the subsequent chip function will not be affected when the electrode 12 of the chip 1 is damaged.

[0043] The second method, as shown in Figures 3 and 4, is an example in which the first preset distance includes a second distance. The minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the trace of the second conductive layer 132 in the first direction of the substrate 11 is the second distance, so that there are no traces of the second conductive layer 132 in the entire arrangement area of ​​the electrode 12 along the second direction of the substrate 11.

[0044] This embodiment is a implementation method where all traces are avoided. The first preset distance includes a second distance. The minimum distance between the edge of the substrate 11 where the electrode 12 is located and the trace of the second conductive layer 132 in the first direction of the substrate 11 is the second distance. This ensures that the entire arrangement area of ​​the electrode 12 has no trace of the second conductive layer 132 along the second direction of the substrate 11. In other words, the trace of the second conductive layer 132 below the electrode 12 completely avoids the arrangement area of ​​the electrode 12. Figures 5 and 6 show schematic diagrams of the structure where the arrangement area of ​​the electrode 12 and the trace of the second conductive layer 132 below it are completely avoided. Figure 5 is a top view. The small square on the bottom edge of the chip 1 in Figure 5 represents the electrode 12 of the chip 1, and the large square above it represents the trace of the second conductive layer 132. It can be seen that the trace of the electrode 12 and the trace of the second conductive layer 132 of the chip 1 do not overlap in the second direction, and there is a complete avoidance space.

[0045] The inventors discovered that when the electrodes 12 of chip 1 are connected to the circuit board via ACF bonding, foreign objects (such as silicon debris) can easily accumulate on the electrodes 12. Therefore, in this embodiment, the entire arrangement area of ​​the electrodes 12 is free of traces of the second conductive layer 132 along the second direction of the substrate 11. Since there are no traces below the areas where foreign objects are prone to fall, even if the electrodes 12 of chip 1 are damaged, it will not affect subsequent functions. Moreover, because of this complete avoidance method, the normal functional use of the chip is greatly guaranteed even if the electrodes 12 are damaged.

[0046] In one embodiment, the minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the trace of the first conductive layer 131 is a second preset distance, which is less than the first preset distance. In this embodiment, the first conductive layer 131 and the electrode 12 are directly connected conductive layers, and the first conductive layer is the top conductive layer. The trace of the first conductive layer 131 may be located below the area where the electrode 12 is disposed.

[0047] In one embodiment, the circuit board includes a flexible circuit board. In other embodiments, it may be any other printed circuit board that can be connected to the electrodes 12 for chip 1 via ACF bonding process; specific embodiments of this application are not limited thereto.

[0048] In this embodiment, the printed circuit board connected to the electrode 12 of the chip 1 via ACF bonding process can include a flexible circuit board or other types of printed circuit boards. All of them can adopt the wiring design of the internal conductive layer of the chip provided in this application embodiment, thereby solving the problem of possible chip failure or low production yield.

[0049] In one embodiment, the chip 1 includes an ultrasonic fingerprint chip. In this embodiment, the chip 1 provided in this application includes, but is not limited to, an ultrasonic fingerprint chip or other biometric detection chips; it can also be other chips suitable for using ACF bonding technology, and is not specifically limited. An ultrasonic fingerprint chip refers to a chip with embedded ultrasonic fingerprint recognition technology, which can realize functions including ultrasonic fingerprint image acquisition, feature extraction, and feature comparison.

[0050] The ultrasonic fingerprint chip solution provided in this application embodiment has a trace of the second conductive layer 132 located below the electrode 12 of the chip 1. Since the minimum distance in the first direction of the substrate 11 is a first preset distance, there is no trace of the second conductive layer 132 in the arrangement area of ​​the electrode 12 along the second direction of the substrate 11. Therefore, there is space between the circuit of the electrode 12 and the circuit below it. Thus, even if the electrode 12 of the ultrasonic fingerprint chip 1 is damaged, it will not affect the subsequent chip function of the ultrasonic fingerprint chip. This can improve the production yield of the ultrasonic fingerprint chip and reduce the reliability risk of the ultrasonic fingerprint chip, which has great application value.

[0051] In one embodiment, an ultrasonic fingerprint module is provided, comprising an ultrasonic fingerprint chip 1 and a circuit board; the ultrasonic fingerprint chip includes a substrate, the substrate including electrodes located on the substrate and an internal conductive layer located inside the substrate, the internal conductive layer including a first conductive layer located at the top and a second conductive layer located below the first conductive layer, the electrodes being electrically connected to the first conductive layer, the electrodes also being used for electrical connection to the circuit board via anisotropic conductive film (ACF) bonding process, the minimum distance between the edge of the substrate where the electrodes are disposed and the trace of the second conductive layer in a first direction of the substrate is a first preset distance, such that the area where the electrodes are disposed is entirely or partially free of traces of the second conductive layer along a second direction of the substrate.

[0052] Therefore, an ultrasonic fingerprint module is provided, wherein an anisotropic conductive adhesive film 3 is disposed between the gold fingers 21 of the circuit board 2 and the electrodes of the chip 1. The ACF bonding process utilizes conductive particles 31 to connect the electrodes between the chip 1 and the substrate 11 to achieve conductivity. In this ultrasonic fingerprint module, the area where the electrode 12 is located is entirely or partially free of the traces of the second conductive layer 132 along the second direction of the substrate 11. Therefore, there is a clearance space between the electrode 12 and the traces below in the second direction. Thus, even if the electrode 12 of the chip 1 is damaged, it will not cause a short circuit, and will not affect the subsequent chip function. This improves the production yield and reduces the reliability risk of the chip 1, and has significant application value.

[0053] It should be noted that in the ultrasonic fingerprint module provided in this application, the minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the trace of the second conductive layer 132 in the first direction of the substrate 11 is a first preset distance, so that there is no trace of the second conductive layer 132 in the arrangement area of ​​the electrode 12 along the second direction of the substrate 11. There are many ways to achieve this, which will be described below.

[0054] In the first method, as shown in Figures 3 and 4, as an example, the first preset distance includes a first distance. The first distance is the minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the trace of the second conductive layer 132 in the first direction of the substrate 11, so that the part of the arrangement area of ​​the electrode 12 has no trace of the second conductive layer 132 along the second direction of the substrate 11.

[0055] In the ultrasonic fingerprint module provided in this embodiment, a partial routing avoidance implementation is adopted. The first preset distance includes a first distance. The minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the routing of the second conductive layer 132 in the first direction of the substrate 11 is the first distance. This ensures that a portion of the arrangement area of ​​the electrode 12 has no routing of the second conductive layer 132 along the second direction of the substrate 11. That is, the routing of the second conductive layer 132 below the electrode 12 avoids the arrangement area of ​​the electrode 12. Figures 3 and 4 show schematic diagrams of the structure in which the arrangement area of ​​the electrode 12 and the routing of the second conductive layer 132 below it partially avoid each other. Figure 4 is a top view. The small square on the bottom edge of the chip 1 in Figure 4 represents the electrode 12 of the chip 1, and the large square represents the routing of the second conductive layer 132. It can be seen that the electrode 12 and the routing of the second conductive layer 132 of the chip 1 partially overlap in the second direction, and there is a partial avoidance space. Moreover, since it is a partial avoidance method, part of the traces of the second conductive layer 132 are still located below the electrode 12, so that the traces of the second conductive layer 132 in the chip 1 will not occupy much chip space, ensuring that the chip size will not be too large.

[0056] In one embodiment, the proportion of a portion of the electrode 12's arrangement area to the entire arrangement area of ​​the electrode 12 is greater than 50%. In this embodiment, more than half of the electrode 12's arrangement area is separated from the traces of the underlying second conductive layer 132. Therefore, it can be effectively ensured that the subsequent chip function will not be affected when the electrode 12 of the chip 1 is damaged.

[0057] The second method, as shown in Figures 5 and 6, is an example in which the first preset distance includes a second distance. The minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the trace of the second conductive layer 132 in the first direction of the substrate 11 is the second distance, so that there is no trace of the second conductive layer 132 in the entire arrangement area of ​​the electrode 12 along the second direction of the substrate 11.

[0058] In the ultrasonic fingerprint module provided in this embodiment, which is an implementation method in which all traces are avoided, the first preset distance includes a second distance. The minimum distance between the edge of the substrate 11 on which the electrode 12 is disposed and the trace of the second conductive layer 132 in the first direction of the substrate 11 is the second distance, so that there are no traces of the second conductive layer 132 in the entire arrangement area of ​​the electrode 12 along the second direction of the substrate 11. That is, the traces of the second conductive layer 132 below the electrode 12 completely avoid the arrangement area of ​​the electrode 12. Figures 5 and 6 show schematic diagrams of a structure where the arrangement area of ​​electrode 12 and the traces of the second conductive layer 132 below are completely avoided. Figure 5 is a top view. The small square at the bottom of chip 1 in Figure 5 represents the electrode 12 of chip 1, and the large square at the top represents the traces of the second conductive layer 132. It can be seen that the electrode 12 of chip 1 and the traces of the second conductive layer 132 do not overlap in the second direction, and there is a complete avoidance space. Moreover, due to the complete avoidance method, the normal functioning of the chip is greatly guaranteed when the electrode 12 is damaged.

[0059] In one embodiment, the minimum distance between the edge of the substrate 11 where the electrode 12 is disposed and the trace of the first conductive layer 131 is a second preset distance, which is less than the first preset distance. In this embodiment, the first conductive layer 131 and the electrode 12 are directly connected conductive layers, and the first conductive layer is the top conductive layer. The trace of the first conductive layer 131 may be located below the area where the electrode 12 is disposed.

[0060] In one embodiment, the circuit board 2 in the ultrasonic fingerprint module includes a flexible circuit board. In other embodiments, it may also be other printed circuit boards that can be connected to the electrodes 12 for the chip 1 via ACF bonding technology; specific embodiments of this application are not limited thereto.

[0061] In this embodiment, the printed circuit board connected to the electrode 12 of the chip 1 via ACF bonding process can include a flexible circuit board or other types of printed circuit boards. All of them can adopt the wiring design of the internal conductive layer of the chip provided in this application embodiment, thereby solving the problem of possible chip failure or low production yield and improving the applicability of the solution.

[0062] In the ultrasonic fingerprint module provided in this application embodiment, the traces of the second conductive layer 132 located below the electrode 12 of the chip 1 are such that the minimum distance in the first direction of the substrate 11 is a first preset distance, so that the arrangement area of ​​the electrode 12 is completely or partially free of the traces of the second conductive layer 132 along the second direction of the substrate 11. Therefore, there is space between the circuit of the electrode 12 and the circuit below it. Thus, even if the electrode 12 of the ultrasonic fingerprint chip 1 is damaged, it will not affect the subsequent chip function of the ultrasonic fingerprint chip, which can improve the production yield of the ultrasonic fingerprint chip and reduce the reliability risk of the ultrasonic fingerprint chip, and has great application value.

[0063] In one embodiment, this application also provides an electronic device, which includes the chip or ultrasonic fingerprint module mentioned in any of the foregoing embodiments. The specific details will not be repeated here, but can be found in the above embodiments.

[0064] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0065] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A chip, wherein, The chip includes a substrate, on which electrodes are located on the substrate and an internal conductive layer is located inside the substrate; The internal conductive layer inside the substrate includes a first conductive layer at the top and a second conductive layer below the first conductive layer. The electrode is electrically connected to the first conductive layer. The electrode is also used to be electrically connected to the circuit board via anisotropic conductive film (ACF) bonding process. The minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer in the first direction of the substrate is a first preset distance, so that the area where the electrode is disposed is wholly or partially free of traces of the second conductive layer along the second direction of the substrate. The first direction is perpendicular to the second direction.

2. The chip according to claim 1, wherein, The first preset distance includes a first distance, where the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer are disposed, and the minimum distance in the first direction of the substrate is the first distance, so that the part of the electrode's placement area has no trace of the second conductive layer along the second direction of the substrate.

3. The chip according to claim 2, wherein, The proportion of the partial arrangement area of ​​the electrodes to the total arrangement area of ​​the electrodes is greater than 50%.

4. The chip according to claim 1, wherein, The first preset distance includes a second distance. The minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer in the first direction of the substrate is the second distance, so that there are no traces of the second conductive layer in the entire arrangement area of ​​the electrode along the second direction of the substrate.

5. The chip according to any one of claims 1-4, wherein, The minimum distance between the edge of the substrate on which the electrode is provided and the trace of the first conductive layer is a second preset distance, and the second preset distance is less than the first preset distance.

6. The chip according to any one of claims 1-4, wherein the second conductive layer comprises multiple conductive layers.

7. The chip according to any one of claims 1-4, wherein, The circuit board includes a flexible circuit board.

8. The chip according to any one of claims 1-4, wherein, The circuit board includes a printed circuit board connected to the electrodes via an ACF bonding process.

9. The chip according to any one of claims 1-4, wherein, The chip includes a biometric detection chip.

10. The chip according to claim 9, wherein, The chip includes an ultrasonic fingerprint chip.

11. The chip according to claims 1-4, wherein, The substrate includes a silicon-based substrate, a silicon carbide substrate, or a gallium nitride substrate.

12. An ultrasonic fingerprint module, wherein, The ultrasonic fingerprint module includes an ultrasonic fingerprint chip and a circuit board; The ultrasonic fingerprint chip includes a substrate, on which electrodes are located and an internal conductive layer is located. The internal conductive layer includes a first conductive layer at the top and a second conductive layer below the first conductive layer. The electrodes are electrically connected to the first conductive layer. The electrodes are also used to be electrically connected to the circuit board via anisotropic conductive film (ACF) bonding process. The minimum distance between the edge of the substrate where the electrodes are located and the trace of the second conductive layer in a first direction of the substrate is a first preset distance, so that the area where the electrodes are located is entirely or partially free of traces of the second conductive layer along a second direction of the substrate.

13. The ultrasonic fingerprint module according to claim 12, wherein, The first preset distance includes a first distance, where the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer are disposed, and the minimum distance in the first direction of the substrate is the first distance, so that the part of the electrode's placement area has no trace of the second conductive layer along the second direction of the substrate.

14. The ultrasonic fingerprint module according to claim 13, wherein, The proportion of the partial arrangement area of ​​the electrodes to the total arrangement area of ​​the electrodes is greater than 50%.

15. The ultrasonic fingerprint module according to claim 12, wherein, The first preset distance includes a second distance. The minimum distance between the edge of the substrate on which the electrode is disposed and the trace of the second conductive layer in the first direction of the substrate is the second distance, so that there are no traces of the second conductive layer in the entire arrangement area of ​​the electrode along the second direction of the substrate.

16. The ultrasonic fingerprint module according to any one of claims 12-15, wherein, The minimum distance between the edge of the substrate on which the electrode is provided and the trace of the first conductive layer is a second preset distance, and the second preset distance is less than the first preset distance.

17. The ultrasonic fingerprint module according to any one of claims 12-15, wherein the second conductive layer comprises multiple conductive layers.

18. The ultrasonic fingerprint module according to any one of claims 12-15, wherein, The circuit board includes a printed circuit board connected to the electrodes via an ACF bonding process.

19. The ultrasonic fingerprint module according to any one of claims 12-15, wherein, The circuit board includes a flexible circuit board.

20. An electronic device, wherein, Includes the chip as described in any one of claims 1-11, or the ultrasonic fingerprint module as described in any one of claims 12-19.

Images