Selective area growth with improved selectivity for nanowires

Abstract

The nanowire structure includes a substrate, a patterned mask layer, and nanowires. The patterned mask layer includes an opening through which the substrate is exposed. Furthermore, the patterned mask layer has a thermal conductivity greater than 20 W / (m·K). The nanowires are on the substrate within the opening in the patterned mask layer. By providing a patterned mask layer with a thermal conductivity greater than 20 W / (m·K), the patterned mask layer can maintain a desired temperature at the surface of the mask layer as the nanowires are deposited. This prevents undesired parasitic growth on the patterned mask layer, thereby improving the performance of the nanowire structure.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to nanowires, and more particularly to nanowires with reduced parasitic growth and methods for making same. [Background technology]

[0002] Nanowires hold great promise for applications in quantum computing. Unfortunately, producing high-quality nanowires is difficult. Conventional processes for producing nanowires involve selective-area-growth (SAG), in which nanowires are selectively grown directly onto a substrate through openings in a patterned mask layer. In such processes, it is desirable for nanowires to be grown only onto the substrate through the openings in the patterned mask layer, and not onto the patterned mask layer itself. Material growth that occurs during nanowire growth on a patterned mask layer is referred to as parasitic growth. The degree to which nanowires grow on the substrate rather than on the patterned mask layer is referred to as selectivity. Current nanowire manufacturing techniques result in an undesirable degree of parasitic growth and, therefore, an undesirably low degree of selectivity.

[0003] In view of the above, there is a need for nanowires with reduced parasitic growth and methods for fabricating same. Summary of the Invention

[0004] In one embodiment, a nanowire structure includes a substrate, a patterned mask layer, and nanowires. The patterned mask layer includes an opening through which the substrate is exposed. Furthermore, the patterned mask layer has a thermal conductivity greater than 20 W / (m·K). The nanowires are on the substrate within the opening in the patterned mask layer. By providing a patterned mask layer with a thermal conductivity greater than 20 W / (m·K), the patterned mask layer has a thermal conductivity comparable to, if not greater than, the thermal conductivity of the substrate, resulting in a temperature gradient within the mask layer comparable to that within the substrate. This leads to a negligible temperature drop across the mask, and the temperature at the mask surface is approximately equal to the temperature of the substrate at the growth surface. This prevents undesired parasitic growth on the patterned mask layer, thereby improving the performance and yield of the nanowire structure.

[0005] In one embodiment, the patterned mask layer has a thermal conductivity greater than 40 W / (m·K). With a thermal conductivity this high, the mask layer can have a significantly higher thermal conductivity than the substrate, further acting to improve temperature uniformity across the growth surface on the substrate. The patterned mask layer can comprise one or more of diamond, graphite, aluminum nitride, silicon carbide, and boron nitride. The nanowires can comprise one or more of indium arsenide, indium antimonide, and indium arsenide antimonide. The substrate can comprise one or more of gallium arsenide, gallium antimonide, indium phosphide, gallium phosphide, silicon, and germanium.

[0006] In one embodiment, the nanowire structure further comprises a superconductor layer covering the nanowires.

[0007] Those skilled in the art will appreciate the scope of the present disclosure and realize further aspects of the present disclosure after reading the following detailed description of the preferred embodiments in connection with the accompanying drawings. [Brief explanation of the drawings]

[0008] The accompanying drawing figures, which are incorporated in and constitute a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Figure 1] FIG. 1 illustrates a nanowire structure according to one embodiment of the present disclosure. [Figure 2] FIG. 1 illustrates a nanowire structure according to one embodiment of the present disclosure. [Figure 3] FIG. 1 is a flow diagram illustrating a method for fabricating a nanowire structural element according to one embodiment of the present disclosure. [Figure 4A] 4A-4E illustrate a method for fabricating a nanowire structural element according to one embodiment of the present disclosure. [Figure 4B] 4A-4E illustrate a method for fabricating a nanowire structural element according to one embodiment of the present disclosure. [Figure 4C] 4A-4E illustrate a method for fabricating a nanowire structural element according to one embodiment of the present disclosure. [Figure 4D] 4A-4E illustrate a method for fabricating a nanowire structural element according to one embodiment of the present disclosure. [Figure 4E] 4A-4E illustrate a method for fabricating a nanowire structural element according to one embodiment of the present disclosure. [Figure 5] FIG. 2 is a flow diagram detailing a method for fabricating a nanowire structural element according to one embodiment of the present disclosure. [Figure 6A] 6A and 6B are diagrams illustrating details of a method for fabricating a nanowire structure according to one embodiment of the present disclosure. [Figure 6B] 6A and 6B are diagrams illustrating details of a method for fabricating a nanowire structure according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments described below represent the information necessary to enable one skilled in the art to practice the embodiments and illustrate the best modes for practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, one skilled in the art will understand the concepts of the present disclosure and will recognize applications of those concepts not specifically addressed herein. It is understood that these concepts and applications are within the scope of this disclosure and the appended claims.

[0010] It is understood that although terms such as first, second, etc. may be used herein to describe various elements, the elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0011] It is understood that when an element, e.g., a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it can be directly on or extending directly onto the other element, or intervening elements can be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Similarly, it is understood that when an element, e.g., a layer, region, or substrate, is referred to as being "over" or extending "over" another element, it can be directly on or extending directly onto the other element, or intervening elements can be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It is also understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0012] Relative terms such as "lower" or "upper," or "upper" or "lower," or "horizontal" or "vertical," may be used herein to describe the relationship of one element, layer, or region shown in the figures to another element, layer, or region. It is understood that these terms and the terms described above are intended to encompass devices in different orientations in addition to the orientation depicted in the figures.

[0013] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It is further understood that the terms "have," "having," "include," and / or "including," when used herein, specify the presence of stated features, numbers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.

[0014] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is further understood that terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0015] 1 shows a nanowire structure 10 according to one embodiment of the present disclosure. The nanowire structure 10 includes a substrate 12, a high thermal conductivity patterned mask layer 14 on the substrate 12, and nanowires 16 on the substrate 12 that pass through openings in the high thermal conductivity patterned mask layer 14. Additionally, the nanowire structure 10 may include a superconductor layer 18 on the nanowires 16. In some embodiments, the superconductor layer 18 may extend over a portion of the high thermal conductivity patterned mask layer 14.

[0016] In one embodiment, the high thermal conductivity patterned mask layer 14 has a thermal conductivity greater than 20 W / (m·K) (Watts per meter·Kelvin). In some embodiments, this thermal conductivity can be effective at temperatures between 400°C and 700°C, which are typical temperatures used for nanowire growth. In further embodiments, the high thermal conductivity patterned mask layer 14 has a thermal conductivity greater than 40 W / (m·K). The high thermal conductivity patterned mask layer can include, for example, diamond (600-2000 W / (m·K)), including crystalline, polycrystalline, nanocrystalline, and ultrananocrystalline diamond, graphite (170 W / (m·K)), aluminum nitride (300 W / (m·K)), silicon carbide (400 W / (m·K)), and boron nitride (700 W / (m·K)). The thickness of the high thermal conductivity patterned mask layer 14 can be between 1 nm and 10 microns. By providing a high thermal conductivity patterned mask layer 14 having a thermal conductivity greater than 20 W / (m·K), the exposed surface of the high thermal conductivity patterned mask layer 14 can be maintained at a high temperature during the nanowire 16 growth process, as will be described in detail below. Maintaining a high temperature at the exposed surface of the high thermal conductivity patterned mask layer 14 during nanowire 16 growth can suppress parasitic growth on the high thermal conductivity patterned mask layer 14, improving selectivity. This, in turn, can improve the overall performance and yield of the nanowire structure 10.

[0017] Nanowire 16 may comprise one of indium arsenide, indium antimonide, and indium arsenide antimonide. Although shown as one layer, nanowire 16 may comprise several layers in some embodiments. Nanowire 16 may have a thickness between 20 nm and 300 nm. Additionally, nanowire 16 may have a thickness of nanometers (10 -9The superconductor layer 18 may have a diameter on the order of 1000 nm (meters) or a length-to-width ratio of over 1000. The substrate 12 may comprise one or more of gallium arsenide, gallium antimonide, gallium arsenide antimonide, indium phosphide, silicon, and germanium. The superconductor layer 18 may comprise one of aluminum, lead, niobium, indium, tin, and vanadium. The thickness of the superconductor layer 18 may be between 3 nm and 30 nm.

[0018] As described above, nanowire 16 may have multiple layers. For example, as shown in FIG. 2 , nanowire 16 may include a buffer layer 20 on substrate 12 through an opening in high thermal conductivity patterned mask layer 14, and an active layer 22 on buffer layer 20. Buffer layer 20 may include one or more of gallium arsenide antimonide, indium gallium arsenide, aluminum antimonide, indium aluminum antimonide, and indium aluminum arsenide. Active layer 22 may include one of indium arsenide, indium antimonide, and indium arsenide antimonide. Buffer layer 20 may have a thickness between 0 nm and 10 microns. Active layer 22 may have a thickness between 3 nm and 200 nm.

[0019] FIG. 3 is a flow diagram illustrating a method for fabricating a nanowire structure 10 according to one embodiment of the present disclosure. FIGS. 4A-4E illustrate the method of FIG. 3 and will therefore be described in conjunction with FIG. 3. A substrate 12 is provided (block 100 and FIG. 4A). A high thermal conductivity mask layer 14a is provided on the substrate (block 102 and FIG. 4B). As shown in FIG. 4B, the high thermal conductivity mask layer 14a is provided as a blanket layer covering the substrate 12. The high thermal conductivity mask layer 14a is patterned to form a high thermal conductivity patterned mask layer 14 (block 104 and FIG. 4C). Patterning the high thermal conductivity mask layer 14a can be performed by any suitable process. For example, the high thermal conductivity mask layer 14a can be patterned by a lithography process, such as an electron beam lithography process. Nanowires 16 are provided on the substrate 12 through openings in the high thermal conductivity patterned mask layer 14 (block 106 and FIG. 4D). The nanowires 16 may be provided by any suitable process, but in some embodiments are provided by a SAG process, which is described in more detail below. A superconductor layer 18 is provided on the nanowires 16, and in some embodiments, on portions of the high thermal conductivity patterned mask layer 14 (block 108 and FIG. 4E).

[0020] FIG. 5 is a flow diagram detailing the provision of nanowires 16 on a substrate 12 through openings in a high-thermal-conductivity patterned mask layer 14, according to one embodiment of the present disclosure. FIGS. 6A and 6B illustrate the method of FIG. 5 and are therefore discussed in conjunction with FIG. 5. The backside of the substrate 12 is heated (block 200 and FIG. 6A). As described herein, the backside of the substrate 12 is the side of the substrate 12 opposite the high-thermal-conductivity patterned mask layer 14. The backside of the substrate 12 may be heated in any suitable manner, and in one embodiment, is heated by direct contact with a heat source 24. The heat source 24 may be any suitable heat source. Nanowires 16 are then grown on the substrate 12 through the openings in the high-thermal-conductivity patterned mask layer 14 by molecular beam epitaxy (block 202 and FIG. 6B). By using the high thermal conductivity patterning mask layer 14, the surface of the high thermal conductivity patterning mask layer 14 opposite the substrate 12 conducts the heat provided by the heat source 24 and remains at a relatively high temperature. The high temperature of the surface of the high thermal conductivity patterning mask layer 14 inhibits or prevents parasitic growth from the nanowires 16, thus improving selectivity. Therefore, the performance of the nanowire structure 10 may be improved.

[0021] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A substrate; a patterned mask layer on the substrate; the patterned mask layer having an opening through which the substrate is exposed; the patterned mask layer has a thermal conductivity of greater than 20 W / (m·K) and comprises one or more of diamond and graphite; a patterned mask layer; nanowires on the substrate within the openings in the patterned mask layer; A nanowire structure having:

2. 10. The nanowire structure of claim 1, wherein the nanowire comprises one of indium arsenide, indium antimonide, and indium arsenide antimonide.

3. 3. The nanowire structure of claim 2, wherein the substrate comprises one or more of gallium arsenide, gallium antimonide, indium phosphide, gallium phosphide, silicon, and germanium.

4. 10. The nanowire structure of claim 1, further comprising a superconductor layer covering the nanowire.

5. 1. A method for fabricating a nanowire structure, comprising: Prepare the board, providing a patterned mask layer on the substrate; the patterned mask layer having an opening through which the substrate is exposed; the patterned mask layer has a thermal conductivity greater than 20 W / (m·K) and comprises one or more of diamond and graphite; providing nanowires on the substrate within the openings in the patterned mask layer; How to have that.

6. The method of claim 5 , wherein providing the nanowires comprises growing the nanowires by a selective area growth (SAG) process.

7. The method of claim 6 , wherein the nanowires comprise one of indium arsenide, indium antimonide, and indium arsenide antimonide.

8. The method of claim 5 , wherein the nanowires comprise one of indium arsenide, indium antimonide, and indium arsenide antimonide.

9. 9. The method of claim 8, wherein the substrate comprises one or more of gallium arsenide, gallium antimonide, indium phosphide, gallium phosphide, silicon, and germanium.

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